Dual processor architecture for deterministic forwarding and selective higher order function execution

Abstract

The invention relates to an edge system with a dual-processor architecture, which integrates a broadband processor and an enterprise network processor through coordinated function configuration. The service level of the packet flow is divided by the post-provisioning data and the telemetry data, and it is determined whether to transmit the packet by the broadband processor or to selectively perform a high-order function, such as deep packet detection, data encryption, or data compression, by the enterprise network processor. Embodiments include logical coupling of virtual area networks, a signalling mechanism of segment routing / micro identity identification, a transport mechanism of memory sharing and without duplication, and a hybrid coupling combining logical control and data transport entity structures.

Description

Technical Field

[0001] This invention relates to network systems and their architectures, particularly to an edge system with a dual-processor or dual-engine architecture, wherein a broadband processor and an enterprise network processor work together under a service-aware control mechanism to perform packet processing. Background Technology

[0002] Existing network gateways and routers that incorporate two processors, such as architectures that couple a broadband system-on-a-chip (SoC) with an application processor, typically rely on fixed or standard policies to determine which processor handles specific traffic. Such designs generally lack telemetry feedback and frequently duplicate or reproduce packet streams between processors, resulting in unpredictable latency and low processing efficiency. Furthermore, these existing systems cannot support real-time adaptation when load conditions or application combinations change.

[0003] Therefore, there is an urgent need for a self-coordinating architecture that can analyze real-time telemetry data and dynamically allocate packet flows, while ensuring consistent and reliable broadband traffic performance when enterprise-level functions must be implemented. Summary of the Invention

[0004] One embodiment of the present invention provides an edge system with a dual-processor architecture, comprising: A broadband processor capable of performing broadband network access and packet processing, wherein the broadband processor provides one of the input / output interfaces of the dual-processor architecture; An enterprise network processor capable of performing packet processing and data processing; A software-based network interface connects the broadband processor to the enterprise network processor; A coordination unit determines a service level based on a post-processor data input and, based on telemetry data analysis related to the broadband processor and the enterprise processor, determines a processing entity between the broadband processor and the enterprise processor; and A function configuration unit, based on the service level determined by the coordination unit and the telemetry data analysis, instructs that only the broadband processor or only the enterprise network processor process one of the packet streams related to the post-data input.

[0005] Another embodiment of the present invention provides an edge system with a dual-processor architecture, comprising: a broadband processor capable of performing broadband network access and packet processing, wherein the broadband processor provides one input / output interface of the dual-processor architecture; an enterprise network processor performing packet processing and data processing, wherein the broadband processor and the enterprise processor share a high-speed memory structure to provide zero-copy transmission of packet descriptors and packet stream telemetry data; a coordination unit determining a service level based on a post-data input and determining a processing entity between the broadband processor and the enterprise network processor based on telemetry data analysis related to the broadband processor and the enterprise network processor; and a function configuration unit processing a packet stream related to the post-data input based on the service level determined by the coordination unit and the telemetry data analysis. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of an edge device based on a dual-processor architecture proposed in this invention.

[0007] Figure label: Dual-processor architecture for edge devices 100 First processor module 10 Network Input / Output Interface 11 Second processor module 20 High-speed shared memory module 30 Processor Interface Module 40 Data transmission path 41 Packet guiding module 50 Detailed Implementation

[0008] To make the objectives, technical solutions, and advantages of this invention clearer, the following detailed description is provided in conjunction with specific embodiments.

[0009] In one embodiment, a network edge system includes a broadband processor, an enterprise network processor, a coordination unit, and a function configuration unit; wherein a software-based network interface connects the broadband processor and the enterprise processor.

[0010] In one embodiment, the broadband processor may be a network system-on-a-chip (SoC) that performs high-speed packet forwarding and broadband access functions, while the enterprise network processor performs deep packet inspection, data encryption, data analysis, or tasks related to software-defined wide area networks (SD-WAN). A data path is formed between the broadband processor and the enterprise processor, through which packet streams processed by the enterprise network processor first pass through the broadband processor and then leave the system via the data path.

[0011] A software-based network interface provides a logical connection between the broadband processor and the enterprise processor, which can be implemented using Virtual Local Area Network (VLAN), Virtual Scalable Local Area Network (VxLAN), or equivalent channel technologies.

[0012] The high-speed telemetry data sharing of these processors is provided via PCIe, enabling the coordination unit to monitor operational status in real time, including CPU utilization, queue depth, and latency metrics. When relevant metrics exceed preset thresholds, packet streams are migrated from one processor to another, and this redirection is performed by the function configuration unit.

[0013] In a data path VLAN segmentation implementation, management, control, and data isolation between processors are achieved through logical segmentation to ensure that the mutual interference time between planes is less than 2 microseconds and to support deterministic and consistent control responses.

[0014] In a data path SRv6 / uSID signaling embodiment, packet flows are encapsulated using a Segment Routing IPv6 (SRv6) header. This SRv6 header contains activities monitored through micro-segmentation technology using a microdevice identifier (uSID), reflecting the corresponding service level. This is achieved by monitoring or encoding a series of functions through each uSID, such as data decryption, artificial intelligence inference, or data compression, with the additional processing burden of each functional stage limited to tens of microseconds. Typically, a specific service level includes a specific set of functions and corresponds to a unique sequence in which those functions participate.

[0015] In one embodiment, an SRv6 fast path is formed to redirect packet streams directly to the enterprise network processor, bypassing the broadband processor.

[0016] In a data path shared memory coupling embodiment, a high-speed shared memory structure allows zero-copy transmission of packet descriptors and telemetry data, for example, through a PCIe 3.0 × 4 connection, achieving a transmission bandwidth of 25–35 Gb / s, with a latency of approximately 0.8–1.2 microseconds, and a response time of approximately 50 microseconds under backpressure conditions.

[0017] In a hybrid data path coupling embodiment, control signals are transmitted through logical segmentation, while the data plane uses shared memory for transmission, resulting in an overall coordination delay of approximately 1–2 microseconds under end-to-end conditions.

[0018] In one embodiment, the software-based network interface (e.g., VLAN or Switched Virtual Interface (SVI)) divides a single physical network into multiple logical networks, and these multiple logical segments can coexist with SRv6 to maintain point-to-point service level continuity.

[0019] In one embodiment, the broadband processor may be a multi-core system-on-a-chip (SoC) responsible for service level classification, quality of service (QoS) policy enforcement, and SRv6 fast path processing. Taking a system using the DWE architecture as an example, it is determined that it can provide downlink transmission capabilities of approximately 10 Gb / s and uplink transmission capabilities of approximately 5 Gb / s.

[0020] In one embodiment, the enterprise network processor may be a multi-core system-on-a-chip (such as the C3 series) providing AI analytics, data encryption, and Network Functions Virtualization (NFV) capabilities. The enterprise network processor may load applications such as AI inference, IPsec / WireGuard, or SRv6 policy enforcement. Because high-performance enterprise network processors can perform continuous computations, the loaded applications typically involve data encryption or compression operations.

[0021] In one embodiment, the enterprise network processor is only called when necessary. In a representative part, higher value-added applications account for about 20-40% of the total network traffic. This is subject to redirection through the network engine. If C3 resources are fully utilized, near-line speed performance can be maintained on the broadband path.

[0022] In one embodiment, the coordination unit determines the service class and function vector based on meta-data. This meta-data includes policy functions displayed in pairs (meta-level summary of content, telemetry metrics of service), and the corresponding outputs are also displayed in pairs (service-class, processor). In one embodiment, this provides a defined and consistent quality of service (QoS).

[0023] In one embodiment, when network traffic becomes congested or security requirements increase, the coordination unit calls the enterprise network processor. When the utilization rate of the broadband processor's central processing unit exceeds approximately 80% or the queue latency exceeds approximately 2–3 microseconds, the latency can be maintained within the expected range so that the promised service quality is not compromised.

[0024] In one embodiment, the function configuration unit applies a quality of service policy to either the broadband processor or the enterprise network processor, with a switching latency maintained between 100 and 300 microseconds, and confirms packet order integrity using a sequence counter.

[0025] In one embodiment, under high load conditions, approximately 20–40% of packet flow can be migrated to the enterprise network processor, while the overall throughput can still be maintained at 90–95% or more of the available capacity.

[0026] Broadband applications that cannot be effectively handled by ASICs are outsourced to enterprise network processors, such as deep packet inspection, threat analysis, data encryption / decryption, AI-assisted analysis, and video processing. The processing stages of each high-level function are designed to add only a certain range of latency. For example, each stage in a typical execution is about tens of microseconds, so that the cumulative latency still meets the latency targets set by the corresponding service level.

[0027] In one embodiment, the functions of the coordination unit and the function configuration unit can be implemented by firmware, software, or combinational logic circuitry, including interaction with an external service enhancement device management system (SE-EMS). This forms a closed-loop mechanism for network-wide optimization and proactive customer service analysis.

[0028] In a logical segmentation implementation, a Virtual Local Area Network (VLAN) is configured so that management, control, data and other related sequences have a defined scheduling mode, and the related latency can be considered individually.

[0029] In a single-segment routing service signal implementation, the microdevice identification code (uSID) is typically divided into 8 stages or fewer to limit the necessary processing time and keep the latency of each function below about 20 microseconds per stage.

[0030] In a shared memory implementation, multiple PCIe 3.0 interfaces are configured to form four segments, achieving a throughput of 25–35 Gb / s and a transmission latency of 0.8–1.2 microseconds.

[0031] In a hybrid mode embodiment, under representative conditions, the overall coordination delay from the control plane to the data plane can be maintained within the range of 1–2 microseconds end-to-end.

[0032] In one embodiment, the system is aligned with the telemetry cycle, with an operation time between 1 and 5 milliseconds, and employs a synchronization communication protocol to prevent state drift between processors.

[0033] The aforementioned hybrid configuration forms a unified dual-engine edge device that combines real-time telemetry with selective transfer mechanisms, limiting latency to a fixed range and expandable to future generations of hardware and different access areas.

[0034] In one embodiment, the enterprise network processor is called only when necessary. In one embodiment, packet streams associated with the Server Message Block (SMB) protocol cannot call the enterprise network processor. In one embodiment, the enterprise network processor is not called by trusted packet streams. In one embodiment, the enterprise network processor is not called by packet streams used for Internet access. In one embodiment, the enterprise network processor is called to perform security functions, such as deep packet inspection, data decryption, AI inference, or video analytics.

[0035] In one embodiment, the coordination unit determines the service level and function vector based on a post-processor data input, wherein the function vector consists of Virtual Network Functions (VNFs) and / or extended functions, and distributes workload between the broadband processor and the enterprise network processor based on telemetry data analysis. In one embodiment, the highest service level is Platinum class, followed by Gold class and Silver class. In one embodiment, the coordination unit determines the implementing entity of the Quality of Service (QoS) policy related to the service level based on post-processor data input and telemetry data analysis of the broadband processor and the enterprise network processor. In one embodiment, telemetry and policy-driven execution can be implemented, with self-adaptive optimization capabilities.

[0036] In one embodiment, when network traffic becomes congested due to the broadband processor, the coordination unit decides to call the enterprise network processor to handle subsequent packet flows. In one embodiment, when a service level's quality of service policy intent (e.g., Platinum) includes a high level of security protection, the coordination unit decides to rely on the computing power provided by the enterprise network processor to perform security functions, such as deep packet inspection, secure virtual network functionality, data decryption, or AI inference / video analytics. In one embodiment, the coordination unit is located within the broadband processor. In one embodiment, the convergence of computing resources at the telecommunications edge and the enterprise network edge can be achieved.

[0037] In one embodiment, the function configuration unit delivers a quality of service policy to either the broadband processor or the enterprise network processor for implementation, based on the service level and processing entity determined by the coordination unit. In another embodiment, the function configuration unit instructs either the broadband processor or the enterprise network processor (but not both simultaneously) to perform packet processing for a packet flow. Only the broadband processor or only the enterprise network processor (but not both) can perform SRv6 packet encapsulation. When the enterprise network processor is invoked by the function configuration unit, the packet flow passes through the broadband processor via SRv6 before being delivered to the enterprise network processor for processing. In one embodiment, deterministic line rate forwarding can be implemented for cut-through traffic.

[0038] In one embodiment, when the coordination unit determines, based on telemetry data analysis or service level assessment, that processing by the enterprise network processor is required, the function configuration unit calls the enterprise network processor to perform the transfer processing. In another embodiment, intelligent transfer of each packet stream for higher-level functions can be implemented when necessary.

[0039] In one embodiment, the broadband processor can perform broadband network access and packet processing. The enterprise network processor can perform packet processing and data processing, such as data encryption, data compression, and data conversion. The data conversion may involve algorithms, such as Fourier transform. In one embodiment, the packet processing may include data filtering for keyword searching. In one embodiment, the data processing may include noise filtering to clean up data. In one embodiment, the packet processing includes deep packet inspection.

[0040] In addition, please refer to Figure 1 The present invention proposes another edge device 100 with a dual-processor architecture, characterized in that it comprises: A first processor module 10 is used to perform network packet forwarding processing and has at least one network input / output interface 11; A second processor module 20 is used to perform data processing or packet processing operations; A high-speed shared memory module 30 is operatively connected between the first processor module 10 and the second processor module 20 for shared access to packet description information or packet-related data. A processor interface module 40 connects the first processor module 10 and the second processor module 20, forming a data transmission path 41; and A packet guiding module 50, connected to the processor interface module 40, is used to guide the packet stream to either the first processor module 10 or the second processor module 20 for processing. The first processor module 10 and the second processor module 20 are configured in the same edge device body, and a dual-processor coupling structure is formed by the high-speed shared memory module 30 and the processor interface module 40.

[0041] However, the above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the claims and patent specification of the present invention shall still fall within the scope of the present invention.

Claims

1. An edge system with a dual-processor architecture, comprising: A broadband processor capable of performing broadband network access and packet processing, wherein the broadband processor provides one of the input / output interfaces of the dual-processor architecture; An enterprise network processor capable of performing packet processing and data processing; A coordination unit, operatively coupled to the broadband processor and the enterprise network processor, wherein the coordination unit determines a service level based on a post-processor data input and determines a processing entity between the broadband processor and the enterprise network processor based on telemetry data analysis associated with the broadband processor and the enterprise network processor; and A function configuration unit is operatively coupled to the broadband processor, the enterprise network processor, and the coordination unit, wherein the function configuration unit instructs, based on the service level determined by the coordination unit and the telemetry data analysis, that either the broadband processor or the enterprise network processor alone should process one of the packet streams related to the relay data input.

2. The system as described in claim 1, wherein the packet processing includes deep packet inspection.

3. The system as described in claim 1, wherein the data processing includes data encryption, data compression, or data conversion.

4. The system as claimed in claim 1, wherein a data path is formed between the broadband processor and the enterprise network processor, and the data path is virtually segmented to achieve data isolation between the broadband processor and the enterprise network processor.

5. The system as described in claim 1, wherein a memory system is configured between the broadband processor and the enterprise network processor, wherein, The memory system is connected to the broadband processor and the enterprise network processor via a PCIe data path.

6. The system as described in claim 5, wherein, The memory system provides a data sharing function for the broadband processor and the enterprise network processor, wherein the coordination unit determines the processing entity based on telemetry data provided by the broadband processor and the enterprise network processor and stored in the memory system.

7. The system as described in claim 1, wherein the coordinating unit encapsulates the SRv6 Segment Routing IPv6, Internet Protocol version 6 (IPv6) header into the packet stream, wherein, The SRv6 header includes a uSID micro identifier corresponding to the service class, which triggers a network-wide service chain or quality of service implementation across the entire network.

8. The system as described in claim 1, wherein the coordinating unit performs a traffic migration procedure related to feedback, wherein, When telemetry data shows that latency, throughput, or power usage associated with a corresponding service level has crossed a threshold, the traffic migration procedure reallocates the current packet flow between the broadband processor and the enterprise processor.

9. The system as described in claim 1, wherein, The coordination unit transmits service level-related telemetry data and processor utilization data to a Service-Enhanced Element Management System (SE-EMS) or a remote controller, thereby achieving policy optimization and maintaining consistent service levels across multiple systems throughout the network.

10. The system as described in claim 5, wherein a high-speed memory structure operates according to the memory system and the PCIe data paths, and operates in conjunction with a logically segmented virtual interface, such that the control plane is coordinated through the logically segmented virtual interface and the data plane is transmitted through the high-speed memory structure, thereby achieving hybrid coupling between the broadband processor and the enterprise network processor.

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