Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate, and etching a first surface of the substrate to form a plurality of grooves; sequentially forming a lower pole plate, a dielectric layer and an upper pole plate of the trench capacitor in the trench; a first through hole conductive structure is formed above at least part of the grooves, and the first through hole conductive structure is electrically connected to the lower pole plate in the groove below the first through hole conductive structure and is electrically connected with the metal wire located on the second face of the substrate through the lower pole plate; the first through hole conductive structure and the second through hole conductive structure used for being connected with an upper electrode plate of the groove capacitor can be synchronously formed, and plane capacitors can be prepared in parallel while the groove capacitor is formed. According to the invention, through pre-forming and embedding the through hole conductive structure in the groove etching and capacitor preparation stage, the etching depth required by the subsequent top layer through hole can be obviously shortened, the high aspect ratio etching difficulty and the side wall damage risk are reduced, the metal filling is improved, and the interconnection alignment tolerance and yield are improved; and meanwhile, the method is compatible with the existing planar capacitor and rear-end interconnection process, and is beneficial to the reliability and the process stability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] As the integration density and interconnect layer count of semiconductor devices increase, the spatial layout of on-chip capacitors and interconnects becomes increasingly compact. In existing technologies, trench capacitors are typically formed independently and separately from top-vias used to connect the underlying metal traces: the trench capacitor is etched separately first, and then a deep via is created in a subsequent interconnect process to penetrate multiple layers of dielectric to reach the underlying metal traces. However, with process miniaturization, the etching depth and aspect ratio of the top-vias increase significantly, leading to increased difficulty in the dry etching process. Problems such as sidewall damage, uneven etching, chamfering, and micro-residues frequently occur, which in turn affect the density of metal filling and interconnect reliability, reducing yield.

[0003] Deep etching can also easily lead to voids and uneven deposition in the metal filler, causing CMP step effects and surface unevenness, increasing the manufacturing difficulty and cost of subsequent wiring layers. Meanwhile, mismatches in timing and geometry between independently formed vias and trench capacitors can increase the height difference of top-via landing points, narrow alignment tolerances, and cause localized stress concentrations, limiting the flexibility of parallel placement of trench capacitors and planar capacitors on the same interconnect layer. In summary, existing processes have significant shortcomings in meeting the requirements of high-density capacitor integration and reliable interconnection. There is an urgent need for a manufacturing solution that, without significantly increasing process complexity, can reduce the etching depth of top-level vias, alleviate the challenges of high aspect ratio etching, and simultaneously ensure capacitor performance and interconnect reliability. Summary of the Invention

[0004] To address the problems existing in the prior art, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, forming a plurality of trenches on a first surface of the substrate; forming trench capacitors in the plurality of trenches, and forming a first via conductive structure on at least a portion of the trenches; wherein the first via conductive structure is electrically connected to a lower electrode in the trench below it, and is electrically connected to a metal trace located on a second surface of the substrate through the lower electrode.

[0005] Furthermore, the trench capacitor forming step includes: depositing conductive material in the trench to form a lower electrode; depositing a dielectric layer on the lower electrode; and depositing conductive material on the dielectric layer to form an upper electrode.

[0006] Furthermore, at least a portion of the trench capacitor has a second through-hole conductive structure formed on it and electrically connected to the upper plate of the trench capacitor, wherein the second through-hole conductive structure and the first through-hole conductive structure are formed simultaneously.

[0007] Furthermore, at least a portion of the lower electrode of the trench capacitor is electrically connected to the metal traces on the second surface of the substrate.

[0008] Furthermore, while forming the trench capacitor, one or more planar capacitors are formed on the substrate, and at least part of the second through-hole conductive structure is electrically connected to the upper plate of the planar capacitor.

[0009] Furthermore, an insulating layer is formed on the upper electrode of the trench capacitor; before forming the first through-hole conductive structure, a portion of the upper electrode below the first through-hole conductive structure is removed.

[0010] Furthermore, the upper ends of the first through-hole conductive structure and the second through-hole conductive structure are electrically connected to a metal trace located on the first surface of the substrate.

[0011] Furthermore, at least a portion of the lower plate of the trench capacitor does not contact the metal traces located on the second surface of the substrate.

[0012] Furthermore, a protective layer is formed on the insulating layer, the protective layer covering the insulating layer and the sidewall of the upper electrode plate.

[0013] Furthermore, after forming the protective layer, an interlayer insulating layer is formed on the surface of the substrate; then, through-holes are formed in the interlayer insulating layer by etching; the etching of the through-holes stops at the surface of the capacitor plates.

[0014] The present invention also provides a semiconductor structure prepared according to the above method, the semiconductor structure comprising a substrate, a first through-hole conductive structure, and a second through-hole conductive structure, the substrate comprising a first metal trace located on a first surface and a second metal trace located on a second surface; a plurality of capacitor structures are provided near the second surface of the substrate, the capacitor structures comprising trench capacitors and / or planar capacitors; the first metal trace is electrically connected to the second metal trace through the first through-hole conductive structure and the lower electrode of a portion of the capacitor structure.

[0015] Compared with the prior art, the present invention introduces the formation process of the through-hole conductive structure simultaneously in the trench capacitor formation stage, which has significant technical advantages compared with the prior art in which the trench capacitor and the through-hole structure are formed independently in steps.

[0016] Firstly, in existing technologies, it is typically necessary to simultaneously form deep vias and shallow vias for connecting metal traces at different levels within the same interlayer dielectric. Due to the significant difference in etching depth between the two, process window conflicts can easily occur under the same etching conditions: shallow vias are prone to over-etching, causing unnecessary damage to the underlying structure or electrodes, while deep vias are prone to under-etching, leading to incomplete contact or decreased electrical connection reliability, thus significantly increasing the difficulty of via etching and the risk of process instability. This invention, however, pre-integrates the conductive structure of the vias used to connect the underlying metal traces into the trench capacitor structure, significantly shortening the etching depth of the top-level vias required in the subsequent interconnect stage. This effectively reduces the difficulty of etching high aspect ratio vias, minimizes the risks of sidewall damage, uneven etching, and micro-residues, and improves the etching window and process stability from a process perspective.

[0017] Secondly, by reducing the height difference between the via conductive structure and the underlying metal trace, the consistency of metal filling can be significantly improved, the probability of void formation can be reduced, and the CMP planarization effect can be enhanced, thereby improving the reliability and yield of the interconnect structure. Furthermore, while realizing trench capacitors, this invention can simultaneously form via conductive structures electrically connected to the upper and lower plates, and supports parallel integration with planar capacitors, enhancing the flexibility of capacitor layout and interconnect design, and making it suitable for various circuit topology requirements.

[0018] Finally, this invention reduces the critical size of vias while shortening the etching depth of the top-layer vias, effectively improving the integration density of integrated circuits. This invention achieves the above effects without significantly increasing additional process steps, exhibits strong compatibility with existing semiconductor manufacturing processes, and helps reduce manufacturing costs while improving the overall electrical performance and long-term reliability of devices. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a semiconductor structure in the prior art; Figure 2-10 This is a schematic diagram of the semiconductor structure fabrication process according to Embodiment 1 of the present invention; Figure 11-19 This is a schematic diagram of the semiconductor structure fabrication process in Embodiment 2 of the present invention; Figure 20 This is a schematic diagram of the semiconductor structure in Embodiment 3 of the present invention; Figure 21-29 This is a schematic diagram of the semiconductor structure fabrication process in Embodiment 4 of the present invention. Detailed Implementation

[0020] like Figure 1The diagram shows a schematic of a top-mounted via conductive structure 111 fabricated using existing technology. A first metal trace 110 is formed on the first surface of the substrate 100, and a second metal trace 101 is formed on the second surface. To connect the first metal trace 110 and the second metal trace 101, after fabricating the trench capacitor, an additional etching process is typically required to penetrate the substrate 100 and the interlayer dielectric layer 108 thereon, thereby forming a via and exposing or contacting the underlying metal layer. This via etching often requires a large etching depth to span multiple dielectric and metal interconnect layers, resulting in a high aspect ratio for the via.

[0021] In existing technologies, multiple vias often exist within the same device structure, used to connect metal traces at different levels or different functional structures. These vias are designed with different target etching depths. For example, vias used to connect the top layer metal to the upper plate of a trench capacitor or a planar capacitor are typically shallow vias, while vias used to directly connect the top layer metal to the bottom layer metal traces require a greater etching depth. Therefore, in actual manufacturing processes, it is often necessary to form both deep and shallow vias simultaneously under the same etching process conditions, inevitably introducing the problem of etching process window conflicts.

[0022] Specifically, under uniform etching conditions, shallow vias are prone to over-etching due to improper control of etching time or etching rate, which can cause unnecessary damage to underlying electrodes, metal traces, or dielectric structures. Deep vias, on the other hand, are prone to under-etching, resulting in insufficient exposure or incomplete contact of the metal at the bottom of the via, leading to increased contact resistance and unstable electrical connections. This coexistence of shallow and deep vias significantly increases the difficulty of process control and places higher demands on etching uniformity, endpoint control, and equipment stability.

[0023] Because deep vias need to traverse multiple layers of dielectric and metal interconnect structures, their etching depth is significant, resulting in vias with high aspect ratios. Under high aspect ratio conditions, dry etching processes are prone to etching non-uniformity and micro-loading effects, leading to non-straight sidewall profiles, abnormal bottom morphology, or difficulty in completely removing etching residues. This further affects the coverage consistency and interface reliability of subsequent metal deposition. Simultaneously, high aspect ratio vias are more likely to generate voids or discontinuous filling during subsequent metal filling, increasing interconnect resistance and the risk of electromigration failure.

[0024] On the other hand, since the landing height of the top-layer vias is usually significantly different from the top surface of the surrounding trench capacitors or planar capacitor layers, local step structures are easily formed on the device surface, increasing the difficulty of chemical mechanical planarization, affecting surface flatness, and further limiting the reliable stacking of upper interconnect structures. In addition, the introduction of multiple photolithography and alignment steps not only increases process complexity and manufacturing cost, but also makes the electrical connection between the vias and the internal electrodes of the capacitor more susceptible to alignment errors and height differences, resulting in poor contact or short circuit risks.

[0025] In summary, Figure 1 The existing technology shown has significant shortcomings in terms of etching process stability, interconnect reliability, device yield, and manufacturing cost. It has become an important constraint on the further development of high-density trench capacitors and multilayer interconnect integrated structures.

[0026] To address the technical problems existing in the prior art, this invention proposes a semiconductor structure and its formation method, the specific implementation of which is as follows. Example 1

[0027] like Figure 2-10 As shown, this embodiment provides a method for fabricating a semiconductor structure. First, a substrate 100 is provided. The substrate 100 can be a silicon substrate or a semiconductor substrate containing an epitaxial layer, and necessary active devices or interconnect structures have already been formed inside it. On a first surface of the substrate 100, multiple trenches are formed using photolithography and etching processes for the subsequent construction of trench capacitors. Simultaneously, multiple second metal traces 101 are formed on a second surface of the substrate 100. The second metal traces 101 can be bottom interconnect metals used to realize electrical connections between devices and peripheral circuits or other interconnect layers.

[0028] Subsequently, a metal material is deposited within the trench on the first side of the substrate 100 to form a lower electrode 102. This metal material can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroplating, ensuring that the lower electrode 102 at least covers the bottom and sidewalls of the trench, thereby providing a stable lower electrode structure for the trench capacitor. After the lower electrode 102 is formed, a dielectric material is deposited on its surface to form a dielectric layer 103. The dielectric layer 103 is preferably a high dielectric constant material, such as HfO, ZrO, or AlxOy, and is formed by atomic layer deposition (ALD) or other suitable thin film deposition processes to obtain good thickness uniformity and dielectric properties.

[0029] Next, a metal material is deposited on the surface of the dielectric layer 103 to fill multiple trenches, forming the upper electrode 104. Through the above steps, the lower electrode 102, the dielectric layer 103, and the upper electrode 104 form multiple trench capacitor structures within the trenches, thereby achieving a high capacitance density within a limited area. Subsequently, a first dielectric layer 105 and a second dielectric layer 106 are sequentially deposited on the surface of the upper electrode 104. The first dielectric layer 105 and the second dielectric layer 106 can be insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, used for isolation and protection during the subsequent via formation process.

[0030] After the dielectric layer deposition is completed, selective etching is performed on a portion of the area above the trenches to remove the upper electrode 104, the first dielectric layer 105, and the second dielectric layer 106 at the corresponding locations. This partially exposes or removes the upper electrode 104 in the trench area, thereby providing structural conditions for the subsequent formation of the via conductive structure. Subsequently, an insulating protective layer 107 is deposited on the first surface of the substrate 100. The insulating protective layer 107 at least covers the sidewalls of the upper electrode 104 to prevent damage to the sidewalls of the upper electrode during subsequent etching or filling processes, while also suppressing the risk of leakage between adjacent structures.

[0031] Next, the trenches lacking the upper electrode 104, the first dielectric layer 105, and the second dielectric layer 106, as well as the areas between adjacent trenches, are etched to remove the corresponding insulating protective layer 107, lower electrode 102, and dielectric layer 103, thereby forming a structural separation region on the first surface of the substrate 100. Subsequently, an interlayer dielectric material 108 is deposited integrally on the first surface of the substrate 100 to cover the aforementioned structure and achieve surface planarization, providing a flat process foundation for subsequent interconnection processes.

[0032] After the interlayer dielectric material 108 is formed, vias are formed at predetermined locations using photolithography and etching processes, connecting the vias to the lower electrode 102 or the upper electrode 104 of the trench capacitor. Since the vias leading to the lower electrode 102 are located inside or near the trench, the etching depth of the vias is significantly reduced compared to vias that directly penetrate the multilayer dielectric and contact the bottom metal traces in the prior art. Subsequently, conductive material is filled into the vias to form a first via conductive structure 109A and a second via conductive structure 109B, respectively. The first via conductive structure 109A is electrically connected to the lower electrode 102 of the trench capacitor, and the second via conductive structure 109B is electrically connected to the upper electrode 104 of the trench capacitor.

[0033] Finally, a first metal trace 110 is formed on the first surface of the substrate 100, and the first metal trace 110 is electrically connected to the lower electrode 102 or the upper electrode 104 of the trench capacitor through the first through-hole conductive structure 109A or the second through-hole conductive structure 109B, thereby completing the fabrication of the overall semiconductor structure.

[0034] In this embodiment, since the first via conductive structure 109A that needs to connect the bottom second metal trace 101 is not directly etched to the second surface of the substrate 100, but is electrically connected by means of the lower electrode 102 of the trench capacitor, the termination position of the via etching is located inside or above the trench capacitor structure, thereby effectively reducing the height difference of the via etching. Compared with the prior art, which requires the formation of high aspect ratio vias to directly connect the upper and lower metal traces, this embodiment significantly reduces the aspect ratio requirement of via etching, reduces the etching difficulty and the risk of sidewall damage, and is conducive to improving etching uniformity and process window.

[0035] Furthermore, due to the reduced etching depth of the vias, the filling of conductive material within the vias is easier, effectively reducing the probability of metal-filled voids and poor contact, thereby improving the electrical connection reliability of the interconnect structure and the device yield. Simultaneously, by introducing the via conductive structure design during the trench capacitor formation stage, this embodiment eliminates the need for an additional deep via etching process, exhibiting good process compatibility, which helps reduce overall manufacturing costs and improve process stability.

[0036] In this embodiment, the first metal trace 110, the second metal trace 101, the upper electrode 104, the lower electrode 102, and the first through-hole conductive structure 109A and the second through-hole conductive structure 109B can typically be one or more of metals such as Au, Cu, Ag, and Al; the dielectric layer 103 is preferably a high dielectric constant material, such as one or more of HfO, ZrO, and AlxOy; the interlayer dielectric material 108 is typically an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. The selection of the above materials can be adjusted according to the specific device requirements and process conditions, and does not constitute a limitation on the scope of protection of this invention. Example 2

[0037] like Figure 11-19 As shown, this embodiment provides a method for fabricating a semiconductor structure. Based on Embodiment 1, this embodiment differentiates the trench structure of the trench capacitor by forming trenches of varying depths to construct a trench capacitor structure combining high and low trenches. This ensures capacitor performance while further enhancing the layout flexibility of the underlying metal traces and saving wiring space.

[0038] First, a substrate 100 is provided, which may be a silicon substrate, an SOI substrate, or a semiconductor substrate containing an epitaxial layer, with necessary active devices or underlying interconnect structures already formed therein. A plurality of second metal traces 101 are pre-formed on the second surface of the substrate 100. These second metal traces 101 serve as underlying interconnect metals for realizing electrical connections between devices or between different interconnect layers.

[0039] Subsequently, multiple trenches are formed on the first surface of the substrate 100 using photolithography and etching processes. Unlike Embodiment 1, the trenches formed in this embodiment include at least two types: first trenches and second trenches. The first trenches have a greater etching depth, extending vertically and etching to a position close to or in contact with the second metal trace 101. The second trenches have a relatively smaller etching depth; their bottom is not etched to the height of the second metal trace 101, but rather maintains a certain distance from the second metal trace 101 in the vertical direction. Through this method, trench structures of varying heights are formed on the first surface of the substrate 100, providing a foundation for the subsequent construction of high and low trench MIM capacitors.

[0040] After trench etching is completed, a metal material is uniformly deposited in the trenches of the first and second trenches on the first side of the substrate 100 to form a lower electrode plate 102. The lower electrode plate 102 can be formed by physical vapor deposition, chemical vapor deposition, or electroplating processes, so that the metal material covers the bottom and sidewalls of each trench. For the first trench, the lower electrode plate 102 can be electrically connected to the second metal trace 101; while for the second trench, since the trench depth is shallower, the bottom of the lower electrode plate 102 is still isolated from the second metal trace 101 by the substrate material or dielectric layer, thus forming a lower electrode plate that does not directly contact the bottom metal trace in structure.

[0041] After the lower electrode 102 is formed, a dielectric material is deposited on its surface to form a dielectric layer 103. The dielectric layer 103 is preferably a high dielectric constant material, such as HfO, ZrO, AlxOy, etc., and can be formed by atomic layer deposition to ensure good coverage and dielectric consistency in trenches of different depths. Subsequently, a metallic material is deposited on the surface of the dielectric layer 103 to fill each trench, forming the upper electrode 104. Thus, the lower electrode 102, dielectric layer 103, and upper electrode 104 together constitute multiple trench capacitor structures in trenches of different depths.

[0042] Next, a first dielectric layer 105 and a second dielectric layer 106 are sequentially deposited on the surface of the upper electrode 104. The first dielectric layer 105 and the second dielectric layer 106 can be made of silicon oxide, silicon nitride, or silicon oxynitride to achieve insulation and isolation at the top of the trench capacitor and protection for subsequent processes. After the dielectric layer deposition is completed, selective etching is performed on a portion of the area above the trench to remove the upper electrode 104, the first dielectric layer 105, and the second dielectric layer 106 at the corresponding locations, thereby exposing or removing a portion of the upper electrode structure within the trench.

[0043] Subsequently, an insulating protective layer 107 is deposited on the first surface of the substrate 100. The insulating protective layer 107 at least covers the sidewall of the upper electrode 104, thereby effectively protecting the sidewall of the upper electrode during subsequent etching and suppressing electrical crosstalk between adjacent trench capacitors. Next, the trench regions without the upper electrode 104, the first dielectric layer 105, and the second dielectric layer 106, as well as adjacent regions, are etched to remove the insulating protective layer 107, the lower electrode 102, and the dielectric layer 103 at the corresponding locations, in order to form the necessary structural isolation regions.

[0044] After completing the above structural processing, an interlayer dielectric material 108 is deposited integrally on the first surface of the substrate 100 to cover all trench capacitor structures and achieve surface planarization, providing a stable process platform for subsequent interconnection processes. Subsequently, vias are formed at predetermined positions through photolithography and etching processes, connecting the vias to the lower electrode 102 or upper electrode 104 of different trench capacitors, and conductive material is filled into the vias to form the first via conductive structure 109A and the second via conductive structure 109B.

[0045] Specifically, for the trench capacitor formed by the first trench, the first through-hole conductive structure 109A can be further electrically connected to the second metal trace 101 through the lower electrode 102; while for the trench capacitor formed by the second trench, its lower electrode 102 does not directly contact the second metal trace 101, and the first through-hole conductive structure 109A is only connected to the corresponding lower electrode 102, thereby achieving independent arrangement of the capacitor structure. Finally, a first metal trace 110 is formed on the first surface of the substrate 100, and the first metal trace 110 is electrically connected to the corresponding upper or lower electrode of the trench capacitor through the through-hole conductive structure, thereby completing the fabrication of the overall semiconductor structure.

[0046] In this embodiment, by forming trench structures of varying depths on the same substrate, the lower plates of some trench capacitors no longer directly occupy or contact the bottom second metal trace 101, thereby freeing up more metal layer space below the MIM capacitors for wiring. Compared to the scheme in Embodiment 1 where all trenches are etched to the bottom metal layer, this embodiment allows for flexible configuration of the trench capacitor height distribution, effectively alleviating wiring congestion on the underlying metal layer while meeting capacitance density requirements, and improving the overall interconnect design freedom.

[0047] Furthermore, the introduction of high and low trench capacitor structures allows for differentiated design of trench capacitor layouts based on the needs of different circuit regions, avoiding unnecessary deep trench etching, thereby reducing process complexity and further improving device integration and manufacturing yield.

[0048] In this embodiment, the first metal trace 110, the second metal trace 101, the upper electrode 104, the lower electrode 102, and the through-hole conductive structures 109A and 109B can be one or more metals such as Au, Cu, Ag, and Al; the dielectric layer 103 can be a high dielectric constant material such as HfO, ZrO, or AlxOy; and the interlayer dielectric material 108 can be an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. The above materials and process parameters can be adjusted according to specific application requirements and do not constitute a limitation on the scope of protection of this invention. Example 3

[0049] like Figure 20 As shown, this embodiment further expands upon the process flow and overall structure of Embodiment 2: while simultaneously preparing the trench lower electrode plate, dielectric layer and upper electrode plate with the trench capacitor, a planar capacitor structure is reserved and formed at a position on the substrate 100 where no trench is etched. Thus, a planar capacitor, a trench capacitor and a through-hole conductive structure for interconnection with the lower metal layer are obtained in one process, realizing the integrated fabrication of multiple capacitors and through-hole structures without adding any additional processes.

[0050] Specifically, the differences described in this embodiment are as follows: First, when depositing metal on the first surface of the substrate 100 to form the lower electrode 102, in addition to forming the lower electrode of the trench capacitor within the trench, the lower electrode of the planar capacitor (hereinafter referred to as "planar lower electrode") is simultaneously deposited and formed in the surface area of ​​the unetched trench according to the planar capacitor layout. Subsequently, a dielectric layer 103 is uniformly deposited on the surface of all the lower electrodes. The dielectric layer material can be a high dielectric constant material to increase the capacitance density. Metal is uniformly deposited and filled on the dielectric layer to form the upper electrode 104, including the upper electrode in the trench and the upper electrode in the planar area (hereinafter referred to as "planar upper electrode"). This step is completed synchronously with the trench capacitor construction step of Embodiment 2, without introducing additional deposition cycles or independent processing steps.

[0051] After the dielectric and upper electrode are deposited, the upper electrode 104 and the dielectric layer it covers are selectively removed and morphologically modified according to design requirements: in the corresponding area of ​​the planar capacitor, the complete planar upper electrode can be retained to achieve the required capacitor area; where it is necessary to leave a passage for the lower electrode to connect to the via, the upper electrode 104 (whether located at the top of the trench or in the planar area) is partially removed or windowed, so that the upper electrode will not block the subsequent etching to form the via connecting to the lower electrode. The removal action can be completed in one step by photolithography and etching, which has the advantage of being consistent with the process of opening windows in the trench in Example 2, avoiding the need for additional steps.

[0052] Subsequently, an insulating protective layer 107 is deposited over the entire first surface, covering at least the sidewalls of the upper electrode and simultaneously the peripheral area of ​​the planar upper electrode, thereby providing protection, isolation, and short-circuit protection during subsequent via etching and filling processes. For planar capacitors, to prevent short circuits between the planar upper electrode and vias or adjacent structures, specific protective or spacer structures can be retained on the insulating layer, and via locations can be reserved where necessary.

[0053] Next, after forming and planarizing the interlayer dielectric material 108, vias are formed at predetermined locations through photolithography and etching. These vias include those connecting the upper and lower plates of the trench capacitor, as well as those connecting the upper and lower plates of the planar capacitor. The etching depth and termination surface of the vias can be controlled by masking and etching stop, ensuring that vias connecting the lower plate terminate near or at the top of the lower plate, thereby significantly reducing the height difference between the subsequent top-layer vias and the lower plate. Subsequently, a barrier layer / seed layer is deposited within the vias and filled with conductive material, forming a via conductive structure electrically connected to the lower and upper plates of the trench capacitor and the lower and upper plates of the planar capacitor (i.e., the via conductive structure can connect to the four types of electrodes respectively).

[0054] In other embodiments, the key points and optional variations of this embodiment include, but are not limited to: 1) The geometric dimensions of the planar capacitor and the trench capacitor are designed separately according to circuit requirements, and the photolithography definition can be completed within the same mask group, which facilitates the printing process. Figure 1 1) Integration; 2) For areas where it is desired to save space for lower layer wiring, more capacitors can be arranged in the form of planar capacitors to avoid deep trenches occupying the lower layer metal channels; 3) The removal position of the upper plate should be aligned with the subsequent via landing point, and the removal depth and range need to take into account both capacitor performance and via accessibility; 4) The thickness and porosity of the insulating protective layer need to be controlled to provide good sidewall protection and avoid bubble formation during via etching and metal filling; 5) Metal filling in vias can be achieved by electroplating or chemical deposition combined with chemical mechanical polishing to achieve a flat top surface.

[0055] This embodiment integrates planar capacitors, trench capacitors, and via conductive structures leading to the lower metal layer into a single process without adding independent steps, significantly improving process efficiency and interconnect layout flexibility. By simultaneously forming the lower electrode / dielectric layer / upper electrode in a planar region and partially removing the upper electrode to avoid vias, this embodiment further reduces the height difference between the vias and the lower electrode, lowering the technical difficulty of high aspect ratio etching. Simultaneously, the unified deposition, etching, and filling process improves the consistency of metal filling, reduces voids, and enhances the consistency of chemical mechanical polishing, thereby improving interconnect reliability and device yield. This embodiment is particularly suitable for chip design scenarios requiring both high-density capacitors and flexible wiring space with a limited number of interconnect layers.

[0056] In this embodiment, the various metal electrodes and interconnects include, but are not limited to, gold, copper, silver, aluminum, etc., the dielectric layer can be made of high dielectric constant materials such as hafnium oxide, zirconium oxide, aluminum oxide, etc., and the interlayer dielectric can be made of silicon dioxide, silicon oxynitride, or silicon nitride, etc. Example 4

[0057] like Figure 21 As shown in Figure 29, this embodiment also provides a method for fabricating a semiconductor structure. The difference from Embodiment 1 is that this embodiment includes at least one type of trench with smaller critical dimensions, preferably a trench structure with a relatively narrow trench opening width; the remaining structures are essentially the same as in Embodiment 1.

[0058] Specifically, a substrate 100 is first provided. The structure, material composition, and pre-formed active devices or interconnect structures on the first and second surfaces of the substrate 100 are the same as in Embodiment 1, and will not be repeated here. Subsequently, multiple trenches are formed on the first surface of the substrate 100 by photolithography and etching processes, wherein at least some of the trenches have relatively small critical dimensions for constructing trench capacitor structures; at the same time, a second metal trace 101 is formed on the second surface of the substrate 100 for realizing bottom-layer interconnects.

[0059] In this embodiment, when metal material is deposited in the trench to form the lower electrode 102, due to the narrow opening size of the trench, the lower electrode metal material can quickly converge inside the trench and directly fill the entire trench space during the metal material deposition process, making the trench a solid metal-filled structure after the lower electrode 102 is formed. Compared with the case in Embodiment 1 where the lower electrode mainly covers the bottom and sidewalls of the trench, the lower electrode 102 in this embodiment also serves as a trench filling structure, and its upper surface is basically flush or nearly flush with the first surface of the substrate 100.

[0060] After the lower electrode 102 is formed, a dielectric material is deposited on its surface to form a dielectric layer 103. Since the trench is already filled with the lower electrode metal material, the dielectric layer 103 continuously covers the surface of the first surface of the substrate 100 and the upper surface of the lower electrode 102, without entering the trench. Subsequently, a metal material is deposited on the surface of the dielectric layer 103 to form an upper electrode 104. In this embodiment, the upper electrode 104 does not fill into the trench, but forms a continuous metal film structure parallel to the first surface of the substrate 100, thereby forming a planar capacitor structure with the lower electrode 102 through the dielectric layer 103.

[0061] After the formation of the upper electrode plate 104 is completed, the subsequent process flow is basically the same as in Example 1. Specifically, it includes: forming a first dielectric layer 105 and a second dielectric layer 106 sequentially on the surface of the upper electrode plate 104; selectively etching a predetermined area to expose or remove the upper electrode plate 104 at the corresponding position; depositing an insulating protective layer 107 on the first surface of the substrate 100; etching a portion of the area to form a structural separation region; and then depositing an interlayer dielectric material 108 to achieve surface coverage and planarization.

[0062] After the interlayer dielectric material 108 is formed, through-holes are formed by photolithography and etching processes, connecting the through-holes to the lower electrode 102 or the upper electrode 104 respectively. Conductive material is filled into the through-holes to form a first through-hole conductive structure 109A and a second through-hole conductive structure 109B. Finally, a first metal trace 110 is formed on the first surface of the substrate 100, which is electrically connected to the lower electrode 102 or the upper electrode 104 through the through-hole conductive structures, thereby completing the fabrication of the overall semiconductor structure.

[0063] In this embodiment, by reducing the critical dimensions of the trench, the lower electrode metal material can directly fill the trench during the deposition process, thereby changing the spatial distribution of the upper and lower electrodes in the trench capacitor, allowing the upper electrode 104 to be formed parallel to the substrate surface. This structure not only reduces the process complexity caused by the stacking of multiple thin films inside the trench, but also further reduces the height difference in subsequent via etching, which is beneficial to improving etching consistency and metal filling reliability. In addition, this embodiment does not require the introduction of additional process steps; the change in capacitor structure can be achieved simply by adjusting the trench size, exhibiting good process compatibility and design flexibility.

[0064] This embodiment, by reducing the etching drop of the via conductive structure, further shrinks the critical size of the via. This not only helps reduce the layout area occupied by a single via, but also allows for more interconnect structures and functional units to be accommodated within the same chip area, significantly improving the overall wiring density and structural integration. Especially for devices such as image sensors that are highly sensitive to pixel size and array density, shrinking the via size can effectively free up layout space in the pixel area, providing greater design margin for the arrangement of pixel circuits, storage capacitors, or other functional structures. This allows for higher resolution, more complex circuit integration, or better device performance without increasing the chip area.

[0065] This invention achieves a process layout that allows the top-level vias, which would otherwise be deeply etched at the back end, to be "pre-embedded" or partially placed within the capacitor structure by simultaneously designing and fabricating a matching via conductive structure (and, when needed, forming the upper and lower electrode structures of a planar capacitor) during the formation stage of the trench capacitor. Specifically, the process includes: simultaneously constructing the lower electrode, dielectric layer, and upper electrode of the trench in one etching / deposition cycle; simultaneously depositing the upper and lower electrodes of the planar capacitor in a planar region without trenches; reserving via positions by partially removing the upper electrode or forming via positions on the interlayer dielectric, so that subsequent top-level vias only need to penetrate a thin capping layer to connect with the embedded electrodes; and finally, filling and planarizing the vias with metal to complete the interconnection.

[0066] The resulting technical benefits are significant: First, it greatly reduces the etching depth and aspect ratio requirements of top-layer vias, minimizing sidewall damage, uneven etching, and micro-residue risks during the etching process. Second, it improves the consistency of via metal filling, reduces void / defect rates, and enhances chemical mechanical polishing planarization, thereby improving interconnect reliability and overall yield. Third, it allows for a smaller via critical size and saves layout area, increasing the integration density of pixel arrays or other high-density circuits. Fourth, it expands the flexibility of layout and routing through the parallel arrangement of high and low trenches and / or planar capacitors, freeing up lower-layer metal trace resources. Fifth, this solution is compatible with existing manufacturing processes without significantly increasing independent processes, facilitating simultaneous cost and performance optimization on existing process platforms. These combined effects make this invention particularly suitable for manufacturing high-density semiconductor devices with stringent requirements for area, interconnectivity, and reliability.

[0067] The materials and parameters described in the above embodiments can be adjusted according to process nodes and device design requirements, but do not constitute a limitation on the scope of protection of this invention. It should be understood that the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship. "Multiple" in the embodiments of this application refers to two or more. The descriptions of "first," "second," etc., appearing in the embodiments of this application are only for illustration and to distinguish the described objects; they have no order and do not indicate a special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0068] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, A substrate is provided, and a plurality of trenches are formed on a first surface of the substrate; Trench capacitors are formed in the plurality of trenches, and first through-hole conductive structures are formed in at least a portion of the trenches; The first through-hole conductive structure is electrically connected to the lower electrode plate in the trench below it, and is electrically connected to the metal trace located on the second side of the substrate through the lower electrode plate.

2. The method as described in claim 1, characterized in that, The steps for forming the trench capacitor include: Conductive material is deposited in the trench to form the lower electrode plate; A dielectric layer is deposited on the lower electrode plate; A conductive material is deposited on the dielectric layer to form the upper electrode.

3. The method as described in claim 1, characterized in that, A second through-hole conductive structure is formed on at least a portion of the trench capacitor and electrically connected to the upper plate of the trench capacitor, wherein the second through-hole conductive structure and the first through-hole conductive structure are formed simultaneously.

4. The method as described in claim 1, characterized in that, At least a portion of the lower electrode of the trench capacitor is electrically connected to the metal trace on the second side of the substrate.

5. The method as described in claim 1, characterized in that, While forming the trench capacitor, one or more planar capacitors are formed on the substrate, and at least part of the second through-hole conductive structure is electrically connected to the upper plate of the planar capacitor.

6. The method as described in claim 1, characterized in that, An insulating layer is formed on the upper electrode of the trench capacitor; Before forming the first through-hole conductive structure, a portion of the upper electrode plate below the first through-hole conductive structure is removed.

7. The method as described in claim 3, characterized in that, The upper ends of the first through-hole conductive structure and the second through-hole conductive structure are electrically connected to the metal trace located on the first surface of the substrate.

8. The method as described in claim 1, characterized in that, At least a portion of the lower plate of the trench capacitor does not contact the metal trace located on the second side of the substrate.

9. The method as described in claim 6, characterized in that, A protective layer is formed on the insulating layer, the protective layer covering the insulating layer and the sidewall of the upper electrode plate.

10. The method as described in claim 9, characterized in that, After the protective layer is formed, an interlayer insulating layer is formed on the surface of the substrate; Then, through-holes are formed in the interlayer insulating layer by etching. The etching of the through-hole stops at the surface of the capacitor's plates.

11. A semiconductor structure prepared by the method according to any one of claims 1-10, characterized in that, The semiconductor structure includes a substrate, a first through-hole conductive structure, and a second through-hole conductive structure. The substrate includes a first metal trace located on a first surface and a second metal trace located on a second surface. A plurality of capacitor structures are present near the second surface of the substrate, the capacitor structures including trench capacitors and / or planar capacitors; The first metal trace is electrically connected to the second metal trace through the first through-hole conductive structure and the lower electrode of part of the capacitor structure.

Images