A method of manufacturing a metal gate device structure and a metal gate device structure

Abstract

This application discloses a method for manufacturing a metal gate device structure and a metal gate device structure, comprising: forming a fin on a substrate; sequentially forming a gate dielectric layer and a cap layer on the surface of the fin; forming a sacrificial and buffer layer on the surface of the cap layer, and then performing heat treatment to allow atoms in the sacrificial and buffer layer material to diffuse into the cap layer material to improve the diffusion blocking capability of the cap layer, and then removing the sacrificial and buffer layer; sequentially forming a work function layer and a gate electrode layer on the surface of the cap layer after removing the sacrificial and buffer layer, wherein the work function layer includes multiple work function material layers stacked sequentially from the inside out; wherein the surfaces of one or more inner work function material layers formed before the outermost work function material layer are respectively oxidized to smooth the rough surface of the inner work function material layers and suppress interface diffusion, thereby improving the stability of the threshold voltage.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and in particular to a method for manufacturing a metal gate device structure and a metal gate device structure manufactured using this method. Background Technology

[0002] In the gate-on voltage regulation steps of different device regions using high-k dielectric metal gate (HKMG) technology, different voltage controls (customized threshold voltages) are achieved by depositing metal work function materials of varying thicknesses (such as TaN, TiN, TiAl, etc.). Therefore, work function layers of different thicknesses exist in different device regions. These work function layers require multiple thin-film depositions. At advanced nodes, due to the extremely thin thickness of each work function material layer (approximately 0.5 nm to 2 nm), poor surface roughness (uneven surface) often results in the deposited material. Poor surface roughness of the preceding layer not only directly affects the growth quality of the subsequent layer but also, the superposition of multiple work function materials with certain roughness affects the final threshold voltage value of the metal gate device, leading to uncontrollable threshold voltage fluctuations and insufficient gate-on voltage stability in different device regions. Furthermore, the diffusion blocking capability of the TiN cap layer beneath the work function layer becomes increasingly insufficient due to its thinness, impacting device reliability. Therefore, it is necessary to investigate a process method that can significantly improve the above problems. Summary of the Invention

[0003] The purpose of this application is to overcome the above-mentioned problems existing in the prior art and to provide a method for manufacturing a metal gate device structure and a metal gate device structure.

[0004] To achieve the above objectives, the technical solution of this application is as follows:

[0005] According to a first aspect of this application, embodiments of this application provide a method for manufacturing a metal gate device structure, comprising:

[0006] Provide substrate;

[0007] Fins are formed on the substrate;

[0008] A gate dielectric layer and a cap layer are sequentially formed on the surface of the fin.

[0009] A sacrificial and buffer layer is formed on the surface of the cap layer, and then heat treatment is performed to allow atoms in the sacrificial and buffer layer material to diffuse into the cap layer material to improve the diffusion barrier capability of the cap layer. The sacrificial and buffer layer is then removed.

[0010] On the surface of the cap layer after removing the sacrificial and buffer layers, a work function layer and a gate electrode layer are sequentially formed. The work function layer comprises multiple work function material layers stacked sequentially from the inside out.

[0011] Specifically, the surfaces of one or more inner work function material layers formed before the outermost work function material layer are all subjected to oxidation treatment to smooth the rough surfaces of the inner work function material layers and suppress interface diffusion.

[0012] In some embodiments, the cap layer includes a TiN layer, the sacrificial and buffer layer includes an amorphous silicon layer, and the heat treatment includes peak annealing. By performing the heat treatment, silicon atoms in the amorphous silicon layer material preferentially react with diffused oxygen atoms to block oxygen atoms from diffusing into the channel. The amorphous silicon layer material is also used to fill and smooth the rough surface of the TiN layer, forming a uniform interface. This allows silicon atoms in the amorphous silicon layer material to form a consistent interface reaction when diffusing into the TiN layer material and to enter the lattice gaps or grain boundaries of TiN, thereby improving the diffusion blocking capability of the TiN layer when it acts as the cap layer.

[0013] In some embodiments, silicon atoms in the amorphous silicon layer material are diffused into the TiN layer material and reacted to form a silicon-containing compound layer as a first auxiliary barrier layer to further improve the diffusion barrier capability of the cap layer.

[0014] In some embodiments, prior to performing the heat treatment, the method further includes: cleaning the surface of the amorphous silicon layer with hot deionized water to passivate the surface of the amorphous silicon layer.

[0015] In some embodiments, the sacrificial and buffer layers are removed sequentially using diluted hydrofluoric acid and NH4OH, and then dried using hot isopropanol.

[0016] In some embodiments, the heat treatment is performed at a temperature of 850°C to 950°C.

[0017] In some embodiments, the thickness of the cap layer is 10 Å to 20 Å.

[0018] In some embodiments, the thickness of the sacrificial and buffer layer is 40 Å to 60 Å.

[0019] In some embodiments, the oxidation treatment is performed using oxygen free radicals to preferentially oxidize the protrusions on the rough surface of the inner work function material layer, thereby achieving chemical mechanical smoothing of the surface and forming a dense oxide layer on the surface of the inner work function material layer as a second auxiliary barrier layer to suppress the interdiffusion of oxygen and / or nitrogen between different work function material layers and stabilize the interfacial stoichiometry. The oxygen free radicals are obtained by exciting oxygen gas with helium metastable particles and filtering out charged particles therein, and the helium metastable particles are obtained by exciting helium gas and filtering out charged particles therein.

[0020] In some embodiments, during the oxidation process, the helium flow rate is 1000 sccm to 9000 sccm, the oxygen flow rate: helium flow rate = 1:1 to 10:1, the temperature is 50℃ to 180℃, the source power is 100W to 1000W, the pressure is 100mTorr to 1000mTorr, the time is 30s to 300s, and the ion filter is turned on while the bias power is turned off.

[0021] In some embodiments, the one or more inner work function material layers include a first work function material layer and n second work function material layers sequentially formed outside the first work function material layer, where n is a natural number including zero.

[0022] In some embodiments, the first work function material layer includes a TaN layer.

[0023] In some embodiments, the second work function material layer includes a TiN layer.

[0024] In some embodiments, the outermost work function material layer includes a TiAl layer.

[0025] In some embodiments, the thickness of the first work function material layer is 8 Å to 15 Å.

[0026] In some embodiments, the thickness of the second work function material layer is 5 Å to 15 Å.

[0027] In some embodiments, the thickness of the outermost work function material layer is 20 Å to 60 Å.

[0028] According to a second aspect of this application, embodiments of this application also provide a metal gate device structure, which is obtained using the metal gate device structure manufacturing method provided in any of the embodiments of the first aspect above.

[0029] The embodiments of this application may have, or at least have, the following advantages:

[0030] (1) By forming a work function layer on the surface of the cap layer, the work function layer includes multiple work function material layers stacked sequentially from the inside out. The surfaces of one or more inner work function material layers formed before the outermost work function material layer are oxidized. The oxidation treatment can effectively passivate the dangling bonds and active sites on the surface of the inner work function material layer and reduce the surface energy inhomogeneity. This allows for the preferential oxidation of the protrusions on the rough surface of the inner work function material layer (protrusions have higher surface energy and more dangling bonds than depressions, and are therefore more sensitive to oxidation). The oxidation process generates slight atomic migrations or promotes the relaxation of unstable atoms at grain boundaries, effectively "filling" or "smoothing" the microscopic undulations of the original surface, making the surface smoother. This achieves atomic-level chemimechanical smoothing of the rough surface of the inner work function material layer, reducing the micro-roughness (RMS). Consequently, it reduces threshold voltage fluctuations and improves the stability of threshold voltage regulation. Furthermore, the dense oxide layer formed on the surface of the inner work function material layer by oxidation suppresses the interdiffusion of oxygen and / or nitrogen between different work function material layers, stabilizing the interfacial stoichiometry. Therefore, by reducing the interfacial state density and stabilizing the metal work function, the electrical pathway ultimately improves threshold voltage stability.

[0031] (2) By using helium metastable particles to generate low-energy oxygen free radicals, a surface oxidation treatment with lower energy and almost no damage can be achieved. This effectively avoids the problem of needing to increase the initial value of the film thickness and causing a large loss of the film by using surface treatments such as acid washing with excessive intensity. It can also simplify the manufacturing process.

[0032] (3) By forming an amorphous silicon layer on the surface of the cap layer (TiN layer) as a sacrificial layer and buffer layer during subsequent heat treatment, the amorphous silicon layer can be used as an oxygen "getter layer" to preferentially react with diffused oxygen to generate SiO. x To prevent oxygen atoms from diffusing into the channel and thus avoid performance degradation, the amorphous silicon layer can also fill the microscopic irregularities on the TiN layer surface, forming a more uniform interface that facilitates consistent interface reactions during subsequent heat treatment. Specifically, high-temperature heat treatment (peak annealing) allows the amorphous silicon layer to react with the TiN layer, causing silicon atoms to diffuse into the TiN lattice interstices or grain boundaries. This physically blocks the rapid diffusion of impurities such as oxygen and hydrogen along the grain boundaries, significantly improving the diffusion barrier capability of the TiN layer. In some regions, stable silicon-rich TiSiN compound layers or more stable nitride phases may also form, which themselves possess excellent barrier properties. Simultaneously, high-temperature heat treatment can passivate interface traps, which is crucial for improving positive and negative bias temperature instability and stabilizing the interface stoichiometry.

[0033] (4) By cleaning the surface of the amorphous silicon layer with hot deionized water before performing heat treatment, the -OH in the water molecules will react with the dangling bonds on the surface of the amorphous silicon to form a Si-OH (silicon hydroxyl) passivation layer, which can significantly reduce the surface energy and inhibit the surface migration of silicon atoms at low temperature, thereby ensuring the morphological stability and uniformity of the amorphous silicon layer before annealing.

[0034] (5) By using diluted hydrofluoric acid (DHF) and NH4OH in sequence to remove the sacrificial and buffer layers, the amorphous silicon material of the main body can be removed quickly and isotropically using DHF, while avoiding damage to the TiN cap layer below. Then, NH4OH is used to finely remove the remaining small amount of amorphous silicon material. The property of NH4OH to form soluble complexes with many metal ions can be used to effectively remove metal contaminants adsorbed on the surface of the TiN cap layer. The high chemical activity of hot isopropanol can be used to further clean and dry the surface of the TiN cap layer, effectively removing organic residues and particle adsorption, achieving perfect dehydration and drying, and providing an activated TiN cap layer surface, which is conducive to the high-quality deposition of subsequent film layers.

[0035] In summary, the embodiments of this application can effectively improve the voltage stability of the metal work function and the reliability of the device.

[0036] Other advantages of this application will be described in the following detailed description. Attached Figure Description

[0037] Figure 1 This is a flowchart illustrating a preferred embodiment of a metal gate device structure manufacturing method provided in this application.

[0038] Figure 2 This is a schematic diagram of a fin formed on a substrate, provided as a preferred embodiment of this application.

[0039] Figure 3 This is a schematic diagram of a preferred embodiment of the present application after a gate dielectric layer and a cap layer are sequentially formed on the fin.

[0040] Figure 4 This is a schematic diagram of a preferred embodiment of the present application after a sacrificial and buffer layer has been formed on the cap layer.

[0041] Figure 5 This is a schematic diagram of a preferred embodiment of the present application, showing a first work function material layer, an outermost work function material layer, and a gate electrode layer sequentially formed on a cap layer after the removal of the sacrificial and buffer layers.

[0042] Figure 6This is a schematic diagram of a preferred embodiment of the present application, showing a first work function material layer, a second work function material layer, an outermost work function material layer, and a gate electrode layer sequentially formed on a cap layer after the removal of the sacrificial and buffer layers.

[0043] Figure 7 This is a schematic diagram of a preferred embodiment of the present application, showing a first work function material layer, two second work function material layers, an outermost work function material layer, and a gate electrode layer sequentially formed on a cap layer after the removal of the sacrificial and buffer layers.

[0044] Figure 8 This is a schematic diagram of a preferred embodiment of the present application, showing a first work function material layer, three second work function material layers, an outermost work function material layer, and a gate electrode layer sequentially formed on a cap layer after the removal of the sacrificial and buffer layers.

[0045] In the figure: 10. Substrate; 11. Fin; 12. Isolation structure; 13. Gate dielectric layer; 14. Cap layer; 15. Sacrificial and buffer layer; 16. First work function material layer; 17. Outermost work function material layer; 18. Gate electrode layer; 19. Fifth work function material layer; 20. Fourth work function material layer; 21. Third work function material layer. Detailed Implementation

[0046] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0047] refer to Figure 1 This application provides a method for manufacturing a metal gate device structure, which may include the following steps in sequence:

[0048] Step S11: Provide a substrate.

[0049] refer to Figure 2 In some embodiments, substrate 10 is used to fabricate a metal gate device structure on substrate 10. Substrate 10 may include any suitable type of semiconductor substrate and material. For example, substrate 10 may include a silicon (Si) substrate, a germanium (Ge) substrate, or a germanium-silicon (SiGe) substrate, or a III / V compound semiconductor substrate, such as a gallium arsenide (GaAs) substrate, an indium gallium arsenide (InGaAs) substrate, or similar materials.

[0050] In some embodiments, substrate 10 may be a substrate wafer.

[0051] Step S12: Form fins on the substrate.

[0052] refer to Figure 2In some embodiments, a patterning process may be used to form protruding fins 11 on the surface of the substrate 10, for further forming a metal gate structure on the surface of the fins 11. An isolation structure 12 is formed on the substrate 10 surrounding the fins 11, the isolation structure 12 defining an active region on the substrate 10 and isolating the device region where the fins 11 are located.

[0053] Step S13: A gate dielectric layer and a cap layer are sequentially formed on the surface of the fin.

[0054] refer to Figure 3 In some embodiments, a deposition process may be used to sequentially form a gate dielectric layer 13 and a cap layer 14 on the surface of the fin 11.

[0055] In some embodiments, the material of the gate dielectric layer 13 includes a high dielectric constant material, such as HfO2.

[0056] In some embodiments, the material of the cap layer 14 includes TiN, etc.

[0057] In some embodiments, the gate dielectric layer 13 includes an HfO2 layer.

[0058] In some embodiments, the cap layer 14 includes a TiN layer.

[0059] In some embodiments, the thickness of the cap layer 14 is 10 Å to 20 Å. For example, the thickness of the cap layer 14 may be 10 Å, 11 Å, 12 Å, 13 Å, 14 Å, 15 Å, 16 Å, 17 Å, 18 Å, 19 Å or 20 Å, or any value between any two of the aforementioned thickness values.

[0060] Step S14: A sacrificial and buffer layer is formed on the surface of the cap layer, followed by heat treatment, and then the sacrificial and buffer layer is removed.

[0061] refer to Figure 4 In some embodiments, a deposition process may be used to form a sacrificial and buffer layer 15 on the surface of the cap layer 14, followed by heat treatment to allow atoms in the sacrificial and buffer layer 15 to diffuse into the cap layer 14 material, thereby improving the diffusion barrier capability of the cap layer 14.

[0062] In some embodiments, the material of the sacrificial and buffer layer 15 includes amorphous silicon.

[0063] In some embodiments, the sacrificial and buffer layer 15 includes an amorphous silicon layer.

[0064] In some embodiments, the thickness of the sacrificial and buffer layer 15 is 40 Å to 60 Å. For example, the thickness of the sacrificial and buffer layer 15 may be 40 Å, 41 Å, 42 Å, 45 Å, 48 Å, 50 Å, 51 Å, 53 Å, 58 Å, 59 Å or 60 Å, or any value between any two of the aforementioned thickness values.

[0065] In some embodiments, a furnace tube process may be used to form an amorphous silicon layer as a sacrificial and buffer layer 15 on the surface of the cap layer 14 by thermal decomposition.

[0066] In some embodiments, when forming an amorphous silicon layer using a furnace tube process, the temperature is 300°C to 400°C. For example, the temperature can be 300°C, 310°C, 320°C, 330°C, 340°C, 350°C, 360°C, 370°C, 380°C, 390°C, or 400°C, or any value between any two of the aforementioned temperature values.

[0067] In some embodiments, before performing heat treatment, the surface of the amorphous silicon layer 15, which serves as a sacrificial and buffer layer, is cleaned with hot deionized water. The purpose is to passivate the surface of the amorphous silicon layer and prevent uncontrolled agglomeration or pre-crystallization of the amorphous silicon before heat treatment.

[0068] In some embodiments, the temperature of the hot deionized water used to clean the surface of the amorphous silicon layer, which serves as the sacrificial and buffer layer 15, is 50°C to 90°C. For example, the temperature may be 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C, 85°C, or 90°C, or any value between any two of the aforementioned temperature values.

[0069] The surface of a freshly deposited amorphous silicon layer contains numerous dangling bonds, which are highly reactive. In air or under heat, these dangling bonds promote silicon atom migration and rearrangement, leading to localized aggregation or crystallization. When the surface of the amorphous silicon layer is cleaned with hot deionized water, the -OH groups in the water molecules react with these dangling bonds to form a Si-OH (silanol) passivation layer. This passivation layer acts like a stable protective film on the highly reactive amorphous silicon surface, significantly reducing surface energy and inhibiting silicon atom migration at low temperatures, thus ensuring the morphological stability and uniformity of the amorphous silicon layer before heat treatment. Skipping this cleaning step and proceeding directly to heat treatment may result in roughening of the amorphous silicon and affect the final interface quality.

[0070] In some embodiments, after cleaning the surface of the amorphous silicon layer 15, which serves as a sacrificial and buffer layer, hot isopropanol (IPA) can be used to further clean the surface of the amorphous silicon layer. The purpose is to thoroughly and non-damagingly remove the moisture from the surface of the substrate 10 after hot deionized water cleaning, and to achieve defect-free drying.

[0071] After cleaning with hot deionized water, a water film remains on the surface of substrate 10 and within the nanoscale patterned structure. If direct heat treatment (high-temperature annealing) is performed, the residual moisture will rapidly vaporize, forming a "watermark" on the surface, or causing "pattern collapse" in the fine structure due to capillary forces. However, hot IPA, due to its extremely low surface tension and high volatility, can achieve uniform and stress-free drying through the "Marangoni effect," replacing and removing the residual moisture without leaving any contaminants on the surface after evaporation, thus providing a clean and dry starting point for subsequent high-temperature annealing.

[0072] In some embodiments, the heat treatment includes peak annealing.

[0073] In some embodiments, the temperature during heat treatment is 850°C to 950°C. For example, the temperature may be 850°C, 860°C, 870°C, 880°C, 890°C, 900°C, 910°C, 920°C, 930°C, 940°C, or 950°C, or any value between any two of the aforementioned temperature values.

[0074] Although the cap layer 14 (TiN layer) in the metal gate stack structure can block most impurities, its extremely thin thickness means that oxygen atoms can still diffuse from the bottom layer or sidewalls through the TiN grain boundaries to the gate dielectric layer 13 (HfO2) interface during subsequent high-temperature processing, oxidizing the silicon channel and degrading performance. By forming an amorphous silicon layer on the cap layer 14 as a sacrificial layer and morphology buffer layer, it can be used as an oxygen "getter layer" during subsequent peak annealing, preferentially reacting with diffused oxygen to form SiO. x This protects the critical channel interface, thereby preventing oxygen atoms from diffusing into the channel and avoiding performance degradation. The amorphous silicon layer can also fill any microscopic irregularities that may exist on the surface of the cap layer 14, forming a more uniform interface, which helps to form a consistent interface reaction during subsequent peak annealing.

[0075] Peak annealing drives the reaction and densification, primarily aiming to activate and achieve the design goals of the entire "interface engineering." At high temperatures (850℃~950℃), the amorphous silicon layer reacts with the TiN material in the cap layer 14. Silicon atoms in the amorphous silicon layer diffuse into the lattice gaps or grain boundaries of TiN. This has two advantages: (a) Blocking grain boundaries: Silicon atoms fill the grain boundary channels of TiN, physically blocking the rapid diffusion of impurities such as oxygen and hydrogen along the grain boundaries, significantly improving the diffusion barrier capability of TiN. (b) Formation of more stable compounds: Silicon-rich TiSiN or more stable nitride phases may form in some areas, which themselves also have excellent barrier properties. Therefore, by allowing silicon atoms in the amorphous silicon layer material to diffuse into the lattice gaps or grain boundaries of TiN, the diffusion barrier capability of the TiN layer as the cap layer 14 is improved. Furthermore, by allowing silicon atoms to react with TiN to form a silicon-containing compound layer (the first auxiliary barrier layer), the diffusion barrier capability of the cap layer 14 is further improved, resulting in a superimposed effect that enhances the diffusion barrier capability of the cap layer 14.

[0076] Meanwhile, peak annealing can produce the following effects: (a) Passivation of interface traps: High-temperature annealing can promote the repair of dangling bonds at the interface and anneal the defect states (oxygen vacancies, etc.) at the interface of the lower gate dielectric layer 13, reducing the charge trap density. This is the key to improving the positive and negative bias temperature instability (PBTI / NBTI). (b) Stabilization of interface stoichiometry: Through controlled reactions, the oxygen distribution near the interface between the gate dielectric layer 13 and the substrate 10 is made more stable, which can reduce the generation and migration of oxygen vacancies under electrical stress.

[0077] In some embodiments, the sacrificial and buffer layer 15 is removed by sequentially using diluted hydrofluoric acid (DHF) and NH4OH, and then dried using hot isopropanol.

[0078] In some embodiments, the temperature of the hot isopropanol used for drying is 50°C to 80°C. For example, the temperature may be 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, or 80°C, or any value between any two of the aforementioned temperature values.

[0079] By sequentially using diluted hydrofluoric acid and NH4OH to remove the sacrificial and buffer layer 15, the amorphous silicon material of the main body can be removed rapidly and isotropically using DHF, avoiding damage to the underlying TiN cap layer 14 (DHF has a high etching rate and selectivity for silicon, and can efficiently thin or remove the amorphous silicon layer. However, DHF has an etching effect on TiN. Once TiN is attacked by DHF, it will cause a change in work function, so it is necessary to control the use time of DHF to ensure that a small amount of amorphous silicon layer is retained). Then, using the key properties of NH4OH for fine control and surface treatment, the remaining small amount of amorphous silicon material can be finely removed (NH4OH has a moderate etching ability for silicon, which can remove the extremely thin silicon layer or silicon polymer residues remaining after the DHF etching step, and has an extremely low etching rate for the underlying TiN layer, with extremely high etching selectivity, which can almost not damage the TiN layer). Furthermore, the ability of NH4OH to form soluble complexes with many metal ions can be utilized to effectively remove metal contaminants that may be adsorbed on the surface of the TiN cap layer 14. Additionally, the high chemical activity of hot isopropanol can be used to further clean and dry the surface of the TiN cap layer 14, effectively removing organic residues and particle adsorption, achieving perfect dehydration and drying, while also providing an activated surface for the TiN cap layer 14, which is beneficial for the high-quality deposition of subsequent film layers.

[0080] Step S15: A work function layer comprising multiple work function material layers is formed on the surface of the cap layer after the sacrificial and buffer layers are removed, and the surfaces of one or more inner work function material layers formed before the outermost work function material layer are oxidized respectively.

[0081] In the turn-on voltage regulation steps of different device regions using high dielectric constant metal gate (HKMG) technology, different voltage controls (customized threshold voltages) are achieved by depositing metal work function materials of different thicknesses (such as TaN, TiN, TiAl, etc.). Therefore, work function layers of different thicknesses will be formed in different device regions, and work function layers of different thicknesses need to be formed through multiple thin film depositions.

[0082] In some embodiments, the work function layer includes multiple work function material layers. Specifically, the work function layer includes one or more inner work function material layers and an outermost work function material layer stacked sequentially from the inside out. The one or more inner work function material layers include a first work function material layer and n second work function material layers sequentially formed outside the first work function material layer, where n is a natural number including zero (e.g., n = 0, 1, 2, 3, etc.).

[0083] refer to Figure 5In some embodiments, a deposition process may be used to form a work function layer comprising two work function material layers on the surface of the cap layer 14 after the sacrificial and buffer layers 15 have been removed. In this embodiment, the work function layer formed on the surface of the cap layer 14 after the sacrificial and buffer layers 15 have been removed includes, from the inside out, a first work function material layer 16 and an outermost work function material layer 17, for a total of two work function material layers (i.e., the case where there is no second work function material layer (n=0)).

[0084] refer to Figure 6 In some embodiments, a deposition process can be used to form a work function layer comprising three work function material layers on the surface of the cap layer 14 after the sacrificial and buffer layers 15 have been removed. In this embodiment, the work function layer formed on the surface of the cap layer 14 after the sacrificial and buffer layers 15 have been removed comprises, from the inside out, one first work function material layer 16, one second work function material layer, and one outermost work function material layer 17, for a total of three work function material layers (i.e., when the number of second work function material layers is n=1). The one second work function material layer in this embodiment is referred to as the fifth work function material layer 19. That is, the second work function material layer is composed of the fifth work function material layer 19.

[0085] refer to Figure 7 In some embodiments, a deposition process can be used to form a work function layer comprising four work function material layers on the surface of the cap layer 14 after the sacrificial and buffer layers 15 have been removed. In this embodiment, the work function layer formed on the surface of the cap layer 14 after the sacrificial and buffer layers 15 have been removed comprises, from the inside out, one first work function material layer 16, two second work function material layers, and an outermost work function material layer 17, for a total of four work function material layers (i.e., when the number of second work function material layers is n=2). In this embodiment, the two second work function material layers are referred to, from the inside out, as the fourth work function material layer 20 and the fifth work function material layer 19. That is, the second work function material layer is composed of the fourth work function material layer 20 and the fifth work function material layer 19.

[0086] refer to Figure 8In some embodiments, a deposition process can be used to form a work function layer comprising five work function material layers on the surface of the cap layer 14 after the sacrificial and buffer layers 15 have been removed. In this embodiment, the work function layer formed on the surface of the cap layer 14 after the sacrificial and buffer layers 15 have been removed comprises, from the inside out, one first work function material layer 16, three second work function material layers, and an outermost work function material layer 17, for a total of five work function material layers (i.e., when the number of second work function material layers is n=3). In this embodiment, the three second work function material layers are, from the inside out, designated as the third work function material layer 21, the fourth work function material layer 20, and the fifth work function material layer 19. That is, the second work function material layer is composed of the third work function material layer 21, the fourth work function material layer 20, and the fifth work function material layer 19.

[0087] In some embodiments, the first work function material layer 16 includes a TaN layer.

[0088] In some embodiments, the second work function material layer (the third work function material layer 21, the fourth work function material layer 20, and the fifth work function material layer 19) includes a TiN layer.

[0089] In some embodiments, the outermost work function material layer 17 includes a TiAl layer.

[0090] In some embodiments, the thickness of the first work function material layer 16 is 8 Å to 15 Å. For example, the thickness of the first work function material layer 16 may be 8 Å, 9 Å, 10 Å, 11 Å, 12 Å, 13 Å, 14 Å or 15 Å, or any value between any two of the aforementioned thickness values.

[0091] In some embodiments, the thickness of the second work function material layer is 5 Å to 15 Å. For example, the thickness of the second work function material layer may be 5 Å, 6 Å, 7 Å, 8 Å, 9 Å, 10 Å, 11 Å, 12 Å, 13 Å, 14 Å or 15 Å, or any value between any two of the aforementioned thickness values.

[0092] In some embodiments, the thickness of the third work function material layer 21 is 5 Å to 10 Å. For example, the thickness of the third work function material layer 21 may be 5 Å, 6 Å, 7 Å, 8 Å, 9 Å or 10 Å, or any value between any two of the aforementioned thickness values.

[0093] In some embodiments, the thickness of the fourth work function material layer 20 is 5 Å to 10 Å. For example, the thickness of the fourth work function material layer 20 may be 5 Å, 6 Å, 7 Å, 8 Å, 9 Å or 10 Å, or any value between any two of the aforementioned thickness values.

[0094] In some embodiments, the thickness of the fifth work function material layer 19 is 5 Å to 15 Å. For example, the thickness of the fifth work function material layer 19 may be 5 Å, 6 Å, 7 Å, 8 Å, 9 Å, 10 Å, 11 Å, 12 Å, 13 Å, 14 Å or 15 Å, or any value between any two of the aforementioned thickness values.

[0095] In some embodiments, the thickness of the outermost work function material layer 17 is 20 Å to 60 Å. For example, the thickness of the outermost work function material layer 17 may be 20 Å, 21 Å, 24 Å, 25 Å, 27 Å, 30 Å, 35 Å, 40 Å, 45 Å, 50 Å, 55 Å or 60 Å, or any value between any two of the aforementioned thickness values.

[0096] Because the first work function material layer 16 and each subsequent second work function material layer are extremely thin, they often suffer from poor surface roughness after deposition. Furthermore, poor surface roughness of the preceding work function material layer not only directly affects the growth quality of the next work function material layer, but the stacking of multiple work function material layers with varying roughness also affects the final threshold voltage of the metal gate device, leading to uncontrollable threshold voltage fluctuations and insufficient turn-on voltage stability in different device regions. Therefore, oxidation treatment can be performed on the surfaces of one or more inner work function material layers formed before the outermost work function material layer 17 (i.e., oxidation of the surface of the inner work function material layers). Figure 5 The surface of the first work function material layer 16 in the middle is oxidized, or the surface of the first work function material layer 16 is subjected to oxidation treatment. Figure 6 The surfaces of the first work function material layer 16 and the fifth work function material layer 19 are respectively oxidized, or subjected to oxidation treatment. Figure 7 The surfaces of the first work function material layer 16, the fourth work function material layer 20, and the fifth work function material layer 19 are respectively oxidized, or subjected to oxidation treatment. Figure 8 The surfaces of the first work function material layer 16, the third work function material layer 21, the fourth work function material layer 20, and the fifth work function material layer 19 are respectively oxidized to smooth the rough surfaces of each inner work function material layer, reduce the roughness of the surface (treated surface) of the one or more inner work function material layers being treated, and suppress interfacial diffusion.

[0097] In some embodiments, oxygen free radicals are used for oxidation treatment to preferentially oxidize the protrusions present on the rough surface of each inner work function material layer, thereby achieving chemical mechanical smoothing of the surface and forming a dense oxide layer on the surface of the inner work function material layer as a second auxiliary barrier layer to suppress the interdiffusion of oxygen and / or nitrogen elements between different work function material layers and stabilize the interfacial stoichiometry.

[0098] In some embodiments, when the surface of the first work function material layer 16 of the TaN material is oxidized, the dense oxide layer formed on the surface of the first work function material layer 16 includes a TaON layer (TaO). x N y When the surfaces of the second work function material layers (third work function material layer 21, fourth work function material layer 20, and fifth work function material layer 19) of TiN material are oxidized, the dense oxide layers formed on the surface of each second work function material layer include TiON layers (TiO2). x N y layer).

[0099] By using oxygen free radicals to oxidize the surfaces of one or more inner work function material layers formed before the outermost work function material layer 17, the extremely high chemical reactivity of oxygen free radicals allows for controlled oxidation reactions with the treated surface at relatively low temperatures, generating an extremely thin (typically a few atomic layers), uniform, and dense oxide layer (TaO). x N y Layer / TiO x N y The oxide layer acts as a transition layer (layer 1) and serves as an interface passivation layer. Oxidation treatment effectively passivates dangling bonds and active sites on the treated surface, reduces surface energy inhomogeneity, and selectively oxidizes rough surfaces. At the nanoscale, the "peaks" (protrusions) on the treated surface have higher surface energy and more dangling bonds than the "valleys" (recesses), making them more sensitive to oxidation. Oxygen free radicals preferentially oxidize and consume these "peaks," and the oxide layer can "fill" or "smooth" the micro-undulations of the original surface. The oxidation process may drive slight migration of metal atoms (Ta / Ti atoms) on the film surface or promote the "relaxation" of unstable atoms at grain boundaries, making the surface smoother and thus achieving atomic-level chemical mechanical smoothing of the surface, reducing micro-roughness (RMS). At the same time, this dense oxide layer can also serve as a second auxiliary barrier layer, inhibiting the interdiffusion of elements such as oxygen and nitrogen between different inner work function material layers in subsequent processes and stabilizing the interfacial stoichiometry. Therefore, by reducing the interface state density (the flat, passivated interface significantly reduces charge traps at the interface) and stabilizing the metal work function (the uniform interface layer stabilizes the effective work function of each inner layer of work function material, preventing it from drifting under electrothermal stress due to interface reaction or impurity diffusion), the electrical path of improving threshold voltage stability is ultimately improved.

[0100] In some embodiments, oxygen free radicals are obtained by exciting oxygen gas with helium metastable particles and filtering out charged particles therein. The helium metastable particles are obtained by exciting helium gas and filtering out charged particles therein. By using helium metastable particles to generate low-energy oxygen free radicals, a lower-energy, almost damage-free surface oxidation process can be achieved. This effectively avoids the problems of previous surface treatments such as acid pickling, which required an additional initial value for the film thickness and caused significant film loss, and also simplifies the manufacturing process.

[0101] In some embodiments, during the oxidation process, the flow rate ratio of oxygen to helium is 1 to 10 (oxygen flow rate: helium flow rate = 1:1 to 10:1). For example, the flow rate ratio of oxygen to helium can be 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10, or any value between any two of the aforementioned flow rate ratios.

[0102] In some embodiments, the flow rate of helium gas during oxidation treatment is 1000 sccm to 9000 sccm. For example, the flow rate of helium gas can be 1000 sccm, 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, or 9000 sccm, or any value between any two of the aforementioned flow rate values.

[0103] In some embodiments, the oxidation treatment is performed at a temperature of 50°C to 180°C. For example, the temperature may be 50°C, 60°C, 70°C, 80°C, 90°C, 100°C, 110°C, 120°C, 130°C, 140°C, 150°C, 160°C, 170°C, or 180°C, or any value between any two of the aforementioned temperature values.

[0104] In some embodiments, the source power during oxidation treatment is 100W to 1000W. For example, the source power may be 100W, 200W, 300W, 400W, 500W, 600W, 700W, 800W, 900W, or 1000W, or any value between any two of the aforementioned power values.

[0105] In some embodiments, the pressure during oxidation treatment is 100 mTorr to 1000 mTorr. For example, the pressure may be 100 mTorr, 200 mTorr, 300 mTorr, 400 mTorr, 500 mTorr, 600 mTorr, 700 mTorr, 800 mTorr, 900 mTorr, or 1000 mTorr, or any value between any two of the aforementioned pressure values.

[0106] In some embodiments, the oxidation treatment is performed for a time of 30s to 300s. For example, the time can be 30s, 35s, 40s, 45s, 50s, 55s, 60s, 80s, 100s, 130s, 150s, 180s, 200s, 220s, 250s, 290s, or 300s, or any value between any two of the aforementioned time values.

[0107] In some embodiments, during oxidation, ion filtering is turned on and bias power is turned off.

[0108] By synergistically controlling the flow ratio, temperature, source power, pressure, time, etc., lower energy oxygen free radicals can be obtained, achieving ultra-low damage surface oxidation treatment.

[0109] In some embodiments, prior to oxidation, nitrogen free radicals excited by metastable particles may be used to nitrid the surfaces of one or more inner work function material layers formed before the outermost work function material layer 17 (i.e., to...). Figure 5 The surface of the first work function material layer 16 in the middle is sequentially subjected to nitriding and oxidation treatment, or to... Figure 6 The surfaces of the first work function material layer 16 and the fifth work function material layer 19 are respectively subjected to nitriding and oxidation treatments, or to... Figure 7 The surfaces of the first work function material layer 16, the fourth work function material layer 20, and the fifth work function material layer 19 are respectively subjected to nitriding and oxidation treatments, or to... Figure 8 The surfaces of the first work function material layer 16, the third work function material layer 21, the fourth work function material layer 20, and the fifth work function material layer 19 are subjected to nitriding and oxidation treatments, respectively. Nitrogen free radicals can be obtained by exciting nitrogen gas with helium metastable particles and filtering out charged particles. Helium metastable particles can be obtained by exciting helium gas and filtering out charged particles.

[0110] By using nitrogen free radicals for nitriding treatment, nitrogen atoms are injected into the treated surface, allowing for precise control of the surface nitrogen content, repair of nitrogen vacancies, alteration of the Fermi level position, and the formation of a nitrogen-rich surface layer (TaN) on the treated surface. x / TiN x This allows for precise adjustment of the stoichiometry and work function (the work function is closely related to the nitrogen content of the material layer). Furthermore, based on the already optimized nitrided surface, oxidation treatment can be used to eliminate surface roughness, achieving surface smoothing and interface stabilization. This also helps to lock in the chemical state achieved in the previous nitriding adjustment, preventing nitrogen loss in subsequent processes and thus enhancing the long-term stability of the threshold voltage.

[0111] In some embodiments, the outermost work function material layer 17 includes a TiAlC layer (a titanium-aluminum compound layer containing carbon (C)). By employing a TiAlC layer as the outermost work function material layer 17, the lattice structure and electronic properties of the material can be optimized by introducing carbon elements, thereby enabling more precise and stable control of the transistor's work function and threshold voltage (Vth). Specifically, the added C elements form more complex chemical bonds with Ti and Al or fill the lattice interstices, slightly altering the electronic density of states near the Fermi level, thus achieving precise fine-tuning of the work function value to several decimal places. This is crucial for differentiating transistors of different specifications, such as ultra-low power (ULP), standard performance (SVt), and high performance (HVt), at advanced nodes. Furthermore, the addition of C helps stabilize the microstructure of TiAl, preventing phase transitions or excessive grain growth during subsequent high-temperature processes (such as annealing). Simultaneously, C atoms effectively suppress the diffusion of Al atoms into the gate dielectric layer 13 (a high-K material), avoiding threshold voltage drift and reliability issues. Therefore, by using a TiAlC layer as the outermost work function material layer 17, the lattice structure and electronic properties of the material can be optimized, enabling more precise and stable control of the work function and threshold voltage of the transistor, thereby significantly improving the stability and yield of the device.

[0112] In some embodiments, after depositing the TiAlC layer as the outermost work function material layer 17, H2 can be used to treat the surface of the TiAlC layer to remove adsorbed carbon impurities on the surface of the TiAlC layer, thereby stabilizing the work function, optimizing performance, and providing an active deposition surface for subsequent film deposition.

[0113] Step S16: Form a gate electrode layer on the surface of the work function layer.

[0114] refer to Figure 5 , Figure 6 , Figure 7 or Figure 8 In some embodiments, a deposition process may be used to form a gate electrode layer 18 on the surface of the outermost work function material layer 17.

[0115] In some embodiments, the gate electrode layer 18 includes a tungsten (W) layer.

[0116] Furthermore, a deposition process can be used to first form a top diffusion barrier layer (not shown) on the surface of the outermost work function material layer 17, and then form a gate electrode layer 18 on the surface of the top diffusion barrier layer.

[0117] In some embodiments, the top diffusion barrier layer comprises a TiN layer.

[0118] This completes the fabrication of the entire metal gate stack structure.

[0119] According to a second aspect of this application, embodiments of this application also provide a metal gate device structure, which is obtained using the metal gate device structure manufacturing method provided in any of the embodiments of the first aspect above.

[0120] refer to Figure 5 , Figure 6 , Figure 7 or Figure 8 In some embodiments, the metal gate device structure is disposed on a substrate 10, including a fin 11 disposed on the substrate 10, and an isolation structure 12 for isolating the active region is disposed on the substrate 10 surrounding the fin 11. A gate dielectric layer 13, a cap layer 14, a work function layer, and a gate electrode layer 18 are sequentially disposed on the surface of the fin 11. The work function layer includes multiple work function material layers stacked sequentially from the inside out. Specifically, the work function layer includes one or more inner work function material layers and an outermost work function material layer 17 stacked sequentially from the inside out. The one or more inner work function material layers include a first work function material layer 16 and n second work function material layers sequentially formed outside the first work function material layer 16, where n is a natural number including zero (e.g., n = 0, 1, 2, 3, etc.).

[0121] For example, the work function layer may include a first work function material layer 16 and an outermost work function material layer 17 arranged sequentially from the inside out, such as... Figure 5 As shown.

[0122] Alternatively, the work function layer may include, from the inside out, a first work function material layer 16, a second work function material layer (a fifth work function material layer 19), and an outermost work function material layer 17, as follows: Figure 6 As shown.

[0123] Alternatively, the work function layer may include, from the inside out, a first work function material layer 16, two second work function material layers (a fourth work function material layer 20 and a fifth work function material layer 19), and an outermost work function material layer 17, as follows: Figure 7 As shown.

[0124] Alternatively, the work function layer may include, from the inside out, a first work function material layer 16, three second work function material layers (a third work function material layer 21, a fourth work function material layer 20, and a fifth work function material layer 19), and an outermost work function material layer 17, as follows: Figure 8 As shown.

[0125] Among them, such as Figure 5 The region where the metal gate device structure is located can be an NLVT (N-type low threshold voltage) region or a NULVT (N-type ultra-low threshold voltage) region. For example... Figure 6The region where the metal gate device structure is shown can be the NSVT (N-type standard threshold voltage) region. For example... Figure 7 The region where the metal gate device structure is shown can be the PSVT (P-type standard threshold voltage) region. For example... Figure 8 The region where the metal gate device structure is located can be a PLVT (P-type low threshold voltage) region or a PULVT (P-type ultra-low threshold voltage) region. By utilizing work function layers of different thicknesses (number of layers) in the metal gate stack structure respectively located in the NLVT, NULVT, NSVT, PSVT, PLVT, and PULVT regions, the turn-on voltage of different device regions can be controlled, i.e., a customized threshold voltage can be achieved.

[0126] Furthermore, by subjecting the surfaces of one or more inner work function material layers formed before the outermost work function material layer 17 to oxidation treatment, atomic-level chemical mechanical smoothing of the rough surfaces of the inner work function material layers is achieved, reducing the micro-roughness (RMS). This reduces threshold voltage fluctuations, improves the stability of turn-on voltage regulation, stabilizes the interfacial stoichiometry, and ultimately improves the electrical path for threshold voltage stability. Further, by forming a sacrificial and buffer layer 15 (amorphous silicon layer) on the surface of the cap layer 14 (TiN layer) and performing heat treatment, the diffusion blocking capability of the cap layer 14 can be significantly improved, the bias temperature instability (BTI) effect can be mitigated, and interfacial traps can be passivated, stabilizing the interfacial stoichiometry. This effectively improves the voltage stability of the metal work function and the reliability of the device.

[0127] In a third aspect, embodiments of this application also provide a plasma processing apparatus for performing the metal gate device structure manufacturing method corresponding to the above embodiments to form the metal gate device structure corresponding to the above embodiments. The plasma processing apparatus includes inductively coupled plasma (ICP) etching equipment or capacitively coupled plasma (CCP) etching equipment, etc.

[0128] In other aspects, embodiments of this application also provide an electronic device, including a metal gate device structure obtained using the metal gate device structure manufacturing method of the above embodiments. The electronic device can be a storage device, mobile phone, computer, tablet computer, electronic instrument, television, artificial intelligence device, etc.

[0129] In summary, this embodiment utilizes oxygen free radicals excited by metastable particles to oxidize the surfaces of one or more inner work function material layers formed before the outermost work function material layer 17. This avoids damage to the treated surfaces and achieves atomic-level chemical mechanical smoothing of the treated rough surfaces, reducing micro-roughness (RMS). Consequently, it reduces threshold voltage fluctuations and improves the stability of turn-on voltage regulation. Furthermore, by forming a sacrificial and buffer layer 15 on the surface of the cap layer 14 and performing heat treatment, the diffusion blocking capability of the cap layer 14 is significantly improved, mitigating the bias temperature instability (BTI) effect. Simultaneously, it passivates interface traps and stabilizes the interface stoichiometry. Therefore, it ultimately improves the voltage stability of the metal work function at advanced nodes, enhances device reliability, and increases yield.

[0130] The above are merely preferred embodiments of this application. These embodiments are not intended to limit the scope of protection of this application. Therefore, any equivalent changes made based on the description and drawings of this application should also be included within the scope of protection of this application.

Claims

1. A method of fabricating a metal gate device structure, the method comprising: include: Provide substrate; Fins are formed on the substrate; A gate dielectric layer and a cap layer are sequentially formed on the surface of the fin. A sacrificial and buffer layer is formed on the surface of the cap layer, and then heat treatment is performed to allow atoms in the sacrificial and buffer layer material to diffuse into the cap layer material to improve the diffusion barrier capability of the cap layer. The sacrificial and buffer layer is then removed. On the surface of the cap layer after removing the sacrificial and buffer layers, a work function layer and a gate electrode layer are sequentially formed. The work function layer comprises multiple work function material layers stacked sequentially from the inside out. Among them, the surfaces of one or more inner work function material layers formed before the outermost work function material layer are all subjected to oxidation treatment to smooth the rough surface of the inner work function material layer and suppress interface diffusion. The cap layer includes a TiN layer, the sacrificial and buffer layer includes an amorphous silicon layer, and the heat treatment includes peak annealing. The amorphous silicon layer material fills and smooths the rough surface of the TiN layer, forming a uniform interface. This allows silicon atoms in the amorphous silicon layer to form a consistent interfacial reaction when diffusing into the TiN layer, and to enter the lattice gaps or grain boundaries of TiN, thereby improving the diffusion barrier capability of the TiN layer as the cap layer. Furthermore, by allowing silicon atoms in the amorphous silicon layer to diffuse into the TiN layer and react to form a silicon-containing compound layer as a first auxiliary barrier layer, the diffusion barrier capability of the cap layer is further improved. The barrier effect is achieved by using oxygen free radicals to perform oxidation treatment, preferentially oxidizing the protrusions on the rough surface of the inner work function material layer to achieve chemical mechanical smoothing of the surface. Through controlled oxidation reaction, a dense oxide layer is formed on the surface of the inner work function material layer as a second auxiliary barrier layer to suppress the interdiffusion of oxygen and / or nitrogen between different work function material layers and stabilize the interfacial stoichiometry. The oxygen free radicals are obtained by exciting oxygen with helium metastable particles and filtering out charged particles therein. The helium metastable particles are obtained by exciting helium gas and filtering out charged particles therein.

2. The method of claim 1, wherein Before performing the heat treatment, the process further includes: cleaning the surface of the amorphous silicon layer with hot deionized water to passivate the surface of the amorphous silicon layer; and / or, sequentially using diluted hydrofluoric acid and NH4OH to remove the sacrificial and buffer layers, and drying with hot isopropanol.

3. The method of claim 1, wherein When performing the heat treatment, the temperature is 850℃~950℃; and / or, the thickness of the cap layer is 10Å~20Å; and / or, the thickness of the sacrificial and buffer layer is 40Å~60Å.

4. The method of claim 1, wherein During the oxidation process, the helium flow rate is 1000 sccm to 9000 sccm, the oxygen flow rate: helium flow rate ratio is 1:1 to 10:1, the temperature is 50℃ to 180℃, the source power is 100W to 1000W, the pressure is 100mTorr to 1000mTorr, the time is 30s to 300s, and the ion filter is turned on while the bias power is turned off.

5. The method of claim 1, wherein The one or more inner work function material layers include a first work function material layer and n second work function material layers formed sequentially outside the first work function material layer, where n is a natural number including zero.

6. The method of claim 5, wherein The first work function material layer includes a TaN layer; and / or, the second work function material layer includes a TiN layer; and / or, the outermost work function material layer includes a TiAl layer; and / or, the thickness of the first work function material layer is 8 Å to 15 Å; and / or, the thickness of the second work function material layer is 5 Å to 15 Å; and / or, the thickness of the outermost work function material layer is 20 Å to 60 Å.

7. A metal gate device structure, characterized by, It is obtained using the metal gate device structure manufacturing method as described in any one of claims 1-6.

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