Trigger system for source tables and source tables

Abstract

This application discloses a triggering system and source table for a source table, including a trigger logic processing module and a signal channel. The signal channel includes an ARM layer, a trigger layer, and an execution layer. When the signal channel is in a ready state: the ARM layer is configured in ARM layer normal mode, and upon receiving a first expected trigger source signal, it outputs a first trigger signal. The trigger logic processing module is configured to generate a state ready signal in response to the first trigger signal. When the trigger layer is configured in trigger layer normal mode, in response to the state ready signal, upon receiving a second expected trigger source signal, it outputs a second trigger signal. The trigger logic processing module is configured to generate an execution signal in response to the second trigger signal. The execution layer is configured to perform a predetermined operation in response to the execution signal. By configuring the first and second expected trigger signals, combinations of different trigger source signals can be achieved. The trigger source configuration is rich, meeting the needs of complex measurement and testing environments. It is simple to use and reduces costs.

Description

Technical Field

[0001] This invention relates to the field of measurement and testing technology, and specifically to a triggering system and a source table for a source table. Background Technology

[0002] A source measurement unit (SMU), commonly known as a source meter, is a precision test device that integrates voltage / current source and voltage / current measurement functions. It is widely used in semiconductor device characteristic analysis, material electrical performance testing, and integrated circuit testing. In automated test systems (ATE) or multi-channel parallel testing scenarios, source meters typically need to work in conjunction with vector network analyzers, oscilloscopes, probe stations, or other multiple source meters. Therefore, the performance of its triggering system directly determines the synchronization accuracy and data consistency of the entire test system.

[0003] In existing technologies, traditional source table triggering systems can only be configured with a single trigger source. This means that users have no choice in software or hardware configuration and can only specify one trigger source. The limitation to configuring only a single trigger source results in limited functionality, which cannot meet the needs of complex measurement and testing environments (such as automated chip testing in industry). Consequently, multiple devices are required to work together to complete tests in complex environments, leading to complexity and high costs. Summary of the Invention

[0004] The main technical problem solved by this invention is that the triggering system can only be configured with a single trigger source, which is limited in function and cannot meet the needs of complex measurement and testing environments. As a result, multiple devices need to work together to complete the test in complex measurement and testing environments, leading to the problem of complexity and high cost.

[0005] According to the first aspect, one embodiment of this application provides a triggering system for a source table, including: a triggering logic processing module and at least one signal channel;

[0006] The signal channel's operating state includes at least a ready state. The signal channel includes an ARM layer, a trigger layer, and an execution layer. The trigger logic processing module is connected to the ARM layer, the trigger layer, and the execution layer. The ARM layer's operating mode includes at least an ARM layer normal mode. The trigger layer's operating mode includes at least a trigger layer normal mode.

[0007] When the signal channel is in the ready state:

[0008] The ARM layer is configured to receive a first trigger event when it is in working state and the working mode is the normal mode of the ARM layer. The first trigger event includes multiple types of first trigger source signals. When the received first trigger event includes a first expected trigger source signal, a first trigger signal is output to the trigger logic processing module. The trigger logic processing module is configured to cause the trigger layer to enter the working state in response to the first trigger signal.

[0009] The triggering layer is configured to receive a second triggering event when it is in working state and the working mode is the normal mode of the triggering layer. The second triggering event includes multiple types of second triggering source signals. When the second triggering event includes a second expected triggering source signal, the triggering layer outputs a second triggering signal to the triggering logic processing module. The triggering logic processing module is configured to generate an execution signal in response to the second triggering signal and output it to the execution layer.

[0010] The execution layer is configured to perform a predetermined operation in response to the execution signal.

[0011] In one embodiment, the first triggering event includes: a first internal triggering source signal, a first bus triggering source signal, a first local area network triggering source signal, and a first external triggering source signal; and / or, the second triggering event includes: a second internal triggering source signal, a second bus triggering source signal, a second local area network triggering source signal, and a second external triggering source signal.

[0012] In one embodiment, the signal channel includes: a hardware circuit connected to the trigger logic processing module, wherein the ARM layer and the trigger layer share the hardware circuit;

[0013] When the ARM layer needs to enter the working state, the trigger logic processing module is also configured to configure the hardware circuit as the ARM layer;

[0014] When the trigger layer needs to enter the working state, the trigger logic processing module is also configured to configure the hardware circuit as the trigger layer.

[0015] In one embodiment, the operating mode of the ARM layer further includes an ARM layer bypass mode; the operating mode of the trigger layer further includes a trigger layer bypass mode.

[0016] When the ARM layer enters the working state and the working mode is the ARM layer bypass mode, the hardware circuit is configured to be switched to the trigger layer after entering the ARM layer;

[0017] When the trigger layer enters the working state and the working mode is the trigger layer bypass mode, the trigger logic processing module generates the execution signal and outputs it to the execution layer.

[0018] In one embodiment, the hardware circuit includes: a signal selection unit, a trigger counting unit, and a timing trigger signal generation unit; the trigger logic processing module is connected to the signal selection unit, the trigger counting unit, and the internal signal generation unit.

[0019] When the hardware circuit is configured for the ARM layer:

[0020] The signal selection unit is configured to receive the first trigger event when the ARM's operating mode is the ARM layer normal mode, and to output the first trigger signal to the trigger logic processing module when the first expected trigger source signal is received.

[0021] The trigger counting unit is configured to increment the count once when the ARM layer's operating mode is determined to be the ARM layer's normal mode, and to increment the count once when the ARM layer's operating mode is determined to be the ARM layer's bypass mode, so as to generate a first count value and output it to the trigger logic processing module.

[0022] The timing trigger signal generation unit is configured to generate a first internal timing trigger source signal in response to a first signal generation command;

[0023] When the hardware circuit is configured as the trigger layer:

[0024] The signal selection unit is configured to receive the second trigger event when the working mode of the trigger layer is the normal mode of the trigger layer, and to output the second trigger signal to the trigger logic processing module when the second expected trigger source signal is received;

[0025] The trigger counting unit is configured to increment the count once when the working mode of the trigger layer is determined to be the normal mode of the trigger layer, and to increment the count once when the working mode of the trigger layer is determined to be the bypass mode of the trigger layer, so as to generate a second count value and output it to the trigger logic processing module.

[0026] The timing trigger signal generation unit is configured to generate a second internal timing trigger source signal in response to a second signal generation command;

[0027] The trigger logic processing module is further configured to generate the first signal generation instruction when the first trigger event includes the first internal timed trigger source signal; and is further configured to generate the second signal generation instruction when the second trigger event includes the second internal timed trigger source signal.

[0028] In one embodiment, the operating state of the signal channel further includes an idle state;

[0029] The trigger logic processing module is further configured to:

[0030] After the execution layer completes the predetermined operation, it is determined whether the second count value has reached the second preset value. If the second count value has reached the second preset value, it is determined whether the first count value has reached the first preset value. If the first count value has reached the first preset value, the signal channel is switched from the ready state to the idle state. If the first count value has not reached the first preset value, the hardware circuit is configured as the ARM layer. When the ARM layer is in the normal mode, it can receive the first trigger event and output the first trigger signal when it receives the first expected trigger source signal. When the ARM layer is in the bypass mode, the hardware circuit is switched from the ARM layer to the trigger layer.

[0031] If the second count value does not reach the second preset value, the hardware circuit is configured as the trigger layer. When the trigger layer is in the normal trigger layer mode, it can receive the second trigger event and output the second trigger signal when it receives the second expected trigger source signal. When the trigger layer is in the trigger bypass mode, it generates the execution signal and outputs it to the execution layer.

[0032] In one embodiment, the signal channel switches from the idle state to the ready state in response to a user operation;

[0033] When the signal channel switches from the idle state to the ready state, the first count value is reset to the first initial value;

[0034] When the hardware circuit is switched from the ARM layer to the trigger layer, the second count value is reset to the second initial value.

[0035] In one embodiment, the execution layer is further configured to output a pre-execution indication signal before the predetermined operation is executed, and to output a post-execution indication signal after the predetermined operation is executed;

[0036] The signal channel also includes a status indication module, which is connected to the trigger logic processing module.

[0037] The trigger logic processing module is further configured to:

[0038] When the ARM layer outputs an enable signal, it outputs a first state indication signal to the state indication module in response to the first trigger signal, so that the state indication module outputs an ARM layer action feedback signal when it receives the expected first state indication signal.

[0039] When the trigger layer output is enabled, a second state indication signal is output to the state indication module in response to the second trigger signal, so that the state indication module outputs a trigger layer action feedback signal when it receives the expected second state indication signal;

[0040] When the execution layer outputs an enable signal, a third state indication signal is output to the state indication module in response to the pre-execution indication signal, so that the state indication module outputs a pre-execution feedback signal when it receives the expected third state indication signal.

[0041] When the execution layer output is enabled, a fourth state indication signal is output to the state indication module in response to the post-execution indication signal, so that the state indication module outputs a post-execution feedback signal when it receives the expected fourth state indication signal.

[0042] In one embodiment, the execution layer includes: an excitation output module and / or a measurement acquisition module;

[0043] The excitation output module is configured to output an excitation signal to the device under test after receiving the execution signal;

[0044] The measurement acquisition module is configured to acquire measurement data output by the device under test after receiving the execution signal.

[0045] According to a second aspect, one embodiment of this application provides a source table, including the triggering system for the source table as described above.

[0046] According to the triggering system and source table for the source table in the above embodiments, when the first trigger event received by the ARM layer includes a first expected trigger source signal, a first trigger signal can be output; when the second trigger event received by the trigger layer includes a second expected trigger source signal, a second trigger signal can be output. Since the first trigger event includes multiple types of first trigger source signals and the second trigger event includes multiple types of second trigger source signals, different combinations of trigger source signals can be achieved by configuring different first expected trigger signals and different second expected trigger signals. That is, by configuring different first expected trigger signals to select different first trigger source signals, and by configuring different second expected trigger signals to select different second trigger source signals, different combinations of trigger source signals can be achieved. The trigger source configuration is rich and can meet the needs of complex measurement and testing environments. It does not require multiple devices to cooperate and coordinate to complete the test, thereby simplifying the use and reducing the cost. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of a triggering system for a source table according to one embodiment.

[0048] Figure 2 This is a flowchart illustrating the process of entering the ARM layer in one embodiment;

[0049] Figure 3 This is a flowchart illustrating the process of entering the trigger layer in one embodiment;

[0050] Figure 4 This is a flowchart illustrating the execution layer performing predetermined operations in one embodiment.

[0051] Figure label:

[0052] 100. Trigger logic processing module; 200. Hardware circuit; 201. Signal selection unit; 202. Trigger counting unit; 203. Timing trigger signal generation unit; 300. Status indication module; 400. Execution layer; 401. Source output module; 402. Measurement and acquisition module. Detailed Implementation

[0053] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0054] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0055] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0056] This application provides a triggering system for source tables. Different first trigger source signals can be selected by configuring different first expected trigger signals, and different second trigger source signals can be selected by configuring different second expected trigger signals. Since the first trigger event includes multiple types of first trigger source signals and the second trigger event includes multiple types of second trigger source signals, combinations of different trigger source signals can be realized. The trigger source configuration is rich and can meet the needs of complex measurement and testing environments. It eliminates the need for multiple devices to cooperate in completing the test, making it simpler to use and reducing costs.

[0057] In some embodiments, the triggering system may include a trigger logic processing module 100 and at least one signal channel; the operating state of the signal channel includes at least a ready state. For example... Figure 1As shown, the signal channel may include an ARM layer, a trigger layer, and an execution layer 400. The trigger logic processing module 100 is connected to the ARM layer, the trigger layer, and the execution layer 400. The working modes of the ARM layer include ARM layer normal mode (ARM layer Bypass off) and ARM layer bypass mode (ARM layer Bypass on). The working modes of the trigger layer include trigger layer normal mode (trigger layer Bypass off) and trigger layer bypass mode (trigger layer Bypass on).

[0058] When the signal channel is in a ready state: the ARM layer is configured to receive a first trigger event when it is in a working state and the working mode is the ARM layer normal mode. The first trigger event includes multiple types of first trigger source signals. When the received first trigger event includes a first expected trigger source signal, the first trigger signal is output to the trigger logic processing module 100. The trigger logic processing module 100 is configured to cause the trigger layer to enter a working state in response to the first trigger signal. The trigger layer is configured to receive a second trigger event when it is in a working state and the working mode is the trigger layer normal mode. The second trigger event includes multiple types of second trigger source signals. When the received second trigger event includes a second expected trigger source signal, the second trigger signal is output to the trigger logic processing module 100. The trigger logic processing module 100 is configured to generate an execution signal in response to the second trigger signal and output it to the execution layer 400. The execution layer 400 is configured to perform a predetermined operation in response to the execution signal.

[0059] Specifically, the signal channel includes an idle state and a ready state. When the signal channel is in the idle state, the first expected trigger source signal corresponding to the ARM layer can be configured, the second expected trigger source signal corresponding to the trigger layer can be configured, and the predetermined operation corresponding to the execution layer 400 can be configured.

[0060] The signal channel is in a ready state:

[0061] When the ARM layer enters the working state and the working mode is the normal mode of the ARM layer, the ARM layer waits for the first trigger event to arrive. When the first expected trigger source signal is received, the ARM layer outputs the first trigger signal to the trigger logic processing module 100. The trigger logic processing module 100 responds to the first trigger signal to make the trigger layer enter the working state, that is, enter the trigger layer.

[0062] After entering the trigger layer, when the trigger layer is in the normal trigger layer mode, the trigger layer waits for the second trigger event to arrive. When the second expected trigger source signal is received, the trigger layer outputs the second trigger signal to the trigger logic processing module 100, so that the trigger logic processing module 100 generates an execution signal and outputs it to the execution layer 400, thereby causing the execution layer 400 to perform the predetermined operation.

[0063] Since the first triggering event includes multiple types of first triggering source signals and the second triggering event includes multiple types of second triggering source signals, different combinations of triggering source signals can be achieved by configuring different first expected triggering signals and different second expected triggering signals. That is, by configuring different first expected triggering signals to select different first triggering source signals, and by configuring different second expected triggering signals to select different second triggering source signals, different combinations of triggering source signals can be achieved. The triggering source configuration is rich and can meet the needs of complex measurement and testing environments. It does not require multiple devices to cooperate and coordinate to complete the test. It is simple to use and reduces costs.

[0064] In some embodiments, the first triggering event may include a first internal triggering source signal, a first bus triggering source signal, a first local area network triggering source signal, and a first external triggering source signal.

[0065] The first internal trigger source signal can be an internal timing trigger source signal generated autonomously by the timer integrated within the triggering system at the ARM layer, based on a preset time threshold or clock cycle; that is, an internal timing trigger source signal at the ARM layer. Alternatively, the first internal trigger source signal can be an internal trigger source signal generated by the trigger logic processing module 100 through the execution of program instructions or firmware logic at the ARM layer.

[0066] The first bus trigger source signal is a trigger source signal transmitted through the system's internal bus (such as a BUS). The first local area network (LAN) trigger source signal refers to a trigger signal transmitted through a local area network (LAN), which usually originates from other devices in the same network (such as a host computer, server, or other node devices). The LAN can be Ethernet, Wi-Fi, industrial Ethernet, etc.

[0067] The first external trigger source signal refers to the hardware trigger signal that is directly input from the outside through a dedicated physical interface. This hardware trigger signal can be the EXT1 trigger signal, EXT2 trigger signal, EXT3 trigger signal, EXT4 trigger signal, EXT5 trigger signal, or EXT6 trigger signal.

[0068] In some embodiments, the second trigger source signal may include a second internal trigger source signal, a second bus trigger source signal, a second local area network trigger source signal, and a second external trigger source signal.

[0069] The second internal trigger source signal can be an internal timing trigger source signal that is autonomously generated by the timer integrated within the triggering system according to a preset time threshold or clock cycle when the triggering layer is in operation; that is, an internal timing trigger source signal of the triggering layer. Alternatively, the second internal trigger source signal can be an internal trigger source signal generated by the triggering logic processing module 100 through the execution of program instructions or firmware logic when the triggering layer is in operation.

[0070] The second bus trigger source signal is a trigger source signal transmitted through the system's internal bus (such as a BUS). The second LAN trigger source signal refers to a trigger signal transmitted through a local area network (LAN), which usually originates from other devices in the same network (such as a host computer, server, or other node devices). The LAN can be Ethernet, Wi-Fi, industrial Ethernet, etc.

[0071] The second external trigger source signal refers to the hardware trigger signal that is directly input from the outside through a dedicated physical interface. This hardware trigger signal can be the EXT1 trigger signal, EXT2 trigger signal, EXT3 trigger signal, EXT4 trigger signal, EXT5 trigger signal, or EXT6 trigger signal.

[0072] In application, the first expected trigger source signal can be configured as the first internal trigger source signal, and the second expected trigger source signal can be configured as the second external trigger source signal, that is, the combination of the first internal trigger source signal and the second external trigger source signal can be realized.

[0073] Of course, the first expected trigger source signal can also be configured to other values. For example, a first external trigger source signal or a first bus trigger source signal. Similarly, the second expected trigger source signal can also be configured to other values. For example, a second external trigger source signal or a second bus trigger source signal.

[0074] In some embodiments, such as Figure 1 As shown, the signal channel includes a hardware circuit 200, which is connected to the trigger logic processing module 100. The ARM layer and the trigger layer share the hardware circuit 200. When the ARM layer needs to enter the working state, the trigger logic processing module 100 is also configured to configure the hardware circuit 200 as the ARM layer. When the trigger layer needs to enter the working state, the trigger logic processing module 100 is also configured to configure the hardware circuit 200 as the trigger layer.

[0075] In other words, when the triggering system requires ARM layer action, hardware circuit 200 is switched to ARM layer, and trigger logic processing module 100 calls the configuration parameters corresponding to ARM layer as the configuration parameters for hardware circuit 200 operation. When the triggering system requires trigger layer action, hardware circuit 200 is switched to trigger layer, and trigger logic processing module 100 calls the configuration parameters corresponding to trigger layer as the configuration parameters for hardware circuit 200 operation. Since the ARM layer and trigger layer can share hardware circuit 200, there is no need to set up separate hardware circuits 200 for the ARM layer and trigger layer, further reducing costs.

[0076] In some embodiments, when the signal channel switches from an idle state to a ready state, the hardware circuit 200 is configured as an ARM layer. That is, the ARM layer needs to enter a working state. When the ARM layer enters a working state, it triggers the logic processing module 100 to call the configuration parameters corresponding to the ARM layer as the configuration parameters for the hardware circuit 200 to run. For example, Figure 2 As shown, when the ARM layer operates in ARM layer bypass mode, the trigger logic control module switches hardware circuit 200 from ARM layer to trigger layer after entering the ARM layer. That is, the trigger layer enters the working state when needed. When the ARM layer operates in ARM layer normal mode, the ARM layer waits for the arrival of the first expected trigger source signal. That is, after responding to the first trigger signal, the trigger logic control module configures hardware circuit 200 as the trigger layer, causing the trigger layer to enter the working state.

[0077] After the trigger layer enters the working state, the trigger logic processing module 100 calls the configuration parameters corresponding to the trigger layer as the configuration parameters for the hardware circuit 200 during operation. For example, Figure 3 As shown, after the trigger layer enters the working state, when the working mode of the trigger layer is the normal mode, the trigger layer waits for the arrival of the second expected trigger source signal. That is, the trigger logic control module generates an execution signal in response to the second trigger signal and outputs it to the execution layer 400. When the working mode of the trigger layer is the trigger layer bypass mode, the trigger logic control module generates an execution signal and outputs it to the execution layer 400.

[0078] In some embodiments, such as Figure 1 As shown, the hardware circuit 200 may include a signal selection unit 201, a trigger counting unit 202, and a timing trigger signal generation unit 203; the trigger logic processing module 100 is connected to the signal selection unit 201, the trigger counting unit 202, and the internal signal generation unit.

[0079] like Figure 2 As shown, when the hardware circuit 200 is configured as an ARM layer: the signal selection unit 201 is configured to receive a first trigger event when the ARM layer is in the normal ARM layer operating mode, and output a first trigger signal to the trigger logic processing module 100 when a first expected trigger source signal is received; the trigger counting unit 202 is configured to increment the count once when the first expected trigger source signal is received after determining that the ARM layer is in the normal ARM layer operating mode, and increment the count once when the ARM layer is determined to be in the ARM layer bypass mode, so as to generate a first count value and output it to the trigger logic processing module 100; the timing trigger signal generation unit 203 is configured to generate a first internal timing trigger source signal in response to a first signal generation instruction.

[0080] like Figure 3 As shown, when the hardware circuit 200 is configured as a trigger layer: the signal selection unit 201 is configured to receive a second trigger event when the working mode of the trigger layer is the normal trigger layer mode, and output a second trigger signal to the trigger logic processing module 100 when a second expected trigger source signal is received; the trigger counting unit 202 is configured to increment the count once when the working mode of the trigger layer is determined to be the normal trigger layer mode, and increment the count once when the working mode of the trigger layer is determined to be the trigger layer bypass mode, so as to generate a second count value and output it to the trigger logic processing module 100; the timing trigger signal generation unit 203 is configured to generate a second internal timing trigger source signal in response to a second signal generation instruction.

[0081] The trigger logic processing module 100 is also configured to generate a first signal generation instruction when the first trigger event includes a first internal timed trigger source signal; and is also configured to generate a second signal generation instruction when the second trigger event includes a second internal timed trigger source signal.

[0082] Specifically, such as Figure 1 As shown, the signal selection unit 201 can be, but is not limited to, an input source trigger arbitrator; when the hardware circuit 200 is configured as an ARM layer, the selection signal configured for the input source trigger arbitrator is a first expected trigger source signal; when the hardware circuit 200 is configured as a trigger layer, the selection signal configured for the input source trigger arbitrator is a second expected trigger source signal.

[0083] like Figure 1 As shown, the timing trigger signal generation unit 203 is a timer. In the ARM layer, this timer is configured to generate an internal timing trigger source signal (i.e., a first internal timing trigger source signal) in response to a first signal generation instruction. In the trigger layer, this timer is configured to generate an internal timing trigger source signal (i.e., a second internal timing trigger signal source) in response to a second signal generation instruction. That is, when the first expected trigger source signal is the first internal timing trigger source signal, and the hardware circuit 200 is configured for the ARM layer, the trigger logic processing module 100 periodically generates a first signal generation instruction through parameter configuration and outputs it to the timer, causing the timer to periodically generate the first internal timing trigger source signal required by the ARM layer. When the second expected trigger source signal is the second internal timing trigger source signal, the trigger logic processing module 100 periodically generates a second signal generation instruction through parameter configuration and outputs it to the timer, causing the timer to periodically generate the second internal timing trigger source signal required by the trigger layer.

[0084] like Figure 1As shown, the trigger counting unit 202 is a trigger counter. When it is determined that the ARM layer is in the normal ARM layer mode, upon receiving the first expected trigger source signal, the trigger logic processing unit triggers the trigger counter once, incrementing the count by one. When it is determined that the ARM layer is in the bypass ARM layer mode, the trigger logic processing unit triggers the trigger counter once, incrementing the count by one, to generate the first count value, which is then output to the trigger logic processing module 100.

[0085] When the working mode of the trigger layer is determined to be the normal mode, the trigger logic processing unit triggers the trigger counter once upon receiving the second expected trigger source signal, and the count is incremented once. When the working mode of the trigger layer is determined to be the bypass mode, the trigger logic processing unit triggers the trigger counter once, and the count is incremented once, to generate a second count value, which is then output to the trigger logic processing module 100.

[0086] In some embodiments, such as Figure 4 As shown, the trigger logic processing module 100 is further configured to, after the execution layer 400 completes the predetermined operation, determine whether the second count value has reached the second preset value. If the second count value reaches the second preset value, then determine whether the first count value has reached the first preset value. If the first count value reaches the first preset value, then switch the signal channel from the ready state to the idle state. If the first count value does not reach the first preset value, then the hardware circuit 200 is configured as an ARM layer. When the ARM layer is in the normal ARM layer mode, it can receive the first trigger event. When it receives the first expected trigger source signal, it outputs the first trigger signal. When the ARM layer is in the ARM layer bypass mode, the hardware circuit 200 switches from the ARM layer to the trigger layer.

[0087] If the second count value does not reach the second preset value, the hardware circuit 200 is configured as a trigger layer. When the trigger layer is in the normal trigger layer mode, it can receive the second trigger event. When it receives the second expected trigger source signal, it outputs the second trigger signal. When the trigger layer is in the trigger bypass mode, it generates an execution signal and outputs it to the execution layer 400.

[0088] Specifically, during counting, when the signal channel switches from an idle state to a ready state, the first count value is initialized to the first initial value. That is, the first count value is generated based on the first initial value. When the hardware circuit 200 switches from the ARM layer to the trigger layer, the second count value is initialized to the second initial value. That is, the second count value is generated based on the second initial value.

[0089] In this embodiment, the first initial value can be, but is not limited to, 0. The first count value is incremented by 1 each time it is generated. That is, at the ARM layer, when the trigger logic processing module 100 determines that the ARM layer's operating mode is ARM layer bypass mode, it triggers a trigger counter, incrementing the current first count value by 1. When the ARM layer is in ARM layer normal mode, the ARM layer needs to wait for the first trigger event. Upon receiving the first expected trigger source signal, the current first count value is incremented by 1. For example, if the current first count value is the first initial value, then 1 is added to 0, making the first count value 1. In the next count, the current first count value will be 1. Of course, the first initial value can also be other values, and the incremented value during counting can also be other values, which will not be elaborated upon here.

[0090] Similarly, the second initial value can be, but is not limited to, 0. When generating the second count value, it increments by 1 each time. That is, in the trigger layer, when the trigger logic processing module 100 determines that the trigger layer's operating mode is trigger layer bypass mode, it triggers the trigger counter once, incrementing the current second count value by 1. When the trigger layer is in trigger layer normal mode, the trigger layer needs to wait for the second trigger event. When the second expected trigger source signal is received, the current second count value is incremented by 1. For example, if the current second count value is the second initial value, then it is incremented by 1 from 0, and the second count value becomes 1. In the next count, the current second count value will be 1. Of course, the second initial value can also be other values, and the value incremented each time during counting can also be other values, which will not be elaborated further here.

[0091] In some embodiments, the first preset value and the second preset value can be configured in the trigger logic processing module 100 according to the actual situation. After each predetermined operation is completed, the execution layer 400 first determines whether the second count value has reached the second preset value. If the second count value has not reached the second preset value, the hardware circuit 200 is configured as the trigger layer again, and the determination of the working mode of the trigger layer is restarted. When the working mode of the trigger layer is the trigger layer bypass mode, the current second count value is incremented by 1, enters the execution layer 400, and outputs an execution signal to the execution layer 400 so that the execution layer 400 performs the predetermined operation. When the working mode of the trigger layer is the trigger layer normal mode, it waits for the arrival of the second expected trigger source signal. After the arrival, the current second count value is incremented by 1, and the second trigger signal is output to the trigger logic processing module 100 so that the trigger logic processing module 100 outputs an execution signal to the execution layer 400 so that the execution layer 400 performs the predetermined operation. If the second count value reaches the second preset value, the trigger logic processing module 100 determines whether the first count value has reached the first preset value. If the first count value reaches the first preset value, the signal channel switches from the ready state to the idle state, indicating that the current task has been completed and is waiting for the next start. If the first count value has not reached the first preset value, the hardware circuit 200 is switched to the ARM layer. Starting from determining the working mode of the ARM layer, when the working mode of the ARM layer is the ARM layer bypass mode, the current first count value is incremented by 1. When the working mode of the ARM layer is the ARM layer normal mode, it waits for the arrival of the first expected trigger source signal. After the signal arrives, the current first count value is incremented by 1, and the first trigger signal is output to the trigger logic processing module 100. The trigger logic processing module 100 responds to the first trigger signal by configuring the hardware circuit 200 as the trigger layer, causing the trigger layer to start operating. Thus, it can be seen that in the application process, when the second count value reaches the second preset value and the first count value reaches the first preset value, the triggering system can automatically stop triggering, further simplifying and facilitating operation.

[0092] In some embodiments, the execution layer 400 is further configured to output a pre-execution indication signal before the predetermined operation is executed, and to output a post-execution indication signal after the predetermined operation is executed; such as Figure 1As shown, the signal channel also includes a status indication module 300; the status indication module 300 is connected to the trigger logic processing module 100, and the trigger logic processing module 100 is further configured to: when the ARM layer outputs an enable signal, output a first status indication signal to the status indication module 300 in response to a first trigger signal, so that the status indication module 300 outputs an ARM layer action feedback signal when it receives the expected first status indication signal; and when the trigger layer outputs an enable signal, output a second status indication signal to the status indication module 300 in response to a second trigger signal, so that the status indication module 300 outputs an ARM layer action feedback signal when it receives the expected first status indication signal; and when the trigger layer outputs an enable signal, output a second status indication signal to the status indication module 300 in response to a second trigger signal, so that the status indication module 300 outputs an ARM layer action feedback signal when it receives the expected first status indication signal. When the second state indication signal is received, a trigger layer action feedback signal is output; when the execution layer 400 outputs an enable signal, a third state indication signal is output to the state indication module 300 in response to the pre-execution indication signal, so that the state indication module 300 outputs a pre-execution feedback signal when it receives the expected third state indication signal; when the execution layer 400 outputs an enable signal, a fourth state indication signal is output to the state indication module 300 in response to the post-execution indication signal, so that the state indication module 300 outputs a post-execution feedback signal when it receives the expected fourth state indication signal.

[0093] In some embodiments, the status indication module 300 may be, but is not limited to, an output trigger source arbitrator, which is connected to the trigger logic processing module 100. When the hardware circuit 200 is configured as an ARM layer, if the ARM layer outputs an enable signal, the selection signal of the output trigger source arbitrator is configured to be the expected first status indication signal, so that an ARM layer feedback signal is output when the expected first status indication signal is received. When the hardware circuit 200 is configured as a trigger layer, if the trigger layer outputs an enable signal, the selection signal of the output trigger source arbitrator is configured to be the expected second status indication signal, so that a trigger layer feedback signal is output when the expected second status indication signal is received. When execution layer 400 is active, if execution layer 400 outputs an enable signal, before execution layer 400 performs a predetermined operation, the selection signal of the output trigger source arbitrator is configured to the expected third state indication signal, so that upon receiving the expected third state indication signal, execution layer 400 outputs a pre-action feedback signal; after execution layer 400 performs the predetermined operation, the selection signal of the output trigger source arbitrator is configured to the expected fourth state indication signal, so that upon receiving the expected fourth state indication signal, execution layer 400 outputs a post-action feedback signal. Therefore, the current running process of the triggering system can be determined based on the feedback signal output by the output trigger source arbitrator, i.e., whether the first expected trigger source signal is received at the ARM layer; whether the second expected trigger source signal is received at the trigger layer; and whether the predetermined action has been executed at execution layer 400.

[0094] In some embodiments, the feedback signals output by the output trigger source arbitrator (ARM layer feedback signal, trigger layer feedback signal, pre-action feedback signal of execution layer 400, and post-action feedback signal of execution layer 400) can be output to the outside via a physical port, enabling collaborative operation with external devices. Alternatively, they can be output to the input trigger source arbitrator in another signal channel via a physical port, allowing collaborative operation between signal channels. They can also be directly output to the trigger logic processing module 100, which then outputs the feedback signals to the input trigger source arbitrator in another signal channel, enabling collaborative operation between signal channels. Compared to outputting feedback signals to the input trigger source arbitrator in another signal channel via a physical port, outputting feedback signals via the trigger logic processing module 100 eliminates the need for external cables, thus improving reliability.

[0095] In some embodiments, the execution layer 400 may include an excitation output module and / or a measurement acquisition module 402; the excitation output module is configured to output an excitation signal to the device under test after receiving an execution signal; the measurement acquisition module 402 is configured to acquire measurement data output by the device under test after receiving an execution signal.

[0096] Specifically, the execution layer 400 includes an excitation output module and a measurement acquisition module 402. When the predetermined operation is to output an excitation signal to the device under test, the logic processing module 100 is triggered to output an execution signal to the excitation output module, so that the excitation output module outputs an excitation signal. When the predetermined operation is to acquire the measurement data output by the device under test, the logic processing module 100 is triggered to output an execution signal to the measurement acquisition module 402, so that the measurement acquisition module 402 outputs the acquired measurement data output by the device under test.

[0097] In some embodiments, the excitation output module and the measurement acquisition module 402 can be turned on simultaneously in the same signal channel, that is, the excitation transmission module and the measurement acquisition module 402 can both operate; or the excitation output module or the measurement acquisition module 402 can be turned on separately, that is, the excitation transmission module or the measurement acquisition module 402 can both operate.

[0098] To further understand the triggering system for the source table provided in this application, a specific usage process will be used to illustrate it again, such as... Figure 2 , Figure 3 and Figure 4 As shown, the details are as follows:

[0099] Step 1: Configure the parameters of the triggering system. The configured parameters include the parameters of the ARM layer, the parameters of the trigger layer, and the parameters of the execution layer 400. Among them, the parameters of the ARM layer include the working mode of the ARM layer, the first preset value, whether the ARM layer outputs enable, the first expected trigger source signal, the delay time, and the timing time. The parameters of the trigger layer include the working mode of the trigger layer, the second preset value, whether the trigger layer outputs enable, the second expected trigger source signal, the delay time, and the timing time. The parameters of the execution layer 400 include the scheduled operation and whether the execution layer 400 outputs enable.

[0100] Step 2: When the user performs an operation on the source table, the signal channel switches from the idle state to the ready state in response to the user's operation.

[0101] Step 3: The trigger logic processing module 100 configures the hardware circuit 200 as the ARM layer, configures the parameters of the hardware circuit 200 as the parameters of the ARM layer, and resets the trigger counter.

[0102] Step 4: When the ARM layer is in ARM layer bypass mode, the trigger counter is incremented by 1, switching hardware circuit 200 from the ARM layer to the trigger layer. When the ARM layer is in ARM layer normal mode, the input trigger source arbitrator waits for the first expected trigger source signal. When the first expected trigger source signal arrives, the trigger counter is incremented by 1, switching hardware circuit 200 from the ARM layer to the trigger layer. The trigger logic processing module 100 records the current first count value. When the ARM layer outputs enable, the trigger logic processing module 100 outputs a first status indication signal to the output source trigger arbitrator. When the ARM layer does not output enable, it does not output a first status indication signal to the output source trigger arbitrator.

[0103] Step 5: After entering the trigger layer, reset the trigger counter to zero.

[0104] Step 6: When the trigger layer is in trigger layer bypass mode, the trigger counter increments by 1, and the system enters execution layer 400. When the trigger layer is in trigger layer normal mode, the input trigger source arbitrator waits for the second expected trigger source signal. When the second expected trigger source signal arrives, the trigger counter increments by 1, and the system enters execution layer 400. The trigger logic processing module 100 records the current second count value. When the trigger layer outputs enable, the trigger logic processing module 100 outputs a second status indication signal to the output source trigger arbitrator. When the trigger layer does not output enable, no second status indication signal is output. After entering execution layer 400, when execution layer 400 outputs enable, before executing the predetermined operation, the trigger logic processing module 100 outputs a third status indication signal to the output trigger source arbitrator. After executing the predetermined action, the trigger logic processing module 100 outputs a fourth status indication signal to the output trigger source arbitrator.

[0105] After the execution layer 400 performs the action, the trigger logic processing module 100 determines whether the second count value has reached the second preset value. If the second count value has reached the second preset value, it determines whether the first count value has reached the first preset value. If the first count value has reached the first preset value, the signal channel is switched from the ready state to the idle state. If the first count value has not reached the first preset value, the hardware circuit 200 is configured as the ARM layer, and the fourth, fifth and sixth steps are executed again in the ARM layer. If the second count value has not reached the second preset value, the trigger layer is re-entered and the sixth step is executed.

[0106] In one application scenario, a stepped sequence of voltages needs to be output from the source meter. When each execution signal arrives, it excites the output module to output voltage, and the output voltage increases by 1V. The physical characteristics of the chip and other components within 1 second under different voltages (such as voltage drop, current or resistance across the components) can be measured by the measurement and acquisition modules 402 (i.e. CH1_ACQ / CH2_ACQ) in the other two signal channels. First, the trigger logic processing module 100 in the current signal channel outputs a feedback signal before the execution layer 400 operates to one of the other two signal channels (CH1_ACQ). The measurement and acquisition module 402 of this signal channel performs 1000 measurements at a time interval of 1ms. Then, the trigger logic processing module 100 in the current signal channel outputs a feedback signal after the execution layer 400 operates to the other signal channel (CH2_ACQ). That is, after outputting the sequence voltage, the feedback signal after the execution layer 400 operates is output to the other signal channel. The measurement and acquisition module 402 of this other signal channel performs 1000 measurements at a time interval of 1ms. When this other signal channel has completed 1000 measurements, it exits from the trigger layer to the ARM layer and outputs a trigger layer operation feedback signal. This trigger layer operation feedback signal serves as the trigger signal for the next sequence step voltage output. This cycle continues until the output step sequence trigger ends or the trigger system is manually turned off, thus realizing the characteristic measurement of the component. In this scenario, CH1_ACQ is used to measure the process of a component changing voltage from static to dynamic, while CH2_ACQ is used to measure the physical characteristics of the component after the voltage output has stabilized. Compared to measuring using only the current channel, this reduces the amount of data processing, avoids invalid data, and ensures accurate measurement of valid data (measuring using only the current channel results in a large amount of data, most of which is repetitive and a lot of useless data).

[0107] In some embodiments, the triggering system is constructed using an FPGA (Field-Programmable Gate Array). Specifically, the hardware circuit 200, the trigger logic processing module 100, the status indication module 300, the source output module 401, and the measurement acquisition module 402 are all implemented by the hardware circuitry within the FPGA.

[0108] In some embodiments, this application also provides a source table, including the triggering system for the source table as described above. Specific implementations are as described in the specific embodiment of the triggering system for the source table above, and will not be elaborated further here.

[0109] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A trigger system for a source table, the trigger system comprising: include: Trigger logic processing module and at least one signal channel; The signal channel's operating state includes at least a ready state. The signal channel includes an ARM layer, a trigger layer, and an execution layer. The trigger logic processing module is connected to the ARM layer, the trigger layer, and the execution layer. The ARM layer's operating mode includes at least an ARM layer normal mode. The trigger layer's operating mode includes at least a trigger layer normal mode. When the signal channel is in the ready state: The ARM layer is configured to receive a first trigger event when it is in working state and the working mode is the normal mode of the ARM layer. The first trigger event includes multiple types of first trigger source signals. When the received first trigger event includes a first expected trigger source signal, a first trigger signal is output to the trigger logic processing module. The trigger logic processing module is configured to cause the trigger layer to enter the working state in response to the first trigger signal. The triggering layer is configured to receive a second triggering event when it is in working state and the working mode is the normal mode of the triggering layer. The second triggering event includes multiple types of second triggering source signals. When the second triggering event includes a second expected triggering source signal, the triggering layer outputs a second triggering signal to the triggering logic processing module. The triggering logic processing module is configured to generate an execution signal in response to the second triggering signal and output it to the execution layer. The execution layer is configured to perform a predetermined operation in response to the execution signal.

2. The trigger system for a source table of claim 1, wherein, The first triggering event includes: a first internal triggering source signal, a first bus triggering source signal, a first local area network triggering source signal, and a first external triggering source signal; and / or, the second triggering event includes: a second internal triggering source signal, a second bus triggering source signal, a second local area network triggering source signal, and a second external triggering source signal.

3. The trigger system for a source table of claim 2, wherein, The signal channel includes a hardware circuit, which is connected to the trigger logic processing module. The ARM layer and the trigger layer share the hardware circuit. When the ARM layer needs to enter the working state, the trigger logic processing module is also configured to configure the hardware circuit as the ARM layer; When the trigger layer needs to enter the working state, the trigger logic processing module is also configured to configure the hardware circuit as the trigger layer.

4. The trigger system for a source table of claim 3, wherein, The ARM layer's operating mode also includes an ARM layer bypass mode; the trigger layer's operating mode also includes a trigger layer bypass mode; When the ARM layer enters the working state and the working mode is the ARM layer bypass mode, the hardware circuit is configured to be switched to the trigger layer after entering the ARM layer; When the trigger layer enters the working state and the working mode is the trigger layer bypass mode, the trigger logic processing module generates the execution signal and outputs it to the execution layer.

5. The trigger system for a source table of claim 4, wherein, The hardware circuit includes: a signal selection unit, a trigger counting unit, and a timed trigger signal generation unit; the trigger logic processing module is connected to the signal selection unit, the trigger counting unit, and the timed trigger signal generation unit. When the hardware circuit is configured for the ARM layer: The signal selection unit is configured to receive the first trigger event when the ARM's operating mode is the ARM layer normal mode, and to output the first trigger signal to the trigger logic processing module when the first expected trigger source signal is received. The trigger counting unit is configured to increment the count once when the ARM layer's operating mode is determined to be the ARM layer's normal mode, and to increment the count once when the ARM layer's operating mode is determined to be the ARM layer's bypass mode, so as to generate a first count value and output it to the trigger logic processing module. The timing trigger signal generation unit is configured to generate a first internal trigger source signal in response to a first signal generation command and output it to the signal selection unit; When the hardware circuit is configured as the trigger layer: The signal selection unit is configured to receive the second trigger event when the working mode of the trigger layer is the normal mode of the trigger layer, and to output the second trigger signal to the trigger logic processing module when the second expected trigger source signal is received; The trigger counting unit is configured to increment the count once when the working mode of the trigger layer is determined to be the normal mode of the trigger layer, and to increment the count once when the working mode of the trigger layer is determined to be the bypass mode of the trigger layer, so as to generate a second count value and output it to the trigger logic processing module. The timing trigger signal generation unit is configured to generate a second internal trigger source signal in response to a second signal generation command, and output it to the signal selection unit; The trigger logic processing module is also configured to periodically generate the first signal generation instruction through parameter configuration and output it to the timed trigger signal generation unit; The trigger logic processing module is also configured to periodically generate the second signal generation instruction through parameter configuration and output it to the timed trigger signal generation unit.

6. The trigger system for a source table of claim 5, wherein, The working state of the signal channel also includes an idle state; The trigger logic processing module is further configured to: After the execution layer completes the predetermined operation, it is determined whether the second count value has reached the second preset value. If the second count value has reached the second preset value, it is determined whether the first count value has reached the first preset value. If the first count value has reached the first preset value, the signal channel is switched from the ready state to the idle state. If the first count value has not reached the first preset value, the hardware circuit is configured as the ARM layer. When the ARM layer is in the normal mode, it can receive the first trigger event and output the first trigger signal when it receives the first expected trigger source signal. When the ARM layer is in the bypass mode, the hardware circuit is switched from the ARM layer to the trigger layer. If the second count value does not reach the second preset value, the hardware circuit is configured as the trigger layer. When the trigger layer is in the normal trigger layer mode, it can receive the second trigger event and output the second trigger signal when it receives the second expected trigger source signal. When the trigger layer is in the bypass trigger layer mode, it generates the execution signal and outputs it to the execution layer.

7. The trigger system for a source table of claim 6, wherein, The signal channel switches from the idle state to the ready state in response to a user operation; When the signal channel switches from the idle state to the ready state, the first count value is reset to the first initial value; When the hardware circuit is switched from the ARM layer to the trigger layer, the second count value is reset to the second initial value.

8. The trigger system for a source table of claim 1 or 2, wherein, The execution layer is also configured to output a pre-execution indication signal before the predetermined operation is executed, and to output a post-execution indication signal after the predetermined operation is executed. The signal channel also includes a status indication module, which is connected to the trigger logic processing module. The trigger logic processing module is further configured to: When the ARM layer outputs an enable signal, a first state indication signal is output to the state indication module in response to the first trigger signal, so that the state indication module outputs an ARM layer action feedback signal when it receives the expected first state indication signal. When the trigger layer output is enabled, a second state indication signal is output to the state indication module in response to the second trigger signal, so that the state indication module outputs a trigger layer action feedback signal when it receives the expected second state indication signal. When the execution layer outputs an enable signal, a third state indication signal is output to the state indication module in response to the pre-execution indication signal, so that the state indication module outputs a pre-execution feedback signal when it receives the expected third state indication signal. When the execution layer output is enabled, a fourth state indication signal is output to the state indication module in response to the post-execution indication signal, so that the state indication module outputs a post-execution feedback signal when it receives the expected fourth state indication signal.

9. The trigger system for a source table of claim 1 or 2, wherein, The execution layer includes: an excitation output module and / or a measurement acquisition module; The excitation output module is configured to output an excitation signal to the device under test after receiving the execution signal; The measurement acquisition module is configured to acquire measurement data output by the device under test after receiving the execution signal.

10. A source table, comprising: Includes the triggering system for the source table as described in any one of claims 1-9.

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