Method, device and interface circuit for parallel output of multiple paths of serial data

Abstract

The invention relates to the technical field of digital signal processing and integrated circuits, and provides a method and device for parallel output of multiple paths of serial data and an interface circuit. The method comprises the following steps: transmitting a plurality of data and at least one clock associated with the plurality of data through a plurality of data paths; generating a plurality of effective mark signals in one-to-one correspondence with the plurality of effective data, and generating a plurality of groups of selection control signals in one-to-one correspondence with the plurality of output interfaces based on respective data identifiers and mapping relationships of the plurality of effective data; data signal selectors, clock signal selectors and enable signal selectors respectively associated with the plurality of output interfaces are respectively controlled through a plurality of groups of selection control signals. Therefore, resource occupation and circuit area consumption are reduced, and reliability and real-time performance of data output are improved.

Description

Technical Field

[0001] This application relates to the fields of digital signal processing and integrated circuit technology, and in particular to a method, apparatus and interface circuit for parallel output of multiple serial data. Background Technology

[0002] With the development of large-scale artificial intelligence models and high-speed digital communication technologies, higher demands are placed on high-performance memory and high-performance data transmission, often requiring the decoding of multiple serial data streams to achieve large-scale parallel output. Multiple serial data streams transmitted according to high-speed serial data transmission standards, such as serializers / deserializers (SERDES) and Peripheral Component Interconnect Express (PCIe), are parsed and used for parallel output, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) and High Bandwidth Memory (HBM). The data senders may come from different devices, such as different PCIe devices, or from different machines, such as devices interconnected via SERDES technology. This means that different clock frequencies may exist between the multiple serial data streams, and frequency and phase differences may also exist from the sender of the multiple serial data streams to the receiver used for parallel output. Therefore, in applications involving parallel output of multiple serial data streams, a challenge is how to overcome the frequency and phase differences that may exist in cross-clock domain data transmission. One existing solution uses asynchronous First-In-First-Out (FIFO) memory to absorb frequency and phase differences. However, this requires a separate asynchronous FIFO for each serial data path, leading to high storage resource requirements in large-scale parallel output applications. Another challenge in multi-channel serial output parallel scenarios is achieving configurable mapping between output interfaces and data. For example, where one output interface originally corresponded to one serial data path, it needs to be changed to correspond to another. One existing solution stores all data in registers and uses combinational logic switching circuits to achieve configurable mapping between any output interface and any data path. However, this requires significant storage resources, complex combinational logic circuits for cross-clock domain signal transmission, and support for complex cross-clock synchronization or clock switching mechanisms. Furthermore, as the number of output interfaces and data paths increases, resource consumption and circuit area increase accordingly. In particular, the size of the combinational logic circuit is proportional to the product of the number of output interfaces and the amount of data, introducing metastability risks and increasing overall latency.

[0003] To this end, this application provides a method, apparatus and interface circuit for parallel output of multiple serial data, which not only effectively reduces resource consumption and circuit area consumption, but also effectively overcomes the frequency difference and phase difference problems of cross-clock domain signal transmission. It does not require a complex cross-clock synchronization processing mechanism or clock switching mechanism, which helps to reduce the cross-clock transmission risk and metastability risk caused by large-scale combinational logic, and is conducive to improving the reliability and real-time performance of data output. Summary of the Invention

[0004] In one aspect, this application provides a method for parallel output of multiple serial data streams. The method includes: transmitting multiple data and at least one clock associated with the multiple data through multiple data paths, wherein the multiple data includes multiple valid data, the maximum number of the multiple valid data is not higher than the number of multiple output interfaces, and a mapping relationship indicates that the multiple valid data are separately and non-repeatingly assigned to the multiple output interfaces; generating multiple valid flag signals corresponding one-to-one with the multiple valid data; and generating multiple sets of selection control signals corresponding one-to-one with the multiple output interfaces based on the data identifiers of the multiple valid data and the mapping relationship, wherein the timing relationship between the valid level segments of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data, and each set of selection control signals consists of a data selection signal, a clock selection signal, and an enable selection signal; and controlling the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces respectively through the multiple sets of selection control signals, wherein the multiple data paths serve as inputs to the data signal selector and clock signal selector associated with each of the multiple output interfaces, and the multiple valid flag signals serve as inputs to the enable signal selector associated with each of the multiple output interfaces.

[0005] The first aspect of this application not only effectively reduces resource consumption and circuit area consumption, but also effectively overcomes the frequency difference and phase difference problems of cross-clock domain signal transmission. It does not require complex cross-clock synchronization processing mechanisms or clock switching mechanisms, which helps to reduce the cross-clock transmission risk and metastability risk caused by large-scale combinational logic, and is conducive to improving the reliability and real-time performance of data output.

[0006] In one possible implementation of the first aspect of this application, the given output interface is any one of the plurality of output interfaces, the given selection control signal in the plurality of selection control signals corresponds to the given output interface, the data selection signal of the given selection control signal is used to control the data signal selector associated with the given output interface to select from the plurality of data paths a data signal line for transmitting a given valid data allocated to the given output interface, the clock selection signal of the given selection control signal is used to control the clock signal selector associated with the given output interface to select from the plurality of data paths a clock signal line for transmitting a given clock associated with the given valid data, and the enable selection signal of the given selection control signal is used to control the enable signal selector associated with the given output interface to select from the plurality of valid flag signals a given valid flag signal corresponding to the given valid data.

[0007] In one possible implementation of the first aspect of this application, the output of the enable signal selector associated with the given output interface is used to enable or disable the output of the clock signal selector associated with the given output interface, thereby obtaining the register clock signal associated with the given output interface, and the register clock signal associated with the given output interface is used to trigger the output of the data signal selector associated with the given output interface.

[0008] In one possible implementation of the first aspect of this application, the output of the enable signal selector associated with the given output interface serves as the input to the control terminal of the latch circuit associated with the given output interface, the output of the clock signal selector associated with the given output interface serves as the input to the signal terminal of the latch circuit associated with the given output interface, and the register clock signal associated with the given output interface is the output of the latch circuit associated with the given output interface.

[0009] In one possible implementation of the first aspect of this application, the output of the enable signal selector associated with the given output interface serves as the input to the control terminal of the gating circuit associated with the given output interface, the output of the clock signal selector associated with the given output interface serves as the input to the signal terminal of the gating circuit associated with the given output interface, and the register clock signal associated with the given output interface is the output of the gating circuit associated with the given output interface.

[0010] In one possible implementation of the first aspect of this application, the register clock signal associated with the given output interface serves as the input to the control terminal of the trigger circuit associated with the given output interface, and the output of the data signal selector associated with the given output interface serves as the input to the signal terminal of the trigger circuit associated with the given output interface.

[0011] In one possible implementation of the first aspect of this application, the trigger circuit associated with the given output interface has a storage function and can be used to store data with a maximum data bit width not less than the plurality of valid data, and the data signal selector associated with the given output interface has a dynamic output function and can be used to adapt to the maximum data bit width of the plurality of valid data.

[0012] In one possible implementation of the first aspect of this application, the output of the clock signal selector associated with the given output interface is enabled when the output of the enable signal selector associated with the given output interface is at a valid level segment of the given valid flag signal, and the output of the clock signal selector associated with the given output interface is disabled when the output of the enable signal selector associated with the given output interface is not at a valid level segment of the given valid flag signal.

[0013] In one possible implementation of the first aspect of this application, the effective level segment of the given valid flag signal is a high level that lasts for one or more clock cycles.

[0014] In one possible implementation of the first aspect of this application, the at least one clock is a single clock, and the plurality of valid data share the single clock.

[0015] In one possible implementation of the first aspect of this application, the at least one clock includes a plurality of clocks corresponding one-to-one with the plurality of valid data, and the frequencies of the plurality of clocks are all different.

[0016] In one possible implementation of the first aspect of this application, the valid data allocated to each of the plurality of output interfaces is stored in the respective output registers of the plurality of output interfaces, the respective output registers of the plurality of output interfaces are used to output the plurality of valid data in parallel based on a global output clock, and the update order among the respective output registers of the plurality of output interfaces is consistent with the data transmission order among the plurality of valid data.

[0017] In one possible implementation of the first aspect of this application, the plurality of selection control signals are generated by a selection signal generation module, which may be configured to not generate a selection control signal corresponding to at least one of the plurality of output interfaces, or the output of a data signal selector associated with the at least one output interface is used as an input to a D flip-flop and the reset signal of the D flip-flop is kept active.

[0018] In one possible implementation of the first aspect of this application, the plurality of data belongs to the current batch, and the next batch relative to the current batch is transmitted through the plurality of data paths so as to be output in parallel by the plurality of output interfaces, and the data transmission of the next batch begins at least after the data transmission of the current batch is completed.

[0019] In one possible implementation of the first aspect of this application, the method further includes: changing the mapping relationship at least after the current batch of data transmission is completed and before the next batch of data transmission.

[0020] In one possible implementation of the first aspect of this application, the plurality of data belongs to the current batch of a plurality of batches, the plurality of batches are transmitted respectively through the plurality of data paths so as to be output in parallel by the plurality of output interfaces respectively, the data of each of the plurality of batches includes a corresponding batch identifier, and the plurality of output interfaces are used to output all valid data of the same batch of the plurality of batches in parallel based on the batch identifier of the data of each of the plurality of batches and a global output clock.

[0021] In one possible implementation of the first aspect of this application, data transmission of the next batch relative to the current batch begins before the data transmission of the current batch is completed.

[0022] In one possible implementation of the first aspect of this application, the plurality of data paths are further configured to transmit at least one enable signal associated with the plurality of data, wherein a valid flag signal corresponding to valid data associated with the at least one enable signal is generated based on the at least one enable signal.

[0023] Secondly, this application provides an apparatus for parallel output of multiple serial data streams. The apparatus includes: a selection signal generation module, wherein the selection signal generation module generates multiple valid flag signals corresponding one-to-one with multiple valid data streams, the timing relationship between the valid level segments of each of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data streams, multiple data paths are used to transmit multiple data streams and at least one clock associated with the multiple data streams, the multiple data streams include the multiple valid data streams, the maximum number of the multiple valid data streams is not higher than the number of multiple output interfaces, and the mapping relationship stored in the selection signal generation module indicates that the multiple valid data streams are separately and non-repeatedly allocated to the multiple output interfaces; and the multiple output interfaces. Each output interface has its own associated data signal selector, clock signal selector, and enable signal selector. The selection signal generation module is further configured to generate multiple sets of selection control signals corresponding one-to-one with the multiple output interfaces based on the data identifiers of the multiple valid data and the mapping relationship. The multiple sets of selection control signals control the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces, respectively. The multiple data paths serve as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals serve as inputs to the enable signal selectors associated with each of the multiple output interfaces.

[0024] The second aspect of this application not only effectively reduces resource consumption and circuit area consumption, but also effectively overcomes the frequency difference and phase difference problems of cross-clock domain signal transmission. It does not require complex cross-clock synchronization processing mechanisms or clock switching mechanisms, which helps to reduce the cross-clock transmission risk and metastability risk caused by large-scale combinational logic, and is conducive to improving the reliability and real-time performance of data output.

[0025] Thirdly, this application provides an interface circuit. The interface circuit includes: multiple output interfaces, wherein the multiple output interfaces are used for parallel output of multiple serial data, multiple data paths are used for transmitting multiple data and at least one clock associated with the multiple data, the multiple data includes multiple valid data as the multiple serial data, the maximum number of the multiple valid data is not higher than the number of the multiple output interfaces, and a mapping relationship stored in a selection signal generation module indicates that the multiple valid data are separately and non-repeatingly allocated to the multiple output interfaces; the selection signal generation module is used to generate multiple valid flag signals corresponding one-to-one with the multiple valid data, the timing relationship between the valid level segments of each of the multiple valid flag signals is related to the multiple valid data... The timing relationship between the valid data is consistent; and the data signal selector, clock signal selector, and enable signal selector associated with each of the plurality of output interfaces, wherein the selection signal generation module is further configured to generate multiple sets of selection control signals corresponding one-to-one with the plurality of output interfaces based on the data identifiers of the plurality of valid data and the mapping relationship, and the multiple sets of selection control signals respectively control the data signal selector, clock signal selector, and enable signal selector associated with each of the plurality of output interfaces, the plurality of data paths serving as inputs to the data signal selector and clock signal selector associated with each of the plurality of output interfaces, and the plurality of valid flag signals serving as inputs to the enable signal selector associated with each of the plurality of output interfaces.

[0026] The third aspect of this application not only effectively reduces resource consumption and circuit area consumption, but also effectively overcomes the frequency difference and phase difference problems of cross-clock domain signal transmission. It does not require complex cross-clock synchronization processing mechanisms or clock switching mechanisms, which helps to reduce the cross-clock transmission risk and metastability risk caused by large-scale combinational logic, and is conducive to improving the reliability and real-time performance of data output. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram illustrating an application scenario of parallel output of multiple serial data streams. Figure 2 This is a schematic diagram illustrating another application scenario of parallel output of multiple serial data streams. Figure 3A flowchart illustrating a method for parallel output of multiple serial data channels, provided as an embodiment of this application; Figure 4 A signal timing diagram of the output interface provided in the first embodiment of this application; Figure 5 A signal timing diagram of the output interface provided in the second embodiment of this application; Figure 6 Signal timing diagram of the output interface provided in the third embodiment of this application; Figure 7 A schematic diagram of a data signal selector, a clock signal selector, and an enable signal selector associated with an output interface provided in an embodiment of this application; Figure 8 A schematic diagram illustrating the data transmission of multiple batches according to a first embodiment of this application; Figure 9 A schematic diagram illustrating the data transmission of multiple batches according to a second embodiment provided in this application. Figure 10 A schematic diagram of an apparatus for parallel output of multiple serial data channels provided in an embodiment of this application; Figure 11 This is a schematic diagram of an interface circuit provided in an embodiment of this application. Detailed Implementation

[0029] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0030] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0031] Figure 1 This is a schematic diagram illustrating an application scenario involving parallel output of multiple serial data streams. For example... Figure 1 As shown, sender A101 sends multiple serial data streams to receiver A103. Figure 1The example illustrates multiple serial data streams including a first serial data stream, a second serial data stream, a third serial data stream, and a fourth serial data stream. It should be understood that the number of serial data streams is arbitrary and not limited here. Then, the receiver A103 converts the received serial data streams into multiple parallel outputs. In applications such as large-scale artificial intelligence models and high-speed digital communication, such as high-performance memory and high-performance data transmission, it is often necessary to decode multiple serial data streams to achieve large-scale parallel output. The party providing the multiple serial data streams can be considered the sender, for example... Figure 1 In the example, the sender A101, and the party that receives multiple serial data streams and implements large-scale parallel output, can be considered the receiver, for example... Figure 1 The receiver is A103. Multiple serial data streams can refer to any suitable high-speed serial data transmission standard, such as serializer / deserializer (SERDES) and Peripheral Component Interconnect Express (PCIe). After parsing, the multiple serial data streams are used for parallel output, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) and High Bandwidth Memory (HBM). Generally, multiple serial data streams transmitted from the same sender use the same clock domain; however, the sender and receiver may use the same clock domain or different clock domains, for example... Figure 1In this scenario, the sender A101 and receiver A103 may each use the same or different clock signal frequencies. Therefore, in applications with multiple serial outputs and parallel outputs, a challenge is overcoming the frequency and phase differences that may arise from cross-clock domain data transmission. When the clock frequency used by sender A101 to coordinate the transmission of multiple serial data differs from the clock frequency used by receiver A103 to coordinate the parallel output, receiver A103 needs to process the received serial data to ensure the correctness and reliability of cross-clock domain signal transmission. If an asynchronous First-In-First-Out (FIFO) memory is used to absorb the frequency and phase differences, it means using sender A101's clock signal at the write end of the asynchronous FIFO and receiver A103's clock signal at the read end. This can meet the requirements for cross-clock domain signal transmission; however, this requires a separate asynchronous FIFO for each serial data stream. As the scale of multi-serial data transmission increases, and receiver A103 needs to meet the requirements of large-scale parallel output, the asynchronous FIFO solution leads to high storage resource requirements. In applications with multiple serial and parallel outputs, another challenge is achieving configurable mapping between output interfaces and data. For example, where one output interface originally corresponded to one serial data path, it needs to be changed to correspond to another serial data path. To achieve this configurable mapping, it's necessary to implement arbitrary mapping relationships between M output interfaces and S data paths, totaling N data points. If all data is stored in registers and combinational logic switching circuits are used to achieve this configurable mapping, it requires significant storage resources, complex combinational logic circuits for cross-clock domain signal transmission, and support for complex cross-clock synchronization or clock switching mechanisms. Furthermore, as the number of output interfaces and data paths increases, resource consumption and circuit area increase accordingly. The size of the combinational logic circuit is directly proportional to the product of the number of output interfaces and the amount of data (M multiplied by N multiplied by the data bit width), introducing metastability risks and increasing overall latency. Figure 1 The exemplary application scenario of parallel output of multiple serial data channels only shows the case of a single sender. However, there may be multiple senders of multiple serial data channels, and the data senders may come from different devices, such as different PCIe devices, or from different machines, such as devices interconnected via SERDES technology. This means that there may be different clock frequencies between the multiple serial data channels. The following section will discuss this further. Figure 2 Let me explain in more detail.

[0032] Figure 2 This is a schematic diagram illustrating another application scenario involving parallel output of multiple serial data streams. For example... Figure 2 As shown, sender B210 sends the first and second serial data streams to receiver B220, sender C212 sends the third serial data stream to receiver B220, and sender D214 sends the fourth serial data stream to receiver B220. Receiver B220 converts the received serial data streams into multiple parallel outputs. (Reference) Figure 1 and Figure 2 , Figure 1 There is only one sender in the system. Generally, multiple serial data sent from the same sender use the same clock domain. However, the sender and receiver may use the same clock domain or different clock domains. Figure 2 There are multiple transmitters, which may use the same clock domain or different clock domains. This means that there may be different clock frequencies between multiple serial data streams, and there may also be frequency and phase differences from the transmitters of the multiple serial data streams to the receivers used for parallel output. For example, transmitters B210 and C212 may use different clock domains, which could lead to frequency and phase differences between the first and third serial data streams, increasing the difficulty for receiver B220 to implement a multi-channel parallel output scheme. Multiple transmitters may be different devices, machines, computing nodes, etc., such as different PCIe devices or devices interconnected via SERDES technology. Therefore, in applications involving parallel output of multiple serial data streams, such as large-scale artificial intelligence models and high-speed digital communication, it is necessary to overcome both the challenges of frequency and phase differences in cross-clock domain data transmission and the challenge of configurable mapping between arbitrary output interfaces and arbitrary data paths. The following describes, with reference to specific embodiments of this application, how the method, apparatus and interface circuit provided in this application for parallel output of multi-channel serial data realizes cross-clock domain data transmission and configurable mapping between arbitrary output interfaces and arbitrary data paths. This not only effectively reduces resource consumption and circuit area consumption, but also effectively overcomes the frequency difference and phase difference problems of cross-clock domain signal transmission. It does not require complex cross-clock synchronization processing mechanisms or clock switching mechanisms, which helps to reduce the cross-clock transmission risk and metastability risk caused by large-scale combinational logic, and is conducive to improving the reliability and real-time performance of data output.

[0033] Figure 3 This is a flowchart illustrating a method for parallel output of multiple serial data streams, provided as an embodiment of this application. Figure 3 As shown, the method includes the following steps.

[0034] Step S301: Transmit multiple data and at least one clock associated with the multiple data through multiple data paths, wherein the multiple data includes multiple valid data, the maximum number of the multiple valid data is not higher than the number of multiple output interfaces, and the mapping relationship indicates that the multiple valid data are allocated to the multiple output interfaces separately and without repetition.

[0035] Step S303: Generate multiple valid flag signals corresponding one-to-one with the multiple valid data, and, based on the data identifiers of the multiple valid data and the mapping relationship, generate multiple sets of selection control signals corresponding one-to-one with the multiple output interfaces, wherein the timing relationship between the valid level segments of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data, and each set of selection control signals consists of a data selection signal, a clock selection signal, and an enable selection signal.

[0036] Step S305: Control the data signal selector, clock signal selector and enable signal selector associated with each of the multiple output interfaces respectively through the multiple sets of selection control signals, and the multiple data paths serve as inputs to the data signal selector and clock signal selector associated with each of the multiple output interfaces, and the multiple valid flag signals serve as inputs to the enable signal selector associated with each of the multiple output interfaces.

[0037] See Figure 3 Multiple data streams and at least one associated clock are transmitted through multiple data paths. To achieve parallel output, a single clock is typically used to coordinate the parallel output of multiple interfaces. Since the multiple data streams transmitted through these paths may use the same or different clocks, at least one clock is transmitted through multiple data paths. Furthermore, more than one data signal line may share the same clock signal line. For example, assuming there are eight data signal lines, DQ0 to DQ7, DQ0 to DQ3 might share CLK0, DQ4 and DQ5 might share CLK1, DQ6 might use CLK2, and DQ7 might use CLK3. Therefore, the correspondence between data signal lines and clock signal lines is difficult to determine definitively. This means that various data and clock configurations may exist between multiple serial data streams, necessitating sufficiently high flexibility in the parallel output to accommodate these configurations. (See also...) Figure 1 and Figure 2As can be seen, if there is only one sender, generally, multiple serial data transmitted from the same sender use the same clock domain. However, the sender and receiver may use the same clock domain or different clock domains. If there are multiple senders, they may use the same clock domain or different clock domains. This means that there may be different clock frequencies between multiple serial data streams, and there may also be frequency and phase differences from the sender of the multiple serial data streams to the receiver used for parallel output. Therefore, the method for parallel output of multiple serial data streams provided in this application can not only meet the requirements for parallel output of multiple serial data streams within the same clock domain, but also meet the requirements for parallel output of multiple serial data streams across clock domains under a single clock domain, and also meet the requirements for parallel output of multiple serial data streams across clock domains under multiple clock domains.

[0038] See Figure 3To achieve arbitrary mapping relationships between M output interfaces and a total of N data points across S data paths, two important design constraints are proposed. One constraint is that the maximum number of valid data points does not exceed the number of output interfaces, and the mapping relationship indicates that the valid data points are allocated to the output interfaces separately and without repetition. Therefore, given M output interfaces and N valid data points, N must not exceed M. Furthermore, by limiting N to no more than M, the mapping relationship constructs a non-repeating allocation of N valid data points to M output interfaces. Thus, two valid data points will necessarily be allocated to different output interfaces, and the same output interface will not be allocated more than one valid data point. When N is less than M, some output interfaces may not be allocated valid data. Moreover, under this design constraint (the maximum number of valid data points does not exceed the number of output interfaces, and the mapping relationship indicates that the valid data points are allocated to the output interfaces separately and without repetition), the sending side needs to process the data to be sent in batches, ensuring that the maximum number of valid data points in each batch does not exceed the number of output interfaces. This can be achieved through counters and data validity checks, such as filtering out invalid data and controlling the size of each batch of data sent. It can be seen that to increase the maximum number of valid data in each batch, it may be necessary to increase the number of multiple output interfaces. That is, as N increases, to keep N no greater than M, it may be necessary to increase M accordingly. Considering that in practical applications, the number of multiple output interfaces on the receiving side for large-scale parallel output is generally fixed, for example, due to hardware limitations or the need to comply with data transmission protocol specifications, the number of valid data N can be limited based on the number of multiple output interfaces M. The mapping relationship is pre-defined, and any suitable algorithm or model can be used, as long as it can ensure that the multiple valid data are allocated to the multiple output interfaces separately and without repetition. In some embodiments, the non-repetitive allocation to multiple output interfaces can be achieved according to the order of data. For example, the mapping relationship can indicate that the first data is allocated to the first output interface, the second data to the second output interface, thus achieving non-repetitive allocation of multiple valid data to multiple output interfaces according to the order of valid data.

[0039] Continue reading Figure 3As mentioned above, one design constraint is that the maximum number of valid data items is no greater than the number of output interfaces, and the mapping relationship indicates that the valid data items are allocated to the output interfaces separately and without repetition. Another design constraint is to generate multiple valid flag signals corresponding one-to-one with the valid data items, and the timing relationship between the valid level segments of each of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data items. The timing relationship between the multiple valid data items indicates their order. Multiple valid data items are transmitted through multiple data paths. Only one valid data item can be transmitted on the same data path at a time, and two data paths may be transmitting valid data simultaneously. Therefore, there may be some overlap in the timing relationships of two valid data items, meaning that these two valid data items are transmitted through two separate data paths. Here, by generating multiple valid flag signals corresponding one-to-one with the multiple valid data items, and ensuring that the timing relationship between the valid level segments of each of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data items, the data transmission time period of the corresponding valid data can be identified by detecting the valid level segments of the valid flag signals. It should be understood that the specific definition of the valid level segment of the valid flag signal can be adjusted as needed. For example, a high level segment can be set as the valid level segment, or a low level segment can be set as the valid level segment. Although the accompanying drawings and other embodiments of this application use a high level segment as the valid level segment, the definition of the valid level segment of the valid flag signal should not be constrained by this. Instead, it should be more broadly understood as detecting the data transmission time period of the corresponding valid data by detecting the valid level segment, thereby identifying the timing relationship between multiple valid data.

[0040] Continue reading Figure 3Based on the two design constraints mentioned above, namely (1) the maximum number of valid data is no higher than the number of output interfaces, and the mapping relationship indicates that the valid data is allocated to the output interfaces separately and without repetition; and (2) multiple valid flag signals are generated corresponding one-to-one with the multiple valid data, and the timing relationship between the valid level segments of each of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data, through the optimized design combining hardware and software, a configurable mapping relationship can be realized from multiple valid data transmitted through multiple data paths to multiple output interfaces, and the frequency difference and phase difference between signals across clock domains can be effectively overcome. Specifically, at the software level, not only are multiple valid flag signals corresponding one-to-one with the multiple valid data generated, but also, based on the data identifiers of each of the multiple valid data and the mapping relationship, multiple sets of selection control signals corresponding one-to-one with the multiple output interfaces are generated. Here, each set of selection control signals consists of a data selection signal, a clock selection signal, and an enable selection signal. At the hardware level, data signal selectors, clock signal selectors, and enable signal selectors associated with each of the plurality of output interfaces are provided. Furthermore, through a combination of software and hardware levels, the data signal selectors, clock signal selectors, and enable signal selectors associated with each of the plurality of output interfaces are controlled separately by the plurality of sets of selection control signals. Therefore, for each of the plurality of output interfaces, the data selection signal in the selection control signal corresponding to that output interface controls the data signal selector associated with that output interface, the clock selection signal in the selection control signal corresponding to that output interface controls the clock signal selector associated with that output interface, and the enable selection signal in the selection control signal corresponding to that output interface controls the enable signal selector associated with that output interface. Further, the data signal selectors, clock signal selectors, and enable signal selectors associated with each of the plurality of output interfaces, under the action of the selection control signals corresponding to each of the plurality of output interfaces, select from their respective inputs and then output. Specifically, the plurality of data paths serve as inputs to the data signal selectors and clock signal selectors associated with each of the plurality of output interfaces, and the plurality of valid flag signals serve as inputs to the enable signal selectors associated with each of the plurality of output interfaces. Thus, combining the two design constraints mentioned above with the hardware and software design, it supports the implementation of arbitrary mapping relationships between M output interfaces and a total of N data points across S data paths. The following section will discuss this further. Figures 4 to 7 Further details.

[0041] See Figure 4 , Figure 4This is a signal timing diagram of the output interface provided in the first embodiment of this application. Taking two data paths as an example, the clock signal CLK0 corresponding to data path S0 and the clock signal CLK1 corresponding to data path S1 are shown respectively. Additionally, valid data D0, D1, and D2 transmitted through data path S0 are also shown. As described above, multiple valid flag signals are generated, each corresponding to one of the multiple valid data, and the timing relationship between the valid level segments of each of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data. Therefore, for valid data D0 and D1, a valid flag signal EN0 corresponding to valid data D0 and a valid data signal EN1 corresponding to valid data D1 are generated respectively. It can be seen that a high-level segment is used as the valid level segment, and the timing relationship between the valid level segment (high-level segment) of the valid flag signal EN0 corresponding to valid data D0 and the valid level segment (high-level segment) of the valid data signal EN1 corresponding to valid data D1 is consistent with the timing relationship between valid data D0 and valid data D1. As described above, based on the data identifiers of the various valid data and the mapping relationship, multiple sets of selection control signals are generated, each corresponding to one of the multiple output interfaces. The mapping relationship indicates that the multiple valid data are allocated to the multiple output interfaces separately and without repetition. Therefore, for each of the multiple output interfaces, the data selection signal in the selection control signal corresponding to that output interface is used to control the data signal selector associated with that output interface, the clock selection signal in the selection control signal corresponding to that output interface is used to control the clock signal selector associated with that output interface, and the enable selection signal in the selection control signal corresponding to that output interface is used to control the enable signal selector associated with that output interface. Here, valid data D0 is allocated to output interface A400. The data selection signal of the selection control signal corresponding to the output interface A400 is used to control the data signal selector associated with the output interface A400 to select from multiple data paths the data signal line for transmitting the valid data D0 allocated to the output interface A400. The clock selection signal of the selection control signal corresponding to the output interface A400 is used to control the clock signal selector associated with the output interface A400 to select from multiple data paths the clock signal line associated with the valid data D0. The enable selection signal of the selection control signal corresponding to the output interface A400 is used to control the enable signal selector associated with the output interface A400 to select the valid flag signal EN0 corresponding to the valid data D0 from multiple valid flag signals.Thus, when the mapping relationship indicates that valid data D0 is allocated to output interface A400, the selection control signal corresponding to output interface A400 controls the data signal selector associated with output interface A400 to select the data signal line (i.e., data path S0) for transmitting valid data D0. It also controls the clock signal selector associated with output interface A400 to select the clock signal line (i.e., clock signal CLK0) corresponding to data path S0 for transmitting the clock associated with valid data D0. Considering that multiple data may be transmitted sequentially on the same data path, for example, data path S0 may transmit valid data D0, D1, and D2 sequentially, it is necessary to distinguish between valid data transmitted sequentially through the same data path. Here, based on the data identifiers of the multiple valid data and the mapping relationship, multiple sets of selection control signals corresponding one-to-one with the multiple output interfaces are generated. Thus, configurable mapping of output interfaces can be conveniently achieved through data identifiers; for example, the corresponding selection control signals can be generated by combining the output interface identifiers. Based on the selection of data path S0 and clock signal CLK0 corresponding to data path S0 through the selection control signal corresponding to output interface A400, the valid flag signal EN0 corresponding to valid data D0 is also selected through the selection control signal corresponding to output interface A400.

[0042] Continue reading Figure 4As mentioned above, the mapping relationship indicates that the multiple valid data are allocated to the multiple output interfaces separately and without repetition. Therefore, two different valid data will inevitably not be allocated to the same output interface, and the mapping relationship can be ensured by limiting the maximum number of the multiple valid data to no more than the number of multiple output interfaces. By generating multiple valid flag signals that correspond one-to-one with the multiple valid data, the data transmission time period of the corresponding valid data can be detected by detecting the valid level segment of the valid flag signal. Furthermore, the valid flag signal EN0 corresponding to the valid data D0 is selected by the selection control signal corresponding to the output interface A400. Thus, the enable signal selector associated with output interface A400, under the enable selection signal of the selection control signal corresponding to output interface A400, selects the valid flag signal EN0 corresponding to valid data D0 as the output. Then, the valid flag signal EN0 enables or disables the output of the clock signal selector associated with output interface A400. The clock signal selector associated with output interface A400, under the selection control signal of output interface A400, selects the clock signal CLK0 corresponding to data path S0 as the output, thus obtaining the register clock signal associated with output interface A400. It can be seen that the register clock signal associated with output interface A400 is equivalent to a segment extracted from the clock signal CLK0 corresponding to data path S0 through the valid flag signal EN0 corresponding to valid data D0. Therefore, detecting the data transmission time period of the corresponding valid data by detecting the valid level segment of the valid flag signal also means that the data transmission time period of the corresponding valid data can be detected by detecting the register clock signal associated with the output interface. Furthermore, the data signal selector associated with output interface A400 selects data path S0 as output under the action of the data selection signal of the selection control signal corresponding to output interface A400. Then, the register clock signal associated with output interface A400 triggers the output of the data signal selector associated with output interface A400, thus obtaining valid data D0 output by output interface A400. Thus, based on two design constraints, namely (1) the maximum number of the multiple valid data is not higher than the number of multiple output interfaces, and the mapping relationship indicates that the multiple valid data are allocated to the multiple output interfaces separately and without repetition; and (2) multiple valid flag signals are generated one-to-one with the multiple valid data, and the timing relationship between the valid level segments of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data, a configurable mapping relationship can be realized from the multiple valid data transmitted from the multiple data paths to the multiple output interfaces, and the frequency difference and phase difference between signals across clock domains can be overcome.Thus, for any of the plurality of output interfaces, such as a given output interface and a corresponding given selection control signal, the data selection signal of the given selection control signal controls the data signal selector associated with the given output interface to select from the plurality of data paths a data signal line for transmitting the given valid data allocated to the given output interface. The clock selection signal of the given selection control signal controls the clock signal selector associated with the given output interface to select from the plurality of data paths a clock signal line for transmitting the given clock associated with the given valid data. The enable selection signal of the given selection control signal controls the enable signal selector associated with the given output interface to select from the plurality of valid flag signals a given valid flag signal corresponding to the given valid data. This enables the output of the enable signal selector associated with the given output interface to enable or disable the output of the clock signal selector associated with the given output interface, thereby obtaining the register clock signal associated with the given output interface. Furthermore, the register clock signal associated with the given output interface triggers the output of the data signal selector associated with the given output interface, ultimately realizing the output of the given valid data by the given output interface. Figure 3 and Figure 4 When multiple valid data are sent sequentially through the same data path, the multiple sets of selection control signals control the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces respectively. The multiple data paths are used as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals are used as inputs to the enable signal selectors associated with each of the multiple output interfaces. Finally, the multiple valid data sent through the data path S0 are distinguished, and the valid data D0 is output through the output interface A400.

[0043] See Figure 5 , Figure 5This is a signal timing diagram of the output interface provided in the second embodiment of this application. Taking two data paths as an example, the clock signal CLK0 corresponding to data path S0 and the clock signal CLK1 corresponding to data path S1 are shown respectively. Additionally, valid data D0, D1, and D2 transmitted through data path S0 are also shown. As described above, multiple valid flag signals are generated, each corresponding to one of the multiple valid data, and the timing relationship between the valid level segments of each of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data. Therefore, for valid data D0 and D1, a valid flag signal EN0 corresponding to valid data D0 and a valid data signal EN1 corresponding to valid data D1 are generated respectively. It can be seen that a high-level segment is used as the valid level segment, and the timing relationship between the valid level segment (high-level segment) of the valid flag signal EN0 corresponding to valid data D0 and the valid level segment (high-level segment) of the valid data signal EN1 corresponding to valid data D1 is consistent with the timing relationship between valid data D0 and valid data D1. See also... Figure 4 and Figure 5 , Figure 4 The diagram illustrates how valid data D0 is assigned to output interface A400 and how output interface A400 outputs valid data D0. Figure 5The diagram illustrates how valid data D1 is assigned to output interface B401 and how output interface B401 outputs valid data D1. Specifically, the enable signal selector associated with output interface B401, under the action of the enable selection signal of the selection control signal corresponding to output interface B401, selects the valid flag signal EN1 corresponding to valid data D1 as the output. Then, the valid flag signal EN1 enables or disables the output of the clock signal selector associated with output interface B401. The clock signal selector associated with output interface B401, under the action of the selection control signal corresponding to output interface B401, selects the clock signal CLK0 corresponding to data path S0 as the output, thus obtaining the register clock signal associated with output interface B401. It can be seen that the register clock signal associated with output interface B401 is equivalent to a segment extracted from the clock signal CLK0 corresponding to data path S0 through the valid flag signal EN1 corresponding to valid data D1. Therefore, detecting the data transmission time period of the corresponding valid data by detecting the valid level segment of the valid flag signal also means that the data transmission time period of the corresponding valid data can be detected by detecting the register clock signal associated with the output interface. Furthermore, the data signal selector associated with output interface B401 selects data path S0 as output under the action of the data selection signal of the selection control signal corresponding to output interface B401. Then, the register clock signal associated with output interface B401 triggers the output of the data signal selector associated with output interface B401, thus obtaining the valid data D1 output by output interface B401.

[0044] Continue reading Figure 5 By comparison Figure 4 and Figure 5 It can be seen that Figure 4 The diagram illustrates how the valid flag signal EN0 corresponding to valid data D0 is used to generate the register clock signal associated with the output interface A400. This allows the output interface A400 to use the register clock signal to trigger and output the selected data signal line, i.e., output valid data D0. This achieves the selection of the corresponding data and clock, and the writing of the target data into the register for parallel output within the selected clock domain to complete the parallel output. Conversely, Figure 5The diagram illustrates how the valid flag signal EN1 corresponding to valid data D1 generates the register clock signal associated with output interface B401. This allows output interface B401 to use the register clock signal to trigger and output the selected data signal line, i.e., output valid data D1. This achieves the selection of the corresponding data and clock, and the writing of the target data into the register for parallel output within the selected clock domain to complete parallel output. It can be seen that when multiple valid data are sent sequentially through the same data path, for example, valid data D0, D1, and D2 sent through data path S0, by generating a valid flag signal and a selection control signal, the selected clock signal is enabled or disabled by detecting the valid level segment of the valid flag signal, thereby generating the corresponding register clock signal. This register clock signal then triggers the output of the selected data signal, achieving data transmission across clock domains. Furthermore, by changing the mapping relationship—that is, changing how the multiple valid data are allocated separately and without repetition to the multiple output interfaces—configurable mapping of M output interfaces to a total of N data from S data paths can be supported. (See also...) Figure 3 , Figure 4 as well as Figure 5Valid data D0 sent through data path S0 is assigned to output interface A400, and valid data D1 sent through data path S0 is assigned to output interface B401. Therefore, the two valid data sets D0 and D1 sent through data path S0 are ultimately output in parallel through output interfaces A400 and B401. If this exemplary mapping needs to be changed, valid data D0 can be assigned to other output interfaces different from output interface A400. This requires changing the original mapping relationship and generating a corresponding new selection control signal. For example, valid data sent from another data path can be assigned to output interface A400. This also requires changing the original mapping relationship and generating a corresponding new selection control signal. It can be seen that by changing the allocation from valid data to output interfaces indicated by the mapping relationship, and combining this with the data identifier of the valid data, a configurable mapping of M output interfaces to a total of N data sets from S data paths can be easily achieved. Furthermore, by detecting the effective level segment of the valid flag signal to detect the corresponding valid data transmission time period, it can be reflected that the corresponding valid data transmission time period can be detected by detecting the clock signal of the register associated with the output interface. In combination with the data signal line and clock signal line selected by the selection control signal associated with each output interface, the corresponding valid data can be selected from the selected data signal line according to the selected clock, and the selected valid data can be written into the register of the corresponding output interface for subsequent parallel output. This eliminates the need for complex cross-clock synchronization processing mechanisms or clock switching mechanisms, and avoids the cross-clock transmission risk and metastability risk brought about by large-scale combinational logic.

[0045] See Figure 3 , Figure 4 and Figure 5For any of the plurality of output interfaces, such as a given output interface and a corresponding given selection control signal for the given output interface, the data selection signal of the given selection control signal is used to control the data signal selector associated with the given output interface to select from the plurality of data paths a data signal line for transmitting a given valid data allocated to the given output interface. The clock selection signal of the given selection control signal is used to control the clock signal selector associated with the given output interface to select from the plurality of data paths a clock signal line for transmitting a given clock associated with the given valid data. The enable selection signal of the given selection control signal is used to control the enable signal selector associated with the given output interface to select from the plurality of valid flag signals a given valid flag signal corresponding to the given valid data. This enables the output of the enable signal selector associated with the given output interface to enable or disable the output of the clock signal selector associated with the given output interface, thereby obtaining the register clock signal associated with the given output interface. Furthermore, the register clock signal associated with the given output interface is used to trigger the output of the data signal selector associated with the given output interface, ultimately realizing the output of the given valid data by the given output interface. When multiple valid data are sent sequentially through the same data path, the multiple sets of selection control signals control the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces respectively. Furthermore, the multiple data paths are used as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals are used as inputs to the enable signal selectors associated with each of the multiple output interfaces. Finally, this distinguishes the multiple valid data sent through data path S0, and enables the output of valid data D0 through output interface A400 and valid data D1 through output interface B401.

[0046] See Figure 6 , Figure 6 This is a signal timing diagram of the output interface provided in the third embodiment of this application. Taking two data paths as an example, the clock signal CLK0 corresponding to data path S0 and the clock signal CLK1 corresponding to data path S1 are shown respectively. Additionally, valid data D0, D1, and D2 transmitted through data path S0 are shown, as well as valid data D3, D4, and D5 transmitted through data path S1. See also... Figure 4 , Figure 5 as well as Figure 6 , Figure 4 and Figure 5 This illustrates how valid data D0 and valid data D1, sent through the same data path, are output by their respective output interfaces. Figure 6This illustrates how valid data transmitted through different data paths is output. Specifically, the enable signal selector associated with output interface C403, under the action of the enable selection signal of the selection control signal corresponding to output interface C403, selects the valid flag signal EN3 corresponding to valid data D3 as the output. Then, the valid flag signal EN3 enables or disables the output of the clock signal selector associated with output interface C403. The clock signal selector associated with output interface C403, under the action of the selection control signal corresponding to output interface C403, selects the clock signal CLK1 corresponding to data path S1 as the output, thus obtaining the register clock signal associated with output interface C403. It can be seen that the register clock signal associated with output interface C403 is equivalent to a segment extracted from the clock signal CLK1 corresponding to data path S1 through the valid flag signal EN3 corresponding to valid data D3. Therefore, detecting the data transmission time period of the corresponding valid data by detecting the valid level segment of the valid flag signal also means that the data transmission time period of the corresponding valid data can be detected by detecting the register clock signal associated with the output interface. Furthermore, the data signal selector associated with the output interface C403 selects the data path S1 as the output under the action of the data selection signal of the selection control signal corresponding to the output interface C403. Then, the register clock signal associated with the output interface C403 triggers the output of the data signal selector associated with the output interface C403, thus obtaining the valid data D3 output by the output interface C403.

[0047] See Figure 4 , Figure 5 as well as Figure 6 As can be seen, when different data paths send their respective valid data, such as valid data D0 and D1 sent through data path S0 and valid data D3 sent through data path S1, different data paths may use different clock signals, thus resulting in frequency and phase differences. This is also a challenge faced in multi-channel serial output and parallel output application scenarios, namely, how to overcome the frequency and phase differences that may exist in cross-clock domain data transmission. This challenge (frequency and phase differences in cross-clock domain data transmission) often coexists with another challenge (how to achieve configurable mapping between the output interface and the data). Here, we take... Figure 4 The output interface A400 in the middle Figure 5 The output interface B401 and Figure 6Taking the output interface C403 as an example, for any of the multiple output interfaces, such as a given output interface and a corresponding given selection control signal, the data selection signal of the given selection control signal is used to control the data signal selector associated with the given output interface to select from the multiple data paths a data signal line for transmitting the given valid data allocated to the given output interface. The clock selection signal of the given selection control signal is used to control the clock signal selector associated with the given output interface to select from the multiple data paths a clock signal line for transmitting the given clock associated with the given valid data. The enable selection signal of the given selection control signal is used to control the enable signal selector associated with the given output interface to select the given valid flag signal corresponding to the given valid data from the multiple valid flag signals. This enables the output of the enable signal selector associated with the given output interface to enable or disable the output of the clock signal selector associated with the given output interface, thereby obtaining the register clock signal associated with the given output interface. Furthermore, the register clock signal associated with the given output interface is used to trigger the output of the data signal selector associated with the given output interface, ultimately realizing the output of the given valid data by the given output interface. Thus, when multiple valid data are sent sequentially from the same data path, or when different data paths send their respective valid data, the multiple sets of selection control signals control the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces. Furthermore, the multiple data paths are used as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals are used as inputs to the enable signal selectors associated with each of the multiple output interfaces. This ultimately distinguishes between different valid data from the same data path and between the valid data from different data paths, ultimately achieving the output of valid data D0 through output interface A400, valid data D1 through output interface B401, and valid data D3 through output interface C403. The following section combines... Figure 7 To further elaborate, this section explains how, based on the implementation of cross-clock domain data transmission and configurable mapping between arbitrary output interfaces and arbitrary data paths, resource consumption and circuit area consumption are effectively reduced.

[0048] Figure 7 This is a schematic diagram of a data signal selector, a clock signal selector, and an enable signal selector associated with an output interface provided in an embodiment of this application. Figure 7 Taking output interface D700 and valid data 730 allocated to output interface 700 as an example, this example illustrates a configurable mapping of M output interfaces to a total of N data points across S data paths. Figure 7 The diagram shows a data signal selector D714 associated with output interface D700, a clock signal selector D710 associated with output interface D700, and an enable signal selector D712 associated with output interface D700. Furthermore, S data signal lines serve as inputs to the data signal selector D714 associated with output interface D700, S clock signal lines serve as inputs to the clock signal selector D710 associated with output interface D700, and N valid flag signals corresponding to N valid data serve as inputs to the enable signal selector D712 associated with output interface D700. Under the action of the enable selection signal 762 in the selection control signal corresponding to the output interface D700, the enable signal selector D712 associated with the output interface D700 selects from the N valid flag signals corresponding to the N valid data and outputs the valid flag signal 740 corresponding to the valid data 730 assigned to the output interface D700. Then, the valid flag signal 740 corresponding to the valid data 730 assigned to the output interface D700 enables or disables the output of the clock signal selector D710 associated with the output interface D700 through the first circuit D780 associated with the output interface D700. In addition, under the action of the clock selection signal 760 in the selection control signal corresponding to the output interface D700, the clock signal selector D710 associated with the output interface D700 selects from the S clock signal lines and outputs the clock signal line 742 used to transmit the clock associated with the valid data 730. Therefore, the valid flag signal 740 corresponding to the valid data 730 assigned to the output interface D700 enables or disables the output of the clock signal line 742 used for transmitting the clock associated with the valid data 730 through the first circuit D780 associated with the output interface D700, thus obtaining the register clock signal 750 associated with the output interface D700. The register clock signal associated with the output interface D700 is equivalent to a segment extracted from the output of the clock signal line 742 by the valid flag signal 740 corresponding to the valid data 730. Therefore, detecting the data transmission time period of the corresponding valid data by detecting the valid level segment of the valid flag signal also means that the data transmission time period of the corresponding valid data can be detected by detecting the register clock signal associated with the output interface. Furthermore, under the action of the data selection signal 764 in the selection control signal corresponding to the output interface D700, the data signal selector D714 associated with the output interface D700 selects and outputs the data signal line 744 for transmitting valid data 730 from the S data signal lines. Then, the register clock signal 750 associated with the output interface D700 triggers the output of the data signal line 744 for transmitting valid data 730 through the second circuit D782 associated with the output interface D700, thus obtaining the output of valid data 730 from the output interface D700.

[0049] Continue reading Figure 7Taking the configurable mapping of M output interfaces to a total of N data points across S data paths as an example, for each output interface, taking output interface D700 as an example, at the hardware level, it is necessary to provide a data signal selector D714 associated with output interface D700, a clock signal selector D710 associated with output interface D700, and an enable signal selector D712 associated with output interface D700. Additionally, it is also necessary to provide a first circuit D780 associated with output interface D700 and a second circuit D782 associated with output interface D700. As mentioned above, with M output interfaces and N valid data points, N must not exceed M. Furthermore, under the constraint that N cannot exceed M, a non-repeating allocation of N valid data points to M output interfaces is constructed through the mapping relationship. Therefore, two valid data points will necessarily be allocated to two different output interfaces, and the same output interface will not be allocated more than one valid data point. Moreover, as mentioned above, the correspondence between data signal lines and clock signal lines is difficult to determine precisely, and various data and clock configurations may exist between multiple serial data streams. If there is only one sender, generally, multiple serial data streams transmitted from the same sender use the same clock domain. However, the sender and receiver may use the same clock domain or different clock domains. If there are multiple senders, they may use the same clock domain or different clock domains. Therefore, at the hardware level, it is necessary to consider the requirements of extreme cases, namely, that each of the S data signal lines uses a different clock signal. For this purpose, S data signal lines and S clock signal lines need to be provided. This allows multiple data streams and at least one clock associated with the multiple data streams to be transmitted through multiple data paths, and can flexibly adapt to various possible data and clock configurations. Therefore, assuming a configurable mapping of M output interfaces to a total of N data points across S data paths, taking the hardware associated with output interface D700 as an example, it is necessary to provide a data signal selector D714 associated with output interface D700 with S inputs and a single output to select the output of data signal line 744 for transmitting valid data 730 from the S data signal lines; an enable signal selector D712 associated with output interface D700 with N inputs and a single output to select the valid flag signal 740 corresponding to the valid data 730 assigned to output interface D700 from the N valid flag signals corresponding to the N valid data; and a clock signal selector D710 associated with output interface D700 with S inputs and a single output to select the output of clock signal line 742 for transmitting the clock associated with the valid data 730 from the S clock signal lines.Additionally, a first circuit D780 associated with output interface D700 is required to enable or disable the output of clock signal selector D710 associated with output interface D700, corresponding to the valid flag signal 740 allocated to valid data 730. A second circuit D782 associated with output interface D700 is also required to trigger the output of data signal line 744 used to transmit valid data 730, via register clock signal 750 associated with output interface D700. Therefore, for each output interface, the required hardware resources include two S-input single-output selectors, one N-input single-output selector, a first circuit with enable / disable functionality, and a second circuit with triggering functionality. Here, the first circuit can be a latch or a gate. The second circuit can be a flip-flop circuit, such as a D flip-flop. It should be understood that the selectors, the first circuit, and the second circuit can adopt any suitable circuit structure and device characteristics, as long as they meet the design principles. Furthermore, for multiple output interfaces, a unified selection signal generation module can be used to generate multiple valid flag signals corresponding one-to-one with the multiple valid data and multiple sets of selection control signals corresponding one-to-one with the multiple output interfaces. Then, the multiple sets of selection control signals are used to control the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces. Taking output interface D700 as an example, the data selection signal 764 in the selection control signal corresponding to output interface D700 controls the data signal selector D714 associated with output interface D700, the enable signal selector D712 associated with output interface D700 controls the enable signal selector D712 associated with output interface D700, and the clock signal selector D710 associated with output interface D700 controls the clock signal selector D710 associated with output interface D700.

[0050] Continue reading Figure 7For each output interface, the required hardware resources include two S-input single-output selectors, one N-input single-output selector, a first circuit with enable / disable functionality, a second circuit with trigger functionality, and a globally shared selection signal generation module. Therefore, to achieve configurable mapping of M output interfaces to a total of N data points across S data paths, a total of twice the number of M S-input single-output selectors, M N-input single-output selectors, M first circuits with enable / disable functionality, M second circuits with trigger functionality, and a globally shared selection signal generation module are needed. It can be seen that as the number of output interfaces (M) and the number of data paths (S) increase, the number of selectors increases linearly, remaining twice the number of M, while the number of inputs that a single selector needs to accommodate also increases linearly, remaining at S inputs. Furthermore, to ensure that the maximum number of valid data points does not exceed the number of output interfaces, N must not exceed M. Therefore, it can be understood that as the number of valid data points (N) to be transmitted increases, the number of output interfaces (M) also needs to increase, thus increasing the number of selectors (keeping it at twice the size of M). However, the overall relationship remains linear, achieving decoupling between the number of output interfaces (M) and the number of valid data points (N). Conversely, if combinational logic circuits are used to implement the configurable mapping of M output interfaces to a total of N data points across S data paths, the size of the required combinational logic circuits is proportional to the product of the number of output interfaces and the number of data points, i.e., proportional to the product of M and N. This means that the size of the combinational logic circuits, such as the number of required components, is proportional to the product of M and N, resulting in a non-linear growth relationship. As the number of output interfaces (M) and the number of valid data points (N) to be transmitted increase, significant resources and circuit area are required. Furthermore, if a combinational logic circuit is used to implement the configurable mapping of M output interfaces to a total of N data points across S data paths, all data needs to be stored in registers. This necessitates considering the impact of the data bit width L, thus requiring a combinational logic switching circuit of size M multiplied by N and then by L. Alternatively, using a selector to select data and clock allows for the setting of corresponding selection control signals based on a pre-configured mapping relationship. This means the selector or similar selection circuit is in a quasi-static state, avoiding dynamic clock or data switching issues. Moreover, the selected data, clock, and valid flag signals have a unique and deterministic source. Therefore, after determining the selection result, the selected signal toggles normally, and the data and clock are now in the same clock domain.

[0051] Continue reading Figure 7As mentioned above, to achieve a configurable mapping of M output interfaces to a total of N data points across S data paths, a total of M times the number of S-input single-output selectors, M times the number of N-input single-output selectors, M times the number of first circuits with enable or disable functions, M times the number of second circuits with trigger functions, and a globally shared selection signal generation module are also required. Here, the influence of the data bit width L is also added... Figure 7 Taking the output interface D700 as an example, the enable signal selector D712 and clock signal selector D710 associated with the output interface D700 are not affected by the data bit width L, because they only need to select the valid flag signal and clock signal line. The data signal selector D714 associated with the output interface D700 needs to select the corresponding data signal line from S data signal lines. Therefore, the data signal selector D714 associated with the output interface D700 needs to be able to adapt to the influence of the data bit width L, but it is only used for dynamic output, so it does not need to have a storage function. Then, the second circuit D782 associated with the output interface D700, because it is used to output valid data 730, needs to have a trigger function and be able to store at least the data bit width L. This means that for the output interface D700, only the second circuit D782 associated with the output interface D700 needs to provide the function of storing the data bit width L, or the function of storing the data bit width L can be provided by the subsequent circuit connected to the second circuit D782 associated with the output interface D700. Overall, taking the configurable mapping of M output interfaces to a total of N data points across S data paths as an example, it requires M number of trigger-enabled second circuits capable of storing data with a width of L (or providing the function of storing data with a width of L through subsequent circuits). Therefore, compared to combinational logic switching circuits of size M multiplied by N and then multiplied by L, the demand for storage hardware resources is significantly reduced, which helps to reduce area consumption.

[0052] See Figures 3 to 7This application provides a method for parallel output of multiple serial data, proposing two design constraints: (1) the maximum number of valid data is not higher than the number of multiple output interfaces, and the mapping relationship indicates that the multiple valid data are allocated to the multiple output interfaces separately and without repetition; and (2) multiple valid flag signals are generated corresponding one-to-one with the multiple valid data, and the timing relationship between the valid level segments of each of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data. Based on the two design constraints, valid flag signals and selection control signals are generated at the software level, and data signal selectors, clock signal selectors, and enable signal selectors associated with each of the multiple output interfaces are provided at the hardware level. Through the combination of the software level and the hardware level, the multiple sets of selection control signals are used to generate valid flag signals and selection control signals. The signals respectively control the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces. Furthermore, by setting the multiple data paths as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals as inputs to the enable signal selectors associated with each of the multiple output interfaces, a configurable mapping relationship can be achieved from multiple valid data transmitted through multiple data paths to multiple output interfaces, overcoming frequency and phase differences between signals across clock domains. In terms of hardware resource consumption and circuit area consumption, the number of output interfaces and the amount of valid data to be transmitted are decoupled, ensuring that hardware resource consumption increases linearly with the data transmission scale, significantly reducing the demand for storage hardware resources and contributing to reduced area consumption. Thus, not only are resource consumption and circuit area consumption effectively reduced, but the frequency and phase difference problems of cross-clock domain signal transmission are also effectively overcome. Complex cross-clock synchronization or clock switching mechanisms are not required, which helps reduce the risks of cross-clock transmission and metastability caused by large-scale combinational logic, improving the reliability and real-time performance of data output.

[0053] See Figures 1 to 7In one possible implementation, the given output interface is any one of the plurality of output interfaces, the given selection control signal in the plurality of selection control signals corresponds to the given output interface, the data selection signal of the given selection control signal is used to control the data signal selector associated with the given output interface to select from the plurality of data paths a data signal line for transmitting a given valid data allocated to the given output interface, the clock selection signal of the given selection control signal is used to control the clock signal selector associated with the given output interface to select from the plurality of data paths a clock signal line for transmitting a given clock associated with the given valid data, and the enable selection signal of the given selection control signal is used to control the enable signal selector associated with the given output interface to select from the plurality of valid flag signals a given valid flag signal corresponding to the given valid data. Thus, valid flag signals and selection control signals are generated at the software level, and data signal selectors, clock signal selectors, and enable signal selectors associated with each of the multiple output interfaces are provided at the hardware level. Through the combination of software and hardware levels, the multiple sets of selection control signals control the data signal selectors, clock signal selectors, and enable signal selectors associated with each of the multiple output interfaces respectively. Furthermore, by setting the multiple data paths as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals as inputs to the enable signal selectors associated with each of the multiple output interfaces, a configurable mapping relationship can be achieved from the multiple valid data transmitted through the multiple data paths to the multiple output interfaces, overcoming frequency and phase differences between signals across clock domains. In terms of hardware resource consumption and circuit area consumption, the number of output interfaces and the amount of valid data to be transmitted are decoupled, so that the hardware resource consumption increases linearly with the data transmission scale, significantly reducing the demand for storage hardware resources and helping to reduce area consumption. In this way, not only is resource consumption and circuit area consumption effectively reduced, but the frequency difference and phase difference problems of cross-clock domain signal transmission are also effectively overcome. There is no need for complex cross-clock synchronization processing mechanism or clock switching mechanism, which helps to reduce the cross-clock transmission risk and metastability risk caused by large-scale combinational logic, and is conducive to improving the reliability and real-time performance of data output.

[0054] In some embodiments, the output of the enable signal selector associated with the given output interface is used to enable or disable the output of the clock signal selector associated with the given output interface, thereby obtaining the register clock signal associated with the given output interface. Furthermore, the register clock signal associated with the given output interface is used to trigger the output of the data signal selector associated with the given output interface. This achieves cross-clock domain data transmission and configurable mapping between any output interface and any data path, while effectively reducing resource consumption and circuit area usage. Through data identifier allocation, mapping relationship resolution, and the output of the original clock register, remapping processing is synchronously completed during multi-channel serial data reception. By decoding multiple channels of serial data, the data identifier and corresponding valid flag signal of each valid data channel are extracted. The problem of selecting output data is transformed into the problem of selecting valid flag signals. Selection control signals are generated to select data and clock. Finally, under the selected clock domain, the target data is written into the parallel output register for parallel output. This approach is compatible with various data decoding methods, as long as the valid data in the final output contains a corresponding valid flag signal. Alternatively, a valid flag register can be used to declare one bit for each valid data point. Setting the valid flag register high (or low) indicates the duration of the required clock cycle, i.e., maintaining a valid flag signal level for a certain duration. Generally, the duration of one or more clock cycles refers to the data processing clock in the digital circuit design, usually related to the data rate. For example, when the data rate is approximately 12.5 gigabits per second, the digital circuit receives or processes 32 bits of data in parallel each clock cycle at a 1 / 32 frequency data processing clock. Therefore, a valid level segment lasting one clock cycle indicates that the 32 bits of data received or processed in that clock cycle are valid, representing the clock used for data processing in the digital circuit. This supports a method for processing multiple serial data streams into large-scale remapped parallel outputs in digital circuits. The system decodes multiple serial data streams separately, extracting valid data and corresponding valid flags for each stream. Based on the number of valid flags for each channel, a unique data identifier is assigned to each valid data stream. A selection control signal is generated based on a preset or configured mapping relationship between the output interface and the valid data, combined with the data identifier and the output interface identifier. Using a selector (or selection circuit), the system filters the target valid data according to the selection control signal and reuses its original clock. Under the selected clock domain, the mapped data is written to the parallel output register, completing the parallel output. By replacing large-scale combinational logic with identifier mapping, the system significantly reduces chip area consumption and eliminates the need for cross-clock synchronization modules, avoiding the risks of cross-clock transmission or direct output of combinational logic, thus improving the reliability and real-time performance of data output.

[0055] In some embodiments, the output of the enable signal selector associated with the given output interface serves as the input to the control terminal of the latch circuit associated with the given output interface, the output of the clock signal selector associated with the given output interface serves as the input to the signal terminal of the latch circuit associated with the given output interface, and the register clock signal associated with the given output interface is the output of the latch circuit associated with the given output interface. Thus, by utilizing the latching function of the latch circuit, and determining when to output the signal terminal input of the latch circuit through the input to the control terminal of the latch circuit, the output of the enable signal selector associated with the given output interface is used to enable or disable the output of the clock signal selector associated with the given output interface, thereby obtaining the register clock signal associated with the given output interface.

[0056] In some embodiments, the output of the enable signal selector associated with the given output interface serves as the input to the control terminal of the gating circuit associated with the given output interface, the output of the clock signal selector associated with the given output interface serves as the input to the signal terminal of the gating circuit associated with the given output interface, and the register clock signal associated with the given output interface is the output of the gating circuit associated with the given output interface. Thus, by utilizing the gating function of the gating circuit, the input of the control terminal of the gating circuit determines when to output the input of the signal terminal of the gating circuit. This enables or disables the output of the clock signal selector associated with the given output interface using the output of the enable signal selector associated with the given output interface, thereby obtaining the register clock signal associated with the given output interface.

[0057] In some embodiments, the register clock signal associated with the given output interface serves as the input to the control terminal of the trigger circuit associated with the given output interface, and the output of the data signal selector associated with the given output interface serves as the input to the signal terminal of the trigger circuit associated with the given output interface. Thus, by utilizing the triggering function of the trigger circuit, the timing of the output of the trigger circuit's signal terminal is determined by the input to the control terminal of the trigger circuit, thereby enabling the register clock signal associated with the given output interface to trigger the output of the data signal selector associated with the given output interface.

[0058] In some embodiments, the trigger circuit associated with the given output interface has a storage function and can be used to store data with a maximum data bit width not less than the plurality of valid data, and the data signal selector associated with the given output interface has a dynamic output function and can be used to adapt to the maximum data bit width of the plurality of valid data. Thus, the data signal selector associated with the output interface needs to be able to adapt to the influence of the data bit width, but is only used for dynamic output, so it does not need a storage function. Then, the trigger circuit associated with the output interface, because it is used to output valid data, needs to have a trigger function and be able to store data with a data bit width of at least L. This means that, for the output interface, only the trigger circuit associated with the output interface needs to provide the function of storing data with a data bit width of L, or the function of storing data with a data bit width of L can be provided by the subsequent circuit connected to it. Overall, taking the configurable mapping of M output interfaces to a total of N data from S data paths as an example, M number of second circuits (trigger circuits) with trigger functions are needed to have the function of storing data with a data bit width of L (or the function of storing data with a data bit width of L can be provided by the subsequent circuit). Therefore, compared to combinational logic switching circuits with a scale of M times N times L, the requirements for storage hardware resources are significantly reduced, which helps to reduce area consumption.

[0059] In some embodiments, when the output of the enable signal selector associated with the given output interface is within the valid level range of the given valid flag signal, the output of the clock signal selector associated with the given output interface is enabled, and when the output of the enable signal selector associated with the given output interface is not within the valid level range of the given valid flag signal, the output of the clock signal selector associated with the given output interface is disabled. Thus, for any of the plurality of output interfaces, such as a given output interface and the corresponding given selection control signal, the data selection signal of the given selection control signal controls the data signal selector associated with the given output interface to select from the plurality of data paths a data signal line for transmitting the given valid data allocated to the given output interface; the clock selection signal of the given selection control signal controls the clock signal selector associated with the given output interface to select from the plurality of data paths a clock signal line for transmitting the given clock associated with the given valid data; and the enable selection signal of the given selection control signal controls the enable signal selector associated with the given output interface to select from the plurality of valid flag signals the given valid flag signal corresponding to the given valid data. This supports enabling or disabling the output of the enable signal selector associated with the given output interface by enabling or disabling the output of the clock signal selector associated with the given output interface, thereby obtaining the register clock signal associated with the given output interface. Furthermore, the register clock signal associated with the given output interface triggers the output of the data signal selector associated with the given output interface, ultimately enabling the given output interface to output a given valid data. Thus, when multiple valid data are sent sequentially from the same data path, or when different data paths send their respective valid data, the multiple sets of selection control signals control the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces respectively. The multiple data paths are used as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals are used as inputs to the enable signal selectors associated with each of the multiple output interfaces. This ultimately distinguishes different valid data from the same data path and distinguishes the valid data from different data paths, facilitating configurable mapping in large-scale parallel output applications.

[0060] In some embodiments, the valid level segment of the given valid flag signal is a high level that lasts for one or more clock cycles. Thus, a valid flag register can be used to declare one bit for each valid data point. Setting the valid flag register high (or low) indicates the required duration of the clock cycle, i.e., maintaining the valid flag signal's valid level segment for a certain duration. Generally, lasting one or more clock cycles refers to the data processing clock in the digital circuit design sense, usually related to the data rate. For example, when the data rate is approximately 12.5 gigabits per second, the digital circuit receives or processes 32 bits of data in parallel each clock cycle at a data processing clock frequency of 1 / 32. Therefore, a valid level segment lasting for one clock cycle indicates that the 32 bits of data received or processed in that clock cycle are valid, representing the clock used for data processing in the digital circuit. This supports a method for processing multiple serial data streams into large-scale remapped parallel outputs in a digital circuit. The system decodes multiple serial data streams separately, extracting valid data and corresponding valid flags for each stream. Based on the number of valid flags for each channel, a unique data identifier is assigned to each valid data stream. A selection control signal is generated based on a preset or configured mapping relationship between the output interface and the valid data, combined with the data identifier and the output interface identifier. Using a selector (or selection circuit), the system filters the target valid data according to the selection control signal and reuses its original clock. Under the selected clock domain, the mapped data is written to the parallel output register, completing the parallel output. By replacing large-scale combinational logic with identifier mapping, the system significantly reduces chip area consumption and eliminates the need for cross-clock synchronization modules, avoiding the risks of cross-clock transmission or direct output of combinational logic, thus improving the reliability and real-time performance of data output.

[0061] In one possible implementation, the at least one clock is a single clock, and the plurality of valid data shares the single clock. In another possible implementation, the at least one clock comprises multiple clocks corresponding one-to-one with the plurality of valid data, and each of the multiple clocks has a different frequency. Here, to meet the design purpose of parallel output, a unified clock is generally used to coordinate the parallel output of multiple output interfaces. Multiple data transmitted through multiple data paths may use the same or different clocks, therefore at least one clock is transmitted through multiple data paths. Furthermore, more than one data signal line may share the same clock signal line. For example, assuming there are eight data signal lines, DQ0 to DQ7, DQ0 to DQ3 may share CLK0, DQ4 and DQ5 may share CLK1, DQ6 may use CLK2, and DQ7 may use CLK3. Therefore, the correspondence between data signal lines and clock signal lines is difficult to determine definitively. This means that various data and clock configurations may exist between multiple serial data streams, requiring sufficiently high flexibility in the parallel output to adapt to various configurations. See also Figure 1 and Figure 2 As can be seen, if there is only one sender, generally, multiple serial data transmitted from the same sender use the same clock domain. However, the sender and receiver may use the same clock domain or different clock domains. If there are multiple senders, they may use the same clock domain or different clock domains. This means that there may be different clock frequencies between multiple serial data streams, and there may also be frequency and phase differences from the sender of the multiple serial data streams to the receiver used for parallel output. Therefore, the method for parallel output of multiple serial data streams provided in this application can not only meet the requirements for parallel output of multiple serial data streams within the same clock domain, but also meet the requirements for parallel output of multiple serial data streams across clock domains under a single clock domain, and also meet the requirements for parallel output of multiple serial data streams across clock domains under multiple clock domains.

[0062] In one possible implementation, the allocated valid data for each of the plurality of output interfaces is stored in the respective output register of each of the plurality of output interfaces. These output registers are used to output the plurality of valid data in parallel based on a global output clock, and the update order among the output registers of the plurality of output interfaces is consistent with the data transmission order among the plurality of valid data. Thus, valid flag signals and selection control signals are generated at the software level, and data signal selectors, clock signal selectors, and enable signal selectors associated with each of the plurality of output interfaces are provided at the hardware level. Through the combination of software and hardware levels, the data signal selectors, clock signal selectors, and enable signal selectors associated with each of the plurality of output interfaces are controlled respectively by the multiple sets of selection control signals. Furthermore, by setting the plurality of data paths as inputs to the data signal selectors and clock signal selectors associated with each of the plurality of output interfaces, and the plurality of valid flag signals as inputs to the enable signal selectors associated with each of the plurality of output interfaces, a configurable mapping relationship can be achieved from the plurality of valid data transmitted through the plurality of data paths to the plurality of output interfaces, overcoming frequency and phase differences between signals across clock domains. In addition, by setting the update order between the output registers of the multiple output interfaces to be consistent with the data transmission order between the multiple valid data, the natural isolation between different batches of data in terms of transmission time can be utilized to support the data transmission of multiple batches.

[0063] In one possible implementation, the multiple sets of selection control signals are generated by a selection signal generation module. This module can be configured to not generate selection control signals corresponding to at least one of the multiple output interfaces. Alternatively, the output of the data signal selector associated with the at least one output interface can be used as the input of a D flip-flop, and the reset signal of the D flip-flop can remain active. Thus, when some output interfaces experience frequent failures, such as link congestion or disconnection issues, this can lead to frequent changes in mapping relationships. It is necessary to ensure that valid data is not assigned to failed output interfaces. To address this, the selection signal generation module can temporarily ignore certain output interfaces, i.e., not generate selection control signals corresponding to at least one of the multiple output interfaces. This restriction on selection control signals avoids excessively frequent changes in mapping relationships, which helps adapt to application scenarios with unstable communication environments. Alternatively, the reset signal mechanism of the D flip-flop can be used. By setting the reset signal of the D flip-flop corresponding to certain output interfaces to always be active, it maintains a reset state, thereby ensuring that certain output interfaces do not provide output, which is equivalent to temporarily ignoring certain output interfaces.

[0064] In one possible implementation, the plurality of data paths are further used to transmit at least one enable signal associated with the plurality of data, wherein a valid flag signal corresponding to valid data associated with the at least one enable signal is generated based on the at least one enable signal. As mentioned above, the valid flag signal is generated based on valid data, and the timing relationship between the valid level segments of each of the plurality of valid flag signals is consistent with the timing relationship between the plurality of valid data. In some cases, data and clock are transmitted through the data path; in other cases, not only data and clock are transmitted through the data path, but also at least one enable signal. This enable signal transmitted through the data path can be considered an external enable signal relative to the valid flag signal, while the valid flag signal can be considered an internal enable signal. For example, the output of the enable signal selector associated with the given output interface is used to enable or disable the output of the clock signal selector associated with the given output interface. When the data path transmits at least one enable signal, the influence of the external enable signal, i.e., the enable signal transmitted by the data path, on the internal enable signal, i.e., the valid flag signal, needs to be considered. Generally, when the external enable signal is disabled, the internal enable signal is also disabled; transmission is only permitted when both the external and internal enable signals are enabled. Therefore, the valid flag signal corresponding to the valid data associated with the at least one enable signal is generated based on the at least one enable signal, thus enabling the transmission of enable signals while adapting the data path.

[0065] Figure 8 This is a schematic diagram illustrating the data transmission of multiple batches according to a first embodiment of this application. (See attached diagram.) Figure 8 As shown, the data transmission of multiple batches in the first embodiment includes performing multiple operations sequentially. Operation S801: Write the first data of the current batch into the output register of the corresponding output interface. Operation S803: Write the last data of the current batch into the output register of the corresponding output interface. Operation S805: Output the multiple data of the current batch stored in the output registers of each of the multiple output interfaces in parallel. Operation S810: Change the mapping relationship between the data and the output interface. Operation S820: Write the first data of the next batch into the output register of the corresponding output interface. See also... Figure 8The multiple data points belong to the current batch. The next batch, relative to the current batch, is transmitted through the multiple data paths for parallel output via the multiple output interfaces. Data transmission of the next batch begins at least after the current batch's data transmission is complete. Thus, no switching occurs until N data points in the same batch have been transmitted, avoiding data loss and circuit transients. In some examples, restrictions on the selection signal generation module can prevent changes to the pre-stored mapping relationship before the current batch's data transmission is complete, thus preserving the generated selection control signal. This achieves time-division multiplexing and natural isolation between different batches of data, preventing the receiver from confusing data from different batches. For example, the last data point in the valid flag signal can be used to represent the last data point in the current batch.

[0066] In some embodiments, the method further includes changing the mapping relationship at least after the current batch of data transmission is completed and before the next batch of data transmission. Thus, if a change in the mapping relationship is required, each output interface needs to be configured before the next data update. This configuration can be done via an external bus, such as a Serial Peripheral Interface (SPI) bus or a two-wire Inter-Integrated Circuit (I2C) bus, ensuring that no new valid data is transmitted during the configuration period. Alternatively, a special mapping configuration sequence can be sent via the data path, and normal data transmission can continue after configuration is completed. In this way, the mapping relationship is adjusted during the interval between the completion of all N data transmissions in the same batch and the transmission of the next batch of data. No switching occurs before the completion of transmission of all N data in the same batch, avoiding data loss, circuit transients, and other problems. Additionally, the configuration within the selection signal generation module can be changed through various methods, such as issuing a configuration table.

[0067] Figure 9 This is a schematic diagram illustrating the data transmission of multiple batches according to a second embodiment provided in this application. (See attached diagram.) Figure 9As shown, the data transmission of multiple batches in the second implementation includes multiple operations. S901: Write the first data of the current batch into the output register of the corresponding output interface, wherein all data in the current batch has the batch identifier of the current batch. S903: Write the last data of the current batch into the output register of the corresponding output interface. S905: Output the multiple data of the current batch stored in the output registers of each of the multiple output interfaces in parallel. S920: Write the first data of the next batch into the output register of the corresponding output interface, wherein all data of the next batch has the batch identifier of the next batch. S922: Write the last data of the next batch into the output register of the corresponding output interface. S924: Output the multiple data of the next batch stored in the output registers of each of the multiple output interfaces in parallel. Operations S901, S903, and S905 constitute the data transmission cycle of the current batch. Operations S920, S922, and S924 constitute the data transmission cycle of the next batch. (Comparison) Figure 8 and Figure 9 It can be seen that, Figure 8 In this context, the data transmission cycle of the current batch and the data transmission cycle of the next batch are naturally isolated. That is, the data transmission of the next batch begins at least after the data transmission of the current batch is completed. This is manifested in operation S820 (writing the first data of the next batch into the output register of the corresponding output interface) following operation S805 (parallel outputting multiple data of the current batch stored in the output registers of multiple output interfaces). Conversely, in... Figure 9 In this approach, batch identifiers are introduced to represent the data in the current batch and the data in the next batch. Operation S920 (writing the first data of the next batch into the output register of the corresponding output interface) occurs before operation S905 (parallel outputting multiple data of the current batch stored in the output registers of multiple output interfaces). See also Figure 9The multiple data items belong to the current batch of multiple batches. These multiple batches are transmitted separately through the multiple data paths so that they can be output in parallel by the multiple output interfaces. Each batch of data includes a corresponding batch identifier. The multiple output interfaces are used to output all valid data of the same batch in parallel based on the batch identifier of each batch of data and a global output clock. Thus, by introducing a batch identifier, the data of multiple batches can be distinguished by including the batch identifier. This means that different batches of data can be sent in a rolling manner. A dedicated field can be provided to store the batch identifier, and the batch identifiers that this field can represent can be cyclically used. For example, a 2-bit field can be used to represent up to four batch identifiers, and therefore can be used cyclically. This results in a partial overlap in the data transmission cycles of two consecutive batches. That is, the first data of the next batch can be processed before the last data of the current batch is processed, and finally, the batch identifier is used to coordinate the parallel output of multiple valid data of the same batch by multiple output interfaces. Thus, by introducing a batch identifier, it helps to avoid confusion between different batches of data at the receiver and improves the overall data throughput efficiency.

[0068] In some embodiments, data transmission of the next batch relative to the current batch begins before the current batch's data transmission is complete. This helps prevent the receiver from confusing data from different batches and improves overall data throughput efficiency.

[0069] Figure 10 This is a schematic diagram of an apparatus for parallel output of multiple serial data streams, provided as an embodiment of this application. Figure 10As shown, a device 1000 for parallel output of multiple serial data channels includes a selection signal generation module A1001. The selection signal generation module A1001 generates multiple valid flag signals corresponding one-to-one with multiple valid data. The timing relationship between the valid level segments of each of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data. Multiple data paths are used to transmit multiple data and at least one clock associated with the multiple data. The multiple data includes the multiple valid data. The maximum number of the multiple valid data is not higher than the number of multiple output interfaces. Furthermore, the mapping relationship stored in the selection signal generation module indicates that the multiple valid data are separately and non-repeatingly allocated to the multiple output interfaces. The device 1000 for parallel output of multiple serial data channels also includes M data signal selectors, clock signal selectors, and enable signal selectors 1003 associated with each of the multiple output interfaces. The selection signal generation module is further configured to generate multiple sets of selection control signals corresponding one-to-one with the multiple output interfaces based on the data identifiers of the multiple valid data and the mapping relationship. These multiple sets of selection control signals respectively control the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces. The multiple data paths serve as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals serve as inputs to the enable signal selectors associated with each of the multiple output interfaces. The device 1000 for parallel output of multiple serial data receives inputs consisting of multiple data paths including S data signal lines for transmitting N valid data (multi-channel serial data), and provides outputs consisting of M output interfaces outputting N valid data in parallel.

[0070] See Figure 10The device 1000 for parallel output of multiple serial data implements a configurable mapping of M output interfaces to a total of N data from S data paths. It receives multiple serial data, which includes multiple data paths with S data signal lines for transmitting N valid data. At the software level, a valid flag signal and a selection control signal are generated by the selection signal generation module A1001. At the hardware level, data signal selectors, clock signal selectors, and enable signal selectors associated with each of the multiple output interfaces are provided, namely, data signal selectors, clock signal selectors, and enable signal selectors 1003 associated with each of the M output interfaces. Thus, through the combination of software and hardware layers, the multiple sets of selection control signals control the data signal selectors, clock signal selectors, and enable signal selectors associated with each of the multiple output interfaces. Furthermore, by setting the multiple data paths as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals as inputs to the enable signal selectors associated with each of the multiple output interfaces, a configurable mapping relationship can be achieved from multiple valid data transmitted through multiple data paths to multiple output interfaces, overcoming frequency and phase differences between signals across clock domains. In terms of hardware resource consumption and circuit area consumption, the number of output interfaces and the amount of valid data to be transmitted are decoupled, ensuring that hardware resource consumption increases linearly with the data transmission scale, significantly reducing the demand for storage hardware resources and helping to reduce area consumption. This not only effectively reduces resource consumption and circuit area consumption but also effectively overcomes the frequency and phase difference problems of cross-clock domain signal transmission. It eliminates the need for complex cross-clock synchronization or clock switching mechanisms, helping to reduce the risks of cross-clock transmission and metastability caused by large-scale combinational logic, and improving the reliability and real-time performance of data output.

[0071] Figure 11 This is a schematic diagram of an interface circuit provided in an embodiment of this application. Figure 11 The interface circuit 1100 includes: multiple output interfaces and a selection signal generation module B1101. Figure 11 The example shown includes output interfaces E1110 and F1120. It should be understood that the number of output interfaces is not specifically limited and can be set as needed. Interface circuit 1100 also includes data signal selectors, clock signal selectors, and enable signal selectors associated with each of the multiple output interfaces. Figure 11 The example shows a data signal selector E1116 associated with output interface E1110, a clock signal selector E1112 associated with output interface E1110, and an enable signal selector E1114 associated with output interface E1110. Figure 11 The diagram exemplifies a data signal selector F1126 associated with output interface F1120, a clock signal selector F1122 associated with output interface F1120, and an enable signal selector F1124 associated with output interface F1120. These multiple output interfaces are used for parallel output of multiple serial data streams, i.e. Figure 11 The system outputs 1154 data points in parallel from multiple output interfaces. Multiple data paths are used to transmit multiple data streams. Figure 11 The data signal lines 1150 in the multiple data paths and at least one clock associated with the multiple data ( Figure 11 The multiple data paths include clock signal lines 1152. The multiple data include multiple valid data as the multiple serial data, the maximum number of the multiple valid data is not higher than the number of multiple output interfaces, and the mapping relationship stored in the selection signal generation module indicates that the multiple valid data are respectively and non-repeatedly assigned to the multiple output interfaces.

[0072] See Figure 11 The selection signal generation module B1101 is used to generate multiple valid flag signals 1180 corresponding one-to-one with the multiple valid data. The timing relationship between the valid level segments of each of the multiple valid flag signals 1180 is consistent with the timing relationship between the multiple valid data. The selection signal generation module B1101 is also used to generate multiple sets of selection control signals corresponding one-to-one with the multiple output interfaces based on the data identifiers of each of the multiple valid data and the mapping relationship. The multiple sets of selection control signals respectively control the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces. The multiple data paths serve as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals serve as inputs to the enable signal selectors associated with each of the multiple output interfaces. Figure 11 The diagram illustrates the connections between multiple data paths, where data signal lines 1150 serve as inputs to data signal selectors E1116 associated with output interface E1110 and F1126 associated with output interface F1120. Clock signal lines 1152 serve as inputs to clock signal selectors E1112 associated with output interface E1110 and F1122 associated with output interface F1120. Multiple valid flag signals 1180 serve as inputs to enable signal selectors E1114 associated with output interface E1110 and F1124 associated with output interface F1120.

[0073] Continue reading Figure 11The interface circuit 1100 also includes a first circuit E1118 associated with the output interface E1110 and a second circuit E1119 associated with the output interface E1110. Thus, under the action of the enable selection signal in the selection control signal corresponding to the output interface E1110, the enable signal selector E1114 associated with the output interface E1110 selects from multiple valid flag signals 1180 and outputs the valid flag signal corresponding to the valid data allocated to the output interface E1110. Then, the valid flag signal corresponding to the valid data allocated to the output interface E1110 enables or disables the output of the clock signal selector E1112 associated with the output interface E1110 through the first circuit E1118 associated with the output interface E1110. Furthermore, under the action of the clock selection signal in the selection control signal corresponding to the output interface E1110, the clock signal selector E1112 associated with the output interface E1110 selects from multiple clock signal lines 1152 in the data path and outputs a clock signal line for transmitting the clock associated with the valid data allocated to the output interface E1110. Therefore, the valid flag signal corresponding to the valid data allocated to output interface E1110 enables or disables the output of the clock signal line used to transmit the clock associated with the valid data allocated to output interface E1110 via the first circuit E1118 associated with output interface E1110, thus obtaining the register clock signal associated with output interface E1110. The register clock signal associated with output interface E1110 is equivalent to a segment extracted from the output of the selected clock signal line by the valid flag signal corresponding to the valid data allocated to output interface E1110. Therefore, detecting the data transmission time period of the corresponding valid data by detecting the valid level segment of the valid flag signal also means that the data transmission time period of the corresponding valid data can be detected by detecting the register clock signal associated with the output interface. Furthermore, under the action of the data selection signal in the selection control signal corresponding to the output interface E1110, the data signal selector E1116 associated with the output interface E1110 selects and outputs a data signal line for transmitting valid data allocated to the output interface E1110 from the data signal lines 1150 in multiple data paths. Then, the register clock signal associated with the output interface E1110 triggers the output of the data signal line for transmitting valid data allocated to the output interface E1110 through the second circuit E1119 associated with the output interface E1110. Thus, the output interface E1110 outputs the valid data allocated to the output interface E1110.

[0074] Continue reading Figure 11The interface circuit 1100 also includes a first circuit F1128 associated with the output interface F1120 and a second circuit F1129 associated with the output interface F1120. Referring to the above description of the output interface E1110, the valid data assigned to the output interface F1110 is finally obtained.

[0075] Figure 11 The interface circuit 1100 shown implements a configurable mapping of M output interfaces to a total of N data from S data paths. It receives multiple serial data, which includes multiple data paths with S data signal lines for transmitting N valid data. At the software level, a valid flag signal and a selection control signal are generated by the selection signal generation module B1101. At the hardware level, it provides data signal selectors, clock signal selectors, and enable signal selectors associated with each of the multiple output interfaces. That is, data signal selectors, clock signal selectors, and enable signal selectors associated with each of the M output interfaces. Thus, by combining software and hardware layers, and by using multiple sets of selection control signals to control the data signal selectors, clock signal selectors, and enable signal selectors associated with each of the multiple output interfaces, and by setting the multiple data paths as inputs to the data signal selectors and clock signal selectors associated with each of the multiple output interfaces, and the multiple valid flag signals 1180 as inputs to the enable signal selectors associated with each of the multiple output interfaces, a configurable mapping relationship can be achieved from multiple valid data transmitted through multiple data paths to multiple output interfaces, overcoming frequency and phase differences between signals across clock domains. In terms of hardware resource consumption and circuit area consumption, the number of output interfaces and the amount of valid data to be transmitted are decoupled, ensuring that hardware resource consumption increases linearly with the data transmission scale, significantly reducing the demand for storage hardware resources and helping to reduce area consumption. In this way, not only is resource consumption and circuit area consumption effectively reduced, but the frequency difference and phase difference problems of cross-clock domain signal transmission are also effectively overcome. There is no need for complex cross-clock synchronization processing mechanism or clock switching mechanism, which helps to reduce the cross-clock transmission risk and metastability risk caused by large-scale combinational logic, and is conducive to improving the reliability and real-time performance of data output.

[0076] The methods and devices provided in this application are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, the embodiments, implementation methods, examples, or methods of implementation of the methods and devices can be referred to each other, and repeated details will not be repeated. This application also provides a system comprising multiple computer devices, the structure of each computer device of which can refer to the structure of the computer devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0077] This application also provides a computer-readable storage medium storing computer instructions. When these computer instructions are executed on a computer device (such as one or more processors), they can implement the method steps described in the above method embodiments. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0078] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this application can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless network communication, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0079] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0080] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A method for parallel output of multiple serial data streams, characterized in that, The method includes: Multiple data and at least one clock associated with the multiple data are transmitted through multiple data paths, wherein the multiple data includes multiple valid data, the maximum number of the multiple valid data is not greater than the number of multiple output interfaces, and the mapping relationship indicates that the multiple valid data are separately and non-repeatedly assigned to the multiple output interfaces; Generate multiple valid flag signals corresponding one-to-one with the multiple valid data, and, based on the data identifiers of the multiple valid data and the mapping relationship, generate multiple sets of selection control signals corresponding one-to-one with the multiple output interfaces, wherein the timing relationship between the valid level segments of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data, and each set of selection control signals consists of a data selection signal, a clock selection signal, and an enable selection signal; and The multiple sets of selection control signals control the data signal selector, clock signal selector, and enable signal selector associated with each of the multiple output interfaces respectively. Furthermore, the multiple data paths serve as inputs to the data signal selector and clock signal selector associated with each of the multiple output interfaces, and the multiple valid flag signals serve as inputs to the enable signal selector associated with each of the multiple output interfaces.

2. The method according to claim 1, characterized in that, The given output interface is any one of the plurality of output interfaces. The given selection control signal in the plurality of selection control signals corresponds to the given output interface. The data selection signal of the given selection control signal is used to control the data signal selector associated with the given output interface to select from the plurality of data paths a data signal line for transmitting the given valid data allocated to the given output interface. The clock selection signal of the given selection control signal is used to control the clock signal selector associated with the given output interface to select from the plurality of data paths a clock signal line for transmitting the given clock associated with the given valid data. The enable selection signal of the given selection control signal is used to control the enable signal selector associated with the given output interface to select from the plurality of valid flag signals a given valid flag signal corresponding to the given valid data.

3. The method according to claim 2, characterized in that, The output of the enable signal selector associated with the given output interface is used to enable or disable the output of the clock signal selector associated with the given output interface, thereby obtaining the register clock signal associated with the given output interface, and the register clock signal associated with the given output interface is used to trigger the output of the data signal selector associated with the given output interface.

4. The method according to claim 3, characterized in that, The output of the enable signal selector associated with the given output interface serves as the input to the control terminal of the latch circuit associated with the given output interface, the output of the clock signal selector associated with the given output interface serves as the input to the signal terminal of the latch circuit associated with the given output interface, and the register clock signal associated with the given output interface is the output of the latch circuit associated with the given output interface.

5. The method according to claim 3, characterized in that, The output of the enable signal selector associated with the given output interface serves as the input to the control terminal of the gating circuit associated with the given output interface, the output of the clock signal selector associated with the given output interface serves as the input to the signal terminal of the gating circuit associated with the given output interface, and the register clock signal associated with the given output interface is the output of the gating circuit associated with the given output interface.

6. The method according to claim 3, characterized in that, The register clock signal associated with the given output interface serves as the input to the control terminal of the trigger circuit associated with the given output interface, and the output of the data signal selector associated with the given output interface serves as the input to the signal terminal of the trigger circuit associated with the given output interface.

7. The method according to claim 6, characterized in that, The trigger circuit associated with the given output interface has a storage function and can be used to store data with a maximum data bit width not less than the plurality of valid data, and the data signal selector associated with the given output interface has a dynamic output function and can be used to adapt to the maximum data bit width of the plurality of valid data.

8. The method according to claim 3, characterized in that, When the output of the enable signal selector associated with the given output interface is at the valid level segment of the given valid flag signal, the output of the clock signal selector associated with the given output interface is enabled, and when the output of the enable signal selector associated with the given output interface is not at the valid level segment of the given valid flag signal, the output of the clock signal selector associated with the given output interface is disabled.

9. The method according to claim 8, characterized in that, The valid level segment of the given valid flag signal is a high level that lasts for one or more clock cycles.

10. The method according to claim 1, characterized in that, The at least one clock is a single clock, and the plurality of valid data share the single clock.

11. The method according to claim 1, characterized in that, The at least one clock includes multiple clocks that correspond one-to-one with the multiple valid data, and each of the multiple clocks has a different frequency.

12. The method according to claim 1, characterized in that, The valid data allocated to each of the plurality of output interfaces is stored in the respective output register of the plurality of output interfaces. The respective output registers of the plurality of output interfaces are used to output the plurality of valid data in parallel based on the global output clock. Furthermore, the update order among the respective output registers of the plurality of output interfaces is consistent with the data transmission order among the plurality of valid data.

13. The method according to claim 1, characterized in that, The multiple sets of selection control signals are generated by a selection signal generation module, which can be configured to not generate a selection control signal corresponding to at least one of the multiple output interfaces, or the output of the data signal selector associated with the at least one output interface is used as the input of a D flip-flop and the reset signal of the D flip-flop is kept active.

14. The method according to claim 1, characterized in that, The multiple data belong to the current batch, and the next batch relative to the current batch is transmitted through the multiple data paths so that it can be output in parallel by the multiple output interfaces. The data transmission of the next batch begins at least after the data transmission of the current batch is completed.

15. The method according to claim 14, characterized in that, The method further includes: changing the mapping relationship at least after the current batch of data transmission is completed and before the next batch of data transmission.

16. The method according to claim 1, characterized in that, The multiple data belong to the current batch in multiple batches. The multiple batches are transmitted through the multiple data paths so that they can be output in parallel by the multiple output interfaces. The data of each batch includes a corresponding batch identifier. The multiple output interfaces are used to output all valid data of the same batch in the multiple batches in parallel based on the batch identifier of the data of each batch and a global output clock.

17. The method according to claim 16, characterized in that, Data transmission for the next batch relative to the current batch begins before the data transmission for the current batch is completed.

18. The method according to claim 1, characterized in that, The plurality of data paths are also used to transmit at least one enable signal associated with the plurality of data, wherein a valid flag signal corresponding to valid data associated with the at least one enable signal is generated based on the at least one enable signal.

19. An apparatus for parallel output of multiple serial data streams, characterized in that, The device includes: A selection signal generation module is used to generate multiple valid flag signals corresponding one-to-one with multiple valid data. The timing relationship between the valid level segments of each of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data. Multiple data paths are used to transmit multiple data and at least one clock associated with the multiple data. The multiple data includes the multiple valid data. The maximum number of the multiple valid data is not higher than the number of multiple output interfaces. Furthermore, the mapping relationship stored in the selection signal generation module indicates that the multiple valid data are allocated to the multiple output interfaces separately and without repetition. The plurality of output interfaces are each associated with a data signal selector, a clock signal selector, and an enable signal selector. The selection signal generation module is further configured to generate multiple sets of selection control signals corresponding one-to-one with the plurality of output interfaces based on the data identifiers of the plurality of valid data and the mapping relationship. The multiple sets of selection control signals control the data signal selector, clock signal selector, and enable signal selector associated with the plurality of output interfaces respectively. The plurality of data paths serve as inputs to the data signal selectors and clock signal selectors associated with the plurality of output interfaces, and the plurality of valid flag signals serve as inputs to the enable signal selectors associated with the plurality of output interfaces.

20. An interface circuit, characterized in that, The interface circuit includes: Multiple output interfaces, wherein the multiple output interfaces are used to output multiple serial data in parallel, multiple data paths are used to transmit multiple data and at least one clock associated with the multiple data, the multiple data includes multiple valid data as the multiple serial data, the maximum number of the multiple valid data is not higher than the number of multiple output interfaces, and the mapping relationship stored in the selection signal generation module indicates that the multiple valid data are respectively and non-repeatedly assigned to the multiple output interfaces. The selection signal generation module is used to generate multiple valid flag signals that correspond one-to-one with the multiple valid data, wherein the timing relationship between the valid level segments of each of the multiple valid flag signals is consistent with the timing relationship between the multiple valid data; and The plurality of output interfaces are each associated with a data signal selector, a clock signal selector, and an enable signal selector. The selection signal generation module is further configured to generate multiple sets of selection control signals corresponding one-to-one with the plurality of output interfaces based on the data identifiers of the plurality of valid data and the mapping relationship. The multiple sets of selection control signals control the data signal selector, clock signal selector, and enable signal selector associated with the plurality of output interfaces respectively. The plurality of data paths serve as inputs to the data signal selectors and clock signal selectors associated with the plurality of output interfaces, and the plurality of valid flag signals serve as inputs to the enable signal selectors associated with the plurality of output interfaces.

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