Display device and driving method thereof

Abstract

The invention provides a display device and a driving method thereof, and relates to the technical field of display, in the display device, an application processor is configured to synthesize first visual angle image data and second visual angle image data into a group of composite image signal sources and output the composite image signal sources; the time schedule controller is configured to receive a composite image signal source output by the application processor, split the composite image signal source into first visual angle image data and second visual angle image data and output the first visual angle image data and the second visual angle image data; a first visual angle driving module in the driving module is used for receiving and outputting first visual angle image data, and a second visual angle driving module is used for receiving and outputting second visual angle image data; a first visual angle pixel unit in the display panel is used for receiving first visual angle image data output by a first visual angle driving module and displaying a first visual angle image, and a second visual angle pixel unit is used for receiving second visual angle image data output by a second visual angle driving module and displaying a second visual angle image. Therefore, the product cost is reduced and the display effect is improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display device and its driving method. Background Technology

[0002] With the development of display technology, there is a strong demand for different display images on the same screen in scenarios such as automotive display systems, public displays and privacy protection, and commercial / home entertainment, in order to provide different display images for different viewing angles. For example, a display screen needs to provide two observers in different spatial positions with independent images that do not interfere with each other. To achieve this effect, panels with specific directional light emission structures are usually used.

[0003] However, existing dual-view display products generally suffer from high hardware costs. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a display device and its driving method, aiming to reduce the hardware cost of display products.

[0005] In a first aspect, this disclosure provides a display device, including an application processor, a timing controller, a driving module, and a display panel. The application processor is configured to synthesize first-view image data and second-view image data into a composite image signal source and output it. The timing controller is electrically connected to the application processor and configured to receive the composite image signal source output by the application processor, decompose the composite image signal source into corresponding first-view image data and second-view image data, and output them. The driving module includes a first-view driving module and a second-view driving module. The first-view driving module receives and outputs first-view image data, and the second-view driving module receives and outputs second-view image data. The display panel includes first-view pixel units and second-view pixel units. The first-view pixel units receive the first-view image data output by the first-view driving module and display the first-view image, and the second-view pixel units receive the second-view image data output by the second-view driving module and display the second-view image.

[0006] Secondly, this disclosure provides a driving method for a display device, including: The application processor combines first-view image data and second-view image data into a composite image signal source and outputs it. A timing controller receives a composite image signal source, splits the composite image signal source into corresponding first-view image data and second-view image data, and outputs them. The first-view driving module receives first-view image data and transmits it to the first-view pixel unit of the display panel; the second-view driving module receives second-view image data and transmits it to the second-view pixel unit of the display panel. The first-view pixel unit in the display panel displays the first-view image based on the first-view image data, and the second-view pixel unit displays the second-view image based on the second-view image data.

[0007] The technical solution provided in this disclosure has the following advantages compared with the prior art: In this embodiment, the dual-view dual-timing controller architecture is simplified to a dual-view single-timing controller architecture. In mass production, the cost of a single high-performance timing controller is far lower than the sum of two terminal timing controllers and their peripheral circuits, thus effectively reducing product costs. Moreover, considering that the application processor needs to connect to the timing controller through physical ports, when only one timing controller is introduced, a set of physical ports can be saved on the application processor side, thereby effectively reducing the wiring complexity of the motherboard where the application processor is located.

[0008] Furthermore, when two timing controllers and two independent signal sources are introduced into the display device, image desynchronization is easily caused by clock jitter. In this embodiment, the application processor encapsulates the first-view image data and the second-view image data within the same composite image signal source, so that the two sets of data within the composite image signal source have a common synchronization signal. This physically ensures that the first-view image data and the second-view image data are absolutely aligned on the time axis, completely eliminating the risk of abnormal display such as screen tearing.

[0009] Furthermore, the display device provided in this disclosure, by introducing only one timing controller, allows for unified scheduling of the display process by a single timing controller. This enables precise allocation of charging time windows for the driving modules of both viewing angles, thus allowing for more accurate control of the driving timing of panel pixels. This avoids the uneven charging time caused by asynchronous data signals when two timing controllers are introduced. Therefore, by employing a single timing controller to uniformly schedule the driving timing of the first and second viewing angle image data, this disclosure avoids the differences in panel pixel charging time caused by asynchronous timing in multi-signal source architectures, thereby improving the brightness consistency and image stability of dual-view displays. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments relating to this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 The diagram shown illustrates one display principle of a dual-view display screen. Figure 2 This is a schematic diagram of a display device in related technologies; Figure 3 The figure shown is a plan view of a display device provided in an embodiment of this disclosure; Figure 4 The diagram shown is a structural schematic of a display device provided in an embodiment of this disclosure; Figure 5 The diagram shown is a schematic representation of signal synthesis and decomposition in a display device provided in an embodiment of this disclosure. Figure 6 The diagram shown is a schematic representation of signal synthesis and decomposition in a display device provided in an embodiment of this disclosure. Figure 7 The diagram shown is a connection schematic of a timing controller in a display device provided in an embodiment of this disclosure; Figure 8 The diagram shown is another connection schematic of the timing controller in the display device provided in the embodiment of this disclosure; Figure 9 The diagram shown is another connection schematic of the timing controller in the display device provided in the embodiment of this disclosure; Figure 10 The image shown is related to Figure 5 A diagram showing the correspondence between the vertical synchronization signal corresponding to the scheme and image data from different perspectives; Figure 11 The diagram shown is another schematic representation of signal synthesis and decomposition in a display device provided in this embodiment of the present disclosure; Figure 12 The image shown is related to Figure 6 A diagram showing the correspondence between the vertical synchronization signal corresponding to the scheme and image data from different perspectives; Figure 13 The diagram shown is another schematic representation of signal synthesis and decomposition in a display device provided in this embodiment of the present disclosure; Figure 14 The image shown is related to Figure 13 A diagram showing the correspondence between the vertical synchronization signal corresponding to the scheme and image data from different perspectives; Figure 15 The diagram shown is a schematic diagram of a film layer of a display panel provided in an embodiment of this disclosure; Figure 16 The diagram shows a connection between the scanning drive circuit and the pixel unit in the display panel. Figure 17 The diagram shown is a flowchart of a driving method provided in an embodiment of this disclosure. Detailed Implementation

[0013] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0014] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0015] Dual-view display technology projects different images onto the same screen for viewers at different angles, achieving simultaneous display of different content. Its main applications include in-vehicle display systems, public displays and privacy protection, and commercial / home entertainment. For in-vehicle display systems, the driver can view navigation or vehicle status while the passenger watches entertainment content without interference, ensuring driving safety. For public displays and privacy protection, such as ATMs or government service windows, only the user directly facing the screen can see sensitive information; observers at an angle see a blurred image or a privacy screen. For commercial / home entertainment, in gaming or television viewing scenarios, two viewers in different positions can watch their respective content in full screen without splitting the screen.

[0016] Please refer to Figure 1 Taking one car cockpit design as an example, the display screen has two types of pixels, corresponding to the driver's and passenger's viewing positions respectively. Figure 1 The diagram shown illustrates one display principle of a dual-view display screen. Figure 2 This is a schematic diagram of a display device in related technologies. Please refer to it. Figure 1 and Figure 2To achieve independent viewing angles for the driver and passenger, two timing controllers are introduced into the display screen for each perspective. Each timing controller independently receives signals from one perspective—the driver's view image data and the passenger's view image data—and sends the corresponding signals to the driver chips for that perspective. The driver chips then drive the pixels for each perspective to display, forming the driver's view and passenger's view images respectively. However, introducing different timing controllers for different perspectives results in high costs for the timing controllers themselves. Furthermore, the different interfaces and peripheral circuits required for each timing controller increase the hardware cost of the display screen. In addition, in... Figure 1 and Figure 2 In the architecture shown, dual-viewing-angle displays typically share the same set of scanning drive circuits 00. If different timing controllers are introduced, the first timing controller usually acts as the master controller connected to the scanning drive circuit 00. The first timing controller directly generates and outputs control signals (such as start pulse signals and clock signals) to the scanning drive circuit 00. The second timing controller is connected to the first timing controller via a synchronization signal line TB, and is in a controlled, subordinate synchronization state. That is, the first timing controller sends a synchronization signal to the second timing controller via the synchronization signal line TB. The first and second timing controllers control the output data signals of the first and second driver chips respectively based on the synchronization signal. In actual driving, there is an unavoidable trace delay in the transmission of the synchronization signal from the first timing controller to the second timing controller. Furthermore, the second timing controller can only control the second driver chip to output data signals after receiving the synchronization signal. Therefore, there is a time difference between the output data signals of the first and second driver chips within the same driving cycle. The start time of writing the data signal corresponding to the viewing angle pixel controlled by the second driver chip is delayed, causing the actual charging time of that viewing angle to be compressed or uneven. In terms of visual effects, this manifests as inconsistent brightness between the main and passenger screens (one bright and one dark), high-frequency flickering, and even severe screen tearing during high-speed scene transitions.

[0017] Therefore, this disclosure provides a display device. Figure 3 The figure shown is a plan view of a display device 100 provided in an embodiment of this disclosure. Figure 4 The diagram shown is a structural schematic of a display device 100 provided in an embodiment of this disclosure. Please refer to it. Figure 3 and Figure 4This disclosure provides a display device 100, including an application processor 10, a timing controller 20, a driving module 30, and a display panel 40. The application processor 10 is configured to synthesize first-view image data and second-view image data into a composite image signal source and output it. The timing controller 20 is electrically connected to the application processor 10 and is configured to receive the composite image signal source output by the application processor 10, split the composite image signal source into corresponding first-view image data and second-view image data, and output them. The driving module 30 includes a first-view driving module 31 and a second-view driving module 32. The first-view driving module 31 receives first-view image data and outputs it to the display panel, and the second-view driving module 32 receives second-view image data and outputs it to the display panel. The display panel 40 includes a first-view pixel unit P1 and a second-view pixel unit P2. The first-view pixel unit P1 receives the first-view image data output by the first-view driving module 31 and displays the first-view image, and the second-view pixel unit P2 receives the second-view image data output by the second-view driving module 32 and displays the second-view image.

[0018] In the display device provided in this disclosure, the application processor 10 can be regarded as the brain of the entire system, responsible for processing high-level image data. In the display link, it is responsible for generating, synthesizing, and outputting the original image signal. In this disclosure, the application processor 10 not only generates the original image data of the first and second perspectives, but also is responsible for synthesizing these two data streams into a composite image signal source according to specific rules. The timing controller 20 can be regarded as the central control station of the entire system, responsible for converting the received external signals into data signals that can be recognized by the driving module 30 of the display panel 40. In this disclosure, after receiving the composite image signal source from the application processor 10, the single timing controller 20 decomposes the mixed first and second perspective data according to a preset algorithm, and accurately allocates the decomposed data to the corresponding driving module 30. The driving module 30 is a driving chip that drives the display panel 40 to display, and is used to convert digital signals into data voltages, write them to the pixels in the display panel 40 through data lines, and drive the pixels in the display panel 40 to emit light.

[0019] The display device provided in this disclosure incorporates only one timing controller 20. Therefore, the application processor 10 only needs to output signals to the timing controller 20 through a set of physical links, without needing to output signals to different timing controllers 20 through different physical links. Instead, it can synthesize the first-view image data and the second-view image data into a composite image signal source. The timing controller 20 included in the display device acts as a core relay, receiving the composite image signal source transmitted by the application processor 10, and using its internal logic algorithm to split the composite image signal source into the original two-channel view data. The two split channels of data are sent to the corresponding driving modules 30 respectively. The first-view driving module 31 drives the first-view pixel unit P1 on the display panel 40 to display according to the received first-view image data, and the second-view driving module 32 drives the second-view pixel unit P2 on the display panel 40 to display according to the received second-view image data, thereby enabling the display panel 40 to present the first-view image in the first view and the second-view image in the second view.

[0020] In this embodiment, the architecture of the dual-view dual-timing controller 20 is simplified to a dual-view single-timing controller 20 architecture. In mass production, the cost of a single high-performance timing controller 20 is far lower than the sum of two terminal timing controllers 20 and their peripheral circuits, thus effectively reducing product costs. Moreover, considering that the application processor needs to connect to the timing controller 20 through a physical port, when only one timing controller 20 is introduced, the application processor 10 can also save a set of physical ports, thereby effectively reducing the wiring complexity of the motherboard where the application processor 10 is located. Here, the application processor 10 can be regarded as the main control chip electrically connected to the motherboard. The image signal generated by the application processor 10 needs to be transmitted to the physical interface through the wiring on the motherboard, and then transmitted to the timing controller 20. If the display product includes two timing controllers 20, the application processor 10 needs to output two sets of independent signals, and two sets of high-speed signal lines need to be laid on the motherboard. The more high-speed signal lines there are, the more difficult the design of anti-interference during motherboard wiring will be, and it may even be necessary to increase the number of film layers on the motherboard, resulting in a significant increase in cost. Therefore, this disclosure introduces a scheme using only one timing controller 20. After the application processor 10 synthesizes the data, only one set of high-speed signal lines needs to be drawn from the application processor 10. This significantly reduces the number of wires on the motherboard, provides more wiring space, reduces interference, and lowers costs. Thus, by introducing a timing controller 20, this disclosure reduces the number of physical transmission channels between the application processor 10 and the timing controller 20 through signal synthesis technology, thereby reducing the wiring density of the system motherboard and optimizing signal integrity.

[0021] Furthermore, when such Figure 2In the illustrated related technologies, when two timing controllers and two independent signal sources are introduced into the display device, considering that pixels from two viewing angles usually share the same set of scanning drive circuits, the first timing controller, as the master control unit, sends the start pulse signal and clock signal of the scanning drive circuit, while the second timing controller is in a controlled subordinate synchronization state. Because the synchronization signal sent from the first timing controller to the second timing controller has a physical delay, the start time of pixel data writing for the viewing angle corresponding to the second timing controller is offset, compressing the effective charging time and resulting in uneven brightness, abnormal display, or flickering between the two viewing angles. In this embodiment, through unified scheduling by a single timing controller 20, the control signals (start pulse signal and clock signal) of the scanning drive circuit 70 and the image data signals of the two viewing angles all originate from the control of the same timing controller 20. The timing controller 20 can accurately allocate perfectly aligned charging times to the first viewing angle drive module 31 and the second viewing angle drive module 32, thereby eliminating the brightness difference and color shift between the two viewing angles at the source, significantly improving the stability and visual consistency of the image quality. The application processor 10 encapsulates the first-view image data and the second-view image data in the same composite image signal source, so that the two sets of data in the composite image signal source have a common synchronization reference. With the control of a single timing controller 20, it effectively eliminates the inconsistent brightness of the dual-view images, high-frequency flicker, and screen tearing that may occur during high-speed image switching in related technologies.

[0022] Considering that when the display device is set as follows Figure 2 When two timing controllers are used, the synchronization signals between them are not synchronized due to trace delays. Since the two viewpoint pixels share the same set of scan drive circuits, when the first timing controller generates a scan signal to activate the row selection of the scan drive circuit and the first drive chip starts transmitting data signals, the data signal emitted by the second drive chip may not be transmitted to the corresponding pixel in time due to delays. This results in a shortened effective charging time for the viewpoint pixel corresponding to the second timing controller, and the system may have to shorten the effective charging time for that viewpoint, leading to unstable voltage received by that viewpoint pixel and uneven charging. In contrast, the display device provided in this disclosure introduces only one timing controller 20, and the display process is uniformly scheduled by one timing controller 20. This allows for precise allocation of charging time windows to the drive modules 30 of the two viewpoints, enabling more precise control of the drive timing of the control pixels and avoiding the uneven charging time caused by asynchronous data signals when two timing controllers 20 are introduced. Therefore, by using a single timing controller 20 to uniformly schedule the driving timing of the first-view image data and the second-view image data, this disclosure avoids the difference in panel pixel charging time caused by asynchronous timing under a multi-signal source architecture, thereby improving the brightness consistency and image stability of dual-view displays.

[0023] It should be noted that the display device provided in this disclosure can be applied to in-vehicle display systems, public displays and privacy protection, commercial / home entertainment, etc., and has extremely high scalability.

[0024] Figure 5 The diagram shown is a schematic representation of signal synthesis and decomposition in a display device provided in this embodiment of the present disclosure. Please refer to it. Figure 4 and Figure 5 In one optional embodiment of this disclosure, the application processor 10 is configured to synthesize a composite image signal source using frequency domain synthesis; the timing controller 20 is configured to extract first-view image data and second-view image data using frequency domain splitting.

[0025] In the field of display technology, frequency domain synthesis refers to high-frequency frame synthesis in the time domain. This involves increasing the transmission frequency to accommodate multiple data streams, allowing the first-view and second-view image data in a composite image signal source to share the bandwidth of the same physical link. For example, application processor 10 compresses and arranges two originally independent low-frequency signals (assuming two 60Hz signals) on the time axis, merging them into a single high-frequency signal (e.g., a 120Hz signal). During frequency domain splitting, timing controller 20 acts as a frequency divider or timing distributor, receiving signals at a high sampling rate and, based on the characteristic information of each frame (such as frame header tags or parity order), restoring the high-frequency signal stream into the low-frequency drive signals required by the two display panels 40. This embodiment of the present disclosure, through frequency domain synthesis, transforms the physical pins of application processor 10 and motherboard wiring from a dual-path to a single-path, reducing the design complexity of the motherboard and facilitating the implementation of compact automotive motherboards or space-constrained ultra-thin displays.

[0026] When a composite image signal source is formed using frequency domain synthesis, the first-view image data and the second-view image data share the bandwidth of the same physical link. Therefore, the physical transmission delay, impedance matching, and electromagnetic interference environment are consistent for all data. Furthermore, in the composite image signal source synthesized by a single timing controller 20, the first-view image data and the second-view image data share a common reference frequency. That is, since the same timing controller 20 is used, the data signals provided to the first-view driving module 31 and the second-view driving module 32, as well as the control signals to the scan driving circuit 70, are all generated by the same timing controller 20. This ensures that under the control of the same scan signal, the writing time of the data signals corresponding to pixels in the same row at different viewpoints is aligned on the time axis. In contrast, in related technologies, due to the delay in the synchronization signal between the two timing controllers, the data signal is easily offset relative to the turn-on signal (scan signal) of the scan driving circuit (e.g., after the scan driving circuit is turned on under the control of the scan signal, the data signal is not written immediately due to the delay). This offset can cause insufficient writing of pixels in one viewpoint due to the shortened effective charging window, or even result in incomplete or torn images in that viewpoint, while the image in the other viewpoint can be displayed normally. If the aforementioned offset is too large, the data originally written to one viewpoint pixel may interfere with the signal from another viewpoint, causing crosstalk. However, this disclosure uses a single timing controller 20 to synchronize the timing of the first-view image data and the second-view image data, effectively solving the problem of screen tearing or crosstalk caused by asynchronous data signal writing.

[0027] Please continue to refer to this. Figure 4 and Figure 5 When this disclosure uses frequency domain synthesis to combine signals that were originally transmitted in parallel on two physical channels into one channel for transmission, in one optional embodiment of this disclosure, the maximum operating frequency supported by the timing controller 20 is greater than or equal to the sum of the display frequency of the first view image and the display frequency of the second view image. In this way, the processing capability of the timing controller 20 can cover the extreme requirements of the two viewpoints at high refresh rates.

[0028] If the maximum operating frequency of the timing controller 20 is less than the sum of the display frequencies of the first-view image and the second-view image, the composite image signal source transmitted from the application processor 10 will overflow or stack at the input of the timing controller 20, resulting in frame drops, screen tearing, or a black screen. Therefore, setting the maximum operating frequency supported by the timing controller 20 to be greater than or equal to the sum of the display frequencies of the two view images ensures that, in single-channel composite signal transmission mode, both the first-view image data and the second-view image data can be fully received and processed, guaranteeing the integrity of the dual-view display.

[0029] Considering that when two timing controllers are introduced into a display device, they can only operate at the same frequency to maintain synchronization, this disclosure introduces only one timing controller 20. When the upper limit of the operating frequency of the timing controller 20 is sufficiently high, the system can support asymmetric bandwidth allocation. For example, first-view image data can be displayed for static navigation (60Hz), while second-view image data can be displayed for high-speed games (90Hz or 120Hz). This configuration makes resource allocation more scientific and effectively improves the user experience.

[0030] Please continue to refer to this. Figure 5 In one optional embodiment of this disclosure, the frame rate of the composite image signal source is greater than or equal to the sum of the display frequency of the first-view image and the display frequency of the second-view image. Here, the frame rate is the number of static image frames transmitted or displayed per second, measured in Hz.

[0031] In this disclosure, since the first-view image data and the second-view image data are combined in the same composite image signal source, the frame rate (i.e., the number of frames transmitted per unit time) of the composite image signal source must be able to accommodate all the data from both perspectives. For example, please refer to... Figure 5 When both the first-view and second-view images are displayed at 60Hz, the frame rate of the composite image signal source must be at least 120Hz. For another example, please refer to... Figure 6 , Figure 6 The diagram illustrates another example of signal synthesis and decomposition in a display device according to an embodiment of this disclosure. When the display frequency of the first-view image is 60Hz and the display frequency of the second-view image is 90Hz, the frame rate of the composite image signal source must be at least 150Hz. To achieve this frame rate, the application processor 10 needs to compress the two images in the time domain. For example, a frame that originally occupied 1 / 60th of a second is compressed into a time slot of approximately 1 / 150th of a second in the composite signal for transmission. If the frame rate of the composite image signal source is lower than the sum of the display frequencies of the first-view image and the second-view image, the application processor 10 will be unable to transmit complete dual-view pixel information within the specified time. Therefore, this embodiment limits the frame rate of the composite image signal source to be greater than or equal to the sum of the display frequencies of the first-view image and the second-view image, ensuring that the display link has sufficient bandwidth capacity. This ensures that even when both perspectives are operating under high load simultaneously (such as when the driver and passenger are watching high frame rate video), image data can be delivered to the timing controller 20 in real time and completely, without causing frame drops, stuttering, or resolution degradation due to insufficient bandwidth.

[0032] This embodiment of the disclosure sets the frame rate of the composite image signal source to be greater than or equal to the sum of the display frequencies of the first-view image and the second-view image. This allows the system to obtain a high-frequency signal stream. The timing controller 20 can then extract different proportions of frames from this high-frequency signal stream and allocate them to the left and right views as needed. For example, please refer to... Figure 6 In a 150Hz composite stream, 2 frames are extracted for the first-person view and 3 frames for the second-person view every 5 frames, thus perfectly supporting the asymmetric refresh rate requirements of the driver and passenger.

[0033] It should be noted that when the frame rate of the composite image signal source is greater than the sum of the display frequencies of the first-view image and the second-view image, the transmission bandwidth becomes redundant. In high-frequency transmission, to prevent data overflow or to allow time for decompression / conversion for the timing controller 20, a slightly higher composite frame rate can be set. This helps ensure more robust signal transmission under complex electromagnetic interference.

[0034] Since the first-view image data and the second-view image data in the composite image signal source are transmitted in the same set of physical links (the connection link between the application processor 10 and a timing controller 20), and the same physical link corresponds to only one vertical synchronization signal at any given time, the first-view image data and the second-view image data are always mounted in the same set of vertical synchronization signal sequences, regardless of whether the frame rate of the composite image signal source is equal to or greater than the sum of the display frequencies of the two views. This ensures that even with bandwidth redundancy, the data frames of the two views still have a fixed relative phase relationship on the time axis, thereby eliminating the risk of frequency drift that is unavoidable between asynchronous signal sources.

[0035] Please continue to refer to this. Figure 4 In one optional embodiment of this disclosure, the timing controller 20 is electrically connected to the first viewpoint driving module 31 via a first output port 21 and to the second viewpoint driving module 32 via a second output port 22. The data transmission bandwidth of the first output port 21 is the same as that of the second output port 22. Bandwidth is a core indicator for measuring data transmission capability, representing the total amount of data that a link can transmit per unit time, i.e., the theoretical maximum rate limit that a port can support. In practical applications, the bandwidth of a port is equal to the product of the number of effective physical channels included in the port and the data transmission rate of a single channel. For example, assuming a port has 4 physical channels, and the data transmission rate of each physical channel is approximately 1.05 Gbps, then the bandwidth of the port is 1.05 × 4 = 4.2 Gbps.

[0036] This embodiment configures the timing controller 20 to output to two viewpoints after splitting the composite image signal source. The timing controller 20 has two sets of independent output ports: the first output port 21 is dedicated to the first viewpoint, and the second output port 22 is dedicated to the second viewpoint. This dedicated design achieves physical isolation of the electrical signals before they reach the pixel units.

[0037] When the data transmission bandwidth of the first output port 21 and the second output port 22 is the same, the number of physical channels allocated by the timing controller 20 to the first output port 21 and the second output port 22 is consistent, regardless of whether the image content displayed in the two viewpoints is the same or the display frequency is the same. The single-channel data transmission rate is also consistent. In display products, if the specifications of the two ports are inconsistent, the motherboard wiring needs to be designed in two different ways for different impedances and speeds. The same bandwidth allows the two ports to use a completely symmetrical hardware circuit design. This not only reduces the complexity of the motherboard wiring where the timing controller 20 is located, but also allows the driver modules 30 for the two viewpoints to use the same type of chip, significantly improving the versatility of components and further reducing supply chain costs.

[0038] Furthermore, by setting the bandwidth of the first output port 21 and the second output port 22 to be the same, the system ensures that even if one viewpoint has extremely high smoothness requirements (such as high frame rate e-sports or video), the other port has the same performance reserve. This design eliminates performance bottlenecks, allowing the system to flexibly handle various complex display combination scenarios.

[0039] If the two ports have different bandwidths, the logic circuitry inside the timing controller 20 needs to handle two completely different sets of clock recovery and data packetization logic, which can easily lead to processing delay differences. Having the same bandwidth ensures that the two output ports inside the timing controller 20 are highly consistent in clock frequency and data packet format. This mirrored output processing ensures that the driving data from the first and second perspectives have extremely high timing synchronization when delivered to their respective pixel units, thereby avoiding brightness differences or uneven charging times caused by mismatched transmission speeds.

[0040] Therefore, by limiting the data transmission bandwidth of the two output ports to be the same, this disclosure not only achieves high symmetry and cost optimization at the hardware level, but also ensures, through the configuration principle of 'higher performance is preferred', that the timing controller 20 can provide sufficient and consistent data throughput to each viewpoint drive module 30 when processing images from different frequencies and perspectives, thus guaranteeing the brightness consistency of the dual-view display from the physical link layer.

[0041] Please refer to Figure 4 and Figure 5In one optional embodiment of this disclosure, the display frequency of the first-view image on the display panel 40 is equal to the display frequency of the second-view image, and the data transmission bandwidth of the first output port 21 and the second output port 22 is greater than or equal to the required transmission bandwidth of the first-view image or the second-view image. Assuming that the display frequencies of both the first-view image and the second-view image are 60Hz, the data transmission bandwidths of the first output port 21 and the second output port 22 can both be set to 60Hz or higher, provided they are equal. It should be noted that this disclosure only uses the example of both the first-view image and the second-view image being 60Hz, but it is not limited to this. In some other embodiments disclosed, the display frequencies of the first-view image and the second-view image can be set to other arbitrary values ​​according to actual application requirements, such as both being 90Hz, both being 120Hz, etc.

[0042] When the display frequencies of the first and second perspectives are equal, the physical transmission capacity provided by the two output ports of the timing controller 20 must cover the highest data volume required by a single perspective at the current frequency. This embodiment ensures that, in dual-view simultaneous operation mode, pixel data from each perspective can be transmitted in real-time at full resolution. It eliminates image compression, frame drops, or color distortion that may occur due to insufficient port bandwidth, guaranteeing a high-quality visual experience for both first-view and second-view users. By setting the bandwidth of the two output ports to be greater than or equal to the transmission bandwidth required for the first-view or second-view image, equal and ample bandwidth can be provided to the first and second output ports, ensuring that signal congestion or errors do not occur during high-dynamic scene (such as video) switching.

[0043] This bandwidth margin is reserved for data transmission when the port bandwidth exceeds the required transmission bandwidth for either the first-view or second-view image. In scenarios with extreme temperature rises or severe electromagnetic interference, such as in automotive applications, this bandwidth margin provides higher signal-to-noise ratio tolerance. Even if slight jitter occurs during signal transmission, the system can maintain a stable display effect due to sufficient bandwidth, effectively improving system reliability.

[0044] The above embodiments describe a scheme where the display frequencies of the first-view image and the second-view image are the same. However, this disclosure is not limited to this; it also applies to situations where the display frequencies of the first-view image and the second-view image are different. For example, please refer to... Figure 4 and Figure 6In one optional embodiment of this disclosure, the display frequency of the first-view image of the display panel 40 is not equal to the display frequency of the second-view image, and the data transmission bandwidth of the first output port 21 and the second output port 22 is greater than or equal to the transmission bandwidth required by the higher display frequency of the first-view image and the second-view image.

[0045] by Figure 6 For example, in this embodiment, the display device needs to be compatible with both a high-frequency display (e.g., 90Hz) and a low-frequency display (e.g., 60Hz). In this case, the first output port 21 and the second output port 22 do not set their bandwidth according to the actual frequency of their respective viewing angles, but instead uniformly adopt the higher frequency principle. When the display frequencies of the two viewing angles are 60Hz and 90Hz respectively, then both the first output port 21 and the second output port 22 are configured to 90Hz or higher. It should be noted that... Figure 6 This embodiment uses a first-view image display frequency of 60Hz and a second-view image display frequency of 90Hz as an example for illustration, but it is not limited to this. In practical applications, the display frequency of the first-view image and the display frequency of the second-view image can be set to any other unequal value.

[0046] When the display frequencies of the first-view image and the second-view image are different, and the first output port 21 and the second output port 22 operate at different bandwidths, related technologies require two independent clock generators within the timing controller. For example, when the first output port transmits data at a display frequency of 60Hz and the second output port transmits data at a display frequency of 90Hz, related technologies typically use two clock generators to make the single-channel data transmission rate of the first output port lower and the single-channel data transmission rate of the second output port higher. However, this disclosure sets the bandwidth of the first output port 21 and the second output port 22 to be uniformly set to be greater than or equal to the transmission bandwidth required by the higher display frequency of the first-view image and the second-view image. The timing controller 20 can share the same clock generator and a common clock reference, making the single-channel data transmission rates of the first output port 21 and the second output port 22 the same. This effectively simplifies the internal design of the timing controller 20, eliminates the dynamic scheduling resources of a clock generator, reduces the computational overhead and hardware heat generation caused by frequency conversion, and effectively ensures the synchronization of data writing under different perspectives. Furthermore, by uniformly setting the bandwidth of both ports to the highest level, it ensures that the "single-channel data transmission rate" of pixels from both viewing angles is completely equal during each frame refresh. For low-frequency viewing angles (such as 60Hz), data transmission at high bandwidth will generate more idle cycles, but this ensures that the start time of its effective charging pulse is completely synchronized with that of the high-frequency viewing angle. This effectively eliminates pixel brightness differences caused by inconsistent driving speeds, ensuring stable brightness consistency even under different frequency conditions.

[0047] This embodiment uses high-frequency ranges as a unified standard, providing a significant bandwidth margin for low-frequency viewing angles. In scenarios with severe electromagnetic interference, this redundancy can significantly improve the signal-to-noise ratio, prevent data transmission errors, and ensure that critical information such as navigation on the low-frequency viewing angle side remains clear and stable.

[0048] In this solution, a high-performance bandwidth configuration strategy is adopted for inter-frequency display scenarios. By unifying the specifications of the physical links, absolute alignment of the driving timing at the logical level is achieved. This not only simplifies the architecture design of the timing controller 20, but more importantly, it ensures that when the high-frequency and low-frequency perspectives share the timing controller 20, their pixel charging waveforms have the same starting characteristics on the time axis, thereby fundamentally solving the pain point of brightness deviation under inter-frequency driving.

[0049] Figure 7 The diagram shown is a connection schematic of the timing controller 20 in the display device provided in this embodiment. Please refer to it. Figure 7In one optional embodiment of this disclosure, the timing controller 20 includes a buffer unit 23, which is configured to buffer image data in the composite image signal source and convert the composite image signal source with a receiving rate of a first bit rate into image data output with a transmitting rate of a second bit rate. The first bit rate is proportional to the sum of the display frame numbers of the first-view image and the second-view image. That is, the higher the display frame number, the greater the required bit rate.

[0050] Please refer to Figure 7 In the timing controller 20, the cache unit 23 is used to temporarily store the composite image signal source retrieved at high speed from the application processor 10. In this embodiment, the second bit rate is the speed at which the timing controller 20 outputs to the first viewpoint driving module 31 and the second viewpoint driving module 32, which can be considered as the read speed. The first bit rate refers to the rate at which the composite image signal source enters the timing controller 20, i.e., the write speed, which can be understood as the bandwidth requirement of the link between the application processor and the cache unit. It is proportional to the sum of the display frames of the first and second viewpoint images. For example, if both viewpoint display frequencies are 60Hz, then within one cycle (1 second), the application processor needs to transmit a total of 120Hz of data to the cache unit 23. Therefore, in order to transmit 120 frames instead of 60 frames per second, the number of frames transmitted per second is proportional to the sum of the display frequencies of the two viewpoints. Similarly, if the viewpoint display frequencies are 60Hz and 90Hz respectively, then within one cycle (1 second), the application processor needs to transmit a total of 150Hz of data to the cache unit 23.

[0051] When only one timing controller 20 is introduced into the display device, the application processor merges the first-view image data and the second-view image data into a composite image signal source and sends it to the timing controller 20 at a relatively high first bit rate. The buffer unit 23 in the timing controller 20 receives the composite data at a high flow rate, buffers it, and then outputs it smoothly according to the rhythm (second bit rate) actually required by the panel. This eliminates the need for the back-end driver module 30 to support extremely high frequencies, thereby reducing the hardware performance requirements of the driver module 30 and contributing to cost reduction.

[0052] Furthermore, considering that during high-speed transmission, the composite image signal source sent by the application processor 10 may experience slight time deviations due to electromagnetic interference, the data undergoes a "data reassembly" after entering the buffer unit 23. The timing controller 20 can reorder the data in the buffer according to its internal precise clock. This means that the signals output to the drive modules 30 of the two viewpoints are trimmed and fully aligned. This further ensures the synchronization of the two viewpoints and avoids screen tearing. When the frequencies of the first viewpoint (e.g., 60Hz) and the second viewpoint (e.g., 90Hz) are inconsistent, the input composite signal stream is highly irregular. The buffer unit 23 can automatically handle this "asymmetric" data stream. It stores the mixed 150 frames of data and then outputs them to different ports according to the respective beats of 60Hz and 90Hz. As a "buffer layer," the buffer unit 23 makes the inter-frequency drive logically transparent and robust, and the system will not experience momentary blackouts or flickering due to frequency switching.

[0053] Therefore, this disclosure achieves effective decoupling between the input high-frequency composite signal and the output viewing angle drive signal by introducing a buffer unit 23 into the timing controller 20. The buffer unit 23 can not only adapt to the viewing angle requirements of different frequencies through rate conversion, but also acts as a timing relay station, eliminating clock jitter in the transmission link and ensuring that the image data received by the back-end drive module 30 has extremely high timeliness determinism, fundamentally optimizing the brightness uniformity and image smoothness of dual-view display.

[0054] Figure 8 The diagram shown is another connection schematic of the timing controller 20 in the display device provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 8 In one optional embodiment of this disclosure, the timing controller 20 includes a frame counter 24, which is configured to identify the frame order of the received composite image signal source. Optionally, the frame counter 24 operates by numbering each frame in real time (e.g., 1, 2, 3, 4...) when the composite image signal source enters the timing controller 20. During frame order identification, the timing controller 20 identifies which viewpoint a frame with a specific number belongs to according to a preset protocol or algorithm. For example, in the odd-even frame synthesis mode, if the counter identifies an "odd number," it is determined to be a first-view image, and if it identifies an "even number," it is determined to be a second-view image.

[0055] The frame counter 24 is a hardware-level, high-speed processing logic device that does not require complex software decoding. Through simple numerical comparison, the timing controller 20 can complete frame attribute determination in a very short time (microseconds) and directly direct it to the corresponding output port. This ensures high real-time performance for dual-view switching. When the display frequencies of the two views are different, the frame arrangement is no longer a simple one-to-one ratio but may involve complex matching principles. In this case, the frame counter 24 can work with more complex logic algorithms to accurately record the position of each frame in a one-second loop. It ensures that even in complex inter-frequency sequences, each frame corresponds to the accurate viewpoint, avoiding crosstalk between the first-view user and the second-view user. Furthermore, the timing controller 20 identifies the "identity" of each frame through the frame counter 24. Based on this identified identity, the timing controller 20 can precisely trigger the activation timing of the corresponding viewpoint's drive module 30. Because the counting is synchronous and continuous, the pixel charging pulses of the first and second views are arranged in an orderly manner on the timeline, completely eliminating timing competition at the logical level and ensuring a high degree of uniformity in brightness performance.

[0056] Therefore, by integrating a frame counter 24 into the timing controller 20, this solution constructs a real-time frame sequence recognition system for high-speed composite signal streams. This counter, serving as the logical benchmark for signal splitting, not only achieves accurate splitting of multi-view image data but also guides the back-end drive module 30 to execute pixel charging actions according to a preset clock through determined frame attribute judgments. This effectively avoids the risk of timing disorder under multi-channel asynchronous driving and ensures the consistency of image purity and brightness in dual-view displays.

[0057] Figure 9 The diagram shown is another connection schematic of the timing controller 20 in the display device provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 9 This embodiment illustrates a timing controller 20 that includes both a frame counter 24 and a buffer unit 23. The composite image signal source output by the application processor 10 is first transmitted to the frame counter 24. After frame order recognition by the frame counter 24, it is then transmitted to the buffer unit 23. The buffer unit 23 stores the data into a specific memory address based on the recognition result of the frame counter 24. For example, data from the first viewpoint can be stored in the first buffer area, and data from the second viewpoint can be stored in the second buffer area. During subsequent transmission, the data in the first buffer area is accurately transmitted to the first viewpoint driving module 31, and the data in the second buffer area is accurately transmitted to the second viewpoint driving module 32. Thus, the frame order recognition established by the frame counter 24 ensures that the data in the buffer unit 23 is always ordered. Therefore, at the physical level, data from one viewpoint will never be included in the pixel period of another viewpoint, effectively improving the transmission accuracy and reliability of the two viewpoint data.

[0058] Figure 10 The image shown is related to Figure 5 A diagram showing the correspondence between the vertical synchronization signal and image data from different viewpoints for the proposed scheme. Please refer to [the diagram]. Figure 4 , Figure 5 and Figure 10 In one optional embodiment of this disclosure, the timing controller 20 is configured to generate a viewpoint switching control signal based on the trigger edge of the vertical synchronization signal. The viewpoint switching control signal is configured to control the opening or closing of the first output port 21 and the second output port 22 of the timing controller 20.

[0059] In practical applications, the vertical synchronization signal is generated by the application processor 10 according to a preset refresh rate. The application processor 10 embeds the vertical synchronization signal into the packet header of the composite image signal source or a specific timing gap, and sends it along with the first-view image data and the second-view image data to the timing controller 20. The vertical synchronization signal can be, for example, a narrow pulse, whose rising or falling edge marks the start of a frame. The vertical synchronization signal serves as the reference for frame synchronization, and its number is consistent with the total number of frames displayed for the first-view and second-view image data. For example, for a composite image signal source of 120Hz, there will be 120 vertical synchronization signals per second, each corresponding to one frame of image data. Similarly, for a composite image signal source of 150Hz, there will be 150 vertical synchronization signals per second, each corresponding to one frame of image data. The frame counter 24 inside the timing controller 20 identifies the sequence number of the vertical synchronization signal and guides the corresponding display frame data to a specific port according to preset logic. That is, the pulse frequency of the vertical synchronization signal matches the sum of the display frames of the first and second viewpoints. The timing controller 20 counts the vertical synchronization signals, identifies the logical sequence number of each frame, and guides the image data to the corresponding output port according to the sequence number to achieve precise splitting of multi-view images. For example, the first vertical synchronization signal corresponds to the first frame of image data. The frame counter 24 identifies which viewpoint the first frame of image data belongs to, thereby triggering the data transmission of the corresponding port. When the frame counter 24 determines that the current frame belongs to the first viewpoint, the data flows to the first output port 21; when the frame counter 24 determines that the current frame belongs to the second viewpoint, the data flows to the second output port 22.

[0060] In dual-view displays, if data from the first view accidentally flows to the second view, or vice versa, ghosting or crosstalk will occur. This embodiment, through the coordination of the vertical synchronization signal and the frame counter 24, ensures that the switching of data packets and the start of the frame period are physically perfectly aligned. This hard-wired triggering mechanism eliminates potential delays caused by software scheduling, guaranteeing a seamless separation between the first and second view images.

[0061] In this disclosure, since the viewing angle switching signal is generated by a single vertical synchronization signal, the "on-window period" of the first output port 21 and the second output port 22 is controlled by the same high-precision clock. This ensures that the driving current delivered to the first and second pixel units is strictly symmetrical or proportionally predetermined in terms of time length. The charging start time of each row of pixels corresponds to the beat of the vertical synchronization signal, eliminating brightness fluctuations at the source. This disclosure controls the opening or closing of the first output port 21 and the second output port 22 by using a viewing angle switching control signal generated based on the trigger edge of the vertical synchronization signal. Through this dynamic "on / off" control, the driving module 30 receives data and operates only within its own frame period. During non-operating time slots, the ports are in a closed state. This time-division multiplexing control method effectively reduces the static power consumption of the module and reduces the heat generated by the vehicle screen during high-power operation.

[0062] Considering that if the timing controller 20 broadcasts data to all ports simultaneously, the back-end driver module 30 would need complex logic to identify which data belongs to it. Therefore, in this embodiment, the timing controller 20 completes the grouping at the front end through the output port switching. For the driver module 30, it only needs to receive the signal when the port is open, without needing to perform complex frame header recognition. This reduces the processing power requirements of the driver module 30 and facilitates the selection of more cost-effective driver chips.

[0063] Therefore, this scheme establishes a direct correlation between the trigger edge of the vertical synchronization signal and the port switch control, realizing a deterministic physical-level time-division multiplexing architecture. This architecture not only locks the charging start time of pixels at each viewing angle through the vertical synchronization signal, eliminating the hidden danger of uneven brightness distribution, but also constructs a physical isolation band between data from different viewing angles through the active shielding mechanism of the port, completely solving the problems of signal crosstalk and power redundancy under high-frequency composite driving.

[0064] Please refer to Figures 7 to 9In one optional embodiment of this disclosure, when the first output port 21 or the second output port 22 is closed, the closed output port remains in a high-impedance state. When the output port is in a high-impedance state, it is electrically equivalent to being disconnected from the back-end drive module 30. At this time, the port neither outputs a high level nor a low level, and current can hardly flow through it. When the trigger edge of the vertical synchronization signal indicates a switch from the first viewing angle to the second viewing angle, the timing controller 20 controls the first output port 21 to enter a high-impedance state, and simultaneously controls the second output port 22 to enter an active operating state. Conversely, when the trigger edge of the vertical synchronization signal indicates a switch from the second viewing angle to the first viewing angle, the timing controller 20 controls the second output port 22 to enter a high-impedance state, and simultaneously controls the first output port 21 to enter an active operating state.

[0065] In high-speed signal transmission, if a closed port merely stops transmitting data but remains at a certain voltage level (e.g., low level), a physical loop still exists between that port and the back-end viewing angle driving module 30, which can easily generate induced current through parasitic capacitance. Maintaining a high-impedance state is equivalent to physically cutting off power. This ensures that residual electrical signals from the first viewing angle will never couple into the driving loop of the second viewing angle, thus guaranteeing the purity of the image at the lowest level and completely eliminating the possibility of overlapping images from different viewing angles. Moreover, if the port remains at a fixed level when not in operation, the output stage circuit will still have static power consumption. In the high-impedance state, the power transistors of the output stage are in the off state, and the current consumption is reduced to the microamp level. This helps to significantly reduce the overall power consumption of the display device. Furthermore, when an output port is in a high-impedance state, it will not exert any load pressure on the power line. This ensures that the power system can focus all its energy on supplying the other output port that is currently working, ensuring the purity and stability of the voltage when charging each frame of pixels.

[0066] Therefore, this embodiment achieves deep electrical isolation during the viewing angle switching process by limiting the closed port to enter a high-impedance state. This design not only significantly reduces the power consumption and temperature rise of the display module by cutting off the static current path, but more importantly, it eliminates electromagnetic interference between inactive ports and active ports, ensuring that the driving energy can act accurately and without interference on the target pixel unit, thereby enhancing the brightness uniformity and color purity of the dual-view display from a physical level.

[0067] Please continue to refer to this. Figure 5 and Figure 6In one optional embodiment of this disclosure, the composite image signal source includes multiple frames of image data. These multiple frames of image data include alternately transmitted first frame group data Z1 and second frame group data Z2, for example, forming a loop of first frame group data Z1, second frame group data Z2, first frame group data Z1, second frame group data Z2… on the time axis. Wherein, the first frame group data Z1 is first-view image data, and the second frame group data Z2 is second-view image data. Each first frame group data Z1 includes at least one frame of image data, and each second frame group data Z2 includes at least one frame of image data.

[0068] In this embodiment, the first frame group data Z1 and the second frame group data Z2 each include at least one frame of image data. Thus, the number of frames in the image data contained in the first frame group data Z1 and the second frame group data Z2 can be set to the same, or they can be set to be different as needed. By adjusting the number of frames contained in the first frame group data Z1 and the second frame group data Z2, different display strategies can be implemented. For example, when the display frequency of the first-view image and the second-view image is the same, the number of frames contained in the first frame group data Z1 can be set to be the same as the number of frames contained in the second frame group data Z2. Figure 5 This example illustrates how both frame group Z1 and frame group Z2 contain 1 frame. For situations where the display frequencies of the first-view and second-view images differ, the number of frames in frame group Z1 and frame group Z2 can be set differently, thereby improving application flexibility. Figure 6 The illustrated embodiment is illustrated by taking the first frame group data Z1, which includes 2 frames, and the second frame group data Z2, which includes 3 frames.

[0069] Because the first frame group data Z1 and the second frame group data Z2 are transmitted alternately and regularly in this disclosure, the timing controller 20 can predict the ownership of subsequent arriving data. This allows the timing controller 20 to allocate extremely regular, periodic opening windows to the first-view and second-view pixels. Even if there are multiple frames within a frame group, because they share the same clock source, the time for each frame pixel to acquire charge is completely constant, thus ensuring a high degree of uniformity in brightness between the first-view and second-view images, eliminating flicker.

[0070] Please continue to refer to this. Figure 5 In one optional embodiment of this disclosure, the number of image data frames included in a first frame group data Z1 is the same as the number of image data frames included in a second frame group data Z2. In this case, both the first frame group data Z1 and the second frame group data Z2 may include only one frame of image data, or they may include two or more frames of image data.

[0071] This implementation describes a scheme where the first-view image data and the second-view image data occupy completely equal time slices in the composite image signal stream. On the time axis, the data exhibits a highly regular periodic arrangement. For example, please refer to... Figure 5 If all frames are 1, the sequence is first-view - second-view - first-view - second-view...; or, please refer to... Figure 11 If the number of frames is 2 for each frame, then the sequence is: first view, first view - second view, second view - first view, first view - second view, second view... where, Figure 11 The diagram shown illustrates another example of signal synthesis and decomposition in the display device provided in this embodiment. Thus, when the timing controller 20 processes two signals, the timing overhead, buffer usage, and port switching frequency of its internal logic are completely consistent. The identical frame rate ensures that the "exposure opportunities" obtained by the two viewpoints per unit time are completely equal. This high degree of visual symmetry effectively eliminates screen flicker caused by uneven refresh rates, ensuring that the smoothness of the image observed from both the first and second viewpoints remains highly consistent.

[0072] Furthermore, when the number of image data frames included in a single first frame group data Z1 is the same as the number of image data frames included in a single second frame group data Z2, the timing controller 20 can employ the simplest toggle logic, operating at the most stable fixed frequency without frequent phase adjustments. This reduces the switching losses of the logic gates inside the timing controller 20, decreases chip heat generation, and also reduces the risk of electromagnetic interference generated by the system.

[0073] Please refer to Figure 6 In one optional embodiment of this disclosure, a first frame group data Z1 includes m frames of image data, and a second frame group data Z2 includes n frames of image data, where m≥1, n≥1, and m≠n. Figure 6Taking a first frame group data Z1 comprising 2 frames of image data and a second frame group data Z2 comprising 3 frames of image data as an example, this is not a limitation. In other embodiments of this disclosure, m and n can be set to any other unequal values ​​as needed. This embodiment describes the case of asymmetric frequency display of the display device. For example, in automotive applications, the driver's view requires low-power 60Hz static conduction, while the passenger's view requires smooth video at 90Hz or 120Hz. Thus, within a complete transmission cycle, the time slices occupied by the first and second views are unequal. The values ​​of m and n directly correspond to the ratio of the two display frequencies. For example, if the composite image signal source is 150Hz, setting m=2 and n=3, then the first view is allocated to 60Hz, and the second view is allocated to 90Hz. This design allows the timing controller 20 to flexibly adjust the output rhythm of the two images by adjusting the division ratio of the internal counter without changing the total bandwidth of the physical link.

[0074] Traditional solutions struggle to drive two viewing angles at different refresh rates on the same display panel 40. This disclosure, by limiting m≠n, allows the system to precisely allocate bandwidth based on the content attributes of each viewing angle. For example, a smaller m value is allocated for the driver watching navigation (not sensitive to frame rate), while a larger n value is allocated for the passenger watching movies (sensitive to smoothness). This not only optimizes the visual experience but also reflects the intelligent allocation of bandwidth in the vehicle display. Forcing the driver to also run at a high frequency of 90Hz would generate unnecessary power consumption. Therefore, this disclosure sets m≠n to allow lower-frequency viewing angles to maintain a lower data update rate. While ensuring display quality, reducing the effective transmission frequency of one path reduces the switching power consumption between the timing controller 20 and the drive module 30, thereby reducing module heat, which is crucial for vehicle center consoles with limited heat dissipation.

[0075] Furthermore, since the "basic time unit" (i.e., the transmission slot of each frame) of m-frames and n-frames is determined by the same master clock, the activation pulses of the first-view and second-view pixels are scaled synchronously. For example, please refer to... Figure 12 , Figure 12 The image shown is related to Figure 6 The diagram shows the correspondence between the vertical synchronization signal and image data from different viewpoints. This ensures that even with different refresh rates, the instantaneous bit rate and timing edge alignment accuracy of the m-frame data from the first viewpoint and the n-frame data from the second viewpoint are completely consistent after entering the timing controller 20 buffer and output to the driver module 30. The single-frame charging time of the two can still maintain a strict proportional consistency, thereby eliminating brightness differences and flicker unevenness.

[0076] Therefore, this disclosure constructs a time-division multiplexing architecture with adjustable ratios by configuring unequal numbers of frames m and n within a frame group. This architecture, while maintaining a unified global reference frequency, achieves on-demand allocation of bandwidth resources for dual-viewpoint displays. This not only effectively supports the differentiated needs of inter-frequency displays from different viewing angles but also ensures pixel charging stability under inter-frequency driving conditions through precise time-domain alignment, resolving the contradiction between performance redundancy and brightness deviation in multi-viewpoint displays.

[0077] Please refer to Figure 8 and Figure 9 In one optional embodiment of this disclosure, when the frame counter 24 identifies the first frame group data Z1, the timing controller 20 is configured to open the first output port 21 and close the second output port 22, and transmit the first frame group data Z1 to the first view driving module 31 through the first output port 21; when the frame counter 24 identifies the second frame group data Z2, the timing controller 20 is configured to close the first output port 21 and open the second output port 22, and transmit the second frame group data Z2 to the second view driving module 32 through the second output port 22.

[0078] In this embodiment, data originally mixed in a single composite image signal source is precisely directed to the corresponding viewpoint driving module 30 by switching the output port through frame counter 24, thereby achieving time window isolation at the physical layer. When the first viewpoint data is transmitted, the second output port 22 is completely closed. This hard logical isolation ensures that a user from one viewpoint cannot see the content of another viewpoint user, avoiding data overlap between different viewpoints. Since the switching action of the first output port 21 and the second output port 22 is based on the internal unified frame counter 24, the starting point and duration of the signals received by the first viewpoint driving module 31 and the second viewpoint driving module 32 are precise and constant. This ensures that the charging curve of each frame pixel is highly aligned on the time axis, and the charging time will not vary due to random drift of the signal source, thus fundamentally ensuring the brightness uniformity of the dual-viewpoint display.

[0079] Considering that if the timing controller 20 simultaneously sends composite image signal sources to the first output port 21 and the second output port 22, and the driving module 30 identifies or extracts the data corresponding to the viewpoint, it would result in significant data waste and power consumption. This disclosure uses a frame counter 24 to identify the first frame group data Z1 and the second frame group data Z2, ensuring that data from the first viewpoint flows only to the first output port 21, and data from the second viewpoint flows only to the second output port 22. Only one output port is open at any given time, while the other is closed. This reduces the dynamic power consumption of the link from the non-working output port to the corresponding driving module 30, which helps alleviate the overheating problem of the display device.

[0080] Therefore, this disclosure constructs a real-time data sorting engine by directly applying the logical determination result of frame counter 24 to the hardware gating switch of the output port. This engine utilizes the uniqueness of frame sequence identification to achieve multi-view data stream transmission on the physical link. This design not only completely eliminates signal crosstalk between viewpoints through physical isolation but also locks the timing phase of pixel-driven operations using a deterministic logical triggering mechanism, ensuring charging consistency of dual-view pixels in alternating working states and significantly improving image quality stability in high-frequency heterogeneous display scenarios.

[0081] Figure 13 The diagram shown is another schematic representation of signal synthesis and decomposition in a display device provided in this embodiment of the present disclosure. Figure 14 The image shown is related to Figure 13 A diagram showing the correspondence between the vertical synchronization signal and image data from different viewpoints is provided. Figure 13 and Figure 14 In one optional embodiment of this disclosure, the composite image signal source includes multiple frames of image data, wherein the first frame to the Nth frame are first-view image data, which can correspond to the first frame group data Z1; the (N+1)th frame to the Mth frame are second-view data, which can correspond to the second frame group data Z2. N is the number of frames corresponding to the first-view image, and MN is the number of frames corresponding to the second-view image, wherein M and N are both positive integers, and M > N. Figure 13 The illustrated embodiment uses M=60 and N=120 as an example for explanation. In this case, the first 60 frames correspond to the first-view image data and the last 60 frames correspond to the second-view image data. However, this is not a limitation. In some other embodiments of this disclosure, M and N can be any other feasible values, such as M=60, N=150, etc., so that the first 60 frames correspond to the first-view image data and the last 90 frames correspond to the second-view image data, which can be applied to the scheme of multi-frequency display.

[0082] This embodiment differs from the frame-by-frame or short-frame-group alternation schemes in the previous embodiments. Its core lies in encapsulating and transmitting the data from the first and second perspectives as large-scale continuous frame clusters. N frames of the first perspective image are transmitted continuously from the first frame to the Nth frame, and MN frames of the second perspective image are transmitted continuously from the N+1th frame to the Mth frame. This method no longer frequently switches perspectives between frames; instead, it transmits all the data for one perspective within a specific period at once before switching to another perspective.

[0083] Considering that switching the port state (on / off / high impedance state) with each frame in high-frequency transmission would generate frequent power surges and transient current fluctuations, this embodiment reduces the switching frequency of the timing controller 20's output port by several times by continuously transmitting multiple frames. This significantly reduces electromagnetic interference and dynamic power consumption of the output stage circuit caused by frequent switching, extends the chip's physical lifespan, and makes the entire system more robust. Furthermore, when the timing controller 20 continuously receives multiple frames of data from the same viewpoint, it does not need to frequently change decompression parameters, minimizing the processing latency within the timing controller 20, thus saving internal logic resources and effectively improving data throughput.

[0084] Furthermore, during the continuous transmission of N frames, except for the first and last frames which involve switching, the intermediate frames are in a stable electrical state. Therefore, this method of encapsulating transmission with a large number of consecutive frame clusters provides the display panel 40 with an ultra-long period of stable driving window. Under this window, the voltage waveform output by the driving module 30 to the pixels is almost identical, thus ensuring a high degree of constant pixel charging over a long period and effectively eliminating the problem of brightness flicker in the display panel 40.

[0085] Therefore, this embodiment constructs a high-throughput driving architecture with low-frequency switching by limiting the alternating transmission of first-view and second-view image data in the form of long sequence frame groups. This architecture utilizes the temporal locality of data to significantly reduce the operating frequency of the timing controller 20's output port, reducing electromagnetic interference while providing a longer-term stable driving environment for the display panel 40. This design not only optimizes cache processing efficiency but also ensures the charging consistency of pixels at each viewpoint within consecutive frame cycles, greatly improving the smoothness of the heterogeneous dual-view display.

[0086] Optionally, N=MN, which is applicable when the display frequencies of the first and second perspectives are the same. Of course, in some other embodiments of this disclosure, N≠MN can also be set to be applicable when the display frequencies of the first and second perspectives are different.

[0087] Please combine Figure 8 , Figure 13 and Figure 14When the first-view image and the second-view image data are transmitted alternately in the form of long sequence frame groups, in an optional embodiment of this disclosure, when the frame counter 24 identifies the first frame to the Nth frame, the timing controller 20 is configured to open the first output port 21 and close the second output port 22, and transmit the first frame to the Nth frame to the first-view driving module 31 through the first output port 21; when the frame counter 24 identifies the N+1 frame to the Mth frame, the timing controller 20 is configured to close the first output port 21 and open the second output port 22, and transmit the N+1 frame to the Mth frame to the second-view driving module 32 through the second output port 22.

[0088] In this embodiment, the frame counter 24 can perform interval judgment, for example, the first frame to the Nth frame belongs to the first viewpoint image data, and the (N+1)th frame to the Mth frame belongs to the second viewpoint image data. During the entire time period of transmitting the first frame to the Nth frame, the first output port 21 remains open, and the second output port 22 remains closed. During the entire time period of transmitting the (N+1)th frame to the Mth frame, the states of the two ports are reversed once. Through this interval-based gating, large blocks of continuous frame data in the composite signal are directed in batches to the corresponding viewpoint driving module 30.

[0089] In high-speed display interfaces, the opening and closing of ports involves the establishment and release of internal voltage levels. Compared to frame-by-frame switching, this embodiment reduces the port switching frequency from "frame frequency" to "frame group frequency," that is, from switching per frame to switching across multiple frames. This greatly reduces transient current jitter generated during switching, making the power supply within the entire module more stable. In this mode, except for the frame at the moment of switching, data from other frames can be transmitted in a constant electrical environment. This helps ensure the regularity of the drive waveform output by the drive module 30 and avoids interference from coupling noise caused by frequent port operations. Moreover, it ensures that the pixel charging process of each frame almost perfectly replicates the previous frame, thereby completely eliminating minor fluctuations in display brightness and ensuring extremely high brightness and color uniformity of the image.

[0090] Please refer to Figure 4In one optional embodiment of this disclosure, in the display panel 40, first-viewpoint pixel units P1 and second-viewpoint pixel units P2 are alternately arranged along a first direction D1. For example, the first-viewpoint pixel units P1 and second-viewpoint pixel units P2 can be arranged in a specific direction according to a fixed periodicity. For instance, a group of first-viewpoint pixel units P1 and a group of second-viewpoint pixel units P2 are alternately arranged in the row direction, or a group of first-viewpoint pixel units P1 and two groups of second-viewpoint pixel units P2 are alternately arranged in the row direction. This alternating arrangement allows pixels at different positions to emit light directed in different directions. Through this arrangement, the first-viewpoint image data output by the timing controller 20 can precisely drive the first-viewpoint pixel unit P1, and the second-viewpoint image data can precisely drive the second-viewpoint pixel unit P2. Combined with the optical film layer on the display panel 40, a user with a first-viewpoint perspective can only see the first-viewpoint image, and a user with a second-viewpoint perspective can only see the second-viewpoint image, thereby achieving two different sets of images on the same display panel 40. Optionally, a first-view pixel unit P1 may include a column of red sub-pixels, a column of green sub-pixels, and a column of blue sub-pixels; similarly, a second-view pixel unit P2 may include a column of red sub-pixels, a column of green sub-pixels, and a column of blue sub-pixels.

[0091] In the display panel 40, when the first-view pixel unit P1 and the second-view pixel unit P2 are arranged alternately, high-frequency operating pixels are avoided from clustering in a certain area, resulting in a more uniform heat distribution in the display panel 40 and reducing the characteristic drift of the transistors inside the display panel 40 caused by severe local temperature rise. Furthermore, considering that if the first-view pixel unit P1 and the second-view pixel unit P2 are arranged haphazardly, interference can easily occur during light splitting, the regular alternating arrangement facilitates alignment with the light control components in the display panel 40, thereby significantly reducing the risk of light mixing between the first-view and second-view images and improving image clarity and edge smoothness.

[0092] Therefore, this disclosure constructs a physical array that highly matches the time-division driving logic of the timing controller 20 by limiting the alternating arrangement of first-viewpoint pixels and second-viewpoint pixels on the display panel 40. This geometric symmetry is not only a prerequisite for achieving spatial beam splitting, but more importantly, it ensures that the two viewpoint pixels have completely equal physical load and thermal field distribution on the driving link. This deep coupling of 'spatial alternation' and 'temporal switching' solves the common pain points of brightness inaccuracy and color deviation in multi-view displays from the bottom layer, significantly improving the visual quality of the vehicle dual-view system.

[0093] Figure 15 The diagram shown is a schematic diagram of a film layer of a display panel 40 provided in an embodiment of this disclosure. It should be noted that... Figure 15This illustration only shows a portion of the film layers in the display panel 40 and does not represent the actual number of film layers contained in the display panel 40. In an optional embodiment of this disclosure, the display panel 40 further includes a light control component 90 disposed on the light-emitting side of the first viewing angle pixel unit P1 and the second viewing angle pixel unit P2. The light control component 90 includes a light-shielding layer 92 and a microlens array 91. The light-shielding layer 92 has multiple light-transmitting openings, and the microlens array 91 is located in the light-transmitting openings. The light-shielding layer 92 and the microlens array 91 are configured to guide the light beam emitted from the first viewing angle pixel unit P1 to a first preset angle range and guide the light beam emitted from the second viewing angle pixel unit P2 to a second preset angle range, so that the first viewing angle pixel unit P1 and the second viewing angle pixel unit P2 form mutually independent visual display areas in space. It should be noted that this embodiment only uses the introduction of a sub-pixel P11 of the first viewing angle pixel unit P1 and a sub-pixel P21 of the second viewing angle pixel unit P2 at the light-transmitting opening position as an example for explanation, but it is not limited thereto.

[0094] In the display device provided in this embodiment, the light-transmitting openings on the light-shielding layer 92 limit the scattering direction of light, thus playing a preliminary role in light containment. The transparent array can deflect light beams from pixels at different locations using the principle of refraction. In dual-view displays, the biggest technical challenge is crosstalk, where the user in the first viewpoint can vaguely see the image of the user in the second viewpoint. This disclosure uses the physical containment of the light-shielding layer 92 and the precise deflection of the microlens array 91 as a double safeguard, strongly confining light within a specific angle. This creates spatially independent visual display areas for the first and second views. This physical-level separation ensures excellent privacy protection and image purity. The microlens array 91 in this disclosure can refract light that would otherwise be lost to non-target areas back to the target viewpoint, significantly improving light utilization. This means that power consumption can be lower at the same display brightness, meeting the energy-saving and emission-reduction requirements of systems such as automotive systems.

[0095] Therefore, this disclosure achieves precise angle mapping of pixel beams from different viewing angles by setting a light control component 90 integrating a light-shielding layer 92 and a microlens array 91 on the light-emitting side of the display panel 40. The limiting effect of the light-shielding layer 92 and the refractive guidance of the microlens work together to not only construct a highly isolated independent visual area in space, eliminating crosstalk between viewing angles, but also effectively improve the overall light utilization rate. This optical architecture is deeply matched with the time-division driving strategy of the front-end timing controller 20, jointly ensuring the brightness balance and visual quality of the dual-view display system from both optoelectronic ends.

[0096] Figure 16 The diagram shown illustrates one possible connection between the scan drive circuit 70 and the pixel unit in the display panel. Please refer to the diagram. Figure 16In one optional embodiment of this disclosure, in the display panel 40, the first viewing angle pixel unit P1 and the second viewing angle pixel unit P2 share a scan driving circuit 70; the scan driving circuit 70 includes a cascaded shift register VSR, and the first viewing angle pixel unit P1 and the second viewing angle pixel unit P2 connected to the same shift register VSR receive the same scan control signal.

[0097] In traditional solutions, achieving different frequencies or independent driving sometimes requires two separate sets of scan lines. This solution, however, returns to a simplified architecture, allowing the first-view and second-view pixels to share the same scan drive circuit 70. When a row of shift registers (VSRs) outputs an effective level, the gates of all first-view and second-view pixels in that row are simultaneously turned on. By sharing the scan drive circuit 70, the number of shift registers (VSRs) in the originally bulky scan drive circuit 70 is halved, which is beneficial for achieving an extremely narrow bezel design. Moreover, the simplified circuit structure reduces the production defect rate. Due to the reduced circuit size, the probability of failure also decreases, improving the electrical reliability of the display device, especially automotive displays, under long-term vibration and high / low temperature shocks. At the same time, since the first-view and second-view pixels receive the same scan pulse, their activation time windows physically overlap. Combined with the time-division multiplexing data output of the front-end timing controller 20, this architecture ensures that there is no difference in the width and phase of the drive pulse between the two view pixels, eliminating the physical cause of brightness deviation from its electrical source.

[0098] Therefore, this disclosure achieves a highly integrated scan drive architecture by limiting the first-view pixel unit P1 and the second-view pixel unit P2 to share the scan drive circuit 70. This architecture, while giving the display panel 40 the physical characteristic of a narrow bezel, utilizes the shared characteristic of the shift register VSR to ensure synchronization of the first-view and second-view pixels in the gate scan timing. This design not only reduces system power consumption and electromagnetic interference at the circuit level, but also perfectly coordinates the current splitting strategy of the front-end timing controller 20 by eliminating the phase difference between the two drive signals, providing an extremely stable electrical reference for dual-view display and ensuring a high degree of consistency in screen brightness.

[0099] Based on the same inventive concept, this disclosure also provides a driving method for a display device. Figure 17 The diagram shown is a flowchart of a driving method provided in an embodiment of this disclosure. Please refer to it. Figure 17 and Figure 4 The driving method includes: Step S1: The application processor 10 combines the first-view image data and the second-view image data into a composite image signal source and outputs it; that is, the application processor 10 encapsulates the two independent image streams in the time domain and converts them into a single high-frequency composite signal.

[0100] Step S2: Receive composite image signal source through a timing controller 20, split the composite image signal source into corresponding first-view image data and second-view image data and output them; that is, the timing controller 20 restores the mixed data packet into two physically independent branches.

[0101] Step S3: The first view driving module 31 receives the first view image data and transmits it to the first view pixel unit P1 of the display panel 40, and the second view driving module 32 receives the second view image data and transmits it to the second view pixel unit P2 of the display panel 40.

[0102] Step S4: The first-view pixel unit P1 in the display panel 40 displays the first-view image based on the first-view image data, and the second-view pixel unit P2 displays the second-view image based on the second-view image data.

[0103] Traditional dual-view solutions often require the application processor 10 to output two independent signals, or to use multiple timing controllers 20 cascaded, resulting in complex hardware links and difficulties in synchronization. The method provided in this disclosure embodiment can complete the driving using only a composite image signal source and a timing controller 20. This flattened architecture greatly reduces the routing complexity on the motherboard and lowers the bill of materials cost.

[0104] Because the application processor 10 combines the first-view image data and the second-view image into a single composite image signal source, the first-view image and the second-view image share a vertical synchronization signal and the same master clock. When the timing controller 20 splits the data, due to the consistent reference, the signals output to the drive modules 30 of the two viewpoints have natural symmetry on the time axis. This ensures that the charging pulse width of all pixels on the display panel 40 is completely consistent, thereby eliminating the brightness difference between the left and right viewpoints and ensuring high uniformity of the image.

[0105] By leveraging flexible synthesis at the application processor 10-end, this method can allocate different numbers of frames to different viewpoints through software-defined logic without altering the physical hardware links. The system can achieve personalized displays for the driver and co-driver without re-locking the frequency, and the switching process is smooth and flicker-free. Due to the use of unified composite signal transmission, the system can perform impedance matching and electromagnetic interference protection more centrally.

[0106] The method disclosed herein establishes a unified time coordinate system for the entire display system using a single composite image signal source, eliminating phase drift between multiple signal sources at the source. Combined with the high-speed splitting capability of the timing controller 20, it not only simplifies the circuit topology but also perfectly solves the long-standing problems of uneven charging and brightness deviation in multi-view displays by ensuring the absolute consistency of the driving pulses, achieving a balance between high performance and low cost.

[0107] Please continue to refer to this. Figure 4 and Figure 17 In one optional embodiment of this disclosure, step S2 above, splitting the composite image signal source into corresponding first-view image data and second-view image data and outputting them, includes: the timing controller 20 identifies the frame order of the received composite image signal source, generates a view switching control signal based on the trigger edge of the vertical synchronization signal, opens the first output port 21 or the second output port 22, and transmits the first-view image data to the first-view driving module 31 when the first output port 21 is opened, and transmits the second-view image data to the second-view driving module 32 when the second output port 22 is opened.

[0108] This disclosure utilizes the transition edge of the vertical sync signal as a precise "switching command" to ensure that the switching action occurs at the instant of alternation between two image frames. The viewpoint switching control signal directly drives the "on" and "off" of the first output port 21 and the second output port 22. Considering that if the signal switching timing is incorrect (e.g., switching midway through the transmission of an image frame), it would cause the display to show the first viewpoint at the top and the second viewpoint at the bottom, resulting in severe screen tearing, controlling the switching via the trigger edge of the vertical sync signal ensures that the opening and closing actions of the ports are strictly locked within the blanking period between frames. This guarantees the integrity of each image frame and completely eliminates dynamic ghosting and screen tearing. Furthermore, since the switching signal is generated based on the same vertical sync signal, the output windows of the first and second viewpoints are absolutely locked on the time axis. This allows the "effective charging time" of the first and second viewpoint pixels to achieve nanosecond-level alignment accuracy, fundamentally eliminating the brightness difference between the left and right viewpoints and achieving perfect brightness balance.

[0109] If both output ports are always on, even without transmitting valid data, sustaining power consumption will still occur. This solution employs a "time-division multiplexing" strategy. When transmitting the first viewpoint, the second port is not only off but also typically in a high-impedance or silent state. This "on-demand" mode significantly reduces the signal line switching frequency, decreases system power consumption, and effectively suppresses electromagnetic radiation generated by high-frequency switching.

[0110] In complex systems, switching perspectives via software commands can result in significant latency. This entire process is implemented at the hardware logic layer of the timing controller 20. Because it doesn't require a software layer, signal splitting is virtually latency-free. This is crucial for applications requiring high real-time performance (such as in-car navigation and passenger-side games), ensuring smooth visuals.

[0111] Therefore, this embodiment uses the vertical synchronization signal as an absolute time anchor point to ensure the physical determinism of the first-view image data and the second-view image data when switching at the output port. This design not only isolates signal interference between viewpoints in the time domain, but also ensures a high degree of constancy in the charging amount of back-end pixels by precisely controlling the output width of each frame. It is a key execution path to achieve consistent brightness and image purity in dual-view displays.

[0112] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0113] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display device, characterized in that, include: The application processor is configured to synthesize first-view image data and second-view image data into a composite image signal source and output it. A timing controller, electrically connected to the application processor, is configured to receive the composite image signal source output by the application processor, split the composite image signal source into corresponding first-view image data and second-view image data, and output them. The driving module includes a first view driving module and a second view driving module. The first view driving module is used to receive and output first view image data, and the second view driving module is used to receive and output second view image data. The display panel includes a first-view pixel unit and a second-view pixel unit. The first-view pixel unit is used to receive the first-view image data output by the first-view driving module and display the first-view image. The second-view pixel unit is used to receive the second-view image data output by the second-view driving module and display the second-view image.

2. The display device according to claim 1, characterized in that, The application processor is configured to synthesize the composite image signal source using frequency domain synthesis; the timing controller is configured to extract the first viewpoint image data and the second viewpoint image data using frequency domain splitting.

3. The display device according to claim 1, characterized in that, The timing controller supports a maximum operating frequency greater than or equal to the sum of the display frequency of the first viewpoint image and the display frequency of the second viewpoint image.

4. The display device according to claim 1, characterized in that, The frame rate of the composite image signal source is greater than or equal to the sum of the display frequency of the first viewpoint image and the display frequency of the second viewpoint image.

5. The display device according to claim 1, characterized in that, The timing controller is electrically connected to the first view driving module through a first output port and to the second view driving module through a second output port. The data transmission bandwidth of the first output port is the same as that of the second output port.

6. The display device according to claim 5, characterized in that, The display frequency of the first-view image on the display panel is equal to the display frequency of the second-view image, and the data transmission bandwidth of the first output port and the second output port is greater than or equal to the transmission bandwidth required for the first-view image or the second-view image.

7. The display device according to claim 5, characterized in that, The display frequency of the first-view image on the display panel is not equal to the display frequency of the second-view image. The data transmission bandwidth of the first output port and the second output port is greater than or equal to the transmission bandwidth required by the higher display frequency of the first-view image and the second-view image.

8. The display device according to claim 1, characterized in that, The timing controller includes a buffer unit configured to buffer image data in the composite image signal source and convert the composite image signal source with a receiving rate of a first bit rate into image data with a transmitting rate of a second bit rate for output, wherein the first bit rate is proportional to the sum of the display frames of the first viewpoint image and the second viewpoint image.

9. The display device according to claim 1, characterized in that, The timing controller includes a frame counter configured to identify the frame order of the received composite image signal source.

10. The display device according to claim 9, characterized in that, The timing controller is configured to generate a viewpoint switching control signal based on the trigger edge of the vertical synchronization signal, and the viewpoint switching control signal is configured to control the opening or closing of the first output port and the second output port of the timing controller.

11. The display device according to claim 10, characterized in that, When the first output port or the second output port is closed, the closed output port remains in a high-impedance state.

12. The display device according to claim 9, characterized in that, The composite image signal source includes multiple frames of image data, which include alternating transmission of first frame group data and second frame group data. The first frame group data is first-view image data, and the second frame group data is second-view image data. Each first frame group data includes at least one frame of image data, and each second frame group data includes at least one frame of image data.

13. The display device according to claim 12, characterized in that, The number of frames of image data included in a single first frame group is the same as the number of frames of image data included in a single second frame group.

14. The display device according to claim 12, characterized in that, A single first frame group data includes m frames of image data, and a single second frame group data includes n frames of image data, where m ≥ 1, n ≥ 1, and m ≠ n.

15. The display device according to claim 12, characterized in that, When the frame counter identifies the first frame group data, the timing controller is configured to open the first output port and close the second output port, and transmit the first frame group data to the first view driving module through the first output port. When the frame counter identifies the second frame group data, the timing controller is configured to close the first output port and open the second output port, and transmit the second frame group data to the second view drive module through the second output port.

16. The display device according to claim 9, characterized in that, The composite image signal source includes multiple frames of image data, wherein the first frame to the Nth frame are the first viewpoint image data, the N+1th frame to the Mth frame are the second viewpoint data, N is the number of frames corresponding to the first viewpoint image, and MN is the number of frames corresponding to the second viewpoint image, wherein M and N are both positive integers, and M > N.

17. The display device according to claim 16, characterized in that, When the frame counter identifies the first frame to the Nth frame, the timing controller is configured to open the first output port and close the second output port, and transmit the first frame to the Nth frame to the first viewpoint driving module through the first output port; When the frame counter identifies frames N+1 to M, the timing controller is configured to close the first output port and open the second output port, and transmit frames N+1 to M to the second viewpoint driving module through the second output port.

18. The display device according to claim 1, characterized in that, In the display panel, first-viewpoint pixel units and second-viewpoint pixel units are arranged alternately along a first direction.

19. The display device according to claim 18, characterized in that, The display panel further includes a light control component disposed on the light-emitting side of the first viewing angle pixel unit and the second viewing angle pixel unit, the light control component including a light-shielding layer and a microlens array; The light-shielding layer is provided with multiple light-transmitting openings. The light-shielding layer and the microlens array layer are configured to guide the light beam emitted by the first viewing angle pixel unit to a first preset angle range and guide the light beam emitted by the second viewing angle pixel unit to a second preset angle range, so that the first viewing angle pixel unit and the second viewing angle pixel unit form mutually independent visual display areas in space.

20. The display device according to claim 1, characterized in that, In the display panel, the first viewing angle pixel unit and the second viewing angle pixel unit share a scanning drive circuit; the scanning drive circuit includes cascaded shift registers, and the first viewing angle pixel unit and the second viewing angle pixel unit connected to the same shift register receive the same scanning control signal.

21. A driving method for a display device, characterized in that, include: The application processor combines first-view image data and second-view image data into a composite image signal source and outputs it. The composite image signal source is received by a timing controller, and the composite image signal source is split into corresponding first-view image data and second-view image data and output. The first-view driving module receives first-view image data and transmits it to the first-view pixel unit of the display panel; the second-view driving module receives second-view image data and transmits it to the second-view pixel unit of the display panel. The first-view pixel unit in the display panel displays a first-view image based on the first-view image data, and the second-view pixel unit displays a second-view image based on the second-view image data.

22. The driving method according to claim 21, characterized in that, The step of splitting the composite image signal source into corresponding first-view image data and second-view image data and outputting them includes: The timing controller identifies the frame order of the received composite image signal source and generates a viewpoint switching control signal based on the trigger edge of the vertical synchronization signal. It then opens either the first output port or the second output port. When the first output port is open, the first viewpoint image data is transmitted to the first viewpoint driving module, and when the second output port is open, the second viewpoint image data is transmitted to the second viewpoint driving module.

Images