Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises: in response to a target operation event, determining a target management area in which a target word line is located in a plurality of management areas, the plurality of management areas being vertically distributed in a memory module according to respective electrical characteristics, the plurality of management areas including a bonding interface area, a bonding transition area, an etching variation area and a central stable area, the target operation events correspond to different types of process defects respectively, and the target operation events indicate to execute target operation on the target word line; determining a target management table corresponding to the target management area from the plurality of management tables; adjusting the reference electrical parameters according to the target management table; and executing a target operation on the target word line according to the adjusted reference electrical parameter. Therefore, the operation performance and / or the operation stability of the storage device can be improved.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202511461658.7 (filed on October 14, 2025, entitled "Memory Management Method and Memory Device"). Technical Field

[0002] This invention relates to the field of memory technology, and in particular to a memory management method and a storage device. Background Technology

[0003] NAND flash memory, as the current mainstream non-volatile storage medium, is widely used in solid-state drives (SSDs), embedded multimedia controllers (eMMCs), universal flash storage (UFS), USB flash drives, and various portable multimedia devices due to its advantages such as high read and write speeds, good shock resistance, and low power consumption.

[0004] In recent years, with the continuous evolution of semiconductor manufacturing processes, especially the rapid development of 3D NAND technology, the storage density of NAND Flash has been continuously improved, and the number of layers has rapidly expanded from the early 32 layers and 64 layers to the current mainstream 128 layers and above.

[0005] In high-layer-count 3D NAND architectures, due to the complexity of the device structure and process limitations, the coupling effect between word lines (WLs) is significantly enhanced, especially in the physical edge regions of the array (i.e., the top and bottom word lines). Word line interference exhibits a non-linear growth trend. This interference effect directly affects the charge stability of memory cells, leading to a significant increase in the raw bit error rate (RBER). Summary of the Invention

[0006] The present invention provides a memory management method and a memory device, which can improve the above-mentioned problems and enhance the operating performance and / or operating stability of the memory device.

[0007] Embodiments of the present invention provide a memory management method for a storage device, the storage device including a memory module, the memory module including a plurality of word lines, and the memory management method comprising: detecting a target operation event, wherein the target operation event indicates that a target operation is performed on a target word line among the plurality of word lines; in response to the target operation event, determining that the target word line is located in a target management area among a plurality of management areas, wherein the plurality of management areas are vertically distributed in the memory module according to their respective electrical characteristics; determining a target management table corresponding to the target management area from a plurality of management tables; adjusting a reference electrical parameter according to the target management table; and performing the target operation on the target word line according to the adjusted reference electrical parameter.

[0008] An embodiment of the present invention further provides a storage device including a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes multiple word lines, and the memory controller is used to: detect a target operation event, wherein the target operation event indicates that a target operation is performed on a target word line among the multiple word lines; in response to the target operation event, determine that the target word line is located in a target management area among multiple management areas, wherein the multiple management areas are vertically distributed in the memory module according to their respective electrical characteristics; determine a target management table corresponding to the target management area from multiple management tables; adjust a reference electrical parameter according to the target management table; and perform the target operation on the target word line according to the adjusted reference electrical parameter.

[0009] Based on the above, upon detecting a target operation event instructing the execution of a target operation on a target word line, in response to this target operation event, the target management area where the target word line is located among multiple management areas can be determined, and a target management table corresponding to the target management area can be determined. Specifically, the multiple management areas are vertically distributed within the memory module according to their respective electrical characteristics. Subsequently, based on the target management table, reference electrical parameters can be adjusted, and the adjusted reference electrical parameters can be used to perform the target operation on the target word line. This improves the operational performance and / or operational stability of the memory device. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0012] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0014] Figures 5 to 8 This is a schematic diagram illustrating the division of management areas according to an embodiment of the present invention;

[0015] Figure 9 This is a schematic diagram illustrating the division of a management area into sub-management areas according to an embodiment of the present invention;

[0016] Figure 10 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0018] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0019] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0020] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0021] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include flash memory controller.

[0022] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0023] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0026] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuitry), which is not limited by the present invention.

[0027] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(B). Each physical unit includes multiple storage units for non-volatile storage of data.

[0028] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, the entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0029] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0030] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0031] In one embodiment, an entity erasure unit may include multiple entity programmable units. In another embodiment, an entity erasure unit may be considered as an entity block.

[0032] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0033] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)~301(A) and 301(A+1)~301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)~301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0034] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0035] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0036] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1) to 302(C) to map physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0037] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0038] In one embodiment, the memory control circuit 23 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logic-to-entity mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logic-to-entity mapping table).

[0039] In one embodiment, the memory module 122 includes a three-dimensional (3D) stacked memory module. This three-dimensional stacked memory module may include 128, 256, 512, or other numbers of word line layers stacked vertically on top of each other. Each word line layer includes multiple word lines. Each word line may include multiple memory cells. Furthermore, the multiple memory cells on each word line may form one or more physical programmable units.

[0040] In one embodiment, multiple word line layers in memory module 122 are stacked vertically together using a bonding process. For example, this bonding process refers to stacking two or more memory chips vertically in semiconductor manufacturing to form a three-dimensional stacked memory module. Therefore, this bonding process increases the number of stacked word line layers, thereby increasing the amount of data stored per unit area (i.e., data storage density) of memory module 122.

[0041] It is important to note that while this bonding process increases data storage density with higher stacking layers, it also introduces serious side effects. One significant side effect is increased interlayer interference, which causes discontinuities in the electrical characteristics between layers at the bonding interfaces and can lead to new interface trap states. If these defects are not specifically addressed and improved, the long-term performance of the entire 3D stacked memory module will be lower than expected.

[0042] In this application, 'electrical characteristics' refers broadly to parameters and phenomena that affect the electrical performance of memory cells during operation. These mainly include, but are not limited to, the threshold voltage (Vt) of the memory cell and its distribution width, the intensity of random telegraph noise (RTN), the magnitude of punch-through leakage current, and the decay rate of charge retention. Differences in these characteristics are primarily caused by the non-uniformity of the manufacturing process in three-dimensional space.

[0043] Therefore, the memory management method and memory device proposed in this invention can, based on a specially configured management table, perform vertical grouping management of word lines in the memory module to meet the needs of electrical defect compensation for word lines with different electrical characteristics (e.g., different process defects). This effectively improves the overall operational performance and / or operational stability of the memory device. Each management table includes, but is not limited to, the following fields: management area identifier, voltage compensation value, voltage step accuracy, temperature compensation coefficient, loss adjustment parameters, etc.

[0044] Figure 4 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figure 4 In one embodiment, it is assumed that the memory module 122 includes a three-dimensional stacked structure 40. In the three-dimensional stacked structure 40, there exist multiple word line layers stacked on top of each other in the vertical direction (i.e., the Z-axis direction), and each word line layer includes multiple word lines. For example, the total number of these stacked word line layers in the vertical direction (i.e., the Z-axis direction) may be 128, 256, 512, or other numbers, depending on practical requirements.

[0045] In one embodiment, the memory control circuit 23 may divide the three-dimensional stacked structure 40 into multiple management areas 41(1) to 41(D). Each management area 41(1) to 41(D) covers a portion of the word lines in the three-dimensional stacked structure 40. In particular, the management areas 41(1) to 41(D) may be vertically distributed in the memory module 122 along the vertical direction (i.e., the Z-axis direction) according to their respective electrical characteristics. For example, in the vertical direction (i.e., the Z-axis direction), one word line in the three-dimensional stacked structure 40 may be located in management area 41(i) (also called the first management area), while another word line in the three-dimensional stacked structure 40 may be located in management area 41(j) (also called the second management area). i and j are integers between 1 and D, and i is different from j.

[0046] In three-dimensional stacked memory, due to the non-uniformity of bonding and etching processes, word lines in different regions exhibit significant differences in electrical characteristics. If a uniform management strategy is adopted, it will lead to operating voltage mismatch, resulting in increased read / write error rates and decreased data retention. To address this issue, this invention divides the memory module into a bonding interface region, a bonding transition region, an etching variation region, and a central stable region, each region corresponding to different process defect characteristics. This division allows for differentiated voltage management and compensation strategies targeting the electrical characteristic defects in different regions, thereby significantly improving the operational stability and data reliability of the memory.

[0047] In one embodiment, after dividing the management areas 41(1) to 41(D) along the vertical direction (i.e., the Z-axis direction), the memory control circuit 23 can configure multiple management tables 401(1) to 401(D) according to the electrical characteristics of each management area 41(1) to 41(D). Simultaneously, the memory control circuit 23 can associate management tables 401(1) to 401(D) with management areas 41(1) to 41(D) respectively. For example, the memory control circuit 23 can associate management tables 401(1) to 401(D) with management areas 41(1) to 41(D) one-to-one. Management table 401(i) (also called the first management table) can be matched with the electrical characteristics (also called the first electrical characteristics) of management area 41(i). Management table 401(j) (also called the second management table) can be matched with the electrical characteristics (also called the second electrical characteristics) of management area 41(j).

[0048] After configuring management tables 401(1) to 401(D), the memory control circuit 23 can manage management areas 41(1) to 41(D) respectively according to management tables 401(1) to 401(D). For example, the memory control circuit 23 can manage the word lines in management area 41(i) (including operation) according to management table 401(i). Alternatively, the memory control circuit 23 can manage the word lines in management area 41(j) (including operation) according to management table 401(j).

[0049] In one embodiment, the management table (e.g., 401(i)) can be a data structure whose fields include, but are not limited to: management area identifier, reference reading voltage, voltage offset, voltage step accuracy adjustment coefficient, temperature compensation coefficient, loss and wear level compensation mapping table, etc.

[0050] After the memory control circuit 23 finds the corresponding management table based on the target management area, it can calculate the final applied operating voltage according to the following formula (or logic):

[0051] Final operating voltage = Reference operating voltage + Voltage offset + Temperature compensation value + Wear compensation value;

[0052] Among them, the reference operating voltage is a standard value for the entire memory module; the voltage offset is a fixed compensation value preset by the management table for the characteristics of the core management area; the temperature compensation value and wear compensation value are dynamic compensation values ​​obtained by mapping from the management table based on the real-time detected temperature information and wear level information.

[0053] In this way, the management table not only provides static compensation parameters, but also dynamic compensation rules, making the voltage adjustment strategy more refined and adaptive.

[0054] In one embodiment, by analyzing the electrical characteristics of each word line layer in the three-dimensional stacked structure 40 and referring to the bonding process and plasma etching process acting on the memory module 122, the memory control circuit 23 can divide the three-dimensional stacked structure 40 into management regions 41(1) to 41(D). For example, management regions 41(1) to 41(D) may include a bonding interface region (BIR), a deck bonding transition region (DBTR), a physical deck edge region (PDER), and a deck center region (DCR). That is, each management region in management regions 41(1) to 41(D) may be one of the bonding interface region (BIR), the bonding transition region (DBTR), the physical deck edge region (PDER), and the deck center region (DCR). It should be noted that, depending on the different process technologies used, at least one of the types of management areas 41(1) to 41(D) may be adjusted according to practical needs, and is not limited to these types.

[0055] In one embodiment, in the three-dimensional stacked structure 40, the management areas 41(1) to 41(D) may have the following characteristics:

[0056] (1) Word lines located in the bonding interface region (BIR) have more significant interface bonding process defects compared to other word lines.

[0057] (2) Word lines located in the etch variation zone (PDER) have more significant plasma etching process defects compared to other word lines.

[0058] (3) Word lines located in the central stable region (DCR) have the most stable electrical characteristics compared to other word lines.

[0059] (4) The electrical characteristics of word lines located in the bonding transition region (DBTR) change gradually according to the word line position.

[0060] Due to the aforementioned characteristics (1), the electrical characteristics of word lines in the bonding interface region (BIR) are extremely unstable due to physical discontinuities and interface traps generated during manufacturing, making it the largest source of interference in the entire three-dimensional stacked structure 40. The programming and reading behavior of word lines located in this region is highly susceptible to the influence of surrounding word lines, resulting in a significant increase in the raw bit error rate (RBER). Therefore, during operation, word lines located in the bonding interface region (BIR) require the most aggressive voltage compensation and / or optimization strategies.

[0061] Regarding the aforementioned characteristic (2), word lines located in the etch variation region (PDER) are often situated at the top and bottom of each stack. Due to the non-uniformity of plasma etching at the solid edges, the physical structure of these word lines often exhibits slight variations. Compared to the bonding interface region (BIR), although the interference level of word lines located in the etch variation region (PDER) is relatively minor, their unstable electrical characteristics still affect the charge retention capability and data integrity of the word lines. Therefore, during operation, word lines located in the etch variation region (PDER) still require appropriate compensation for the deviated electrical characteristics through methods such as adjusting the read or program voltage.

[0062] Regarding the aforementioned characteristic (3), word lines located in the central stable region (DCR) are relatively far from the chip edge and bonding interface, and their location is often at or near the center of the three-dimensional stacked structure 40. Therefore, word lines located in the central stable region (DCR) have the most uniform and stable physical and electrical characteristics and are least affected by interference. In one embodiment, the overall management strategy for the three-dimensional stacked structure 40 mainly involves biasing or differentiating the management strategy (e.g., standard voltage value) relative to the central stable region (DCR).

[0063] Regarding the aforementioned characteristic (4), word lines located in the Bond Transition Region (DBTR) are generally situated between the Bond Interface Region (BIR) and the Central Stability Region (DCR). Therefore, the electrical characteristics of word lines located in the DBTR generally exhibit a gradual change depending on their word line position. For example, within the DBTR, word lines closer to the Bond Interface Region (BIR) have worse electrical characteristics and require greater voltage compensation. Conversely, word lines closer to the Central Stability Region (DCR) (i.e., farther from the Bond Interface Region (BIR)) have more stable electrical characteristics and require less voltage compensation. However, the above characteristics are only an overview; one or more of these characteristics may vary in different applications.

[0064] The following Figures 5 to 8 In the embodiments, various possible management area partitioning methods are shown for memory modules 122 manufactured using different types, models and / or semiconductor processes.

[0065] Figure 5 This is a schematic diagram illustrating the division of management areas according to an embodiment of the present invention. Please refer to... Figure 5 In one embodiment, it is assumed that the memory module 122 includes a three-dimensional stacked structure 50. In the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 50, the bonding interface region (BIR) 501 is located at the stack center of the three-dimensional stacked structure 50, while configuration combinations 51 and 52 are located above and below the bonding interface region (BIR) 501, respectively.

[0066] Configuration 51 includes a Bond Transition Region (DBTR) 511, a Central Stabilization Region (DCR) 512, and an Etching Variation Region (PDER) 513. Configuration 52 includes a Bond Transition Region (DBTR) 521, a Central Stabilization Region (DCR) 522, and an Etching Variation Region (PDER) 523. Furthermore, the Etching Variation Region (PDER) 513 may be located on or connected to the top of the three-dimensional stacked structure 50, while the Etching Variation Region (PDER) 523 may be located on or connected to the bottom of the three-dimensional stacked structure 50.

[0067] Taking a 138-layer vertical stacked structure as an example, in the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 50, the etch variation region (PDER) 523 may contain word line layers 3-7; the central stabilization region (DCR) 522 may contain word line layers 20-59; the bonding transition region (DBTR) 521 may contain word line layers 60-63; the bonding interface region (BIR) 501 may contain word line layers 64-67 and 70-73; the bonding transition region (DBTR) 511 may contain word line layers 74-77; the central stabilization region (DCR) 512 may contain word line layers 80-133; and the etch variation region (PDER) 513 may contain word line layers 134-137. It should be noted that the actual configuration of each management region in the three-dimensional stacked structure 50 and / or the word line layers it covers can also be adjusted according to practical needs.

[0068] In multi-layer stacked structures, the distribution of different process defect regions varies depending on the manufacturing process. If this method cannot flexibly adapt to various stacking configurations, its applicability will be limited. Therefore, this invention supports various vertical distribution configurations of the management areas, such as combining the bonding transition region, central stabilization region, and etch variation region above, below, or in other relative positions on the bonding interface region. This flexible configuration allows the invention to be applied to three-dimensional stacked memories with different numbers of layers and different process nodes, enhancing the method's versatility and practicality.

[0069] Figure 6 This is a schematic diagram illustrating the division of management areas according to an embodiment of the present invention. Please refer to... Figure 6 In one embodiment, it is assumed that the memory module 122 includes a three-dimensional stacked structure 60. In the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 60, a bonding interface region (BIR) 601 is located on or connected to the top of the three-dimensional stacked structure 60, and a configuration assembly 61 is located below the bonding interface region (BIR) 601.

[0070] Configuration 61 includes a Bond Transition Region (DBTR) 611, a Central Stabilization Region (DCR) 612, and an Etching Variation Region (PDER) 613. Furthermore, the Etching Variation Region (PDER) 613 may be located at or connected to the bottom of the three-dimensional stacked structure 60.

[0071] Taking a 147-layer vertical stacked structure as an example, in the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 60, the etch variation region (PDER) 613 may contain word line layers 0-2; the central stabilization region (DCR) 612 may contain word line layers 3-129; the bonding transition region (DBTR) 611 may contain word line layers 130-139; and the bonding interface region (BIR) 601 may contain word line layers 140-146. It should be noted that the actual configuration of each management region in the three-dimensional stacked structure 60 and / or the word line layers it covers can be adjusted according to practical needs.

[0072] Figure 7 This is a schematic diagram illustrating the division of management areas according to an embodiment of the present invention. Please refer to... Figure 7 In one embodiment, it is assumed that the memory module 122 includes a three-dimensional stacked structure 70. In the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 70, the central stabilization region (DCR) 701 is located at the stack center of the three-dimensional stacked structure 70, while configuration combinations 71 and 72 are located above and below the central stabilization region (DCR) 701, respectively.

[0073] Configuration 71 includes an etch variation region (PDER) 711, a bonding transition region (DBTR) 712, and a bonding interface region (BIR) 713. Configuration 72 includes an etch variation region (PDER) 721, a bonding transition region (DBTR) 722, and a bonding interface region (BIR) 723. Furthermore, the bonding interface region (BIR) 713 may be located on or connected to the top of the three-dimensional stacked structure 70, while the bonding interface region (BIR) 723 may be located on or connected to the bottom of the three-dimensional stacked structure 70.

[0074] Taking a 184-layer vertical stacked structure as an example, in the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 70, the bonding interface region (BIR) 723 may contain word line layers 0-3; the bonding transition region (DBTR) 722 may contain word line layers 4-10; the etch variation region (PDER) 721 may contain word line layers 11-15; the central stabilization region (DCR) 701 may contain word line layers 16-167; the etch variation region (PDER) 711 may contain word line layers 168-172; the bonding transition region (DBTR) 712 may contain word line layers 173-179; and the bonding interface region (BIR) 713 may contain word line layers 180-183. It should be noted that the actual configuration of each management region in the three-dimensional stacked structure 70 and / or the word line layers it covers can also be adjusted according to practical needs.

[0075] Figure 8 This is a schematic diagram illustrating the division of management areas according to an embodiment of the present invention. Please refer to... Figure 8In one embodiment, it is assumed that the memory module 122 includes a three-dimensional stacked structure 80. In the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 80, between any two bonding interface regions (BIRs), there exists a configuration combination including a central stabilization region (DCR), an etch variation region (PDER), and a bonding transition region (DBTR).

[0076] Specifically, in the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 80 (or memory module 122), from top to bottom, the components are, in sequence, a bonding interface region (BIR) 801, a configuration combination 81, a bonding interface region (BIR) 802, a configuration combination 82, a bonding interface region (BIR) 803, a configuration combination 83, and a bonding interface region (BIR) 804.

[0077] Configuration combination 81 includes a central stable region (DCR) 811, an etch variation region (PDER) 812, and a bonding transition region (DBTR) 813. Configuration combination 82 includes a central stable region (DCR) 821, an etch variation region (PDER) 822, and a bonding transition region (DBTR) 823. Configuration combination 83 includes a central stable region (DCR) 831, an etch variation region (PDER) 832, and a bonding transition region (DBTR) 833. Furthermore, a bonding interface region (BIR) 801 may be located at or connected to the top of the three-dimensional stacked structure 80, while a bonding interface region (BIR) 804 may be located at or connected to the bottom of the three-dimensional stacked structure 80. It should be noted that the actual configuration of each management region in the three-dimensional stacked structure 80 and / or the word line layers it covers can be adjusted according to practical needs.

[0078] Please return Figure 4 In one embodiment, the memory control circuit 23 may perform cross-word-line noise detection on at least a portion of the word lines in the three-dimensional stacked structure 40 to determine and / or adjust the division range of at least one of the management regions 41(1) to 41(D). For example, this noise detection may include random telegraph noise detection or other types of noise detection to meet one or more types of electrical defect characterization of the management regions.

[0079] In one embodiment, electrical defects located in the bonding interface region (BIR) are primarily affected by random telegraph noise. Random telegraph noise is caused by one or a few interface traps and is characterized by random voltage jumps between two or more discrete energy levels.

[0080] In one embodiment, the division of multiple management zones is based on the electrical characteristic detection results of multiple word lines. The electrical characteristic detection includes random telegraph noise detection and / or critical voltage distribution detection.

[0081] In one embodiment, the memory control circuit 23 can detect random telegraph noise in the three-dimensional stacked structure 40 and accurately locate the word line layer range affected by the bonding process based on the detection results. Then, the memory control circuit 23 can identify the word lines located within this word line layer range as belonging to the bonding interface region (BIR). In one embodiment, after initially determining that some word lines (or word line layers) are located in the bonding interface region (BIR), the memory control circuit 23 can further determine or fine-tune the boundary of this bonding interface region (BIR) through the aforementioned random telegraph noise detection method.

[0082] In one embodiment, the memory control circuit 23 can obtain the critical voltage distribution of at least a portion of the word lines in the three-dimensional stacked structure 40. Based on this critical voltage distribution, the memory control circuit 23 can roughly estimate whether the critical voltage distribution of the partial word lines exhibits electrical defect characteristics of a specific type of management region. For example, if the critical voltage distribution of certain word lines is concentrated and narrow (i.e., the critical voltage distribution of these word lines meets a first distribution condition), the memory control circuit 23 can label these word lines (or the word line layer containing these word lines) as belonging to a central stable region (DCR). For example, the first distribution condition may include the standard deviation of the critical voltage distribution of the word lines being less than a preset value (also referred to as a first threshold, such as 15% or other ratio). Alternatively, if the critical voltage distribution of certain word lines is abnormally wide due to etch variations (i.e., the critical voltage distribution of these word lines meets a second distribution condition), the memory control circuit 23 can label these word lines (or the word line layer containing these word lines) as belonging to an etch variation region (PDER) or a bonding interface region (BIR). For example, the second distribution condition may include a standard deviation of the critical voltage distribution of the word line being greater than a preset value (also known as a second threshold, such as 15% or other ratios). In addition, the aforementioned distribution conditions of various critical voltages may be added or adjusted according to practical needs to meet the grouping requirements of management areas 41(1) to 41(D).

[0083] In one embodiment, after performing preliminary grouping and calibration of management areas 41(1) to 41(D), the memory control circuit 23 can also determine whether the grouping of these word lines is correct or whether the grouping of some word lines can be adjusted based on whether the critical voltage distribution of word lines located at the boundary positions of at least some management areas meets specific distribution conditions. For example, after performing preliminary grouping and calibration of management areas 41(1) to 41(D), if it is initially determined that a certain word line located at the boundary position of the etch variation region (PDER) belongs to the etch variation region (PDER), but the critical voltage distribution of this word line meets the aforementioned first distribution condition (e.g., the critical voltage distribution of this word line is concentrated and narrow), then the memory control circuit 23 can recalibrate this word line to belong to the central stable region (DCR). Alternatively, after preliminary grouping and calibration of management areas 41(1) to 41(D), if it is initially determined that a word line located at the boundary of the central stable region (DCR) belongs to the central stable region (DCR), but the critical voltage distribution of this word line meets the aforementioned second distribution condition (e.g., the critical voltage distribution of this word line is abnormally wide), then the memory control circuit 23 can recalibrate this word line to belong to the etch variation region (PDER). In one embodiment, the memory control circuit 23 can also detect and / or fine-tune the word line calibration and / or grouping of management areas 41(1) to 41(D) in other ways, which will not be described in detail here.

[0084] In one embodiment, management areas 41(1) to 41(D) may further include a virtual word line area. Word lines located in the virtual word line area are not used to store user data. The primary function of the virtual word line area and the word lines therein is to assist in operating surrounding or adjacent word lines. For example, by specifically controlling the voltage of the word lines located in the virtual word line area, operational stability when operating on surrounding or adjacent word lines (e.g., reading data, writing data, or erasing data) can be improved. In one embodiment, the virtual word line area can also be used to isolate word lines in a stacked structure that are too close together and prone to mutual interference.

[0085] In one embodiment, when a read operation is required on a word line in the bonding interface region (BIR) adjacent to the virtual word line region, the memory control circuit 23 first determines the required read voltage (e.g., 4.5V) according to the management table of the bonding interface region. Subsequently, the controller sets a voltage linked to this read voltage (e.g., a fixed proportional value). Instead of a fixed Vpass voltage, it is applied to the word line of the virtual word line area. This can more effectively shield adjacent interference and improve the accuracy of read operations.

[0086] In high-speed or high-precision operations, capacitive coupling and interference between adjacent word lines can cause fluctuations in operating voltage, affecting the accuracy of data reading and writing. To suppress this interference, this invention introduces a virtual word line area. This area does not store user data but instead acts as a shield or stabilizer by applying a fixed voltage or a voltage linked to adjacent areas. This method effectively reduces inter-word line interference and improves the operational stability of adjacent memory areas.

[0087] In one embodiment, the virtual character line area may be located at the outermost (e.g., at the top and / or bottom) or relatively outer edge of the management areas 41(1) to 41(D). In another embodiment, the virtual character line area may also be interspersed between any two specific types of management areas or adjacent to specific types of management areas, as required by practical needs; this invention is not limited thereto.

[0088] In one embodiment, the voltage applied to the virtual word line area can always be a fixed voltage. In another embodiment, the voltage applied to the virtual word line area can also change in conjunction with the voltage applied to any adjacent management area. For example, when the voltage applied to a management area adjacent to a virtual word line area changes, this change can be reflected in this virtual word line area, causing the voltage subsequently applied to the virtual word line area to change accordingly. This optimizes the virtual word line area's operational assistance capabilities to adjacent management areas.

[0089] If the voltage of the virtual word line area remains constant, it may not be able to effectively cope with interference caused by voltage changes in adjacent areas. To solve this problem, this invention supports the voltage of the virtual word line area changing in tandem with the voltage of adjacent management areas. This method allows for real-time response to changes in the operating status of adjacent areas, providing more precise voltage shielding and further improving operational stability.

[0090] In one embodiment, the memory control circuit 23 can further divide a management area into multiple management areas (also called sub-management areas). For example, when a single management table is insufficient to fully reflect the various electrical characteristics within a single management area due to special reasons, the memory control circuit 23 can further divide this management area into multiple sub-management areas. Then, the memory control circuit 23 can configure multiple management tables (also called sub-management tables) to manage these sub-management areas. For example, these sub-management tables can each correspond to one of these sub-management areas.

[0091] In one embodiment, the memory control circuit 23 can determine whether multiple electrical characteristics appear in a previously divided single management area. In response to the presence of multiple electrical characteristics in the previously divided single management area, the memory control circuit 23 can divide this management area into multiple sub-management areas. However, if the previously divided single management area remains with only a single electrical characteristic, the memory control circuit 23 may not perform the aforementioned sub-management area division operation on this management area.

[0092] Figure 9 This is a schematic diagram illustrating the division of a management area into sub-management areas according to an embodiment of the present invention. Please refer to... Figure 9 Management area 91 can be Figure 4 The memory control circuit 23 can divide the management area 91 into multiple sub-management areas 92(1) to 92(E) in response to the presence of multiple electrical characteristics in the management area 91. Each sub-management area 92(1) to 92(E) may have multiple electrical characteristics. Then, the memory control circuit 23 can configure sub-management tables 901(1) to 901(E) to manage the sub-management areas 92(1) to 92(E) respectively.

[0093] In one embodiment, assuming that multiple electrical characteristics F(1) to F(E) simultaneously occur in management area 91, sub-management areas 92(1) to 92(E) can respectively correspond to these electrical characteristics F(1) to F(E). Sub-management area 92(k) can correspond to electrical characteristic F(k), where k is an integer between 1 and E. Subsequently, the memory control circuit 23 can manage sub-management area 92(k) according to sub-management area 92(k). Therefore, even if the electrical characteristics of some management areas change during the operation of the storage device 12, the configuration of each management area can be dynamically adjusted according to current needs.

[0094] In one embodiment, the memory control circuit 23 can detect at least one of the following: wear level information, temperature information, and model information of the memory module 122. The wear level information reflects the degree of wear of the memory module 122. For example, the wear level information may include a wear level value. This wear level value may reflect the wear level (or average wear level) of at least a portion of the management area in the memory module 122. For example, as the usage time, number of uses, and / or frequency of use of the memory module 122 increases, the wear level of the memory module 122 may increase accordingly. The temperature information reflects the temperature of the memory module 122. For example, this temperature information can be obtained through a temperature sensor disposed inside the storage device 12. The model information reflects the brand, model, and / or version of the memory module 122.

[0095] In one embodiment, the memory control circuit 23 can adjust the word line coverage of at least one of the management areas 41(1) to 41(D) based on at least one of the wear level information, temperature information, and model information of the memory module 122. Taking management area 41(i) as an example, in response to a change in at least one of the wear level information, temperature information, and model information of the memory module 122, the memory control circuit 23 can expand the word line coverage of management area 41(i) (e.g., include some word lines near management area 41(i) that were not originally part of management area 41(i) into management area 41(i)) or shrink the word line coverage of management area 41(i) (e.g., exclude some word lines in management area 41(i) that are adjacent to other management areas from management area 41(i).

[0096] As memory usage time increases or ambient temperature changes, the electrical characteristics of word lines may drift, rendering the original management area divisions inapplicable. To address this issue, this invention supports dynamically adjusting the word line coverage of the management area based on factors such as wear level, temperature, and model number. This approach allows for real-time adaptation to the actual state of the memory, maintaining the effectiveness and accuracy of the management strategy.

[0097] In detail, regarding the aforementioned "dynamic adjustment," examples of the triggering conditions and adjustment range are provided. For instance, the memory control circuit 23 can periodically detect the write / erase cycles (P / E cycles) of the memory module 122. When the average write / erase cycles of a certain management area (e.g., the bonding interface area BIR) exceed a preset threshold (e.g., 1000 times), it is determined that its wear level has increased. At this time, the memory control circuit 23 can adjust the read voltage offset recorded in the management table corresponding to that management area from +50mV to +70mV according to a preset algorithm to compensate for the decrease in charge retention capability caused by wear.

[0098] For example, when the temperature sensor detects that the temperature of the memory module 122 rises from 25°C to 70°C, the memory control circuit 23 can query the temperature compensation mapping table in the management table and apply an additional -20mV compensation value to the programming verification voltage of all management areas to counteract the effect of high temperature on the transistor threshold voltage.

[0099] The above numerical or logical examples illustrate the "dynamic adjustment," including the specific implementation methods for its triggering conditions and adjustment range.

[0100] In one embodiment, in response to a change in at least one of the wear level information, temperature information, and model information of the memory module 122, the memory control circuit 23 may also change the total number of the divided management areas 41(1) to 41(D). For example, changing the total number of the divided management areas 41(1) to 41(D) may include adding a new management area to the management areas 41(1) to 41(D), removing a management area from the management areas 41(1) to 41(D), or merging any two adjacent management areas of the management areas 41(1) to 41(D) into a single management area, etc.

[0101] In one embodiment, the memory control circuit 23 can also adjust the contents of at least one of the management tables 401(1) to 401(D) based on at least one of the wear level information, temperature information, and model information of the memory module 122. For example, in response to a change in at least one of the wear level information, temperature information, and model information of the memory module 122, the memory control circuit 23 can update or adjust the contents of at least one of the management tables 401(1) to 401(D). The adjusted contents of the management tables can be more closely aligned with the current electrical characteristics of each management area. For example, the aforementioned operation of updating or adjusting the contents of at least one of the management tables 401(1) to 401(D) may include changing the adjustment parameters recorded in at least one of the management tables 401(1) to 401(D).

[0102] The electrical characteristics of a memory change with usage and environmental factors. If the management table remains unchanged, it will be unable to adapt to actual operational needs. Therefore, this invention can dynamically adjust voltage parameters or other compensation values ​​in the management table based on information such as wear, temperature, and model number. This ensures that the management table always reflects the current memory state, improving the accuracy of voltage compensation and operational reliability.

[0103] Based on the above, even if the state of the storage device 12 itself or the state of the environment changes, the management efficiency of the memory module 122 and / or the operational stability of the memory module 122 can be maintained or even improved by dynamically updating the management area and / or management table.

[0104] In one embodiment, the memory control circuit 23 can manage at least one of the read voltage, read bypass voltage, programming voltage, programming verification voltage, erase voltage, erase verification voltage, and pre-programming voltage applied to the management area 41(i) according to management table 401(i) (also referred to as a first electrical parameter). Furthermore, the memory control circuit 23 can manage at least one of the read voltage, read bypass voltage, programming voltage, programming verification voltage, erase voltage, erase verification voltage, and pre-programming voltage applied to the management area 41(j) according to management table 401(j) (also referred to as a second electrical parameter). It should be noted that the first electrical parameter and / or the second electrical parameter may also include other types of electrical parameters, which are not limited by the present invention. This can improve the efficiency and / or stability of subsequently operating the various management areas in management areas 41(1) to 41(D) using these electrical parameters.

[0105] Different management zones require different optimal operating voltages (such as read voltage, programming voltage, erase voltage, etc.) due to differences in their electrical characteristics. Using uniform voltage parameters would lead to low operating efficiency or increased error rates in some zones. Therefore, this invention provides a separate management table for each management zone, recording its required voltage parameters, thereby achieving targeted voltage compensation. This method optimizes the operating voltage of each zone, improving overall read / write performance and data retention capabilities.

[0106] In one embodiment, after dividing the management areas 41(1) to 41(D), the memory control circuit 23 can detect operation events (also called target operation events) targeting at least one word line (also called a target word line) in the memory module 122. For example, the target operation event can be a read event, a write event, or an erase event targeting the target word line. A read event indicates reading data from the target word line (i.e., reading the data stored in the target word line). A write event indicates writing data to the target word line. An erase event indicates erasing the data stored in the target word line.

[0107] In one embodiment, in response to a target operation event, the memory control circuit 23 can determine a specific management area (also called a target management area) in management areas 41(1) to 41(D) where the target word line is located. For example, the target management area can be management area 41(i) or management area 41(j). Management areas 41(i) and 41(j) can be any two management areas 41(1) to 41(D).

[0108] In one embodiment, if the target word line is located in management area 41(i) (i.e., the target management area is management area 41(i)), the memory control circuit 23 can perform an operation (also called a target operation) on the target word line corresponding to a target operation event based on specific electrical parameters (i.e., a first electrical parameter). Specifically, the first electrical parameter can be matched with the electrical characteristics (i.e., a first electrical characteristic) of management area 41(i). For example, the target operation can be a read operation, a write operation, or an erase operation for the target word line. A read operation is used to read data from the target word line (i.e., read the data stored in the target word line). A write operation is used to write data to the target word line. An erase operation is used to erase the data stored in the target word line.

[0109] On the other hand, if the target word line is located in management area 41(j) (i.e., the target management area is management area 41(j)), the memory control circuit 23 can perform the aforementioned target operation on the target word line based on specific electrical parameters (i.e., second electrical parameters). In particular, the second electrical parameters can be matched with the electrical characteristics (also called second electrical characteristics) of management area 41(j). It should be noted that management areas 41(i) and 41(j) are located at different positions in the vertical direction of memory module 122, so the electrical characteristics of management area 41(i) can be different from the electrical characteristics of management area 41(j).

[0110] In one embodiment, the difference between the first electrical parameter and the second electrical parameter is used to compensate for the difference between the first electrical characteristic and the second electrical characteristic. Taking the read voltage as an example, the read voltage (i.e., the first electrical parameter) used for a read operation (i.e., the target operation) performed on a specific word line (also called the first word line) in management area 41(i) may be different from the read voltage (i.e., the second electrical parameter) used for a read operation (i.e., the target operation) performed on a specific word line (also called the second word line) in management area 41(j). Alternatively, taking the programming voltage as an example, the programming voltage (i.e., the first electrical parameter) used for a write operation (i.e., the target operation) performed on the first word line in management area 41(i) may be different from the programming voltage (i.e., the second electrical parameter) used for a write operation (i.e., the target operation) performed on the second word line in management area 41(j), and so on.

[0111] In one embodiment, the difference between the first electrical parameter and the second electrical parameter (e.g., voltage difference) may be positively correlated with the difference between the first electrical characteristic and the second electrical characteristic. That is, the greater the difference between the first electrical characteristic and the second electrical characteristic, the greater the difference between the first electrical parameter and the second electrical parameter (e.g., voltage difference).

[0112] In one embodiment, the memory control circuit 23 can determine a reference electrical parameter corresponding to the target operation based on the target operation to be performed. For example, this reference electrical parameter may be at least one of read voltage, read pass voltage, programming voltage, programming verification voltage, erase voltage, erase verification voltage, and pre-programming voltage, and the type of this reference electrical parameter is not limited thereto. For example, in one embodiment, this reference electrical parameter may also include voltage step accuracy, etc., which is not limited by the present invention.

[0113] In one embodiment, in response to the target operation being a read operation, the determined reference electrical parameters may include a read voltage and / or a read pass voltage. For example, in a read operation, a read voltage is applied to the target word line, while a read pass voltage is applied to adjacent word lines (non-target word lines). Specifically, the purpose of applying the read voltage to the target word line is to sense the voltage state (or conduction state) of each memory cell in the target word line in order to read data from the target word line. However, the purpose of applying the read pass voltage to adjacent word lines is to enable the memory cells in the adjacent word lines to conduct, thereby facilitating the reading of data from the target word line.

[0114] In one embodiment, when the target operation is a read operation, performing the target operation on the target word line according to the adjusted reference electrical parameters further includes: identifying the management area to which the word line adjacent to the target word line belongs; and determining the read pass voltage applied to the adjacent word line according to the management table corresponding to the management area to which the adjacent word line belongs.

[0115] In one embodiment, in response to a write operation being performed as the target operation, the determined reference electrical parameters may include a programming voltage, a programming verification voltage, and / or a voltage stepping accuracy. For example, in a write operation, multiple program-verify cycles may be executed. In each program-verify cycle, a programming voltage is applied to the target word line to store data to the target word line, and a programming verification voltage is subsequently applied to the target word line to verify that the voltage state of each memory cell in the current target word line meets expectations. Furthermore, in a write operation, this voltage stepping accuracy is used to adjust the adjustment magnitude of the programming voltage and / or the programming verification voltage across the multiple program-verify cycles.

[0116] In one embodiment, in response to the target operation being an erase operation, the determined reference electrical parameters may include an erase voltage, an erase verification voltage, a pre-programmed voltage, and / or a voltage stepping accuracy. For example, in an erase operation, multiple erase-verify cycles may be executed. In each erase-verify cycle, a pre-programmed voltage is applied to the target word line to pre-program the target word line, and an erase voltage may subsequently be applied to the target word line to actually erase the data stored on the target word line. Finally, an erase verification voltage is applied to the target word line to verify whether the voltage state of each memory cell in the current target word line meets expectations. Furthermore, in the erase operation, this voltage stepping accuracy is used to adjust the adjustment magnitude of the erase voltage, erase verification voltage, and / or pre-programmed voltage used multiple times in the multiple erase-verify cycles.

[0117] It should be noted that the reference electrical parameters used in the different types of target operations mentioned above are merely examples. In one embodiment, the type and / or number of reference electrical parameters may be adjusted according to practical needs for different types of target operations.

[0118] In one embodiment, after determining the target management area, the memory control circuit 23 can determine the management table (also called the target management table) corresponding to the target management area from management tables 401(1) to 401(D). For example, if the target management area is management area 41(i), the memory control circuit 23 can determine management table 401(i) as the target management table. Alternatively, if the target management area is management area 41(j), the memory control circuit 23 can determine management table 401(j) as the target management table.

[0119] In one embodiment, after determining the reference electrical parameters and the target management table, the memory control circuit 23 can adjust the reference electrical parameters according to the target management table to obtain the aforementioned first electrical parameter or second electrical parameter. Then, the memory control circuit 23 can perform a target operation on the target word line according to the adjusted reference electrical parameters (i.e., the first electrical parameter or the second electrical parameter). For example, if the target management area is management area 41(i), the memory control circuit 23 can adjust the reference electrical parameters according to management table 401(j) to obtain the first electrical parameter. Then, the memory control circuit 23 can perform a target operation on the target word line according to the first electrical parameter. Alternatively, if the target management area is management area 41(j), the memory control circuit 23 can adjust the reference electrical parameters according to management table 401(j) to obtain the second electrical parameter. Then, the memory control circuit 23 can perform a target operation on the target word line according to the second electrical parameter. Thus, by adaptively adjusting the reference electrical parameters for the target word line (or target management area), the efficiency and / or stability of subsequent target operations performed on the target word line can be improved.

[0120] In one embodiment, depending on the type of the target management region (e.g., belonging to the Bond Interface Region (BIR), Etching Variation Region (PDER), Center Stable Region (DCR), or Bond Transition Region (DBTR)), the selected target management table may have the following characteristics:

[0121] (1) If the target management area belongs to the bonding interface area (BIR), the selected target management table (or the information recorded in the target management table) can be used exclusively or primarily for compensating for interface bonding process defects of the target word line during the target operation. For example, if the target management area belongs to the bonding interface area (BIR), the memory control circuit 23 can adjust the read voltage for the target word line, for example, by increasing this read voltage by an offset value (also called a first offset value). For example, the first offset value can be -0.1V, and the present invention is not limited thereto. In addition, if the target management area belongs to the bonding interface area (BIR), the memory control circuit 23 can also reduce the voltage step accuracy.

[0122] (2) If the target management area belongs to the etch variation zone (PDER), the selected target management table (or the information recorded in the target management table) can be used exclusively or primarily for compensating for plasma etching process defects of the target word line during the target operation. For example, if the target management area belongs to the etch variation zone (PDER), the memory control circuit 23 can adjust the voltage stepping accuracy for the target word line (e.g., reduce the voltage stepping accuracy), for example, reducing this voltage stepping accuracy by a preset amount (also called the first preset amount) (e.g., reducing it by 20%) to improve the verification accuracy, and the present invention is not limited thereto.

[0123] (3) If the target management area belongs to the central stable region (DCR), the selected target management table (or the information recorded in the target management table) can be used exclusively or primarily to compensate for the most stable electrical characteristics of the target word line during the target operation. For example, if the target management area belongs to the central stable region (DCR), the memory control circuit 23 can adjust the voltage step accuracy for the target word line (e.g., increase the voltage step accuracy), for example, by increasing this voltage step accuracy by a preset amount (also called a second preset amount) (e.g., by 10%), to speed up the verification process, and the present invention is not limited thereto.

[0124] (4) If the target management region belongs to the Bonding Transition Region (DBTR), the selected target management table (or the information recorded in the target management table) can be used exclusively or primarily for performing corresponding electrical compensation for the word line position where the target word line is located during the target operation on the target word line. For example, if the target management region belongs to the Bonding Transition Region (DBTR), the memory control circuit 23 can perform gradient compensation for the read voltage used for the target word line. For example, in the Bonding Transition Region (DBTR), for each preset number of word line positions crossed, the memory control circuit 23 can increase (or decrease) the used read voltage by an offset value (also called a second offset value). For example, the second offset value can be 0.05V, and the present invention is not limited thereto.

[0125] It should be noted that in the above embodiments, the division of the management area, the setting of the word line coverage of the management area, the initial content setting of the management table, the content update mechanism of the management table, and the parameter adjustment mechanism corresponding to various types of management areas can all be automatically executed by the memory control circuit 23 based on preset operating logic. For example, by using pre-downloaded and installed firmware code, the memory control circuit 23 can automatically complete the above operations based on this firmware code after the storage device 12 is powered on.

[0126] Figure 10 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 10 In step S1001, a target operation event is detected, wherein the target operation event indicates that a target operation is performed on the target word line. In step S1002, in response to the target operation event, it is determined that the target word line is located in a target management area among multiple management areas. In step S1003, a target management table corresponding to the target management area is determined from multiple management tables. In step S1004, the reference electrical parameters are adjusted according to the target management table. In step S1005, the target operation is performed on the target word line according to the adjusted reference electrical parameters.

[0127] However, Figure 10 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 10 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 10 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0128] In summary, the memory management method and memory device proposed in this invention can, based on a specially configured management table, perform vertical grouping management of word lines in the memory module to compensate for electrical defects in word lines with different electrical characteristics (e.g., different process defects). This effectively improves the overall operational performance and / or operational stability of the memory device.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, Applied to a storage device, the storage device including a memory module, the memory module including multiple word lines, the memory management method includes: In response to a target operation event, it is determined that the target word line among the multiple word lines is located in a target management area among multiple management areas, wherein the multiple management areas are vertically distributed in the memory module according to their respective electrical characteristics. The multiple management areas include a bonding interface area, a bonding transition area, an etching variation area, and a central stable area. The bonding interface area, the bonding transition area, the etching variation area, and the central stable area correspond to different types of process defects, and the target operation event indicates that a target operation is performed on the target word line. From multiple management tables, determine the target management table corresponding to the target management area; Adjust the baseline electrical parameters according to the target management table; and The target operation is performed on the target word line based on the adjusted reference electrical parameters.

2. The memory management method according to claim 1, wherein the word lines located in the bonding interface region have more significant interface bonding process defects compared to other word lines. Word lines located in the etching variation region exhibit more significant plasma etching process defects compared to other word lines. Word lines located in the central stability region have the most stable electrical characteristics compared to other word lines, and The electrical characteristics of the word lines located in the bonding transition region change gradually according to the word line position.

3. The memory management method according to claim 2, wherein if the target management area belongs to the bonding interface area, the target management table is used to compensate for interface bonding process defects of the target word line during the execution of the target operation on the target word line. If the target management area belongs to the etching variation area, the target management table is used to compensate for the plasma etching process defects of the target word line during the target operation performed on the target word line. If the target management area belongs to the central stable area, the target management table is used to compensate for the most stable electrical characteristics of the target word line during the execution of the target operation on the target word line, and If the target management area belongs to the bonding transition area, the target management table is used to perform corresponding electrical compensation for the word line position where the target word line is located during the target operation performed on the target word line.

4. The memory management method according to claim 1, wherein the plurality of management areas includes virtual word lines that intersect between two specific types of management areas. The word lines located in the virtual word line area are not used to store user data, and the voltage applied to the word lines in the virtual word line area changes in conjunction with the operating voltage applied to the adjacent management area.

5. The memory management method according to claim 4, wherein the voltage applied to the word lines in the virtual word line region changes in conjunction with the operating voltage applied to the adjacent management region, comprising: When the voltage applied to the adjacent management area changes, the change can be reflected in the virtual word line area, so that the voltage subsequently applied to the virtual word line area also changes accordingly.

6. A storage device, characterized in that, include: Connection interface, used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory module includes multiple word lines, and the memory controller is configured to perform the memory management method according to any one of claims 1 to 5.

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