Pixel driving circuit, driving method thereof and display device

Abstract

The invention relates to a pixel driving circuit and a driving method thereof, and a display device, the pixel driving circuit comprises a coupling sub-circuit and a holding sub-circuit, the coupling sub-circuit is electrically connected with a second scanning signal end (Gate2), a third scanning signal end (Gate3), a fifth scanning signal end (Gate5), a data signal end (Data), a second input signal end (IN2) and a third node (N3), the third node (N3) is configured to couple a signal of a data signal end (Data) or a second input signal end (IN2) to the third node (N3) under the control of signals of a second scanning signal end (Gate2), a third scanning signal end (Gate3) and a fifth scanning signal end (Gate5); the time period when the signal of the fifth scanning signal end (Gate5) is the effective level signal is at least partially overlapped with the time period when at least one of the second scanning signal end (Gate2) and the third scanning signal end (Gate3) is the effective level signal.

Description

Pixel driving circuit and its driving method, display device

[0001] This application claims priority to Chinese Patent Application No. 202411187376.8, filed on August 27, 2024, entitled "Pixel Driving Circuit and Driving Method Thereof, Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, specifically to a pixel driving circuit and its driving method, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a pixel driving circuit and driving method thereof, as well as a display device.

[0006] In a first aspect, this disclosure provides a pixel driving circuit, including: a driving sub-circuit, a coupling sub-circuit, a holding sub-circuit, a first initial sub-circuit, and a light emission control sub-circuit;

[0007] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node.

[0008] The first initial sub-circuit is electrically connected to the first input signal terminal, the first scan signal terminal, and the first node, respectively, and is configured to provide the signal from the first input signal terminal to the first node under the control of the signal from the first scan signal terminal;

[0009] The coupling sub-circuit is electrically connected to the second scan signal terminal, the third scan signal terminal, the fifth scan signal terminal, the data signal terminal, the second input signal terminal, and the third node, respectively, and is configured to couple the signal from the data signal terminal or the second input signal terminal to the third node under the control of the signals from the second scan signal terminal, the third scan signal terminal, and the fifth scan signal terminal;

[0010] The holding sub-circuit, which is electrically connected to the first node and the third node respectively, is configured to store the voltage difference between the signals of the first node and the third node;

[0011] The light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power supply terminal, the second node, and the fifth node, respectively. It is configured to provide the signal of the first power supply terminal to the second node and the signal of the third node to the fifth node under the control of the signals of the first light-emitting signal terminal and the second light-emitting signal terminal.

[0012] The time period during which the signal at the fifth scanning signal terminal is at an effective level overlaps at least partially with the time period during which at least one of the second and third scanning signal terminals is at an effective level.

[0013] In an exemplary embodiment, the signal received by the second scan signal terminal connected to the i-th row pixel driving circuit is the same signal as the signal received by the first scan signal terminal connected to the iM-th row pixel driving circuit, where M is a positive integer greater than 1.

[0014] In an exemplary embodiment, the coupling sub-circuit includes: a data writing sub-circuit, an initial writing sub-circuit, a connection sub-circuit, and a voltage regulation sub-circuit;

[0015] The data writing sub-circuit is electrically connected to the third scan signal terminal, the data signal terminal, and the fourth node, respectively, and is configured to provide the data signal terminal to the fourth node under the control of the signal from the third scan signal terminal.

[0016] The initial write sub-circuit is electrically connected to the second scan signal terminal, the second input signal terminal, and the fourth node, respectively, and is configured to provide the signal from the second input signal terminal to the fourth node under the control of the signal from the second scan signal terminal.

[0017] The voltage regulator circuit is electrically connected to the third node and the sixth node respectively, and is configured to store the voltage difference between the signals of the third node and the sixth node.

[0018] The connecting sub-circuit is electrically connected to the fifth scanning signal terminal, the fourth node, and the sixth node, respectively, and is configured to provide the signal of the fourth node to the sixth node under the control of the signal of the fifth scanning signal terminal.

[0019] In an exemplary embodiment, the coupling sub-circuit includes: a data writing sub-circuit, an initial writing sub-circuit, a connection sub-circuit, and a voltage regulation sub-circuit;

[0020] The data writing sub-circuit is electrically connected to the third scan signal terminal, the data signal terminal, and the fourth node, respectively, and is configured to provide the data signal terminal to the fourth node under the control of the signal from the third scan signal terminal.

[0021] The initial write sub-circuit is electrically connected to the second scan signal terminal, the second input signal terminal, and the fourth node, respectively, and is configured to provide the signal from the second input signal terminal to the fourth node under the control of the signal from the second scan signal terminal.

[0022] The voltage regulator circuit is electrically connected to the fourth node and the sixth node respectively, and is configured to store the voltage difference between the signals of the fourth node and the sixth node.

[0023] The connecting sub-circuit is electrically connected to the fifth scanning signal terminal, the third node, and the sixth node, respectively, and is configured to provide the signal of the sixth node to the third node under the control of the signal of the fifth scanning signal terminal.

[0024] In an exemplary embodiment, the data writing sub-circuit includes a fourth transistor, and the initial writing sub-circuit includes a second transistor;

[0025] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the second input signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node.

[0026] The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node.

[0027] In an exemplary embodiment, the communication sub-circuit includes an eighth transistor, and the voltage regulator sub-circuit includes a second capacitor;

[0028] The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the sixth node.

[0029] The first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the sixth node.

[0030] In an exemplary embodiment, the communication sub-circuit includes an eighth transistor, and the voltage regulator sub-circuit includes a second capacitor;

[0031] The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the sixth node.

[0032] The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the sixth node.

[0033] In an exemplary embodiment, it further includes: a second initial sub-circuit;

[0034] The second initial sub-circuit is electrically connected to the fourth scan signal terminal, the third input signal terminal, and the fifth node, respectively, and is configured to provide the signal from the third input signal terminal to the fifth node under the control of the signal from the fourth scan signal terminal.

[0035] In an exemplary embodiment, the first initial sub-circuit includes: a first transistor; the holding sub-circuit includes: a first capacitor; the driving sub-circuit includes: a third transistor, the third transistor includes: a first control electrode and a second control electrode; and the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor.

[0036] The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0037] The first control electrode of the third transistor is electrically connected to the first node, the second control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0038] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0039] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0040] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node.

[0041] In an exemplary embodiment, the second initial sub-circuit includes: a seventh transistor;

[0042] The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.

[0043] In an exemplary embodiment, it further includes: a second initial sub-circuit, wherein the coupling sub-circuit includes: a second transistor, a fourth transistor, an eighth transistor, and a second capacitor; the holding sub-circuit includes: a first capacitor; the driving sub-circuit includes: a third transistor; the first initial sub-circuit includes: a first transistor; the second initial sub-circuit includes: a seventh transistor; the light emission control sub-circuit includes: a fifth transistor and a sixth transistor; and the third transistor includes: a first control electrode and a second control electrode.

[0044] The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0045] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the second input signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node.

[0046] The first control electrode of the third transistor is electrically connected to the first node, the second control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0047] The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node.

[0048] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0049] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0050] The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.

[0051] The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the sixth node.

[0052] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node.

[0053] The first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the sixth node.

[0054] In an exemplary embodiment, it further includes: a second initial sub-circuit, wherein the coupling sub-circuit includes: a second transistor, a fourth transistor, an eighth transistor, and a second capacitor; the holding sub-circuit includes: a first capacitor; the driving sub-circuit includes: a third transistor; the first initial sub-circuit includes: a first transistor; the second initial sub-circuit includes: a seventh transistor; the light emission control sub-circuit includes: a fifth transistor and a sixth transistor; and the third transistor includes: a first control electrode and a second control electrode.

[0055] The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0056] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the second input signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node.

[0057] The first control electrode of the third transistor is electrically connected to the first node, the second control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0058] The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node.

[0059] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0060] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0061] The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.

[0062] The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the sixth node.

[0063] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node.

[0064] The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the sixth node.

[0065] In an exemplary embodiment, at least one of the first to the eighth transistors is an N-type transistor, or at least one of the first to the fourth transistors and the sixth to the eighth transistors is an N-type transistor, and the fifth transistor is a P-type transistor.

[0066] In an exemplary embodiment, the signal received by the second input signal terminal connected to the same pixel driving circuit is the same as the signal received by the first input signal terminal.

[0067] In an exemplary embodiment, the display substrate is disposed in a display substrate, and the content displayed by the display substrate includes: a plurality of display frames, at least one display frame including: a refresh frame and at least one hold frame;

[0068] In at least one refresh frame of a display frame, the signal at the fifth scan signal terminal is an active level signal for a portion of the time period, and in at least one hold frame of a display frame, the signal at the fifth scan signal terminal is an inactive level signal.

[0069] In a second aspect, this disclosure also provides a display device, comprising: a display area and a non-display area disposed on at least one side of the display area, wherein the aforementioned pixel driving circuits arranged in an array are disposed in the display area;

[0070] The non-display area is provided with a driving circuit group, which includes: a first driving circuit, and the first driving circuit includes: a plurality of cascaded first shift registers;

[0071] The second scan signal terminal connected to at least one row of pixel driving circuits is connected to the same first shift register as the first scan signal terminal connected to the first M rows of pixel driving circuits.

[0072] In an exemplary embodiment, the signal lines connected to the fifth scan signal terminals of at least two pixel driving circuits in the same row are different.

[0073] Thirdly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit, the method comprising:

[0074] The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes;

[0075] The first initial sub-circuit provides the first input signal terminal signal to the first node under the control of the signal at the first scanning signal terminal;

[0076] Under the control of the signals from the second scan signal terminal, the third scan signal terminal, and the fifth scan signal terminal, the coupler circuit couples the signal from the data signal terminal or the second input signal terminal to the third node;

[0077] Maintain the voltage difference between the signals stored in the first and third nodes in the sub-circuit;

[0078] Under the control of the signals from the first and second light-emitting signal terminals, the light-emitting control sub-circuit provides the first power supply signal to the second node and the third node signal to the fifth node.

[0079] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0080] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0081] Overview of the attached figures

[0082] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0083] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0084] Figure 2 is the equivalent circuit diagram of the first initial sub-circuit;

[0085] Figure 3 shows the equivalent circuit diagram of the holding sub-circuit;

[0086] Figure 4 shows the equivalent circuit diagram of the driver sub-circuit.

[0087] Figure 5 shows the equivalent circuit diagram of the driver sub-circuit (II).

[0088] Figure 6 shows the equivalent circuit diagram of the coupling sub-circuit;

[0089] Figure 7 shows the equivalent circuit diagram of the coupler sub-circuit (II).

[0090] Figure 8 shows the equivalent circuit diagram of the light-emitting control sub-circuit.

[0091] Figure 9 shows the equivalent circuit diagram of the light-emitting control sub-circuit.

[0092] Figure 10 is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment;

[0093] Figure 11 is the equivalent circuit diagram of the second initial sub-circuit in Figure 10;

[0094] Figure 12 is a schematic diagram of the pixel driving circuit provided in another exemplary embodiment;

[0095] Figure 13 is the equivalent circuit diagram of the second initial sub-circuit in Figure 12;

[0096] Figure 14 is the equivalent circuit diagram of the second initial sub-circuit in Figure 12.

[0097] Figure 15 is a schematic diagram of the pixel driving circuit provided in yet another exemplary embodiment;

[0098] Figure 16 is the equivalent circuit diagram of the third initial sub-circuit;

[0099] Figure 17 is an equivalent circuit diagram of a pixel driving circuit.

[0100] Figure 18 is an equivalent circuit diagram of a pixel driving circuit (II).

[0101] Figure 19 is the first driving timing diagram of the pixel driving circuit provided in Figure 18;

[0102] Figure 20 is the second driving timing diagram of the pixel driving circuit provided in Figure 18;

[0103] Figure 21 is an equivalent circuit diagram of a pixel driving circuit.

[0104] Figure 22 is an equivalent circuit diagram of a pixel driving circuit.

[0105] Figure 23 is the first driving timing diagram of the pixel driving circuit provided in Figure 22;

[0106] Figure 24 is the second driving timing diagram of the pixel driving circuit provided in Figure 22;

[0107] Figure 25 is the third driving timing diagram of the pixel driving circuit provided in Figure 22;

[0108] Figure 26 is the fourth driving timing diagram of the pixel driving circuit provided in Figure 22;

[0109] Figure 27 is the fifth driving timing diagram of the pixel driving circuit provided in Figure 22;

[0110] Figure 28 is the driving timing diagram of the pixel driving circuit provided in Figure 22.

[0111] Figure 29 is the driving timing diagram of the pixel driving circuit provided in Figure 22.

[0112] Figure 30 is the driving timing diagram of the pixel driving circuit provided in Figure 22.

[0113] Figure 31 is an equivalent circuit diagram of a pixel driving circuit.

[0114] Figure 32 is an equivalent circuit diagram of a pixel driving circuit.

[0115] Figure 33 is an equivalent circuit diagram of a pixel driving circuit.

[0116] Figure 34 is a driving timing diagram of the pixel driving circuit provided in Figures 32 and 33.

[0117] Figure 35 is the second driving timing diagram of the pixel driving circuit provided in Figures 32 and 33;

[0118] Figure 36 is an equivalent circuit diagram of a pixel driving circuit.

[0119] Figure 37 is an equivalent circuit diagram of a pixel driving circuit.

[0120] Figure 38 is an equivalent circuit diagram of a pixel driving circuit.

[0121] Figure 39 is an equivalent circuit diagram of a pixel driving circuit.

[0122] Figure 40 is an equivalent circuit diagram of a pixel driving circuit.

[0123] Figure 41 is the first driving timing diagram of the pixel driving circuit provided in Figures 39 and 40;

[0124] Figure 42 is the second driving timing diagram of the pixel driving circuit provided in Figures 39 and 40;

[0125] Figure 43 is the third driving timing diagram of the pixel driving circuit provided in Figures 39 and 40;

[0126] Figure 44 is the fourth driving timing diagram of the pixel driving circuit provided in Figures 39 and 40;

[0127] Figure 45 is the fifth driving timing diagram of the pixel driving circuit provided in Figures 39 and 40;

[0128] Figure 46 is the driving timing diagram of the pixel driving circuit provided in Figures 39 and 40.

[0129] Figure 47 is the driving timing diagram of the pixel driving circuit provided in Figures 39 and 40.

[0130] Figure 48 is the driving timing diagram of the pixel driving circuit provided in Figures 39 and 40.

[0131] Figure 49 is a schematic diagram of the pixel driving circuit provided in another embodiment of the present disclosure;

[0132] Figure 50 is a schematic diagram of the structure of a coupling sub-circuit provided in an exemplary embodiment;

[0133] Figure 51 is a schematic diagram of the structure of a coupling sub-circuit provided in another exemplary embodiment;

[0134] Figure 52 is the equivalent circuit diagram of the coupling sub-circuit provided in Figure 50;

[0135] Figure 53 is the equivalent circuit diagram of the coupling sub-circuit provided in Figure 51;

[0136] Figure 54 is another schematic diagram of the pixel driving circuit provided in Figure 50;

[0137] Figure 55 is an equivalent circuit diagram of some sub-circuits of the pixel driving circuit;

[0138] Figure 56 is the equivalent circuit diagram of the second initial sub-circuit of the pixel driving circuit;

[0139] Figure 57 is an equivalent circuit diagram of the pixel driving circuit provided in Figure 50.

[0140] Figure 58 is the second equivalent circuit diagram of the pixel driving circuit provided in Figure 50;

[0141] Figure 59 is the equivalent circuit diagram of the pixel driving circuit provided in Figure 50.

[0142] Figure 60 is the equivalent circuit diagram of the pixel driving circuit provided in Figure 50.

[0143] Figure 61 is a timing diagram of the pixel driving circuit provided in Figures 57 and 59 in the refresh frame.

[0144] Figure 62 is a timing diagram of the pixel driving circuit provided in Figures 58 and 60 in the refresh frame.

[0145] Figure 63 is a timing diagram of the pixel driving circuit provided in Figures 57 and 59 in the holding frame.

[0146] Figure 64 is a timing diagram of the pixel driving circuit provided in Figures 58 and 60 in the holding frame.

[0147] Detailed Explanation

[0148] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0149] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0150] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0151] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0152] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0153] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0154] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0155] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0156] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0157] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0158] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0159] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0160] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0161] The display product includes at least one sub-pixel, which comprises a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light. The pixel driving circuit includes a driving transistor. The gate electrode of the driving transistor is connected to multiple transistors, resulting in a large parasitic capacitance value coupled to the gate electrode of the driving transistor. This reduces the follow-up ratio of the gate electrode voltage and source electrode voltage of the pixel driving circuit, causing a deviation in the driving signal voltage maintained between the gate electrode and source electrode of the driving transistor. This reduces the consistency of the display brightness of the display product and affects the display effect of the display substrate.

[0162] Therefore, this disclosure provides a pixel driving circuit.

[0163] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. As shown in Figure 1, the pixel driving circuit provided in an embodiment of this disclosure may include: a driving sub-circuit, a coupling sub-circuit, a holding sub-circuit, a first initial sub-circuit, and a light emission control sub-circuit.

[0164] The driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2.

[0165] The first initial sub-circuit is electrically connected to the first input signal terminal IN1, the first scan signal terminal Gate1, and the first node N1, respectively, and is configured to provide the signal of the first input signal terminal IN1 to the first node N1 under the control of the signal of the first scan signal terminal Gate1.

[0166] The coupling sub-circuit is electrically connected to at least one scan signal terminal Gate, a data signal terminal Data, a second input signal terminal IN2, and a third node N3, respectively, and is configured to couple the signal of the data signal terminal Data or the signal of the second input signal terminal IN2 to the third node N3 under the control of the signal of at least one scan signal terminal Gate.

[0167] The holding sub-circuit, electrically connected to the first node N1 and the third node N3 respectively, is configured to store the voltage difference between the signals of the first node N1 and the third node N3.

[0168] The light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal EM1, the first power supply terminal VDD, and the second node N2, respectively. It is configured to provide the first power supply terminal VDD signal to the second node N2 under the control of the signal from the first light-emitting signal terminal EM1.

[0169] In an exemplary embodiment, the first power supply terminal VDD can continuously provide a high-level signal, and the signal of the first power supply terminal VDD is a DC signal.

[0170] In this disclosure, the first initial sub-circuit connected to the first node is only electrically connected to the first input signal terminal and the first scan signal terminal. This means that the number of transistors connected to the first node is relatively small. Furthermore, the setting of the coupling sub-circuit can couple the data from the data signal terminal to the third node connected to the driving sub-circuit, reducing the number of transistors directly coupled to the first node connected to the driving sub-circuit. It can also achieve normal data writing and threshold compensation. Therefore, the pixel driving circuit provided in this disclosure embodiment can reduce the parasitic capacitance coupled to the first node N1 while ensuring normal display. This makes it less likely for the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit to deviate, ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0171] In an exemplary embodiment, the pixel driving circuit is configured to drive the light-emitting device L to emit light.

[0172] In an exemplary embodiment, the light-emitting device may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. Exemplarily, the anode of the light-emitting device is electrically connected to a pixel driving circuit, and the cathode of the light-emitting device is electrically connected to a second power supply terminal VSS.

[0173] In an exemplary embodiment, the second power supply terminal VSS can continuously provide a low-level signal, and the signal of the second power supply terminal VSS is a DC signal.

[0174] In exemplary embodiments, the light-emitting device may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). Typical dimensions (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. Typical dimensions (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0175] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0176] Figure 2 is an equivalent circuit diagram of the first initial sub-circuit. As shown in Figure 2, in an exemplary embodiment, the first initial sub-circuit includes a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0177] In an exemplary embodiment, the first input signal terminal IN1 can receive a first initial signal. The first transistor T1 can be referred to as the first initial transistor. Under the signal control of the first scan signal terminal Gate1, the first transistor T1 writes the first initial signal into the first node N1.

[0178] Figure 2 shows only one exemplary structure of the first initial sub-circuit. Those skilled in the art will readily understand that the implementation of the first initial sub-circuit is not limited to this.

[0179] Figure 3 is an equivalent circuit diagram of the holding sub-circuit. As shown in Figure 3, in an exemplary embodiment, the holding sub-circuit includes a first capacitor C1. The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3.

[0180] In an exemplary embodiment, the first capacitor C1 can ensure the stability of the signal of the first node N1 and improve the reliability of the pixel driving circuit.

[0181] Figure 3 shows only one exemplary structure of the hold sub-circuit, and those skilled in the art will readily understand that the implementation of the hold sub-circuit is not limited to this.

[0182] Figure 4 shows the equivalent circuit diagram of the driving sub-circuit. As shown in Figure 4, in an exemplary embodiment, the driving sub-circuit includes a third transistor T3. The third transistor T3 can be a single-gate transistor. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0183] Figure 5 shows the equivalent circuit diagram of the driving sub-circuit. As shown in Figure 5, in an exemplary embodiment, the driving sub-circuit includes a third transistor T3. The third transistor T3 can be a dual-gate transistor. The third transistor T3 includes a first control electrode and a second control electrode. The first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0184] In an exemplary embodiment, the third transistor T3 can be referred to as the driving transistor. The connection method of the third transistor in this disclosure can improve the output saturation characteristics of the third transistor T3.

[0185] Figures 4 and 5 show two exemplary structures of the driver sub-circuit. It will be readily understood by those skilled in the art that the implementation of the driver sub-circuit is not limited to these.

[0186] Figure 6 shows the equivalent circuit diagram of the coupling sub-circuit. As shown in Figure 6, in an exemplary embodiment, at least one scan signal terminal includes a second scan signal terminal Gate2 and a third scan signal terminal Gate3. The coupling sub-circuit may include a second transistor T2, a fourth transistor T4, and a second capacitor C2. Specifically, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0187] In an exemplary embodiment, the second input signal terminal IN2 can receive a second initial signal. The second transistor T2 can be referred to as the second initial transistor. Under the signal control of the second scan signal terminal Gate2, the second transistor T2 writes the second initial signal into the fourth node N4.

[0188] In an exemplary embodiment, the data signal terminal Data can receive data signals. The fourth transistor T4 can be referred to as the write transistor. Under the control of the signal at the third scan signal terminal Gate3, the fourth transistor T4 writes data signals to the fourth node N4.

[0189] Figure 7 shows the equivalent circuit diagram of the coupling sub-circuit. As shown in Figure 7, in an exemplary embodiment, at least one scan signal terminal includes a second scan signal terminal Gate2. The coupling sub-circuit may include a second transistor T2 and a second capacitor C2. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2; the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time period and to the second input signal terminal IN2 for a portion of the time period; the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0190] In an exemplary embodiment, the second input signal terminal IN2 can receive the second initial signal, and the data signal terminal Data can receive the data signal. Under the control of the signal from the second scan signal terminal Gate2, the second transistor T2 writes the data signal to the fourth node N4 for a portion of the time period and writes the second initial signal to the fourth node N4 for a portion of the time period.

[0191] Figures 6 and 7 show two exemplary structures of the coupler circuit. It will be readily understood by those skilled in the art that the implementation of the coupler circuit is not limited to these.

[0192] In an exemplary embodiment, the coupling sub-circuit provided in FIG7 includes fewer transistors than the coupling sub-circuit provided in FIG6, which can reduce the area occupied by the pixel driving circuit and the number of connected signal lines, and can achieve a high PPI of the display device.

[0193] Figure 8 is an equivalent circuit diagram of the light-emitting control sub-circuit. As shown in Figure 8, in an exemplary embodiment, the light-emitting control sub-circuit may include a fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2.

[0194] In an exemplary embodiment, the first power supply terminal VDD can receive a first power signal, and the fifth transistor T5 can be referred to as a light-emitting transistor. Under the signal control of the first light-emitting signal terminal EM1, the fifth transistor T5 writes the first power signal into the second node N2.

[0195] As shown in Figure 8, the light-emitting device L is electrically connected to the third node N3 and the second power supply terminal VSS.

[0196] Figure 9 shows the equivalent circuit diagram of the light-emitting control sub-circuit. As shown in Figure 9, in the exemplary embodiment, the light-emitting control sub-circuit is also electrically connected to the second light-emitting signal terminal EM2, the third node N3, and the fifth node N5. The light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5.

[0197] In an exemplary embodiment, the first power supply terminal VDD can receive a first power supply signal, and the fifth transistor T5 can be referred to as the first light-emitting transistor. Under the signal control of the first light-emitting signal terminal EM1, the fifth transistor T5 writes the first power supply signal into the second node N2. The sixth transistor T6 can be referred to as the second light-emitting transistor. Under the signal control of the second light-emitting signal terminal EM2, the sixth transistor T6 writes the drive signal output from the third node N3 into the fifth node N5.

[0198] As shown in Figure 9, the light-emitting device L is electrically connected to the fifth node N5 and the second power supply terminal VSS.

[0199] Figures 8 and 9 show two exemplary structures of the light-emitting control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the light-emitting control sub-circuit is not limited to these.

[0200] In an exemplary embodiment, the light-emitting control sub-circuit shown in FIG9 isolates the third node N3 from the light-emitting device L, thereby avoiding the influence of the parasitic capacitance of the light-emitting device on the signal of the third node N3.

[0201] Figure 10 is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment. As shown in Figure 10, in the exemplary embodiment, when the light-emitting device is electrically connected to the third node N3, the pixel driving circuit may further include a second initial sub-circuit. The second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and the third node N3, and is configured to provide the signal of the third input signal terminal IN3 to the third node N3 under the control of the signal of the fourth scan signal terminal Gate4.

[0202] Figure 11 is an equivalent circuit diagram of the second initial sub-circuit in Figure 10. As shown in Figure 11, the second initial sub-circuit may include: a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to the third node N3.

[0203] In an exemplary embodiment, the third input signal terminal IN3 can receive a third initial signal. The seventh transistor T7 can be referred to as the third initial transistor. Under the signal control of the fourth scan signal terminal Gate4, the seventh transistor T7 writes the third initial signal into the third node N3 to initialize the third node N3. Exemplarily, the seventh transistor T7 can be turned on once in a display frame, or it can be turned on multiple times, to initialize the anode of the light-emitting device, or to bias the third transistor T3.

[0204] Figure 12 is a schematic diagram of a pixel driving circuit provided in another exemplary embodiment. As shown in Figure 12, in the exemplary embodiment, when the light-emitting device is electrically connected to the fifth node N5, the pixel driving circuit may further include a second initial sub-circuit. The second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and one of the third node N3 and the fifth node N5, respectively, and is configured to provide the signal of the third input signal terminal IN3 to one of the third node N3 and the fifth node N5 under the control of the signal of the fourth scan signal terminal Gate4.

[0205] Figure 13 is an equivalent circuit diagram of the second initial sub-circuit in Figure 12 (Figure 11), and Figure 14 is an equivalent circuit diagram of the second initial sub-circuit in Figure 12 (Figure 14). As shown in Figures 13 and 14, in an exemplary embodiment, the second initial sub-circuit includes a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to one of the third node N3 and the fifth node N5. Figure 13 illustrates the circuit with the second terminal of the seventh transistor electrically connected to the third node N3, and Figure 14 illustrates the circuit with the second terminal of the seventh transistor electrically connected to the fifth node N5.

[0206] In an exemplary embodiment, the third input signal terminal IN3 can receive a third initial signal. The seventh transistor T7 can be referred to as the third initial transistor. Under the signal control of the fourth scan signal terminal Gate4, the seventh transistor T7 writes the third initial signal into the third node N3 or the fifth node N5, thus initializing the third node N3 or the fifth node N5. Exemplarily, the seventh transistor T7 can be turned on once in a display frame, or it can be turned on multiple times; this disclosure does not limit this. When the second terminal of the seventh transistor T7 is electrically connected to the third node N3, the conduction of the seventh transistor T7 can initialize the second terminal of the third transistor T3, or bias the third transistor T3. When the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5, the conduction of the seventh transistor T7 can initialize the anode of the light-emitting device.

[0207] Figures 11, 13 and 14 show an exemplary structure of the second initial sub-circuit, and it will be readily understood by those skilled in the art that the implementation of the second initial sub-circuit is not limited thereto.

[0208] Figure 15 is a schematic diagram of a pixel driving circuit provided in another exemplary embodiment. As shown in Figure 15, in the exemplary embodiment, the pixel driving circuit may further include a third initial sub-circuit. The third initial sub-circuit is electrically connected to the fifth scan signal terminal Gate5, the fourth input signal terminal IN4, and the second node N2, respectively, and is configured to provide the signal of the fourth input signal terminal IN4 to the second node N2 under the control of the signal from the fifth scan signal terminal Gate5.

[0209] Figure 16 is an equivalent circuit diagram of the third initial sub-circuit. As shown in Figure 16, in an exemplary embodiment, the third initial sub-circuit includes an eighth transistor T8. The control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2.

[0210] In an exemplary embodiment, the fourth input signal terminal IN4 can receive a fourth initial signal. The eighth transistor T8 can be referred to as the fourth initial transistor. Under the signal control of the fifth scan signal terminal Gate5, the eighth transistor T8 writes the fourth initial signal into the second node N2, thereby initializing or biasing the second node N2.

[0211] The second initial sub-circuit and the third initial sub-circuit in this disclosure can initialize the second node before the light-emitting device emits light, thereby ensuring the consistency of the light emission brightness in the display device.

[0212] Figure 16 shows an exemplary structure of the third initial sub-circuit. It will be readily understood by those skilled in the art that the implementation of the third initial sub-circuit is not limited to this.

[0213] In an exemplary embodiment, the signals received by the first input signal terminal IN1 and the first power supply terminal VDD connected to the same pixel driving circuit can be the same signal.

[0214] In an exemplary embodiment, the signals received by the first input signal terminal IN1 and the second input signal terminal IN2 connected to the same pixel driving circuit can be the same signal.

[0215] In an exemplary embodiment, the signals received by the second input signal terminal IN2 and the third input signal terminal IN3 connected to the same pixel driving circuit can be the same signal.

[0216] In an exemplary embodiment, the signals received by the second input signal terminal IN2 and the fourth input signal terminal IN4, which are connected to the same pixel driving circuit, can be the same signal.

[0217] In an exemplary embodiment, the voltage value of the third initial signal received by the third input signal terminal IN3 is less than the sum of the voltage value of the signal at the second power supply terminal and the voltage value between the two electrodes of the light-emitting device, so as to ensure that the light-emitting device does not emit light when the anode of the light-emitting device L is initialized.

[0218] In an exemplary embodiment, the first initial signal received by the first input signal terminal IN1 is a positive voltage signal to ensure that the third transistor T3 can be turned on normally, thereby improving the reliability of the pixel driving circuit.

[0219] In an exemplary embodiment, the voltage value of the first initial signal received by the first input signal terminal IN1 may be equal to the voltage value of the second initial signal received by the second input signal terminal IN2, the voltage value of the first initial signal received by the first input signal terminal IN1 may be greater than the voltage value of the third initial signal received by the third input signal terminal IN3, and the voltage value of the third initial signal received by the third input signal terminal IN3 may be greater than the voltage value of the fourth initial signal received by the fourth input signal terminal IN4.

[0220] In an exemplary embodiment, the signal received by the second scanning signal terminal Gate2 connected to the same pixel driving circuit and the signal received by the first light-emitting signal terminal EM1 are the same signal; or, the signal received by the second scanning signal terminal Gate2 connected to the i-th row pixel driving circuit and the first scanning signal terminal Gate1 of the (i-1)-th row pixel driving circuit are the same signal.

[0221] In an exemplary embodiment, when the pixel driving circuit is electrically connected to the fourth scanning signal terminal and the fifth scanning signal terminal respectively, the signals received by the fourth scanning signal terminal Gate4 and the fifth scanning signal terminal Gate5 connected to the same pixel driving circuit are the same signals.

[0222] In an exemplary embodiment, the signals received by the third scanning signal terminal Gate3 connected to the pixel driving circuit of the i-th row and the fourth scanning signal terminal Gate4 of the pixel driving circuit of the (i+K)-th row are the same signal, where K is a positive integer greater than 1.

[0223] In an exemplary embodiment, having at least two signal terminals connected to the pixel driving circuit receive the same signal can reduce the number of signal lines connected to the pixel driving circuit, thereby achieving a high PPI for the display device.

[0224] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0225] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor. The active pattern of the oxide thin-film transistor uses oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current, which can reduce power consumption and improve display quality.

[0226] In an exemplary embodiment, any one of the first capacitors C1 to the second capacitor C2 can be a capacitor device manufactured through a process, for example, by fabricating dedicated capacitor electrodes. Multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, any one of the first capacitors C1 to the second capacitor C2 can be a parasitic capacitance between multiple devices, implemented using the transistor itself and other devices or circuits. The connection method of any one of the first capacitors C1 to the second capacitor C2 includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as the level of the corresponding node is stored. Here, the exemplary embodiments of this disclosure do not limit this.

[0227] Figure 17 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 17, the pixel driving circuit includes: a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. The first initial sub-circuit includes: a first transistor T1; the holding sub-circuit includes: a first capacitor C1; the coupling sub-circuit includes: a second transistor T2 and a second capacitor C2; the driving sub-circuit includes: a third transistor T3; and the light emission control sub-circuit includes: a fifth transistor T5. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time, and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Or... The first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0228] In an exemplary embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 in FIG17 is an N-type transistor. Exemplarily, the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are all N-type transistors, or the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0229] Figure 18 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 18, the pixel driving circuit includes: a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of a second initial sub-circuit and a third initial sub-circuit. Figure 18 illustrates the pixel driving circuit with the second initial sub-circuit and the third initial sub-circuit as an example. Specifically, the first initial sub-circuit includes a first transistor T1, the holding sub-circuit includes a first capacitor C1, the coupling sub-circuit includes a second transistor T2 and a second capacitor C2, the driving sub-circuit includes a third transistor T3, the light emission control sub-circuit includes a fifth transistor T5, the second initial sub-circuit includes a seventh transistor T7, and the third initial sub-circuit includes an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, and the first electrode of the third transistor T3 is electrically connected to the second node N2. The second terminal of transistor T3 is electrically connected to the third node N3; the control terminal of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to the third node N3; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0230] In an exemplary embodiment, at least one of the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, seventh transistor T7, and eighth transistor T8 in FIG18 is an N-type transistor. Exemplarily, the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, seventh transistor T7, and eighth transistor T8 are all N-type transistors, or the first transistor T1, second transistor T2, third transistor T3, seventh transistor T7, and eighth transistor T8 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0231] In Figure 18, the seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. The operation of the first transistor T1, second transistor T2, third transistor T3, and fifth transistor T5 in Figure 18 is the same as that in Figure 17. This disclosure only provides the operation process of the pixel driving circuit shown in Figure 18; the operation process of the pixel driving circuit shown in Figure 17 will not be described again here.

[0232] Figure 19 is a timing diagram of the pixel driving circuit provided in Figure 18. Figure 19 is illustrated using the example of N-type transistors in Figure 18. As shown in Figure 19, the operation of the pixel driving circuit provided in Figure 18 may include:

[0233] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signal at the first light-emitting signal terminal (EM1) is low-level. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal (IN2). The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fifth transistor T5 is turned off.

[0234] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where VIN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0235] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the seventh transistor T7 and the eighth transistor T8 are turned off.

[0236] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0237] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0238] In the third stage, S3, the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0239] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0240] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data(C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0241] In the fourth stage (S4), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0242] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0243] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0244] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0245] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0246] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0247] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0248] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0249] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0250] Figure 20 is a second driving timing diagram of the pixel driving circuit provided in Figure 18. Figure 20 is illustrated using the example of all transistors in Figure 18 being N-type transistors. As shown in Figure 20, the operation of the pixel driving circuit provided in Figure 18 may include:

[0251] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light emission signal terminal (EM1) and the fifth scan signal terminal (Gate5) are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal (IN2). The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5 and the eighth transistor T8 are turned off.

[0252] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0253] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the seventh transistor T7 and the eighth transistor T8 are turned off.

[0254] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0255] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V dataWhen the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0256] In the third stage, S3, the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0257] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0258] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0259] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is high, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), and the fourth scan signal terminal (Gate4) are low. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal (IN2) and the data signal terminal (Data). The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned off.

[0260] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0261] In the fifth stage (S5), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0262] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0263] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0264] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0265] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0266] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0267] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2).

[0268] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0269] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0270] The difference between the pixel driving circuit shown in Figure 20 and the pixel driving circuit shown in Figure 19 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0271] Figure 21 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 21, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. Specifically, the first initial sub-circuit includes a first transistor T1; the holding sub-circuit includes a first capacitor C1; the coupling sub-circuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving sub-circuit includes a third transistor T3; and the light emission control sub-circuit includes a fifth transistor T5. Wherein, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, and the second control electrode of the third transistor T3 is electrically connected to the third node N3. The first terminal of transistor T3 is electrically connected to the second node N2, and the second terminal of transistor T3 is electrically connected to the third node N3; the control terminal of transistor T4 is electrically connected to the third scan signal terminal Gate3, the first terminal of transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of transistor T4 is electrically connected to the fourth node N4; the control terminal of transistor T5 is electrically connected to the first light emission signal terminal EM1, the first terminal of transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of transistor T5 is electrically connected to the second node N2; the first terminal of capacitor C1 is electrically connected to the first node N1, and the second terminal of capacitor C1 is electrically connected to the third node N3; the first terminal of capacitor C2 is electrically connected to the fourth node N4, and the second terminal of capacitor C2 is electrically connected to the third node N3.

[0272] In an exemplary embodiment, at least one of the first transistors T1 to the fifth transistor T5 in FIG21 is an N-type transistor. Exemplarily, all of the first transistors T1 to the fifth transistor T5 are N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0273] Figure 22 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 22, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of a second initial sub-circuit and a third initial sub-circuit. Figure 22 illustrates the pixel driving circuit with the second initial sub-circuit and the third initial sub-circuit as an example. Specifically, the first initial sub-circuit includes: a first transistor T1; the holding sub-circuit includes: a first capacitor C1; the coupling sub-circuit includes: a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving sub-circuit includes: a third transistor T3; the light emission control sub-circuit includes: a fifth transistor T5; the second initial sub-circuit includes: a seventh transistor T7; and the third initial sub-circuit includes: an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3. The first terminal of transistor T4 is electrically connected to the data signal terminal Data; the second terminal of transistor T4 is electrically connected to the fourth node N4; the control terminal of transistor T5 is electrically connected to the first light-emitting signal terminal EM1; the first terminal of transistor T5 is electrically connected to the first power supply terminal VDD; the second terminal of transistor T5 is electrically connected to the second node N2; the control terminal of transistor T7 is electrically connected to the fourth scan signal terminal Gate4; the first terminal of transistor T7 is electrically connected to the third input signal terminal IN3; the second terminal of transistor T7 is electrically connected to the third node N3; the control terminal of transistor T8 is electrically connected to the fifth scan signal terminal Gate5; the first terminal of transistor T8 is electrically connected to the fourth input signal terminal IN4; the second terminal of transistor T8 is electrically connected to the second node N2; the first terminal of capacitor C1 is electrically connected to the first node N1; the second terminal of capacitor C1 is electrically connected to the third node N3; the first terminal of capacitor C2 is electrically connected to the fourth node N4; the second terminal of capacitor C2 is electrically connected to the third node N3.

[0274] In an exemplary embodiment, at least one of the first transistors T1 to T5, the seventh transistor T7, and the eighth transistor T8 in FIG22 is an N-type transistor. Exemplarily, the first transistors T1 to T5, the seventh transistor T7, and the eighth transistor T8 are all N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0275] In Figure 22, the seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. The operation of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5 in Figure 22 is the same as that in Figure 21. This disclosure only provides the operation process of the pixel driving circuit shown in Figure 22; the operation process of the pixel driving circuit shown in Figure 21 will not be described again here.

[0276] Figure 23 is a timing diagram of the pixel driving circuit provided in Figure 22. Figure 23 is illustrated using the example of N-type transistors in Figure 22. Figure 23 is illustrated using the example that the second scan signal terminal connected to the pixel driving circuit in row i and the first scan signal terminal connected to the pixel driving circuit in row (i-1) receive the same signal, and that the fifth scan signal terminal (Gate5) and the fourth scan signal terminal (Gate4) receive the same signal. As shown in Figure 23, the operation of the pixel driving circuit provided in Figure 22 can include:

[0277] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first light emission signal terminal EM1 and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fifth transistor T5 is turned off.

[0278] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0279] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0280] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0281] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0282] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = VIN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0283] In the fourth stage (S4), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0284] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0285] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0286] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(VIN2 -V data (C2 / C1+C2)] 2

[0287] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0288] Figure 24 is the second driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 24 is illustrated using the example that all transistors in Figure 22 are N-type transistors. Figure 24 is illustrated using the example that the second scan signal terminal connected to the pixel driving circuit in the i-th row and the first scan signal terminal connected to the pixel driving circuit in the (i-1)-th row receive the same signal, and the time when the fifth scan signal terminal Gate5 receives the valid level signal is later than the time when the fourth scan signal terminal Gate4 receives the valid level signal. As shown in Figure 24, the operation process of the pixel driving circuit provided in Figure 22 may include:

[0289] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light emission signal terminal EM1, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5 is turned off.

[0290] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0291] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0292] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0293] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0294] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2(C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0295] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fifth transistor (T5), and the seventh transistor (T7) are turned off.

[0296] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0297] In the fifth stage (S5), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0298] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0299] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0300] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0301] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0302] The difference between the pixel driving circuit shown in Figure 24 and the pixel driving circuit shown in Figure 23 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0303] Figure 25 is the third driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 25 is illustrated using the example that all transistors in Figure 22 are N-type transistors. Figure 25 is illustrated using the example that the second scan signal terminal and the first light emission signal terminal connected in the same pixel driving circuit receive the same signal, and the fifth scan signal terminal Gate5 and the fourth scan signal terminal Gate4 receive the same signal. As shown in Figure 25, the operation process of the pixel driving circuit provided in Figure 22 may include:

[0304] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0305] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0306] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0307] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0308] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0309] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0310] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second scanning signal terminal Gate2 are high-level signals, while the signals at the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The second transistor T2 and the fifth transistor T5 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0311] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0312] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0313] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -Vdata (C2 / C1+C2)] 2

[0314] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0315] Figure 26 is the fourth driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 26 is illustrated using the example of all transistors in Figure 22 being N-type transistors. Figure 26 is illustrated using the example of the second scan signal terminal and the first light emission signal terminal connected in the same pixel driving circuit receiving the same signal, and the fifth scan signal terminal Gate5 receiving the valid level signal later than the fourth scan signal terminal Gate4 receiving the valid level signal. As shown in Figure 26, the operation process of the pixel driving circuit provided in Figure 22 may include:

[0316] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1 and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0317] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0318] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0319] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0320] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0321] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0322] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fifth transistor (T5), and the seventh transistor (T7) are turned off.

[0323] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0324] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second scanning signal terminal Gate2 are high-level signals, while the signals at the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The second transistor T2 and the fifth transistor T5 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0325] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0326] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0327] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0328] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0329] The difference between the pixel driving circuit shown in Figure 26 and the pixel driving circuit shown in Figure 25 is that the initialization of the second node N2 occurs during the biasing stage after the data writing stage and before the light emission stage, in order to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0330] Figure 27 is the fifth driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 27 is illustrated using the example that all transistors in Figure 22 are N-type transistors. Figure 27 is illustrated using the example that the fifth scan signal terminal Gate5 and the fourth scan signal terminal Gate4 receive the same signal. As shown in Figure 27, the operation process of the pixel driving circuit provided in Figure 22 may include:

[0331] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0332] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where VIN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0333] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light emission signal terminal EM1 are high-level signals, while the signals at the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0334] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0335] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0336] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(VIN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0337] In the fourth stage (S4), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0338] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0339] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2).

[0340] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0341] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0342] Figure 28 is the driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 28 is illustrated using the example of all transistors in Figure 22 being N-type transistors. Figure 28 is illustrated with the example of the fifth scan signal terminal Gate5 receiving the valid level signal later than the fourth scan signal terminal Gate4 receiving the valid level signal. As shown in Figure 28, the operation of the pixel driving circuit provided in Figure 22 may include:

[0343] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1 and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the seventh transistor T7 are turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned off.

[0344] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0345] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light emission signal terminal EM1 are high-level signals, while the signals at the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0346] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0347] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0348] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0349] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the seventh transistor (T7) are turned off.

[0350] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0351] In the fifth stage (S5), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0352] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0353] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2).

[0354] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0355] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0356] The difference between the pixel driving circuit shown in Figure 28 and the pixel driving circuit shown in Figure 27 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0357] Figure 29 is the driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 29 is illustrated using the example of N-type transistors in Figure 22. The driving timing diagram provided in Figure 29 differs from that provided in Figure 23 only in the duration of the effective level signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2. However, the signals at the multiple signal terminals connected to the pixel driving circuit are the same at different stages. Therefore, the operation process of the pixel driving circuit provided in Figure 29 is exactly the same as that of the pixel driving circuit provided in Figure 23, and will not be described again here.

[0358] Figure 30 is a driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 30 is illustrated using the example of N-type transistors in Figure 22. The driving timing diagram provided in Figure 30 differs from that provided in Figure 24 only in the duration of the effective level signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2. However, the signals at the multiple signal terminals connected to the pixel driving circuit are the same at different stages. Therefore, the operation process of the pixel driving circuit provided in Figure 30 is exactly the same as that of the pixel driving circuit provided in Figure 24, and will not be described again here.

[0359] Figure 31 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 31, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. The first initial sub-circuit includes: a first transistor T1; the holding sub-circuit includes: a first capacitor C1; the coupling sub-circuit includes: a second transistor T2 and a second capacitor C2; the driving sub-circuit includes: a third transistor T3; and the light emission control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5. The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0360] In an exemplary embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 in FIG31 is an N-type transistor. Exemplarily, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are all N-type transistors, or the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0361] Figure 32 is an equivalent circuit diagram of a pixel driving circuit (Figure 6), and Figure 33 is an equivalent circuit diagram of a pixel driving circuit (Figure 7). As shown in Figures 32 and 33, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of a second initial sub-circuit and a third initial sub-circuit. Figures 32 and 33 are illustrated using the example of a pixel driving circuit including a second initial sub-circuit and a third initial sub-circuit. Specifically, the first initial sub-circuit includes a first transistor T1, the holding sub-circuit includes a first capacitor C1, the coupling sub-circuit includes a second transistor T2 and a second capacitor C2, the driving sub-circuit includes a third transistor T3, the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the second initial sub-circuit includes a seventh transistor T7, and the third initial sub-circuit includes an eighth transistor T8.Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1. The first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the control terminal of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5; the control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to one of the nodes N3 and N5; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3. Figure 32 illustrates the connection between the second terminal of the seventh transistor and the third node as an example, and Figure 33 illustrates the connection between the second terminal of the seventh transistor and the fifth node as an example.

[0362] In an exemplary embodiment, at least one of the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 in Figures 32 and 33 is an N-type transistor. Exemplarily, the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 are all N-type transistors, or the first transistor T1, second transistor T2, third transistor T3, seventh transistor T7, and eighth transistor T8 are N-type transistors, and the fifth transistor T5 and sixth transistor T6 are P-type transistors.

[0363] In Figures 32 and 33, the seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. The operation of the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, and sixth transistor T6 in Figures 27 and 28 is the same as that in Figure 26. This disclosure only provides the operation of the pixel driving circuit shown in Figures 27 and 28; the operation of the pixel driving circuit shown in Figure 26 will not be described again here.

[0364] Figure 34 is a timing diagram of the pixel driving circuit provided in Figures 32 and 33. Figure 34 is illustrated using the example of N-type transistors in all transistors in Figures 32 and 33. Figure 34 is also illustrated using the example of the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 receiving the same signal. As shown in Figure 34, the operation of the pixel driving circuit provided in Figures 32 and 33 may include:

[0365] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1) and the second light-emitting signal terminal (EM2) are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal (IN2). The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fifth transistor T5 and the sixth transistor T6 are turned off.

[0366] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0367] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5, and the second light-emitting signal terminal EM2 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0368] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0369] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0370] In the third stage, S3, the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0371] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0372] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0373] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0374] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0375] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0376] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -VIN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0377] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0378] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0379] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2).

[0380] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0381] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0382] Figure 35 is a second timing diagram of the pixel driving circuit provided in Figures 32 and 33. Figure 35 is illustrated using the example of N-type transistors in all transistors in Figures 32 and 33. Figure 35 is illustrated using the example of the effective level signal received at the fifth scan signal terminal Gate5 being received later than the effective level signal received at the fourth scan signal terminal Gate4. As shown in Figure 35, the operation of the pixel driving circuit provided in Figures 32 and 33 may include:

[0383] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off.

[0384] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0385] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5, and the second light-emitting signal terminal EM2 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0386] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0387] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0388] In the third stage, S3, the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0389] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0390] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0391] In the fourth stage, the bias stage, the signal at the fifth scan signal terminal Gate5 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, the first light emission signal terminal EM1, and the second light emission signal terminal EM2 are low-level signals. The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0392] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0393] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0394] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0395] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0396] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0397] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0398] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0399] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2).

[0400] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0401] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0402] Figure 36 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 36, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. The first initial sub-circuit includes a first transistor T1; the holding sub-circuit includes a first capacitor C1; the coupling sub-circuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving sub-circuit includes a third transistor T3; and the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N4. Node N3 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0403] In an exemplary embodiment, at least one of the first transistors T1 to the sixth transistor T6 in FIG36 is an N-type transistor. Exemplarily, all of the first transistors T1 to the sixth transistor T6 are N-type transistors, or the first transistor T1 and the first transistors T1 to the fourth transistor T4 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0404] Figure 37 is an equivalent circuit diagram of a pixel driving circuit (Figure 9), Figure 38 is an equivalent circuit diagram of a pixel driving circuit (Figure 10), Figure 39 is an equivalent circuit diagram of a pixel driving circuit (Figure 11), and Figure 40 is an equivalent circuit diagram of a pixel driving circuit (Figure 12). As shown in Figures 37 to 40, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of a second initial sub-circuit and a third initial sub-circuit. Figures 37 and 38 are illustrated using the example of a pixel driving circuit including a second initial sub-circuit. Figures 39 and 40 are illustrated using the example of a pixel driving circuit including both a second and a third initial sub-circuit. The first initial sub-circuit includes a first transistor T1, the holding sub-circuit includes a first capacitor C1, the coupling sub-circuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2, the driving sub-circuit includes a third transistor T3, the light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the second initial sub-circuit includes a seventh transistor T7, and the third initial sub-circuit includes an eighth transistor T8.Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4. Connections: The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, and the first electrode of the seventh transistor T7 is electrically connected to the third input signal terminal IN. 3. Electrical connections: The second terminal of the seventh transistor T7 is electrically connected to either the third node N3 or the fifth node N5; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3. Figures 37 and 39 illustrate the connection of the second terminal of the seventh transistor T7 to the third node N3 as an example, while Figures 38 and 40 illustrate the connection of the second terminal of the seventh transistor T7 to the fifth node N5 as an example.

[0405] In an exemplary embodiment, at least one of the first transistors T1 to the eighth transistor T8 in Figures 39 and 40 is an N-type transistor. Exemplarily, all of the first transistors T1 to the eighth transistor T8 are N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0406] In Figures 37 to 40, the seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. The operation of the first transistors T1 to the sixth transistor T6 in Figures 37 to 40 is the same as that in Figure 36. Compared to Figure 37, Figure 39 only adds the eighth transistor T8. The operation of the first transistors T1 to the seventh transistor T7 in Figure 39 is the same as that in Figure 37. Compared to Figure 38, Figure 40 only adds the eighth transistor T8. The operation of the first transistors T1 to the seventh transistor T7 in Figure 40 is the same as that in Figure 38.

[0407] This disclosure only provides the operation process of the pixel driving circuits shown in Figures 39 and 40; the operation process of the pixel driving circuits shown in Figures 36, 37 and 39 will not be described in detail here.

[0408] Figure 41 is a timing diagram of the pixel driving circuits provided in Figures 39 and 40. Figure 41 is illustrated using the example of N-type transistors in Figures 39 and 40. Figure 41 is illustrated using the example of the second scan signal terminal connected to the pixel driving circuit in the i-th row receiving the same signal as the first scan signal terminal connected to the pixel driving circuit in the (i-1)-th row, and the fourth scan signal terminal (Gate4) and the fifth scan signal terminal (Gate5) receiving the same signal. As shown in Figure 41, the operation of the pixel driving circuits provided in Figures 39 and 40 can include:

[0409] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), and the third scan signal terminal (Gate3) are low-level signals. The first transistor (T1), the second transistor (T2), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the fifth transistor (T5) and the sixth transistor (T6) are turned off.

[0410] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0411] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0412] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0413] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0414] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0415] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0416] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0417] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = VIN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0418] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0419] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0420] Figure 42 is a second driving timing diagram of the pixel driving circuits provided in Figures 39 and 40. Figure 42 is illustrated using the example of N-type transistors in all transistors in Figures 39 and 40. Figure 42 illustrates the case where the second scan signal terminal connected to the pixel driving circuit in the i-th row receives the same signal as the first scan signal terminal connected to the pixel driving circuit in the (i-1)-th row, and the effective level signal received by the fifth scan signal terminal Gate5 is received later than the effective level signal received by the fourth scan signal terminal Gate4. As shown in Figure 42, the operation of the pixel driving circuits provided in Figures 39 and 40 may include:

[0421] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the third scan signal terminal (Gate3), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1), the second transistor (T2), and the seventh transistor (T7) are turned on, while the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned off.

[0422] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0423] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0424] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0425] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0426] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0427] In the fourth stage, the bias stage, the signal at the fifth scan signal terminal Gate5 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, the first light emission signal terminal EM1, and the second light emission signal terminal EM2 are low-level signals. The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0428] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0429] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0430] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0431] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0432] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0433] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0434] The difference between the pixel driving circuit shown in Figure 42 and the pixel driving circuit shown in Figure 42 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0435] Figure 43 is the third driving timing diagram of the pixel driving circuit provided in Figures 39 and 40. Figure 43 is illustrated using the example of all transistors in Figures 39 and 40 being N-type transistors. Figure 43 is illustrated using the example of the second scan signal terminal and the first light emission signal terminal connected in the same pixel driving circuit receiving the same signal, and the fifth scan signal terminal Gate5 and the fourth scan signal terminal Gate4 receiving the same signal. As shown in Figure 43, the operation process of the pixel driving circuit provided in Figures 39 and 40 can include:

[0436] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), and the third scan signal terminal (Gate3) are low-level signals. The first transistor (T1), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0437] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0438] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0439] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0440] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0441] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0442] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0443] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0444] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0445] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0446] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0447] Figure 44 is the fourth driving timing diagram of the pixel driving circuit provided in Figures 39 and 40. Figure 44 is illustrated using the example that all transistors in Figures 39 and 40 are N-type transistors. Figure 44 is illustrated using the example that the second scan signal terminal and the first light emission signal terminal connected in the same pixel driving circuit receive the same signal, and the time when the fifth scan signal terminal Gate5 receives the valid level signal is later than the time when the fourth scan signal terminal Gate4 receives the valid level signal. As shown in Figure 44, the operation process of the pixel driving circuit provided in Figures 39 and 40 can include:

[0448] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1) and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the seventh transistor (T7) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned off.

[0449] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0450] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0451] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0452] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0453] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0454] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are turned off.

[0455] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0456] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0457] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0458] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0459] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0460] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0461] The difference between the pixel driving circuit shown in Figure 44 and the pixel driving circuit shown in Figure 43 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0462] Figure 45 is the driving timing diagram of the pixel driving circuit provided in Figures 39 and 40. Figure 45 is illustrated using the example that all transistors in Figures 39 and 40 are N-type transistors. Figure 45 is illustrated with the fifth scan signal terminal Gate5 and the fourth scan signal terminal Gate4 receiving the same signal. As shown in Figure 45, the operation of the pixel driving circuit provided in Figures 39 and 40 may include:

[0463] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), and the third scan signal terminal (Gate3) are low-level signals. The first transistor (T1), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0464] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0465] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0466] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0467] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the second light emission signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0468] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -Vdata (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0469] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0470] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0471] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2).

[0472] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0473] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0474] Figure 46 is a timing diagram of the pixel driving circuits provided in Figures 39 and 40. Figure 46 is illustrated using the example of N-type transistors in Figures 39 and 40. Figure 46 illustrates the process with the fifth scan signal terminal (Gate5) receiving the valid level signal later than the fourth scan signal terminal (Gate4). As shown in Figure 46, the operation of the pixel driving circuits provided in Figures 39 and 40 can include:

[0475] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1) and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the seventh transistor (T7) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned off.

[0476] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0477] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0478] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V dataWhen the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0479] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the second light emission signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0480] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0481] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are turned off.

[0482] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = VIN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0483] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0484] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0485] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0486] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0487] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0488] The difference between the pixel driving circuit shown in Figure 46 and the pixel driving circuit shown in Figure 45 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0489] Figure 47 is the driving timing diagram of the pixel driving circuit provided in Figures 39 and 40. Figure 47 is illustrated using the example of all transistors in Figures 39 and 40 being N-type transistors. Figure 47 is illustrated using the example of the fifth scan signal terminal Gate5 and the fourth scan signal terminal Gate4 receiving the same signal. The driving timing diagram provided in Figure 47 differs from the driving timing diagram provided in Figure 41 in that the duration of the valid level signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 is different; the duration of the valid level signal at the second scan signal terminal Gate2 is longer than the duration of the valid level signal at the first scan signal terminal Gate1.

[0490] As shown in Figure 47, the operation of the pixel driving circuits provided in Figures 39 and 40 may include:

[0491] In the first stage (S1), the initialization stage, the signals of the second light-emitting signal terminal EM2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals of the first light-emitting signal terminal EM1 and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fourth transistor T4 and the fifth transistor T5 are turned off.

[0492] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN4 , where V IN2 This is the voltage value of the signal at the fourth input signal terminal IN4. The sixth transistor T6 is turned on, and the signals at the fifth node N5 and the third node N3 are connected.

[0493] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0494] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0495] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0496] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0497] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0498] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0499] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0500] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth)2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0501] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0502] Figure 48 is the driving timing diagram for the pixel driving circuits provided in Figures 39 and 40. Figure 48 is illustrated using the example of N-type transistors in Figures 39 and 40. Figure 48 is illustrated using the example of the fifth scan signal terminal, Gate 5, receiving an effective level signal later than the fourth scan signal terminal, Gate 4. The driving timing diagram provided in Figure 48 differs from that provided in Figure 42 in that the duration of the effective level signals at the first scan signal terminal, Gate 1, and the second scan signal terminal, Gate 2, is different; the duration of the effective level signal at the second scan signal terminal, Gate 2, is longer than the duration of the effective level signal at the first scan signal terminal, Gate 1.

[0503] As shown in Figure 48, the operation of the pixel driving circuits provided in Figures 39 and 40 may include:

[0504] In the first stage (S1), the initialization stage, the signals of the second light-emitting signal terminal EM2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals of the first light-emitting signal terminal EM1, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on, while the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned off.

[0505] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where VIN3 This is the voltage value of the signal at the third input signal terminal IN3. The sixth transistor T6 is turned on, connecting the signals at the fifth node N5 and the third node N3.

[0506] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0507] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0508] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0509] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V dataUnder the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0510] In the fourth stage, the bias stage, the signal at the fifth scan signal terminal Gate5 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, the first light emission signal terminal EM1, and the second light emission signal terminal EM2 are low-level signals. The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0511] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0512] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0513] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0514] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(Vdata -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2).

[0515] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0516] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0517] The difference between the pixel driving circuit shown in Figure 48 and the pixel driving circuit shown in Figure 47 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0518] In the exemplary embodiment, the control electrode (i.e., the first node) of the third transistor (driving transistor) in the pixel driving circuit provided in Figures 17, 18, 21, 22, 31, 32, 33, 36 to 40 is only electrically connected to the first transistor T1. That is, during the light-emitting stage, the capacitance value of the parasitic capacitance coupled to the control electrode of the third transistor is small, so that the parasitic capacitance of the first transistor has little impact on the signal of the first node N1. This makes it less likely for the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit to deviate, ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0519] In the exemplary embodiment, the control electrode (i.e., the first node) of the third transistor (driving transistor) in the pixel driving circuit provided in Figures 17, 18, 21, 22, 31, 32, 33, 36 to 40 is only electrically connected to the first transistor T1. That is, during the light-emitting stage, the capacitance value of the parasitic capacitance coupled to the control electrode of the third transistor is small, so that the parasitic capacitance of the first transistor has little impact on the signal of the first node N1. This makes it less likely for the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit to deviate, ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0520] In an exemplary embodiment, all transistors in the pixel driving circuit can be N-type transistors; or some transistors can be N-type transistors and some transistors can be P-type transistors. N-type transistors can be made of semiconductor oxide materials, while P-type transistors can be made of low-temperature polycrystalline silicon. P-type transistors have a higher MOB (Mean Optical Bound) and Ion (Ion) than N-type transistors, allowing for rapid switching on and off in scenarios with high light emission and anode reset frequencies. For example, the fifth transistor T5 can be a P-type transistor, meaning it is off when the signal at the first light emission signal terminal EM1 is high and on when the signal is low. Alternatively, the fifth and sixth transistors can be P-type transistors, or the fifth, sixth, and seventh transistors can be P-type transistors, which is beneficial for high-frequency refresh and suitable for PWM dimming scenarios. Alternatively, the fourth transistor can be a P-type transistor, which can improve data writing speed. In this case, the second scan signal terminal Gate2 and the third scan signal terminal Gate3 can receive the same signal.

[0521] In the exemplary embodiment, in the pixel driving circuits provided in Figures 17, 18, 21, and 22, before and after the signal of the fourth node N4 undergoes a transition, the variables related to the fourth node N4 satisfy the charge conservation equation of the third node N3.

[0522] [V3-(V IN1 -Vth)]*(C1+C OLED )+{(V3-Vdata)-[(V IN1 -Vth)-V IN2 ]}*C2=0, where C OLED Let V be the parasitic capacitance of the light-emitting device L. V3 = [C2 / (C1+C2+C...] OLED )]*(V IN2 -Vdata)+V IN1 -Vth

[0523] Since the signal of the first node N1 before the light-emitting stage is the signal of the first input signal terminal IN1, that is, V1 = V IN1 Therefore, Vgs = V1 - V3 = [C2 / (C1 + C2 + C OLED )]*(V IN2 -Vdata)+Vth

[0524] In an exemplary embodiment, in the pixel driving circuits provided in Figures 31, 32, 33, 36 to 40, before and after the signal of the fourth node N4 undergoes a transition, the variables related to the fourth node N4 satisfy the charge conservation equation of the third node N3 [V3-(V IN1 -Vth)]*C1+{(V3-Vdata)-[(V IN1 -Vth)-V IN2]}*C2=0 V3=[C2 / (C1+C2)]*(V IN2 -Vdata)+V IN1 -Vth

[0525] Since the signal of the first node N1 before the light-emitting stage is the signal of the first input signal terminal IN1, that is, V1 = V IN1 Therefore, Vgs = V1 - V3 = [C2 / (C1 + C2)] * (V IN2 -Vdata)+Vth

[0526] Regarding the driving timing mentioned above, for embodiments including transistor T7: S1-S4 can be a refresh period. At the first driving frequency, a display frame can include one refresh period. The first driving frequency can be a frequency in high-frequency driving mode. At the second driving frequency, a display frame can include one refresh period and at least one hold period. The hold period can be defined as a self-scanning period where no data signal is written, the data signal written in the refresh period is held, and the pixel emits light. The second driving frequency can be a frequency in low-frequency driving mode. The hold period can include a first hold period and a second hold period. In the first hold period, only the seventh transistor T7 is turned on, and all other transistors are turned off to reset the anode of the light-emitting device, i.e., the signal at the fourth scan signal terminal Gate4 is an effective level signal. The seventh transistor T7 can be turned on multiple times, and the number of times is not limited. In the second hold period, the seventh transistor T7 is turned off, and the fifth transistor T5 and the sixth transistor T6 are turned on, and the light-emitting device L emits light.

[0527] When the embodiment further includes an eighth transistor T8, the eighth transistor T8 may also be turned on during the first holding phase, writing the fourth initial signal into the second node N2 to bias the driving transistor; the turn-on time of the eighth transistor T8 may occur after the turn-on time of the seventh transistor T7, or it may be at the same time as the turn-on time of the seventh transistor T7. This disclosure does not limit this. The eighth transistor T8 may be turned on multiple times, and the number of times is not limited.

[0528] This disclosure also provides a method for driving a pixel driving circuit, configured to drive the pixel driving circuit provided in any of the foregoing embodiments. The method for driving the pixel driving circuit may include:

[0529] Step 100: Under the control of the signal from the first node, the driving sub-circuit provides a driving signal to the third node;

[0530] Step 200: Under the control of the signal at the first scanning signal terminal, the first initial sub-circuit provides the signal at the first input signal terminal to the first node;

[0531] Step 300: Under the control of the signal at at least one scanning signal terminal, the coupling sub-circuit couples the signal at the data signal terminal or the second input signal terminal to the third node;

[0532] Step 400: Maintain the voltage difference between the signals of the first node and the third node stored in the sub-circuit;

[0533] Step 500: Under the control of the signal at the first light-emitting signal terminal, the light-emitting control sub-circuit provides the signal at the first power supply terminal to the second node.

[0534] The third node in the aforementioned pixel driving circuit is easily affected by the signals from the data signal terminal or the second input signal terminal, making the signal of the third node unstable and reducing the reliability of the pixel driving circuit.

[0535] Figure 49 illustrates a pixel driving circuit according to another embodiment of this disclosure. As shown in Figure 49, the pixel driving circuit according to another embodiment of this disclosure may include: a driving sub-circuit, a coupling sub-circuit, a holding sub-circuit, a first initial sub-circuit, and a light emission control sub-circuit.

[0536] As shown in Figure 49, the driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals from the first node N1 and the second node N2; the first initial sub-circuit is electrically connected to the first input signal terminal IN1, the first scan signal terminal Gate1, and the first node N1, respectively, and is configured to provide the signal from the first input signal terminal IN1 to the first node N1 under the control of the signal from the first scan signal terminal Gate1; the coupling sub-circuit is electrically connected to the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fifth scan signal terminal Gate5, the data signal terminal Data, the second input signal terminal IN2, and the third node N3, and is configured to provide a driving signal to the third node N3 under the control of the signals from the first node N1 and the second node N2; Under the control of the signals from Gate2, Gate3, and Gate5, the data signal from the Data terminal or the signal from the second input signal from the IN2 terminal is coupled to the third node N3. The holding sub-circuit, which is electrically connected to the first node N1 and the third node N3 respectively, is configured to store the voltage difference between the signals from the first node N1 and the third node N3. The light emission control sub-circuit, which is electrically connected to the first light emission signal terminal EM1, the second light emission signal terminal EM2, the first power supply terminal VDD, the second node N2, and the fifth node N5 respectively, is configured to provide the first power supply terminal VDD signal to the second node N2 and the third node N3 signal to the fifth node N5 under the control of the signals from the first light emission signal terminal EM1 and the second light emission signal terminal EM2.

[0537] In an exemplary embodiment, the time period during which the signal at the fifth scanning signal terminal Gate5 is at an effective level overlaps at least partially with the time period during which at least one of the second scanning signal terminals Gate2 and the third scanning signal terminal Gate3 is at an effective level.

[0538] The first power supply terminal VDD and the first input signal terminals IN1 to IN3 in the pixel driving circuit shown in Figure 49 can continuously provide DC signals, which are the same as the signal terminals in the pixel driving circuits shown in Figures 31 to 40. This disclosure will not repeat the limitation in this regard. The light-emitting device driven by the pixel driving circuit shown in Figure 49 and the connection method are the same as those driven by the pixel driving circuits shown in Figures 31 to 40. This disclosure will not describe them again here.

[0539] This disclosure, by setting a coupling sub-circuit, can avoid the influence of the signals from the data signal terminal and the second input signal terminal on the third node, thereby improving the stability of the signal of the third node and enhancing the reliability of the pixel driving circuit.

[0540] In an exemplary embodiment, the signal received by the second scan signal terminal Gate2 connected to the i-th row pixel driving circuit is the same signal as the signal received by the first scan signal terminal Gate1 connected to the iM-th row pixel driving circuit, where M is a positive integer greater than 1. The fact that the pixel driving circuit provided in this disclosure receives the same signal as the second scan signal terminal connected to the i-th row pixel driving circuit and the first scan signal terminal connected to the iM-th row pixel driving circuit can reduce the number of driving circuits in the scan driver connected to the pixel driving circuit, thereby achieving a narrow bezel on the display substrate where the pixel driving circuit is located.

[0541] In an exemplary embodiment, FIG50 is a schematic diagram of the structure of a coupling sub-circuit provided in an exemplary embodiment. As shown in FIG50, the coupling sub-circuit includes: a data writing sub-circuit, an initial writing sub-circuit, a connection sub-circuit, and a voltage regulating sub-circuit.

[0542] As shown in Figure 50, the data writing sub-circuit is electrically connected to the third scan signal terminal Gate3, the data signal terminal Data, and the fourth node N4, respectively, and is configured to provide the data signal terminal Data to the fourth node N4 under the control of the signal from the third scan signal terminal Gate3; the initial writing sub-circuit is electrically connected to the second scan signal terminal Gate2, the second input signal terminal IN2, and the fourth node N4, respectively, and is configured to provide the second input signal terminal IN2 to the fourth node N4 under the control of the signal from the second scan signal terminal Gate2; the voltage regulation sub-circuit is electrically connected to the third node N3 and the sixth node N6, respectively, and is configured to store the voltage difference between the signals from the third node N3 and the sixth node N6; the connection sub-circuit is electrically connected to the fifth scan signal terminal Gate5, the fourth node N4, and the sixth node N6, respectively, and is configured to provide the signal from the fourth node N4 to the sixth node N6 under the control of the signal from the fifth scan signal terminal Gate5.

[0543] In an exemplary embodiment, FIG51 is a schematic diagram of the structure of a coupling sub-circuit provided in another exemplary embodiment. As shown in FIG51, the coupling sub-circuit includes: a data writing sub-circuit, an initial writing sub-circuit, a connection sub-circuit, and a voltage regulator sub-circuit.

[0544] As shown in Figure 51, the data writing sub-circuit is electrically connected to the third scan signal terminal Gate3, the data signal terminal Data, and the fourth node N4, respectively, and is configured to provide the data signal terminal Data to the fourth node N4 under the control of the signal from the third scan signal terminal Gate3; the initial writing sub-circuit is electrically connected to the second scan signal terminal Gate2, the second input signal terminal IN2, and the fourth node N4, respectively, and is configured to provide the second input signal terminal IN2 to the fourth node N4 under the control of the signal from the second scan signal terminal Gate2; the voltage regulation sub-circuit is electrically connected to the fourth node N4 and the sixth node N6, respectively, and is configured to store the voltage difference between the signals from the fourth node N4 and the sixth node N6; the connection sub-circuit is electrically connected to the fifth scan signal terminal Gate5, the third node N3, and the sixth node N6, respectively, and is configured to provide the signal from the sixth node N6 to the third node N3 under the control of the signal from the fifth scan signal terminal Gate5.

[0545] The connecting sub-circuit in this disclosure serves to isolate the third node from the data writing sub-circuit and the initial writing sub-circuit, thereby preventing the data signal terminal Data and the second input signal terminal IN2 from affecting the third node N3.

[0546] In an exemplary embodiment, FIG52 is an equivalent circuit diagram of the coupling sub-circuit provided in FIG50, and FIG53 is an equivalent circuit diagram of the coupling sub-circuit provided in FIG51. As shown in FIG52 and FIG53, in the coupling circuits provided in FIG50 and FIG51, the data writing sub-circuit includes: a fourth transistor T4. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4.

[0547] In an exemplary embodiment, as shown in Figures 52 and 53, the initial write sub-circuit in the coupling circuits provided in Figures 50 and 51 includes a second transistor T2. The control terminal of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second terminal of the second transistor T2 is electrically connected to the fourth node N4.

[0548] As shown in Figure 52, in the coupling sub-circuit provided in Figure 50, the connecting sub-circuit may include: an eighth transistor T8. The control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4, and the second terminal of the eighth transistor T8 is electrically connected to the sixth node N6.

[0549] As shown in Figure 52, in the coupling sub-circuit provided in Figure 50, the voltage regulator sub-circuit includes a second capacitor C2. The first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the sixth node N6.

[0550] As shown in Figure 53, in the coupling sub-circuit provided in Figure 51, the connecting sub-circuit includes: an eighth transistor T8. The control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the third node N3, and the second terminal of the eighth transistor T8 is electrically connected to the sixth node N6.

[0551] As shown in Figure 53, in the coupling sub-circuit provided in Figure 51, the voltage regulator sub-circuit includes a second capacitor C2. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the sixth node N6.

[0552] The arrangement of the eighth transistor T8 in the coupling sub-circuit shown in Figure 53 can avoid the direct connection between the third node N3 and the second capacitor C2. When the light-emitting device emits light, it is not necessary to charge the second capacitor C2. This can effectively improve the impact of signal fluctuations of the third node on brightness in low grayscale display, and also improve the turn-on time of the light-emitting device in low grayscale display.

[0553] In an exemplary embodiment, FIG54 is another structural schematic diagram of the pixel driving circuit provided in FIG50. As shown in FIG54, the pixel driving circuit may further include a second initial sub-circuit. The second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and the fifth node N5, respectively, and is configured to provide the signal of the third input signal terminal IN3 to the fifth node N5 under the control of the signal of the fourth scan signal terminal Gate4.

[0554] In an exemplary embodiment, FIG55 is an equivalent circuit diagram of a portion of the sub-circuit of the pixel driving circuit. As shown in FIG55, the first initial sub-circuit includes: a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0555] In an exemplary embodiment, as shown in FIG55, the holding sub-circuit includes a first capacitor C1. The first terminal of the first capacitor C1 is electrically connected to a first node N1, and the second terminal of the first capacitor C1 is electrically connected to a third node N3.

[0556] In an exemplary embodiment, as shown in FIG55, the driving sub-circuit includes a third transistor T3, which includes a first control electrode and a second control electrode. The first control electrode of the third transistor T3 is electrically connected to a first node N1, the second control electrode of the third transistor T3 is electrically connected to a third node N3, the first electrode of the third transistor T3 is electrically connected to a second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0557] In an exemplary embodiment, as shown in FIG55, the light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5.

[0558] Figure 56 is an equivalent circuit diagram of the second initial sub-circuit of the pixel driving circuit. As shown in Figure 56, the second initial sub-circuit includes a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5.

[0559] In an exemplary embodiment, FIG57 is an equivalent circuit diagram one of the pixel driving circuit provided in FIG50, and FIG58 is an equivalent circuit diagram two of the pixel driving circuit provided in FIG50. As shown in FIG57 and FIG58, in the pixel driving circuit, the coupling sub-circuit includes: a second transistor T2, a fourth transistor T4, an eighth transistor T8, and a second capacitor C2; the holding sub-circuit includes: a first capacitor C1; the driving sub-circuit includes: a third transistor T3; the first initial sub-circuit includes: a first transistor T1; the second initial sub-circuit includes: a seventh transistor T7; the light emission control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6; and the third transistor T3 includes: a first control electrode and a second control electrode.

[0560] As shown in Figures 57 and 58, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; the control electrode of the fifth transistor T5 is connected to the first light emission signal terminal EM1. Electrical connections are established as follows: the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the control terminal of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5; the control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4, and the second terminal of the eighth transistor T8 is electrically connected to the sixth node N6; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the sixth node N6.

[0561] Figure 59 is the third equivalent circuit diagram of the pixel driving circuit provided in Figure 50, and Figure 60 is the fourth equivalent circuit diagram of the pixel driving circuit provided in Figure 50. As shown in Figures 59 and 60, in the pixel driving circuit, the coupling sub-circuit includes: the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the second capacitor C2; the holding sub-circuit includes: the first capacitor C1; the driving sub-circuit includes: the third transistor T3; the first initial sub-circuit includes: the first transistor T1; the second initial sub-circuit includes: the seventh transistor T7; the light emission control sub-circuit includes: the fifth transistor T5 and the sixth transistor T6; and the third transistor T3 includes: the first control electrode and the second control electrode.

[0562] As shown in Figures 59 and 60, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; the control electrode of the fifth transistor T5 is connected to the first light emission signal terminal EM1. Electrical connections are established as follows: the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the control terminal of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5; the control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the third node N3, and the second terminal of the eighth transistor T8 is electrically connected to the sixth node N6; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the sixth node N6.

[0563] In an exemplary embodiment, at least one of the first transistors T1 to the eighth transistor T8 is an N-type transistor; or, at least one of the first transistors T1 to the fourth transistor T4 and the sixth transistor T6 to the eighth transistor T8 is an N-type transistor, and the fifth transistor T5 is a P-type transistor. Figures 57 and 59 are illustrated with the example of at least one of the first transistors T1 to the eighth transistor T8 being an N-type transistor, and Figures 58 and 60 are illustrated with the example of at least one of the first transistors T1 to the fourth transistor T4 and the sixth transistor T6 to the eighth transistor T8 being an N-type transistor, and the fifth transistor T5 being a P-type transistor.

[0564] In an exemplary embodiment, the fifth transistor T5 is a P-type transistor, which can make the voltage value of the effective level signal of the first light-emitting signal terminal smaller, thereby making the voltage value of the signal of the high-level power supply terminal connected to the driving circuit that provides the signal to the first light-emitting signal terminal smaller, thus reducing power consumption.

[0565] In an exemplary embodiment, the signal received by the second input signal terminal IN2, which is connected to the same pixel driving circuit, is the same as the signal received by the first input signal terminal IN1.

[0566] In an exemplary embodiment, the display substrate is disposed in a display substrate, and the content displayed on the display substrate includes: a plurality of display frames, at least one display frame including: a refresh frame and at least one hold frame.

[0567] The display substrate includes a first driving mode and a second driving mode. The refresh rate of the first driving mode is lower than that of the second driving mode. For example, the refresh rate of the first driving mode can be 1Hz-60Hz, and the refresh rate of the second driving mode can be 60Hz-480Hz. In the first driving mode, the display frame includes a refresh frame and at least one hold frame. In the second driving mode, the display frame only includes a refresh frame.

[0568] During the refresh frame of at least one display frame, the signal of the fifth scan signal terminal Gate5 is an active level signal for a portion of the time period, and during the hold frame of at least one display frame, the signal of the fifth scan signal terminal Gate5 is an inactive level signal.

[0569] In an exemplary embodiment, in at least one holding frame of at least one display frame, the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are invalid level signals, the signal of the second light emission signal terminal EM2 is an effective level signal, the signal of the first light emission signal terminal EM1 is a high level signal for at least one time period, and the signal of the fourth scan signal terminal Gate4 is an effective level signal for a portion of the time period, and the time period during which the signal of the fourth scan signal terminal is an effective level signal at least partially overlaps with the time period during which the signal of the first light emission signal terminal EM1 is an effective level signal.

[0570] Figure 61 is a timing diagram of the pixel driving circuits provided in Figures 57 and 59 during a refresh frame. As shown in Figure 61, the operation of the pixel driving circuit provided in Figure 57 during a refresh frame may include:

[0571] In the first stage (S1), the initialization stage, the signals at the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first scan signal terminal (Gate1), the third scan signal terminal (Gate3), the first light-emitting signal terminal (EM1), and the second light-emitting signal terminal (EM2) are low-level signals. The second transistor (T2), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the first transistor (T1), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0572] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The voltage value of the signal at the second input signal terminal IN2 is given. The eighth transistor T8 is turned on, and the signal at the fourth node N4 is written to the sixth node N6. The voltage value of the signal at the sixth node N6 is V6 = V IN2 The seventh transistor T7 is turned on, and the signal at the third input signal terminal IN3 is written to the fifth node N5. The voltage value of the signal at the fifth node N5 is V5 = V IN3 .

[0573] In the second stage S2, the threshold compensation stage, the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5 and the first light emission signal terminal EM1 are high-level signals, the signal of the second light emission signal terminal EM2 is low-level signal, the first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are turned on, and the fourth transistor T4 and the sixth transistor T6 are turned off.

[0574] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is continuously written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2， The eighth transistor T8 is turned on, and the signal from the fourth node N4 is written to the sixth node N6. The voltage value of the signal at the sixth node N6 is V6 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth. The seventh transistor T7 is turned on, and the signal at the third input signal terminal IN3 is written to the fifth node N5. The voltage value of the signal at the fifth node N5 is V5 = V. IN3 .

[0575] In the third stage (S3), the data writing stage, the signals at the fourth scan signal terminal (Gate4) and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the first light-emitting signal terminal (EM1), and the second light-emitting signal terminal (EM2) are low-level signals. The signal at the third scan signal terminal (Gate3) is high-level for a portion of the time. The fourth transistor (T4), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the first transistor (T1), the second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0576] The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V6 of the signal at the sixth node N6 also changes abruptly, V6 = V IN1 -Vth+(V data -V IN2 (C1 / C1+C2), where C1 is the capacitance of the first capacitor C1, and C2 is the capacitance of the second capacitor C2. The eighth transistor T8 is turned on, and the signal from the sixth node N6 is written to the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN1 -Vth+(V data -VIN2 (C1 / C1+C2).

[0577] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0578] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0579] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the ...

Claims

1. A pixel driving circuit, comprising: The circuit includes a driving sub-circuit, a coupling sub-circuit, a holding sub-circuit, a first initialization sub-circuit, and a light-emitting control sub-circuit. The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node. The first initial sub-circuit is electrically connected to the first input signal terminal, the first scan signal terminal, and the first node, respectively, and is configured to provide the signal from the first input signal terminal to the first node under the control of the signal from the first scan signal terminal; The coupling sub-circuit is electrically connected to the second scan signal terminal, the third scan signal terminal, the fifth scan signal terminal, the data signal terminal, the second input signal terminal, and the third node, respectively, and is configured to couple the signal from the data signal terminal or the second input signal terminal to the third node under the control of the signals from the second scan signal terminal, the third scan signal terminal, and the fifth scan signal terminal; The holding sub-circuit, which is electrically connected to the first node and the third node respectively, is configured to store the voltage difference between the signals of the first node and the third node; The light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power supply terminal, the second node, and the fifth node, respectively. It is configured to provide the signal of the first power supply terminal to the second node and the signal of the third node to the fifth node under the control of the signals of the first light-emitting signal terminal and the second light-emitting signal terminal. The time period during which the signal at the fifth scanning signal terminal is at an effective level overlaps at least partially with the time period during which at least one of the second and third scanning signal terminals is at an effective level.

2. The pixel driving circuit according to claim 1, wherein, The signal received by the second scan signal terminal connected to the pixel driving circuit of row i is the same signal as the signal received by the first scan signal terminal connected to the pixel driving circuit of row iM, where M is a positive integer greater than 1.

3. The pixel driving circuit according to claim 1, wherein, The coupling sub-circuit includes: a data writing sub-circuit, an initial writing sub-circuit, a connection sub-circuit, and a voltage regulation sub-circuit; The data writing sub-circuit is electrically connected to the third scan signal terminal, the data signal terminal, and the fourth node, respectively, and is configured to provide the data signal terminal to the fourth node under the control of the signal from the third scan signal terminal. The initial write sub-circuit is electrically connected to the second scan signal terminal, the second input signal terminal, and the fourth node, respectively, and is configured to provide the signal from the second input signal terminal to the fourth node under the control of the signal from the second scan signal terminal. The voltage regulator circuit is electrically connected to the third node and the sixth node respectively, and is configured to store the voltage difference between the signals of the third node and the sixth node. The connecting sub-circuit is electrically connected to the fifth scanning signal terminal, the fourth node, and the sixth node, respectively, and is configured to provide the signal of the fourth node to the sixth node under the control of the signal of the fifth scanning signal terminal.

4. The pixel driving circuit according to claim 1, wherein, The coupling sub-circuit includes: a data writing sub-circuit, an initial writing sub-circuit, a connection sub-circuit, and a voltage regulation sub-circuit; The data writing sub-circuit is electrically connected to the third scan signal terminal, the data signal terminal, and the fourth node, respectively, and is configured to provide the data signal terminal to the fourth node under the control of the signal from the third scan signal terminal. The initial write sub-circuit is electrically connected to the second scan signal terminal, the second input signal terminal, and the fourth node, respectively, and is configured to provide the signal from the second input signal terminal to the fourth node under the control of the signal from the second scan signal terminal. The voltage regulator circuit is electrically connected to the fourth node and the sixth node respectively, and is configured to store the voltage difference between the signals of the fourth node and the sixth node. The connecting sub-circuit is electrically connected to the fifth scanning signal terminal, the third node, and the sixth node, respectively, and is configured to provide the signal of the sixth node to the third node under the control of the signal of the fifth scanning signal terminal.

5. The pixel driving circuit according to claim 3 or 4, wherein, The data writing sub-circuit includes a fourth transistor, and the initial writing sub-circuit includes a second transistor; The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the second input signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node. The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node.

6. The pixel driving circuit according to claim 3, wherein, The connecting sub-circuit includes: an eighth transistor; the voltage regulating sub-circuit includes: a second capacitor. The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the sixth node. The first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the sixth node.

7. The pixel driving circuit according to claim 4, wherein, The connecting sub-circuit includes: an eighth transistor; the voltage regulating sub-circuit includes: a second capacitor. The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the sixth node. The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the sixth node.

8. The pixel driving circuit according to claim 1, further comprising: Second initial sub-circuit; The second initial sub-circuit is electrically connected to the fourth scan signal terminal, the third input signal terminal, and the fifth node, respectively, and is configured to provide the signal from the third input signal terminal to the fifth node under the control of the signal from the fourth scan signal terminal.

9. The pixel driving circuit according to claim 1, wherein, The first initial sub-circuit includes: a first transistor; the holding sub-circuit includes: a first capacitor; the driving sub-circuit includes: a third transistor, the third transistor includes: a first control electrode and a second control electrode; the light emission control sub-circuit includes: a fifth transistor and a sixth transistor. The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node. The first control electrode of the third transistor is electrically connected to the first node, the second control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node.

10. The pixel driving circuit according to claim 8, wherein, The second initial sub-circuit includes: a seventh transistor; The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.

11. The pixel driving circuit according to claim 1, further comprising: The second initial sub-circuit includes a coupling sub-circuit comprising a second transistor, a fourth transistor, an eighth transistor, and a second capacitor; a holding sub-circuit comprising a first capacitor; and a driving sub-circuit comprising a third transistor. The first initial sub-circuit includes a first transistor; the second initial sub-circuit includes a seventh transistor; the light-emitting control sub-circuit includes a fifth transistor and a sixth transistor; and the third transistor includes a first control electrode and a second control electrode. The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the second input signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node. The first control electrode of the third transistor is electrically connected to the first node, the second control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node. The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node. The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the sixth node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node. The first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the sixth node.

12. The pixel driving circuit according to claim 1, further comprising: The second initial sub-circuit includes a coupling sub-circuit comprising a second transistor, a fourth transistor, an eighth transistor, and a second capacitor; a holding sub-circuit comprising a first capacitor; and a driving sub-circuit comprising a third transistor. The first initial sub-circuit includes a first transistor; the second initial sub-circuit includes a seventh transistor; the light-emitting control sub-circuit includes a fifth transistor and a sixth transistor; and the third transistor includes a first control electrode and a second control electrode. The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the second input signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node. The first control electrode of the third transistor is electrically connected to the first node, the second control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node. The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node. The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the sixth node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node. The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the sixth node.

13. The pixel driving circuit according to claim 11 or 12, wherein, At least one of the first to the eighth transistors is an N-type transistor, or at least one of the first to the fourth transistors and the sixth to the eighth transistors is an N-type transistor, and the fifth transistor is a P-type transistor.

14. The pixel driving circuit according to claim 1, wherein, The signal received by the second input signal terminal connected to the same pixel driving circuit is the same as the signal received by the first input signal terminal.

15. The pixel driving circuit according to claim 1, wherein, The display substrate is disposed in the display substrate, and the content displayed by the display substrate includes: multiple display frames, at least one display frame including: a refresh frame and at least one hold frame; In at least one refresh frame of a display frame, the signal at the fifth scan signal terminal is an active level signal for a portion of the time period, and in at least one hold frame of a display frame, the signal at the fifth scan signal terminal is an inactive level signal.

16. A display device, comprising: A display area and a non-display area disposed on at least one side of the display area, wherein the pixel driving circuits as described in any one of claims 1 to 15 are arranged in the display area; The non-display area is provided with a driving circuit group, which includes: a first driving circuit, and the first driving circuit includes: a plurality of cascaded first shift registers; The second scan signal terminal connected to at least one row of pixel driving circuits is connected to the same first shift register as the first scan signal terminal connected to the first M rows of pixel driving circuits.

17. The display device according to claim 16, wherein, At least two pixel driving circuits in the same row are connected to different signal lines at their fifth scan signal terminals.

18. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as claimed in any one of claims 1 to 15, the method comprising: The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes; The first initial sub-circuit provides the first input signal terminal signal to the first node under the control of the signal at the first scanning signal terminal; Under the control of the signals from the second scan signal terminal, the third scan signal terminal, and the fifth scan signal terminal, the coupler circuit couples the signal from the data signal terminal or the second input signal terminal to the third node; Maintain the voltage difference between the signals stored in the first and third nodes in the sub-circuit; Under the control of the signals from the first and second light-emitting signal terminals, the light-emitting control sub-circuit provides the first power supply signal to the second node and the third node signal to the fifth node.

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