Quantum architecture search method and device based on noise perception evaluation
By introducing noise-aware evaluation and systematic optimization rules into quantum architecture search, the performance degradation of existing methods in noisy environments is solved, enabling efficient deployment and optimization of quantum circuits on NISQ devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTHEAST UNIV
- Filing Date
- 2025-12-03
- Publication Date
- 2026-05-08
AI Technical Summary
Existing quantum architecture search methods ignore noise factors on real hardware when evaluating candidate circuits, resulting in excellent performance in ideal environments but significant performance degradation on real noisy hardware. Furthermore, the searched circuits contain redundant quantum gates, lack systematic optimization, and are difficult to deploy efficiently on resource-constrained NISQ devices.
By introducing dual evaluation metrics of expressive power and noise resistance, a multi-objective loss function is constructed to evaluate candidate quantum circuits in a noisy environment. The circuits are then iteratively optimized through optimization rules such as gate switching, fusion, and elimination to reduce complexity and redundancy.
It improves the robustness and operational efficiency of quantum circuits on real hardware, significantly reduces the number and depth of circuit gates, and improves the deployment success rate and operational efficiency on NISQ devices.
Smart Images
Figure CN121998117A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to quantum technology, and more particularly to a method and apparatus for searching quantum architectures based on noise-sensing evaluation. Background Technology
[0002] In the era of noisy medium-scale quantum computing (NISQ), quantum devices face multiple hardware constraints, including high noise levels, a limited number of qubits, and short coherence times. Variational quantum algorithm (VQA) is one of the most promising applications of NISQ, solving optimization problems through a hybrid approach of parameterized quantum circuits (PQC) and classical optimizers. A PQC consists of a series of quantum gates arranged in a specific order; its architecture, including the type, order, and connection method of the gates, directly affects the algorithm's expressive power and trainability. Traditional quantum circuit design relies on manual experience or heuristic rules, which is not only time-consuming and labor-intensive but also difficult to guarantee universality across different problems and hardware platforms.
[0003] Differentiable Quantum Architecture Search (DQAS) is a method for automatically discovering quantum circuit architectures. It relaxes the discrete gate selection problem into a continuously differentiable optimization problem and performs efficient search through gradient descent. Existing DQAS methods typically employ the Gumbel-Softmax reparameterization technique to achieve differentiable discrete sampling, controlling the transition from random exploration to deterministic selection through temperature parameters. However, existing methods often only consider performance metrics under ideal, noise-free conditions when evaluating candidate circuits, ignoring the impact of noise factors such as gate errors, decoherence, and measurement errors on real hardware. This evaluation approach results in circuits that perform excellently in ideal environments but experience significant performance degradation on noisy real-world hardware, severely impacting the practicality of quantum algorithms. Furthermore, the candidate circuits often contain a large number of redundant quantum gates and lack systematic post-processing optimization strategies, hindering efficient deployment on resource-constrained NISQ devices. Summary of the Invention
[0004] To address the problems existing in the prior art, the purpose of this invention is to provide a quantum architecture search method and device based on noise perception evaluation that is more robust to noisy hardware and has higher operating efficiency of the searched quantum circuits.
[0005] To achieve the above-mentioned objectives, the present invention provides the following technical solution:
[0006] A quantum architecture search method based on noise-aware evaluation, comprising the following steps:
[0007] (1) Based on the topological connections and native gate set of the target quantum hardware, obtain the operation pool formed by all allowed quantum gate operations, and initialize the architecture parameter matrix;
[0008] (2) Differentiable sampling is performed on the architecture parameter matrix using reparameterization techniques to obtain candidate quantum circuits;
[0009] (3) The performance of candidate quantum circuits is tested in a noisy environment, the expressive power index and the noise resistance index are calculated, and a multi-objective loss function containing the expressive power index, the noise resistance index and the stability regularization term is constructed. The local optimal quantum circuit is obtained by iterative update based on the multi-objective loss function.
[0010] (4) Perform quantum gate operations, such as swapping, merging and eliminating, on the locally optimal quantum circuit until the quantum circuit converges and the final optimized quantum circuit is obtained.
[0011] Furthermore, step (1) specifically includes:
[0012] Based on the topological connections of the target quantum hardware, determine the connection edges between qubits that allow the execution of two-qubit gates;
[0013] Based on the native gate set supported by the target quantum hardware, determine the available single-bit gate operations and two-bit gate operations, and combine all allowed single-bit gate operations and two-bit gate operations to form an operation pool.
[0014] Initialize the architecture parameter matrix.
[0015] Furthermore, step (1) is followed by:
[0016] The architecture parameter matrix is decomposed using a low-rank matrix factorization method. Decomposed into two low-rank matrices and The product of, i.e. .
[0017] Furthermore, step (2) specifically includes:
[0018] Architecture parameter matrix For each line depth in the operation pool, noise is sampled from the Gumbel distribution corresponding to each quantum gate operation. and using temperature parameters The softmax function of the control is normalized to obtain the selection probability of each operation. Among them, temperature parameters As search iterations gradually decrease;
[0019] Based on the probability of selection By selecting quantum gate operations and assembling them in the order of their depth positions, candidate quantum circuits are obtained.
[0020] Furthermore, step (3) specifically includes:
[0021] The candidate quantum circuit was executed multiple times in a noisy environment, and the KL divergence between the measurement result distribution and the ideal Haar random distribution was calculated as an index of expressive power.
[0022] The candidate quantum circuit and its inverse circuit are connected in series to form an identity circuit, which is then executed in a noisy environment. The probability of returning to the initial state is statistically analyzed as an indicator of noise resistance performance.
[0023] Construct a multi-objective loss function that includes an expressive power index, a noise resistance index, and a stability regularization term;
[0024] With the goal of minimizing the loss calculated by the multi-objective loss function, the gradient descent method is used to iterate until convergence, thus obtaining the locally optimal quantum circuit.
[0025] Furthermore, the multi-objective loss function is specifically as follows:
[0026]
[0027] In the formula, C is the multi-objective loss function. , and These are the weighting coefficients. As an indicator of expressive ability, For noise reduction performance indicators, For stability.
[0028] Furthermore, step (4) specifically includes:
[0029] Perform gate swapping on a locally optimal quantum circuit, wherein the gate swapping is based on the commutation relation of quantum gates to move a single-bit gate operation forward before a two-bit gate operation;
[0030] Perform gate fusion on a quantum circuit, wherein the gate fusion is to merge consecutive similar rotating gate operations by accumulating rotation angles;
[0031] Perform gate elimination on the quantum circuit, wherein the gate elimination is the deletion of reciprocal gate operation pairs, self-reversible gate operation pairs, zero-angle rotation gate operation, and identity gate operation;
[0032] The quantum circuit is repeatedly subjected to gate fusion and gate elimination until the number of quantum gate operations and the circuit depth no longer decrease.
[0033] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described above.
[0034] A computer-readable storage medium having a computer program / instructions stored thereon, which, when executed by a processor, implements the above-described method.
[0035] A computer program product includes a computer program / instructions that, when executed by a processor, implement the above-described method.
[0036] Compared with existing technologies, the advantages of this invention are as follows: This invention provides a quantum architecture search method and device based on noise-aware evaluation. By introducing dual evaluation metrics of expressive power and probability of successful trials (PST), this invention constructs a multi-objective loss function to comprehensively evaluate the performance of candidate quantum circuits in a noisy environment, ensuring that the discovered circuits have good robustness and practicality on real hardware. Simultaneously, this invention applies systematic optimization rules such as gate swapping, gate fusion, and gate elimination to the searched quantum circuits. Through iterative iteration, it significantly reduces the number and depth of gates in the circuits, lowering the execution complexity and noise accumulation of quantum circuits on NISQ devices. This effectively improves the success rate and operational efficiency of quantum architecture search in practical hardware deployments, providing important technical support for the practical application of variational quantum algorithms in the NISQ era. Attached Figure Description
[0037] Figure 1 A flowchart illustrating the workflow of the noise-aware evaluation-based quantum architecture search method provided in this embodiment of the invention;
[0038] Figure 2 Examples of candidate quantum circuits obtained by this invention;
[0039] Figure 3 This is an example of a quantum circuit obtained by gate swapping in the post-search optimization process of this invention;
[0040] Figure 4 This is an example of a quantum circuit obtained by gate fusion in the post-search optimization process of this invention;
[0041] Figure 5 This is an example of the final quantum circuit obtained by gate elimination in the post-search optimization process of this invention;
[0042] Figure 6 A structural diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation
[0043] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
[0044] Example 1
[0045] This invention provides a quantum architecture search method based on noise-aware evaluation, such as... Figure 1 As shown, the method includes the following steps:
[0046] (1) Based on the topological connections and native gate set of the target quantum hardware, obtain the operation pool formed by all allowed quantum gate operations, and initialize the architecture parameter matrix.
[0047] This step specifically includes:
[0048] (1.1) Based on the topological connections of the target quantum hardware, determine the connection edges between qubits that allow the execution of two-qubit gates; for example, in a linear topology, the qubits Only with adjacent qubits and A two-bit gate can be executed between any two qubits in a fully connected topology.
[0049] (1.2) Based on the native gate set supported by the target quantum hardware, determine the available single-bit gate operations and two-bit gate operations, and combine all allowed single-bit gate operations and two-bit gate operations to form an operation pool;
[0050] Common single-bit gates include Hadamard gates and rotating gates. , , Pauli Gate , , Common double-bit gates include... , wait.
[0051] For example, based on a 4-qubit linear topology - , - , - Constructed operation pool Includes single-bit gates and double-bit gate .
[0052] (1.3) Initialize the architecture parameter matrix.
[0053] Step (1) is followed by:
[0054] The architecture parameter matrix is decomposed using a low-rank matrix factorization method. Decomposed into two low-rank matrices and The product of, i.e. This reduces the number of parameters and improves search efficiency.
[0055] (2) Differentiable sampling is performed on the architecture parameter matrix using reparameterization technique to obtain candidate quantum circuits.
[0056] This step specifically includes:
[0057] (2.1) Architecture parameter matrix For each line depth in the operation pool, noise is sampled from the Gumbel distribution corresponding to each quantum gate operation. and using temperature parameters The softmax function of the control is normalized to obtain the selection probability of each operation. Among them, temperature parameters As the number of search iterations gradually decreases, the selection process shifts from random exploration to deterministic selection;
[0058] (2.2) Based on the selection probability By selecting quantum gate operations and assembling them in the order of their positions according to the depth of the circuit, a candidate quantum circuit U is obtained, such as... Figure 2 As shown. The candidate quantum circuit U operates on 4 qubits. , , , The circuit contains various types of quantum gates. While it meets the mission requirements, the presence of redundant quantum gates hinders efficient execution on NISQ devices.
[0059] (3) The performance of candidate quantum circuits is tested in a noisy environment, the expressive power index and the noise resistance index are calculated, and a multi-objective loss function containing the expressive power index, the noise resistance index and the stability regularization term is constructed. The local optimal quantum circuit is obtained by iterative update based on the multi-objective loss function.
[0060] This step specifically includes:
[0061] (3.1) Execute the candidate quantum circuit multiple times in a noisy environment and calculate the KL divergence between the distribution of measurement results and the ideal Haar random distribution as an indicator of expressive power;
[0062] In this embodiment, the noise in the noisy environment adopts a noise model based on IBM quantum device calibration data, supporting multiple device selections (such as Fez, Kingston, Marrakesh, etc.), and includes three noise types: depolarization noise, thermal relaxation noise (T1 / T2), and readout errors. Expressive power evaluation uses density matrix simulation to execute the quantum circuit in a noisy environment. Through 50 rounds of parameter sampling and 20 histogram binning statistical fidelity distributions, the KL divergence between the KL divergence and the ideal Haar random distribution is calculated as an expressive power index.
[0063] (3.2) Connect the candidate quantum circuit and its inverse circuit in series to form an identity circuit, and execute it in a noisy environment, with the initial state set to zero. The final quantum state is measured multiple times, and the proportion of measurements that return to the initial zero state is counted out of the total number of measurements. This proportion serves as an indicator of noise resistance. Specifically, 1024 measurements can be performed under the same noise conditions, and the return to the initial state can be counted. The frequency of noise reduction performance is used to calculate the noise reduction performance index.
[0064] (3.3) Construct a multi-objective loss function that includes an expressive power index, a noise resistance index, and a stability regularization term. The multi-objective loss function is as follows:
[0065]
[0066] In the formula, C is the multi-objective loss function. , and These are the weighting coefficients. As an indicator of expressive ability, For noise reduction performance indicators, For stability. In this embodiment, , Stability regularization coefficient .
[0067] (3.4) Taking the minimum loss calculated by the multi-objective loss function as the objective, the gradient descent method is used to iterate until convergence, and the local optimal quantum circuit is obtained.
[0068] (4) Perform quantum gate operations, such as swapping, merging and eliminating, on the locally optimal quantum circuit until the quantum circuit converges and the final optimized quantum circuit is obtained.
[0069] Step (4) specifically includes:
[0070] (4.1) Perform gate swapping on the locally optimal quantum circuit, wherein the gate swapping is based on the commutation relation of quantum gates to move the single-bit gate operation forward before the two-bit gate operation, so as to create conditions for subsequent gate fusion;
[0071] (4.2) Perform gate fusion on the quantum circuit, wherein the gate fusion is to merge consecutive rotating gate operations of the same type by accumulating rotation angles;
[0072] (4.3) Perform gate elimination on the quantum circuit, wherein the gate elimination is the deletion of pairs of reciprocal gate operations (such as rotating gates). and ), self-reverse gate operation pairs (such as consecutive ones) - Door facing - Door facing - Door pairing), zero-angle revolving door operation, and constant door operation;
[0073] (4.4) Repeatedly perform gate fusion and gate elimination on the quantum circuit until the number of quantum gate operations and the circuit depth no longer decrease.
[0074] like Figure 3 The image shows an example of a quantum circuit optimized by gate swapping. Gate swapping is based on the commutation relation of quantum gates, moving commutable single-qubit gates forward before two-qubit gates. Specifically, The first one is right next to the top. Behind the door The door moved to In front of the door, right next to the second Behind the door The door also moved to In front of the door. The door exchange operation creates the conditions for subsequent door merging, allowing similar revolving doors to be arranged adjacent to each other.
[0075] like Figure 4 The image shows an example of a quantum circuit optimized by gate fusion. Gate fusion combines consecutive, similar rotation gates acting on the same qubit into a single rotation gate. superior, , and Three consecutive The doors merged into ;exist superior, and two The doors merged into This is the identity operation. Gate fusion significantly reduces the number of gates in the circuit, thus lowering the execution complexity.
[0076] like Figure 5 The image shows the final quantum circuit after gate elimination optimization. Example. Gate elimination removes redundant quantum gates from circuits, including reciprocal gate pairs, self-reversible gate pairs, zero-angle rotation gates, and identity gates. Specifically, and The identity gate and the small-angle revolving door Deleted; On and Reciprocal gate pairs are deleted; On and Reciprocal gate pairs are removed. After gate elimination, the circuit structure is simpler and more suitable for deployment on NISQ equipment.
[0077] After the complete post-search optimization in step (4), the total number of gates in the line was reduced from the original 23 to 12, a reduction of 47.83%, and the line depth was reduced from 8 layers to 6 layers, a reduction of 25%, which significantly improved the execution efficiency and noise immunity of the line on the NISQ device.
[0078] Example 2
[0079] This invention provides a computer device, which provides services for implementing the method of Embodiment 1 above. For example... Figure 6 As shown, the device may include: a memory 301 storing a computer-executable program; a processor 302 coupled to the memory 301; the processor 302 calls the computer-executable program stored in the memory 301 to perform the steps in the method described in Embodiment 1.
[0080] Memory 301 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) and / or cache memory. The device may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, memory 301 may be used to read and write non-removable, non-volatile magnetic media (commonly referred to as a "hard disk drive"). A program / utility having a set (at least one) of program modules may be stored, for example, in memory 301. Such program modules include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The computer-executable program of the program modules typically performs the functions and / or methods described in the embodiments of the present invention.
[0081] The processor 302 executes various functional applications and data processing by running programs stored in the memory 301, such as implementing the method provided in Embodiment 1 of the present invention.
[0082] The code of a computer executable program can be written in one or more programming languages or a combination thereof. Programming languages include object-oriented programming languages such as Java, Smalltalk, and C++, as well as conventional procedural programming languages such as the "C" language or similar programming languages.
[0083] Example 3
[0084] This invention provides a storage medium containing a computer-executable program, which, when executed by a computer processor, is used to perform the method of Embodiment 1.
[0085] The storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
[0086] Of course, the computer-executable program in the storage medium provided in the embodiments of the present invention is not limited to the above-described method operations, but can also perform related operations in the methods provided in any embodiment of the present invention.
[0087] Example 4
[0088] This invention also provides a computer product, such as an app on a mobile phone or tablet, or an installer on a computer. This product includes a computer program / instructions that, when executed by a processor, implement the method described in Embodiment 1. The code for a computer-executable program that performs the operations of this invention can be written in one or more programming languages or a combination thereof. Programming languages include object-oriented programming languages such as Java, Smalltalk, and C++, as well as conventional procedural programming languages such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0089] It should be understood that the embodiments and descriptions above are only the principles, main features and advantages of the present invention. Various changes and modifications can be made to the present invention without departing from the spirit and scope of the invention, and all such changes and modifications fall within the protection scope of the present invention.
Claims
1. A quantum architecture search method based on noise-aware evaluation, characterized in that... The method includes the following steps: (1) Based on the topological connections and native gate set of the target quantum hardware, obtain the operation pool formed by all allowed quantum gate operations, and initialize the architecture parameter matrix; (2) Differentiable sampling is performed on the architecture parameter matrix using reparameterization techniques to obtain candidate quantum circuits; (3) The performance of candidate quantum circuits is tested in a noisy environment, the expressive power index and the noise resistance index are calculated, and a multi-objective loss function containing the expressive power index, the noise resistance index and the stability regularization term is constructed. The local optimal quantum circuit is obtained by iterative update based on the multi-objective loss function. (4) Perform quantum gate operations, such as swapping, merging and eliminating, on the locally optimal quantum circuit until the quantum circuit converges and the final optimized quantum circuit is obtained.
2. The quantum architecture search method based on noise-aware evaluation according to claim 1, characterized in that, Step (1) specifically includes: Based on the topological connections of the target quantum hardware, determine the connection edges between qubits that allow the execution of two-qubit gates; Based on the native gate set supported by the target quantum hardware, determine the available single-bit gate operations and two-bit gate operations, and combine all allowed single-bit gate operations and two-bit gate operations to form an operation pool. Initialize the architecture parameter matrix.
3. The quantum architecture search method based on noise-aware evaluation according to claim 1, characterized in that, Step (1) is followed by: The architecture parameter matrix is decomposed using a low-rank matrix factorization method. Decomposed into two low-rank matrices and The product of, i.e. .
4. The quantum architecture search method based on noise-aware evaluation according to claim 1, characterized in that, Step (2) specifically includes: Architecture parameter matrix For each line depth in the operation pool, noise is sampled from the Gumbel distribution corresponding to each quantum gate operation. and using temperature parameters The softmax function of the control is normalized to obtain the selection probability of each operation. Among them, temperature parameters As search iterations gradually decrease; Based on the probability of selection By selecting quantum gate operations and assembling them in the order of their depth positions, candidate quantum circuits are obtained.
5. The quantum architecture search method based on noise-aware evaluation according to claim 1, characterized in that, Step (3) specifically includes: The candidate quantum circuit was executed multiple times in a noisy environment, and the KL divergence between the measurement result distribution and the ideal Haar random distribution was calculated as an index of expressive power. The candidate quantum circuit and its inverse circuit are connected in series to form an identity circuit, which is then executed in a noisy environment. The probability of returning to the initial state is statistically analyzed as an indicator of noise resistance performance. Construct a multi-objective loss function that includes an expressive power index, a noise resistance index, and a stability regularization term; With the goal of minimizing the loss calculated by the multi-objective loss function, the gradient descent method is used to iterate until convergence, thus obtaining the locally optimal quantum circuit.
6. The quantum architecture search method based on noise-aware evaluation according to claim 1, characterized in that, The multi-objective loss function is specifically as follows: ， In the formula, C is the multi-objective loss function. , and These are the weighting coefficients. As an indicator of expressive ability, For noise reduction performance indicators, For stability.
7. The quantum architecture search method based on noise-aware evaluation according to claim 1, characterized in that, Step (4) specifically includes: Perform gate swapping on a locally optimal quantum circuit, wherein the gate swapping is based on the commutation relation of quantum gates to move a single-bit gate operation forward before a two-bit gate operation; Perform gate fusion on a quantum circuit, wherein the gate fusion is to merge consecutive similar rotating gate operations by accumulating rotation angles; Perform gate elimination on the quantum circuit, wherein the gate elimination is the deletion of reciprocal gate operation pairs, self-reversible gate operation pairs, zero-angle rotation gate operation, and identity gate operation; The quantum circuit is repeatedly subjected to gate fusion and gate elimination until the number of quantum gate operations and the circuit depth no longer decrease.
8. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor executes the computer program to implement the method as described in any one of claims 1-7.
9. A computer-readable storage medium having a computer program / instructions stored thereon, characterized in that, The computer program / instructions, when executed by a processor, implement the method of any one of claims 1-7.
10. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the method of any one of claims 1-7.