Display device and display driving chip and display driving method thereof

Abstract

The invention discloses a display device and a display driving chip and a display driving method thereof. A display area of the display panel comprises a high-refresh-rate display area and a low-refresh-rate display area. The display driving chip generates a gate clock signal. The gate driver uses a gate clock signal to generate a first scan signal for driving the high refresh rate display area and a second scan signal for driving the low refresh rate display area. The high-refresh-rate display area and the low-refresh-rate display area are both refreshed in the full-refresh frame period. And only the high-refresh-rate display area is refreshed in the local refresh frame period. The gate clock signal has different operating periods or different amplitudes in different portions of the full-refresh frame period (corresponding to different refresh rate display regions).

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more particularly to a display device, its display driver chip, and its display driving method. Background Technology

[0002] In traditional display panels, the entire display area displays one or more images at a single refresh rate. In some applications, such as mobile applications, the entire display area may be divided into multiple zones, all displaying images at the same refresh rate. In many use cases, only one zone needs frequent screen refreshes (e.g., playing animations), while another zone displays static images without frequent refreshes. When the entire display area (all zones) of a traditional display panel operates at a high refresh rate, the panel consumes a lot of power. In this case, the high refresh rate is a waste of power for the zones that don't need frequent screen refreshes. When the entire display area (all zones) of a traditional display panel operates at a low refresh rate, the panel consumes less power, but the refresh rate is too low for the zones that need frequent screen refreshes. Summary of the Invention

[0003] The present invention provides a display device, a display driver chip and a display driver method thereof, so that different display areas (partitions) in the same display panel can adapt to have different frame rates (refresh rates).

[0004] In an embodiment of the present invention, the display driver chip described above includes a controller. The controller is configured to generate a gate clock signal to control the gate driver of a display panel, wherein the display area of ​​the display panel includes a high refresh rate display area and a low refresh rate display area. Both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame period, while only the high refresh rate display area is refreshed during a partial refresh frame period. The gate driver uses the gate clock signal to generate a plurality of first scan signals and a plurality of second scan signals, wherein the first scan signals are used to drive a plurality of scan lines in the high refresh rate display area, and the second scan signals are used to drive a plurality of scan lines in the low refresh rate display area. The gate clock signal has a first active period in a first portion of the full refresh frame period (corresponding to the high refresh rate display area), and a second active period longer than the first active period in a second portion of the full refresh frame period (corresponding to the low refresh rate display area).

[0005] In an embodiment of the present invention, the aforementioned display driver chip includes a controller. The controller is configured to output a gate clock signal to control the gate driver of a display panel, wherein the display area of ​​the display panel includes a high refresh rate display area and a low refresh rate display area. Both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame cycle, while only the high refresh rate display area is refreshed during a partial refresh frame cycle. The gate driver uses the gate clock signal to generate a plurality of first scan signals and a plurality of second scan signals, wherein the first scan signals are used to drive a plurality of scan lines in the high refresh rate display area, and the second scan signals are used to drive a plurality of scan lines in the low refresh rate display area. The gate clock signal has a first amplitude (swing) in the first portion of the full refresh frame cycle (corresponding to the high refresh rate display area), and the gate clock signal has a second amplitude greater than the first amplitude in the second portion of the full refresh frame cycle (corresponding to the low refresh rate display area).

[0006] In an embodiment of the present invention, the display device includes a display panel and a display driver chip. The display panel includes an effective display area and a gate driver. The effective display area includes a high refresh rate display area and a low refresh rate display area. The gate driver is used to generate a plurality of first scan signals driving a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals driving a plurality of scan lines of the low refresh rate display area. The display driver chip includes a controller. The controller is configured to generate a gate clock signal to control the gate driver of the display panel. Both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame cycle, while only the high refresh rate display area is refreshed during a partial refresh frame cycle. The gate driver uses the gate clock signal to generate the plurality of first scan signals and the plurality of second scan signals. The gate clock signal has a first operating period in a first part of the full refresh frame cycle (corresponding to the high refresh rate display area), and the gate clock signal has a second operating period longer than the first operating period in a second part of the full refresh frame cycle (corresponding to the low refresh rate display area).

[0007] In an embodiment of the present invention, the display device includes a display panel and a display driver chip. The display panel includes an effective display area and a gate driver. The effective display area includes a high refresh rate display area and a low refresh rate display area. The gate driver is used to generate a plurality of first scan signals driving a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals driving a plurality of scan lines of the low refresh rate display area. The display driver chip includes a controller. The controller is configured to output a gate clock signal to control the gate driver of the display panel. Both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame cycle, while only the high refresh rate display area is refreshed during a partial refresh frame cycle. The gate driver uses the gate clock signal to generate the plurality of first scan signals and the plurality of second scan signals. The gate clock signal has a first amplitude in the first part of the full refresh frame cycle (the first part of the full refresh frame cycle corresponds to the high refresh rate display area), and the gate clock signal has a second amplitude greater than the first amplitude in the second part of the full refresh frame cycle (the second part of the full refresh frame cycle corresponds to the low refresh rate display area).

[0008] In an embodiment of the present invention, the above-described display driving method includes: generating a gate clock signal to control a gate driver of a display panel, wherein the display area of ​​the display panel includes a high refresh rate display area and a low refresh rate display area, both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame cycle, while only the high refresh rate display area is refreshed during a partial refresh frame cycle; wherein the gate driver uses the gate clock signal to generate a plurality of first scan signals and a plurality of second scan signals, the first scan signals being used to drive a plurality of scan lines of the high refresh rate display area, and the second scan signals being used to drive a plurality of scan lines of the low refresh rate display area; and wherein the gate clock signal has different operating periods during different time periods of the full refresh frame cycle, or the gate clock signal has different amplitudes during different time periods of the full refresh frame cycle.

[0009] Based on the above, the display driver chip described in the embodiments of the present invention can generate a gate clock signal, and the gate driver uses the gate clock signal to generate a scan signal to drive the high refresh rate display area and the low refresh rate display area. During the full refresh frame cycle, both the high refresh rate display area and the low refresh rate display area are refreshed, while during a partial refresh frame cycle, only the high refresh rate display area is refreshed, allowing the refresh rate of the low refresh rate display area of ​​the display panel to differ from that of the high refresh rate display area. After enabling the display partition frequency conversion function, if the boundary position between the high refresh rate display area (high refresh area) and the low refresh rate display area (low refresh area) remains unchanged, over a long period, the display panel will experience an unrecoverable problem of uneven brightness between the high refresh rate and low refresh rate areas. The operating period of the gate drive signal (scan signal) of the display panel is determined by the operating period of the gate clock signal. The gate clock signal has different operating periods or different amplitudes in different parts of the full refresh frame cycle (or different time periods, corresponding to different refresh rate display areas). Therefore, when the display partition frequency conversion function is enabled, the average operating period of the gate clock signal for different refresh rate display areas tends to be the same over a long period. Over time, the aging of pixels in high refresh rate and low refresh rate areas due to stress effect will tend to be consistent, thereby reducing the uneven brightness of display areas with different refresh rates.

[0010] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a circuit block of a display device according to an embodiment of the present invention;

[0012] Figure 2 This is a circuit block diagram of a gate driver according to an embodiment of the present invention;

[0013] Figure 3 This is a schematic diagram of the signal timing of a gate driver according to an embodiment of the present invention;

[0014] Figure 4 This is a flowchart illustrating a display driving method according to an embodiment of the present invention;

[0015] Figure 5 This is a schematic diagram of the gate clock signal waveform of a gate driver according to another embodiment of the present invention;

[0016] Figure 6 This is a schematic diagram of the waveform of the scan signal of the gate driver according to an embodiment of the present invention;

[0017] Figure 7This is a schematic diagram of the gate clock signal waveform of a gate driver according to another embodiment of the present invention;

[0018] Figure 8 This is a schematic diagram of the gate clock signal waveform of a gate driver according to a further embodiment of the present invention;

[0019] Figure 9 This is a schematic diagram of the gate clock signal waveform of a gate driver according to another embodiment of the present invention.

[0020] Symbol explanation:

[0021] 100: Display device

[0022] 110: Display driver chip

[0023] 111: Controller

[0024] 112: Source Driver

[0025] 120: Gate driver

[0026] 121, 122, 123, 124: Shift register groups

[0027] 130: Display panel

[0028] CLR: Reset pulse

[0029] GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8, GL9, GL10, GL11, GL12: Scan lines

[0030] GCK1, GCK2, GCK3, GCK4, GCK5, GCK6, GCK7, GCK8: Gate clock signals

[0031] S410, S420: Steps

[0032] STV: Vertical Initiation Pulse

[0033] VGH, VGH': High logic level

[0034] VGL, VGL': Low logic level Detailed Implementation

[0035] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0036] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0037] Figure 1 This is a schematic diagram of a circuit block of a display device 100 according to an embodiment of the present invention. Figure 1 The display device 100 shown includes a display driver chip 110, a gate driver 120, and a display panel 130. Depending on the design, the display panel 130 can include various types of display panels, such as a liquid crystal display (LCD) panel or other display panels. The display driver chip 110 is coupled to multiple data lines (or source lines) of the display panel 130. The display driver chip 110 can act as a driver (e.g., a source driver) to drive the multiple data lines of the display panel 130.

[0038] Display driver chip 110 is coupled to gate driver 120. Gate driver 120 is coupled to multiple scan lines (or gate lines) of display panel 130. Based on the control of display driver chip 110, gate driver 120 can scan multiple scan lines of display panel 130. Depending on the actual design, gate driver 120 may include gate driver on array (GOA) or other gate driving circuits. With the scanning timing of display panel 130 coordinated with gate driver 120, display driver chip 110 can drive multiple data lines of display panel 130 to display images on display panel 130.

[0039] In some practical application scenarios, Figure 1 The display panel 130 shown may not be partitioned. In such an application scenario, Figure 1The display driver chip 110 can send a reset pulse (native reset pulse) to the gate driver 120 at the beginning (or end) of each frame cycle to clear the scan pulses latched inside the gate driver 120 before scanning the display panel 130. After the native reset pulse occurs, the gate driver 120 can begin scanning the scan lines of the display panel 130 based on the vertical start pulse and gate clock signal provided by the display driver chip 110. Therefore, the entire display area of ​​the display panel 130 can be refreshed.

[0040] In other practical application scenarios, Figure 1 The entire display area of ​​the display panel 130 shown may be divided into two (or more) partitions. For example, the effective display area of ​​the display panel 130 includes a high refresh rate display area and a low refresh rate display area. Based on the control of the gate driver 120 by the display driver chip 110, the high refresh rate display area and the low refresh rate display area in the same display panel 130 are adapted to have different refresh rates.

[0041] For example (but not limited to), suppose Figure 1 The display panel 130 shown includes 1612 scan lines. Based on practical operation, it is assumed that the display driver chip 110 dynamically defines scan lines 1 to 540 (the 540 scan lines at the top of the display panel 130) as a high refresh rate display area, and scan lines 541 to 1612 (the 1072 scan lines at the bottom of the display panel 130) as a low refresh rate display area. Based on the control of the gate driver 120 by the display driver chip 110, the high refresh rate display area of ​​the display panel 130 has a high refresh rate (e.g., 120 Hz, equal to the output frame rate, which determines the length of a frame period), while the low refresh rate display area of ​​the display panel 130 has a low refresh rate (e.g., 60 Hz). Therefore, the display device 100 can reduce power consumption by lowering the refresh rate of the low refresh rate display area while maintaining a high refresh rate in the high refresh rate display area.

[0042] In application scenarios where the display panel 130 is divided into a high refresh rate display area and a low refresh rate display area... Figure 1The display driver chip 110 can select a first number (M) of frame cycles (called a full refresh frame cycle, corresponding to normal display frames) and a second number (N) of frame cycles (called a partial refresh frame cycle) within each frame cycle group (containing multiple consecutive frame cycles, also considered as a refresh cycle) to achieve different refresh rates for different partitions, where M and N are at least one. During a full refresh frame cycle, both the high refresh rate display area and the low refresh rate display area are refreshed, while during a partial refresh frame cycle, only the high refresh rate display area is refreshed. The number of frames in each frame cycle group can be determined according to the actual design and / or actual operation. For example (but not limited to), suppose each frame cycle group includes three consecutive frame cycles. The number of frames in the "full refresh frame cycle" and the number of frames in the "partial refresh frame cycle" within each refresh cycle can be determined according to the actual design and / or actual operation. In some practical scenarios, the display driver chip 110 can treat all frame cycles as a "full refresh frame cycle." In this case, both the high refresh rate display area and the low refresh rate display area of ​​the display panel 130 are refreshed in each frame cycle, meaning that the refresh rate of both the high refresh rate display area and the low refresh rate display area is the same, equal to the output frame rate, such as 120Hz. In other practical scenarios, based on an output frame rate of 120Hz, the display driver chip 110 can select one frame cycle as the "full refresh frame cycle" and the remaining two frame cycles as the "partial refresh frame cycle" within a refresh cycle of three frame cycles. In this way, the refresh rate of the high refresh rate display area of ​​the display panel 130 is equal to the output frame rate of 120Hz, while the refresh rate of the low refresh rate display area of ​​the display panel 130 is equivalent to one-third of 120Hz, or 40Hz. In other practical scenarios, based on an output frame rate of 120Hz, the display driver chip 110 can select two frame cycles as the "full refresh frame cycle" and the remaining frame cycle as the "partial refresh frame cycle" from a frame cycle group of three frame cycles. In this way, the refresh rate of the high refresh rate display area of ​​the display panel 130 is equal to the output frame rate of 120Hz, while the refresh rate of the low refresh rate display area of ​​the display panel 130 is equivalent to two-thirds of the output frame rate of 120Hz, which is 80Hz.

[0043] The display driver chip 110 can send a reset pulse to the gate driver 120 during the full refresh frame cycle and the partial refresh frame cycle to clear the scan pulses latched in the gate driver 120. Based on practical design, in some embodiments, the number of reset pulses in each full refresh frame cycle is less than the number of reset pulses in each partial refresh frame cycle. For example, in some embodiments, the number of reset pulses in each full refresh frame cycle is 1, and the number of reset pulses in each partial refresh frame cycle is 2. The adjacency position between the high refresh rate display area and the low refresh rate display area of ​​the display panel 130 corresponds to a corresponding time point in each full refresh frame cycle and each partial refresh frame cycle. The display driver chip 110 sends an additional reset pulse to the gate driver 120 at the corresponding time point in each partial refresh frame cycle to clear the scan pulses in the gate driver 120.

[0044] For example, in each full refresh frame cycle, the display driver chip 110 sends a single reset pulse (native reset pulse) to the gate driver 120 at the beginning (or end) of the frame to clear the scan pulses locked in the gate driver 120. In each partial refresh frame cycle, the display driver chip 110 sends not only a reset pulse (native reset pulse) at the beginning (or end) of the frame cycle, but also another reset pulse (additional reset pulse) to the gate driver 120 at other points in the frame cycle, corresponding to the adjacent positions between the high refresh rate display area and the low refresh rate display area, to clear the scan pulses locked in the gate driver 120 at different points in each partial refresh frame cycle. Assume that the upper 540 scan lines of the display panel 130 are the high refresh rate display area, and the lower 1072 scan lines of the display panel 130 are the low refresh rate display area. During each local refresh frame cycle, the display driver chip 110 also sends an additional reset pulse to the gate driver 120 when the 540th scan line is completed. Therefore, the low refresh rate display area is not scanned during these local refresh frame cycles, thus allowing the high refresh rate display area and the low refresh rate display area in the same display panel 130 to adapt to different refresh rates.

[0045] exist Figure 1In the illustrated embodiment, the display driver chip 110 includes a controller 111 and a source driver 112. The source driver 112 is coupled to multiple data lines of the display panel 130. The controller 111 is coupled to the source driver 112 and the gate driver 120. Depending on the design, in some embodiments, the display driver chip 110 and / or the controller 111 may be implemented as hardware circuitry. In other embodiments, the display driver chip 110 and / or the controller 111 may be implemented as a combination of hardware, firmware, and software (i.e., programs).

[0046] In hardware terms, the aforementioned display driver chip 110 and / or controller 111 can be implemented as logic circuits on an integrated circuit. For example, the functions of the display driver chip 110 and / or controller 111 can be implemented in various logic blocks, modules, and circuits within one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The functions of the display driver chip 110 and / or controller 111 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits within an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0047] In software and / or firmware form, the functions of the aforementioned display driver chip 110 and / or controller 111 can be implemented as programming codes. For example, the display driver chip 110 and / or controller 111 can be implemented using common programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. An electronic device (e.g., a computer, CPU, controller, microcontroller, or microprocessor) can read and execute the programming code from the non-transitory machine-readable storage medium to implement the functions of the display driver chip 110 and / or controller 111.

[0048] Controller 111 is configured to output a native reset pulse and an additional reset pulse to gate driver 120 during a local refresh frame cycle. During the local refresh frame cycle, the reset pulse occurs before multiple gate clock signals begin toggle, and the additional reset pulse occurs after the gate clock signals stop toggle (see details). Figure 3 , Figure 5 , Figure 6 , Figure 7 , Figure 8 or Figure 9 The reset pulse CLR and gate clock signals GCK1 to GCK8 are shown.

[0049] The controller 111 is configured to generate a vertical start pulse and a gate clock signal to control the gate driver 120 of the display panel 130. The gate driver 120 is used to drive a plurality of scan lines of the display panel 130. For example, the gate driver 120 uses the gate clock signal to generate a plurality of first scan signals and a plurality of second scan signals, wherein the first scan signals are used to drive a plurality of scan lines in the high refresh rate display area of ​​the display panel 130, and the second scan signals are used to drive a plurality of scan lines in the low refresh rate display area of ​​the display panel 130.

[0050] Figure 2 This is a circuit block diagram of a gate driver 120 according to an embodiment of the present invention. Figure 2 The gate driver 120 shown can be used as Figure 1 This is one of many implementation examples of the gate driver 120 shown. Figure 2In the illustrated embodiment, the gate driver 120 includes a plurality of shift register groups, such as Figure 2 The shift register groups 121, 122, 123, and 124 are shown. Each shift register group 121–124 includes multiple shift registers connected in series. The output of each shift register is coupled to multiple scan lines of the display panel 130 (e.g., ...). Figure 2 One of the corresponding scan lines shown in GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8, GL9, GL10, GL11 and GL12 is used to provide different scan signals (scan pulses at different phases).

[0051] The input of the first shift register in each shift register group 121-124 receives the vertical start pulse (STV), while the inputs of the other shift registers receive the scan pulse output from the previous shift register, such as... Figure 2 As shown. Each shift register also receives multiple gate clock signals of different phases (e.g., Figure 2 The corresponding gate clock signal is one of the gate clock signals GCK1 to GCK8 shown. Based on the triggering of gate clock signals GCK1 to GCK8, each shift register latches the scan pulse at its input, and each shift register outputs a different scan signal (scan pulses of different phases) to multiple scan lines of the display panel 130 (e.g., ...). Figure 2 The corresponding scan line in GL1 to GL12 shown. The working period (i.e., the duration of the scan pulse) of the scan signal of the scan line of the display panel 130 is determined by the working period (active period) of the gate clock signals GCK1 to GCK8. In addition, the level and amplitude of the gate clock signals GCK1 to GCK8 can affect the amplitude of the scan signal output by each shift register.

[0052] The display panel's different refresh rates can be achieved by a refresh cycle consisting of M full refresh frame cycles and N partial refresh frame cycles, where M and N are at least one. For example, the following uses... Figure 3 This demonstrates an example of a refresh cycle consisting of a full refresh frame cycle and a partial refresh frame cycle.

[0053] Figure 3 This is a signal timing diagram of a gate driver 120 according to an embodiment of the present invention. Figure 3 The horizontal axis represents time. The vertical start pulse (STV) and shift register may not be limited to one set. Figure 3 The gate clock signals GCK1 to GCK8 shown are used to trigger multiple shift registers of the gate driver 120. Figure 3 The gate clock signals GCK1 to GCK8 are applicable to display panels using amorphous silicon thin film transistor (TFT) substrates. The operating period of the gate clock signals for such display panels must include at least one horizontal line period corresponding to the data write cycle and one horizontal line period earlier as the time for pre-activating pixel switching. Therefore, the operating period of the gate clock signals GCK1 to GCK8 includes at least two horizontal line periods. Figure 3 The example given is that the output frame rate is 120Hz, the high refresh rate display area maintains a refresh rate of 120Hz, and the low refresh rate display area has a refresh rate of 60Hz. Under these conditions, a refresh cycle includes one full refresh frame cycle and one partial refresh frame cycle. Figure 3 The frame period shown on the left is the full refresh frame cycle (normal display frame). During the full refresh frame cycle, the reset pulse CLR first clears the scan pulses of all shift registers in the gate driver 120. Then, the controller 111 can provide the vertical start pulse STV and gate clock signals GCK1 to GCK8 to the gate driver 120. The operating duration of the gate clock signals GCK1 to GCK8 is the same in both the first part (corresponding to the high refresh rate display area) and the second part (corresponding to the low refresh rate display area) of the full refresh frame cycle. Based on the control of the controller 111, the gate driver 120 and the source driver 112 can completely refresh both the high refresh rate display area and the low refresh rate display area during the full refresh frame cycle. Therefore, the entire display area of ​​the display panel 130 can be refreshed normally during the full refresh frame cycle.

[0054] Figure 3The frame period shown on the right is the partial refresh frame cycle. During the partial refresh frame cycle, the gate driver 120 scans the high refresh rate display area but does not scan the low refresh rate display area. The controller 111 sends a native reset pulse CLR to the gate driver 120 at the first point in the partial refresh frame cycle. Then, during the first part of the partial refresh frame cycle (corresponding to the high refresh rate display area), the controller 111 continuously supplies gate clock signals GCK1 to GCK8 to the gate driver 120. The operating time of the gate clock signals GCK1 to GCK8 during this period has the same duration as the operating time of the gate clock signals GCK1 to GCK8 in the first part of the full refresh frame cycle. The controller 111 stops the switching behavior of the gate clock signals GCK1 to GCK8 in the second part of the partial refresh frame cycle (corresponding to the low refresh rate display area). In addition, the controller 111 also sends an additional reset pulse CLR to the gate driver 120 at the second point in the partial refresh frame cycle (the point corresponding to the adjacent position between the high refresh rate display area and the low refresh rate display area of ​​the display panel 130) to clear the scan pulses of the gate driver 120. Therefore, the scan pulse transmission of all shift registers in gate driver 120 is stopped, so that the low refresh rate display area is not refreshed during the local refresh frame cycle. In conjunction with the operating timing of gate driver 120, source driver 112 can refresh the high refresh rate display area in the first part of the local refresh frame cycle and stop refreshing the pixel data of the low refresh rate display area in the second part of the local refresh frame cycle.

[0055] In the second part of the local refresh frame cycle (corresponding to the low refresh rate display area), the source driver 112 may maintain the lowest gray level voltage (or other DC level) to the data lines of the display panel 130, or maintain a hi-Z impedance state to the data lines, or reduce the frequency of changes to the data lines, or the digital data path (digital domain circuit) inside the source driver 112 may enter a power saving mode.

[0056] The controller 111 generates gate clock signals GCK1 to GCK8, and the gate driver 120 uses gate clock signals GCK1 to GCK8 to generate scan signals to drive the high refresh rate display area and the low refresh rate display area of ​​the display panel 130. During a full refresh cycle, both the high refresh rate display area and the low refresh rate display area are refreshed, while during a partial refresh cycle, only the high refresh rate display area is refreshed. This allows the refresh rate of the low refresh rate display area of ​​the display panel 130 to differ from that of the high refresh rate display area. When the display partition frequency conversion function is enabled, if the boundary position between the high refresh rate display area and the low refresh rate display area remains unchanged, over time, the difference in stress effect experienced by the pixel switches (thin-film transistors) in the high refresh rate display area compared to the pixel switches in the low refresh rate display area will widen, leading to an unrecoverable problem of uneven brightness between the high refresh rate display area and the low refresh rate display area in the display panel 130.

[0057] Figure 4 This is a flowchart illustrating a display driving method according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 4 In step S410, the controller 111 generates a gate clock signal to control the gate driver 120 of the display panel 130. The display area of ​​the display panel 130 includes a high refresh rate display area and a low refresh rate display area. Both the high refresh rate and low refresh rate display areas are refreshed during a full refresh frame cycle, while only the high refresh rate display area is refreshed during a partial refresh frame cycle. The gate clock signal has different operating periods of different lengths in each time period corresponding to different refresh rate display areas during the full refresh frame cycle, or the gate clock signal has different amplitudes in each time period corresponding to different refresh rate display areas during the full refresh frame cycle. In step S420, the gate driver 120 uses the gate clock signal to generate multiple first scan signals and multiple second scan signals, wherein the first scan signals are used to drive multiple scan lines in the high refresh rate display area, and the second scan signals are used to drive multiple scan lines in the low refresh rate display area.

[0058] More specifically, in a refresh cycle comprising M full refresh frame cycles and N partial refresh frame cycles, the average value of multiple working periods of the gate clock signal (e.g., any one of GCK1 to GCK8) corresponding to the low refresh rate display area within the M full refresh frame cycles is controlled to be close to or equal to the average value of multiple working periods of the gate clock signal (e.g., any one of GCK1 to GCK8) corresponding to the high refresh rate display area within the M full refresh frame cycles and the average value of multiple working periods of the gate clock signal corresponding to the high refresh rate display area within the N partial refresh frame cycles. Alternatively, in a refresh cycle, the average amplitude of the gate clock signal corresponding to the low refresh rate display area within the M full refresh frame cycles is controlled to be greater than the average amplitude of the gate clock signal corresponding to the high refresh rate display area within the M full refresh frame cycles. Therefore, the degree of pixel aging due to pressure effect in display areas of different refresh rates can also be made similar, reducing the phenomenon of uneven brightness in display areas of different refresh rates. The following will illustrate the adjustment operation of the working periods of the gate clock signals GCK1 to GCK8 in the second part of the full refresh frame cycle with several implementation examples.

[0059] Figure 5 The diagram illustrates the gate clock signals GCK1 to GCK8 of the gate driver 120 according to another embodiment of the present invention. Figure 5 The horizontal axis represents time. Figure 5 The reset pulse CLR, vertical start pulse STV, gate clock signals GCK1~GCK8, full refresh frame period, and partial refresh frame period shown can be referenced. Figure 3 The relevant explanations are then drawn by analogy. Figure 5The gate clock signals GCK1 to GCK8 are suitable for display panels using amorphous silicon thin-film transistor substrates, and Figure 5 This describes a refresh cycle with an output frame rate of 120Hz, where the high refresh rate display area maintains a refresh rate of 120Hz while the low refresh rate display area has a refresh rate of 60Hz. It includes one full refresh frame cycle and one partial refresh frame cycle. When the display partition frequency conversion function is enabled, the controller 111 adds the active period of the gate clock signals GCK1 to GCK8 for the low refresh rate display area during the full refresh frame cycle. The gate clock signals GCK1 to GCK8 have a first active period in the first part of the full refresh frame cycle (corresponding to the high refresh rate display area of ​​the display panel 130), with a length of two horizontal line cycles. The first horizontal line cycle is the pre-on time, and the second horizontal line cycle corresponds to the data write cycle. The gate clock signals GCK1 to GCK8 have a second active period in the second part of the full refresh frame cycle (corresponding to the low refresh rate display area of ​​the display panel 130), which is longer than the first active period and has a length of four horizontal line cycles. The first three horizontal line cycles are the pre-on time, and the last horizontal line cycle corresponds to the data write cycle. In other words, the working period of gate clock signals GCK1 to GCK8 in the second part of the full refresh frame cycle (the second working period) is two horizontal line cycles longer than the working period in the first part of the full refresh frame cycle (the first working period), thus lengthening the pre-on time. Gate clock signals GCK1 to GCK8 have a third working period in the first part of the local refresh frame cycle (corresponding to the high refresh rate display area), with the same length as the first working period, also two horizontal line cycles. Furthermore, gate clock signals GCK1 to GCK8 stop switching in the second part of the local refresh frame cycle (corresponding to the low refresh rate display area). Based on the above settings, in Figure 5 In the refresh cycle shown, the average working period of the gate clock signals GCK1 to GCK8 corresponding to the low refresh rate display area is 2 horizontal line cycles. This is the result of dividing the aforementioned second working period (4 horizontal line cycles) by the total number of all full refresh frame cycles and all partial refresh frame cycles in the refresh cycle (2 frame cycles). Conversely, in Figure 5 The average operating period of the gate clock signals GCK1 to GCK8 corresponding to the high refresh rate display area in the refresh cycle shown is also two horizontal line cycles. Therefore, over time, the aging degree of the pixel switches in the high refresh rate display area and the low refresh rate display area due to stress effect will be similar, thereby reducing the phenomenon of uneven brightness.

[0060] Figure 6 This is a schematic diagram of the waveform of the scan signal of the gate driver 120 according to an embodiment of the present invention. Figure 6 The horizontal axis represents time. Figure 6 The reset pulse CLR, vertical start pulse STV, full refresh frame period, and partial refresh frame period shown can be referenced. Figure 5 The relevant explanations are provided and extrapolated. Gate driver 120 uses... Figure 5 The gate clock signals GCK1 to GCK8 shown generate multiple scan signals to multiple scan lines of the display panel 130 (e.g., Figure 2 and Figure 6 (as shown in GL1~GL12).

[0061] In a full refresh rate cycle, the high refresh rate display area includes scan lines GL1 to GL8, with the corresponding scan signal operating for two horizontal line cycles. The low refresh rate display area includes scan lines GL9, GL10, and subsequent scan lines, with the corresponding scan signal operating for four horizontal line cycles. Therefore, considering a refresh cycle comprising one full refresh rate cycle and one partial refresh rate cycle, the average operating time of the scan signal in the low refresh rate display area is the same as (similar to) that in the high refresh rate display area. When the average operating times of the gate clock signals GCK1 to GCK8 in the high refresh rate and low refresh rate display areas are the same or close, the difference in pixel switching aging caused by stress effects in different display areas can be effectively reduced, thereby mitigating brightness unevenness.

[0062] Figure 7 The diagram illustrates the gate clock signals GCK1 to GCK8 of the gate driver 120 according to another embodiment of the present invention. Figure 7 The horizontal axis represents time. Figure 7 The reset pulse CLR, vertical start pulse STV, gate clock signals GCK1~GCK8, full refresh frame period, and partial refresh frame period shown can be referenced. Figure 3 The relevant explanations are then drawn by analogy. Figure 7 The gate clock signals GCK1 to GCK8 are suitable for display panels using amorphous silicon thin-film transistor (TFT) substrates, and Figure 7This describes a refresh cycle with an output frame rate of 120Hz, where the high refresh rate display area maintains a refresh rate of 120Hz while the low refresh rate display area has a refresh rate of 60Hz. It includes a full refresh frame cycle and a partial refresh frame cycle. When the display partition frequency conversion function is enabled, the controller 111 increases the operating time of the gate clock signals GCK1 to GCK8 in the second part of the full refresh frame cycle (corresponding to the low refresh rate display area), causing the gate clock signals GCK1 to GCK8 to have a second operating time in the second part of the full refresh frame cycle that is longer than the first operating time. Therefore, in one refresh cycle, the average operating time of the gate clock signals GCK1 to GCK8 in the low refresh rate display area can be close to the average operating time of the gate clock signals GCK1 to GCK8 in the high refresh rate display area.

[0063] exist Figure 7 In the full refresh frame cycle shown, the gate clock signals GCK1 to GCK8 operate for two horizontal line cycles in the high refresh rate display area. The first horizontal line cycle is the pre-enable time, and the second horizontal line cycle corresponds to the data write cycle. Figure 7 In the full refresh frame cycle shown, the gate clock signals GCK1 to GCK8 have an additional horizontal line cycle in the second part of the full refresh frame cycle (corresponding to the low refresh rate display area), and this addition is within the pre-on time (indicated by a slash), meaning the pre-on time is increased to 2 horizontal line cycles. This makes the total working time of gate clock signals GCK1 to GCK8 in the second part of the full refresh frame cycle 3 horizontal line cycles. Figure 7 As shown in the refresh cycle, the average operating time of the gate clock signals GCK1 to GCK8 corresponding to the low refresh rate display area is 1.5 horizontal line cycles, which is similar to the average operating time of the gate clock signals GCK1 to GCK8 corresponding to the high refresh rate display area (2 horizontal line cycles). Although not exactly equal, they are similar. Figure 3 The results shown are better when the working periods of gate clock signals GCK1 to GCK8 are not adjusted in the second part of the full refresh rate cycle (corresponding to the low refresh rate display area). When the average working periods of gate clock signals GCK1 to GCK8 in the high refresh rate display area and the low refresh rate display area are close to each other, the difference in the degree of aging of panel pixel switching can be effectively reduced, thereby reducing the phenomenon of uneven brightness.

[0064] The number of full refresh frame cycles and partial refresh frame cycles included in the refresh cycle is determined by the output frame rate (equal to the maximum refresh rate) and the refresh rate of the low refresh rate display area. Therefore, in this embodiment of the invention, the working period of the gate clock signal in the second part of the full refresh frame cycle (corresponding to the low refresh rate display area) should be longer than the working period of the gate clock signal in the first part of the full refresh frame cycle (corresponding to the high refresh rate display area). This is determined based on the number of full refresh frame cycles, the number of partial refresh frame cycles, and the adjusted target average working period in the refresh cycle. Furthermore, this embodiment of the invention is not limited to the type of substrate of the display surface. For example, it is also applicable to display panels using low-temperature polycrystalline silicon (LTPS) thin-film transistor substrates, where the working period of the gate clock signal originally did not require pre-activation of pixel switches, but only corresponded to the data writing cycle. Taking a refresh cycle with the high refresh rate display area maintaining a refresh rate of 120Hz and the low refresh rate display area having a refresh rate of 60Hz as an example, according to an embodiment of the present invention, the gate clock signal used to drive the LTPS TFT display panel has a first working period of 1 horizontal line cycle in the first part of the full refresh frame cycle (corresponding to the high refresh rate display area), and the gate clock signal has a second working period of 2 horizontal line cycles in the second part of the full refresh frame cycle (corresponding to the low refresh rate display area). The later horizontal line cycle corresponds to the data writing cycle, and the earlier horizontal line cycle is used to lengthen the on-time of the pixel switch. In this way, in one refresh cycle, the average working period of the gate clock signal corresponding to the low refresh rate display area is 1 horizontal line cycle, which is the result of dividing the aforementioned second working period (2 horizontal line cycles) by the total number of all full refresh frame cycles and all partial refresh frame cycles in the refresh cycle (2 frame cycles), which is equal to the average working period of the gate clock signal corresponding to the high refresh rate display area (1 horizontal line cycle). Figure 8 The diagram illustrates the gate clock signals GCK1 to GCK8 of the gate driver 120 according to a further embodiment of the present invention. Figure 8 The horizontal axis represents time. Figure 8 The reset pulse CLR, vertical start pulse STV, gate clock signals GCK1~GCK8, full refresh frame period, and partial refresh frame period shown can be referenced. Figure 3The relevant explanations are explained and extrapolated. When the display zone frequency conversion function is enabled, the controller 111 increases the amplitude (swing) of the gate clock signals GCK1 to GCK8 in the second part of the full refresh frame cycle (corresponding to the low refresh rate display area). The gate clock signals GCK1 to GCK8 have a first amplitude in the first part of the full refresh frame cycle (this first part corresponds to the high refresh rate display area of ​​the display panel 130), while the gate clock signals GCK1 to GCK8 have a second amplitude greater than the first amplitude in the second part of the full refresh frame cycle. The gate clock signals GCK1 to GCK8 have the first amplitude in the first part of the partial refresh frame cycle (this first part corresponds to the high refresh rate display area of ​​the display panel 130), while the gate clock signals GCK1 to GCK8 are maintained at a certain inactive voltage level (e.g., low logic level VGL) in the second part of the partial refresh frame cycle (corresponding to the low refresh rate display area of ​​the display panel 130). Figure 8 In the illustrated embodiment, the first amplitude is from low logic level VGL to high logic level VGH (gate clock signals GCK1 to GCK8 switch between low logic level VGL and high logic level VGH), while the second amplitude is from low logic level VGL' to high logic level VGH' (gate clock signals GCK1 to GCK8 switch between low logic level VGL' and high logic level VGH'), where VGH' > VGH and VGL' < VGL. The actual levels of VGH, VGL, VGH', and VGL' can be determined according to the actual design and application. Therefore, in the full refresh frame cycle and the partial refresh frame cycle, the average amplitude of the gate clock signals GCK1 to GCK8 corresponding to the low refresh rate display area can be close to the average amplitude of the gate clock signals GCK1 to GCK8 corresponding to the high refresh rate display area.

[0065] The high and low levels of the scan signal are determined by the high and low logic levels of the gate clock signals GCK1 to GCK8 input to the shift register of the gate driver 120. When the display zone frequency conversion function is enabled, the controller 111 increases the amplitude of the gate clock signals GCK1 to GCK8 in the second part of the full refresh frame cycle (corresponding to the low refresh rate display area), which helps to reduce the difference in aging degree of the TFTs in the high refresh rate area and the low refresh rate area due to the stress effect in the long run.

[0066] Increasing the amplitude of gate clock signals GCK1 to GCK8 can be achieved by increasing the high logic level of GCK1 to GCK8, decreasing the low logic level of GCK1 to GCK8, or adjusting both. In this embodiment, although the average operating periods of gate clock signals GCK1 to GCK8 in the high refresh rate display area and the low refresh rate display area are not consistent, increasing the amplitude of gate clock signals GCK1 to GCK8 during the low refresh rate display area helps to appropriately accelerate pixel aging. On average, pixel aging in the high refresh rate display area and the low refresh rate display area can tend to be consistent. Therefore, increasing the amplitude of gate clock signals GCK1 to GCK8 in the second part of the full refresh frame cycle (corresponding to the low refresh rate display area) can reduce the degree of pixel aging difference between the high and low refresh rate display areas, thereby mitigating the phenomenon of uneven brightness.

[0067] Figure 9 The diagram illustrates the gate clock signals GCK1 to GCK8 of the gate driver 120 according to another embodiment of the present invention. Figure 9 The horizontal axis represents time. Figure 9 The reset pulse CLR, vertical start pulse STV, gate clock signals GCK1~GCK8, full refresh frame period, and partial refresh frame period shown can be referenced. Figure 3 The relevant explanations are then drawn by analogy. When the display zone frequency conversion function is enabled, the controller 111 increases the amplitude of the gate clock signals GCK1 to GCK8 in the second part of the full refresh frame cycle (corresponding to the low refresh rate display area). Gate clock signals GCK1 to GCK8 have a first amplitude in the first part of the full refresh frame cycle (this first part corresponds to the high refresh rate display area of ​​the display panel 130), while gate clock signals GCK1 to GCK8 have a second amplitude greater than the first amplitude in the second part of the full refresh frame cycle. Figure 9 In the illustrated embodiment, the first amplitude is from low logic level VGL to high logic level VGH, while the second amplitude is from VGL to high logic level VGH', where VGH' > VGH.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display driver chip, characterized in that, The display driver chip includes: The controller is configured to generate a gate clock signal to control the gate driver of the display panel, wherein the display area of ​​the display panel includes a high refresh rate display area and a low refresh rate display area, both of which are refreshed during a full refresh frame cycle, while only the high refresh rate display area is refreshed during a partial refresh frame cycle. The gate driver uses the gate clock signal to generate multiple first scan signals to drive multiple scan lines in the high refresh rate display area, and generates multiple second scan signals to drive multiple scan lines in the low refresh rate display area; and The gate clock signal has a first working period in the first part of the full refresh frame cycle, the first part of the full refresh frame cycle corresponding to the high refresh rate display area. The gate clock signal has a second working period in the second part of the full refresh frame cycle that is longer than the first working period, the second part of the full refresh frame cycle corresponding to the low refresh rate display area.

2. The display driver chip according to claim 1, characterized in that, The gate clock signal has a third time period of the same length as the first working time period in the first part of the local refresh frame cycle, the first part of the local refresh frame cycle corresponds to the high refresh rate display area, and the gate clock signal stops switching in the second part of the local refresh frame cycle, the second part of the local refresh frame cycle corresponds to the low refresh rate display area.

3. The display driver chip according to claim 2, characterized in that, The controller is configured to output a reset pulse and an additional reset pulse to the gate driver during the local refresh frame period; as well as Within the local refresh frame cycle, the reset pulse occurs before the multiple gate clock signals begin switching, and the additional reset pulse occurs after the multiple gate clock signals stop switching.

4. The display driver chip according to claim 2, characterized in that, In a refresh cycle consisting of M full refresh frame cycles and N local refresh frame cycles, where M and N are at least one, the average value of multiple working periods of the gate clock signal corresponding to the low refresh rate display area within the M full refresh frame cycles is close to or equal to the average value of multiple working periods of the gate clock signal corresponding to the high refresh rate display area within the M full refresh frame cycles and the average value of multiple working periods of the gate clock signal corresponding to the high refresh rate display area within the N local refresh frame cycles.

5. A display driver chip, characterized in that, The display driver chip includes: The controller is configured to output a gate clock signal to control the gate driver of the display panel, wherein the display area of ​​the display panel includes a high refresh rate display area and a low refresh rate display area, both of which are refreshed during a full refresh frame cycle, while only the high refresh rate display area is refreshed during a partial refresh frame cycle. The gate driver uses the gate clock signal to generate a plurality of first scan signals to drive a plurality of scan lines in the high refresh rate display area, and generates a plurality of second scan signals to drive a plurality of scan lines in the low refresh rate display area; and The gate clock signal has a first amplitude in the first part of the full refresh frame cycle, the first part of the full refresh frame cycle corresponding to the high refresh rate display area, and the gate clock signal has a second amplitude greater than the first amplitude in the second part of the full refresh frame cycle, the second part of the full refresh frame cycle corresponding to the low refresh rate display area.

6. The display driver chip according to claim 5, characterized in that, The gate clock signal has a third amplitude that is the same as the first amplitude in the first part of the local refresh frame cycle, the first part of the local refresh frame cycle corresponding to the high refresh rate display area, while the gate clock signal remains at an ineffective voltage level in the second part of the local refresh frame cycle, the second part of the local refresh frame cycle corresponding to the low refresh rate display area.

7. The display driver chip according to claim 5, characterized in that, The gate clock signal switches between low and high logic levels, and During the full refresh frame cycle, the low logic level of the gate clock signal corresponding to the low refresh rate display area is lower than the low logic level of the gate clock signal corresponding to the high refresh rate display area.

8. The display driver chip according to claim 5, characterized in that, The gate clock signal switches between low and high logic levels, and During the full refresh frame cycle, the high logic level of the gate clock signal corresponding to the low refresh rate display area is higher than the high logic level of the gate clock signal corresponding to the high refresh rate display area.

9. A display device, characterized in that, The display device includes: The display panel includes: The effective display area includes both high refresh rate and low refresh rate display areas; and A gate driver, configured to generate a plurality of first scan signals driving a plurality of scan lines in the high refresh rate display area and a plurality of second scan signals driving a plurality of scan lines in the low refresh rate display area; and Display driver chips include: The controller is configured to generate a gate clock signal to control the gate driver of the display panel, wherein both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame cycle, while only the high refresh rate display area is refreshed during a partial refresh frame cycle. The gate driver uses the gate clock signal to generate the plurality of first scan signals and the plurality of second scan signals; and The gate clock signal has a first working period in the first part of the full refresh frame cycle, the first part of the full refresh frame cycle corresponding to the high refresh rate display area. The gate clock signal has a second working period in the second part of the full refresh frame cycle that is longer than the first working period, the second part of the full refresh frame cycle corresponding to the low refresh rate display area.

10. The display device according to claim 9, characterized in that, The gate clock signal has a third time period of the same length as the first working time period in the first part of the local refresh frame cycle, the first part of the local refresh frame cycle corresponds to the high refresh rate display area, and the gate clock signal stops switching in the second part of the local refresh frame cycle, the second part of the local refresh frame cycle corresponds to the low refresh rate display area.

11. The display device according to claim 10, characterized in that, The controller is configured to output a reset pulse and an additional reset pulse to the gate driver during the local refresh frame period; as well as Within the local refresh frame cycle, the reset pulse occurs before the multiple gate clock signals begin switching, and the additional reset pulse occurs after the multiple gate clock signals stop switching.

12. The display device according to claim 10, characterized in that, In a refresh cycle consisting of M full refresh frame cycles and N local refresh frame cycles, where M and N are at least one, the average value of multiple working periods of the gate clock signal corresponding to the low refresh rate display area within the M full refresh frame cycles is close to or equal to the average value of multiple working periods of the gate clock signal corresponding to the high refresh rate display area within the M full refresh frame cycles and the average value of multiple working periods of the gate clock signal corresponding to the high refresh rate display area within the N local refresh frame cycles.

13. A display device, characterized in that, The display device includes: The display panel includes: The effective display area includes both high refresh rate and low refresh rate display areas; and A gate driver, configured to generate a plurality of first scan signals driving a plurality of scan lines in the high refresh rate display area and a plurality of second scan signals driving a plurality of scan lines in the low refresh rate display area; and Display driver chips include: The controller is configured to output a gate clock signal to control the gate driver of the display panel, wherein both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame cycle, while only the high refresh rate display area is refreshed during a partial refresh frame cycle. The gate driver uses the gate clock signal to generate the plurality of first scan signals and the plurality of second scan signals; and The gate clock signal has a first amplitude in the first part of the full refresh frame cycle, the first part of the full refresh frame cycle corresponding to the high refresh rate display area, and the gate clock signal has a second amplitude greater than the first amplitude in the second part of the full refresh frame cycle, the second part of the full refresh frame cycle corresponding to the low refresh rate display area.

14. The display device according to claim 13, characterized in that, The gate clock signal has a third amplitude that is the same as the first amplitude in the first part of the local refresh frame cycle, the first part of the local refresh frame cycle corresponding to the high refresh rate display area, while the gate clock signal remains at an ineffective voltage level in the second part of the local refresh frame cycle, the second part of the local refresh frame cycle corresponding to the low refresh rate display area.

15. The display device according to claim 13, characterized in that, The gate clock signal switches between low and high logic levels, and During the full refresh frame cycle, the low logic level of the gate clock signal corresponding to the low refresh rate display area is lower than the low logic level of the gate clock signal corresponding to the high refresh rate display area.

16. The display device according to claim 13, characterized in that, The gate clock signal switches between low and high logic levels, and During the full refresh frame cycle, the high logic level of the gate clock signal corresponding to the low refresh rate display area is higher than the high logic level of the gate clock signal corresponding to the high refresh rate display area.

17. A display driving method, characterized in that, The display driving method includes: A gate clock signal is generated to control the gate driver of the display panel, wherein the display area of ​​the display panel includes a high refresh rate display area and a low refresh rate display area. During the full refresh frame cycle, both the high refresh rate display area and the low refresh rate display area are refreshed, while during the partial refresh frame cycle, only the high refresh rate display area is refreshed. The gate driver uses the gate clock signal to generate a plurality of first scan signals to drive a plurality of scan lines in the high refresh rate display area, and generates a plurality of second scan signals to drive a plurality of scan lines in the low refresh rate display area; and The gate clock signal has different operating periods in each time period of the full refresh frame cycle, or the gate clock signal has different amplitudes in each time period of the full refresh frame cycle.

18. The display driving method according to claim 17, characterized in that, The gate clock signal has a first working period in the first part of the full refresh frame cycle, the first part of the full refresh frame cycle corresponding to the high refresh rate display area. The gate clock signal has a second working period in the second part of the full refresh frame cycle that is longer than the first working period, the second part of the full refresh frame cycle corresponding to the low refresh rate display area.

19. The display driving method according to claim 17, characterized in that, The gate clock signal has a first amplitude in the first part of the full refresh frame cycle, the first part of the full refresh frame cycle corresponding to the high refresh rate display area, and the gate clock signal has a second amplitude greater than the first amplitude in the second part of the full refresh frame cycle, the second part of the full refresh frame cycle corresponding to the low refresh rate display area.

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