A Method and System for Calculating the Anti-interference Count of BLDC Motors Based on Dynamic Time Window Verification

Abstract

This invention discloses a method and system for calculating the number of revolutions in a BLDC motor based on dynamic time window verification, belonging to the field of motor control technology. The method includes: acquiring Hall sensor signals from the BLDC motor and performing edge detection and debouncing processing to generate Hall transition edges; obtaining the current period by measuring the time interval between adjacent valid Hall transition edges based on the system clock; calculating the lower and upper bounds of the dynamic time window based on the current period and a dynamic adjustment coefficient; and performing three-level pulse discrimination based on the relationship between the arrival time of the Hall transition edge and the dynamic time window: triggering revolution count accumulation when the pulse is determined to be valid, blocking the pulse when it is determined to be a glitch pulse, and generating a compensation pulse and triggering revolution count accumulation when the pulse is determined to be lost. This invention solves the problems of insufficient anti-interference capability and lack of signal loss compensation mechanism in existing technologies under variable speed conditions and strong electromagnetic interference environments, significantly improving the accuracy and reliability of revolution count calculation.

Description

Technical Field

[0001] This invention belongs to the field of motor control technology, specifically relating to a method and system for calculating the number of revolutions of a BLDC motor based on dynamic time window verification. It is applicable to industrial control, servo systems and precision motion control fields where high rotor position accuracy of brushless DC motors is required. Background Technology

[0002] With the rapid development of industrial automation and intelligent manufacturing technologies, brushless DC motors (BLDC motors) are widely used in CNC machine tools, industrial robots, and precision positioning systems due to their high efficiency, long lifespan, and excellent control performance. In these applications, accurately calculating the number of motor rotations is a fundamental prerequisite for achieving precise positioning and motion control.

[0003] Currently, the rotation count of BLDC motors mainly relies on pulse signals generated by Hall sensors. However, in actual industrial applications, strong electromagnetic interference often exists around the motor. This interference can cause glitches, jitter, or loss of signals from the Hall sensors, directly leading to incorrect rotation counts. Existing anti-interference methods mainly include the following categories, but each has its limitations to varying degrees.

[0004] The first type is the hardware RC filtering method. This method suppresses high-frequency noise by adding an RC low-pass filter circuit to the Hall sensor signal line. However, the cutoff frequency of the RC filter is fixed and cannot be adaptively adjusted according to changes in motor speed. It may filter out normal signals at high speeds, but it cannot effectively filter out low-frequency interference signals at low speeds.

[0005] The second type is the software-based fixed-threshold debouncing method. This method sets a fixed time delay in the microcontroller to eliminate signal jitter. However, because the threshold is fixed, misjudgments are prone to occur during motor acceleration and deceleration—legitimate pulses may be misjudged as interference due to shortened intervals during acceleration, while interference pulses may be misjudged as valid signals due to increased intervals during deceleration. Furthermore, software-based debouncing methods are limited by the microcontroller's processing speed, resulting in insufficient time resolution in high-speed scenarios, making it difficult to meet the requirements for accurate counting.

[0006] The third type is the fixed time window method. This method sets a fixed time range as the criterion for judging the validity of the pulse. However, the fixed window cannot adapt to the variable speed operation of the motor, and it lacks an effective compensation mechanism when the signal is completely lost, resulting in a permanent deviation in the cumulative number of revolutions.

[0007] In summary, existing technologies lack a revolution calculation scheme that can adaptively adjust the discrimination parameters based on the real-time speed of the motor while possessing a complete signal loss compensation capability. Summary of the Invention

[0008] The purpose of this invention is to provide a method and system for calculating the number of revolutions of a BLDC motor based on dynamic time window verification, so as to solve the technical problems of insufficient anti-interference capability, lack of dynamic adaptability, and lack of effective compensation mechanism when signal is lost in existing BLDC motor revolution calculation methods under strong electromagnetic interference environment and variable speed operation.

[0009] To achieve the above-mentioned objectives, the technical solution provided by this invention includes:

[0010] A method for calculating the anti-interference effect of BLDC motor revolutions based on dynamic time window verification includes:

[0011] Collect Hall sensor signals from the BLDC motor, perform edge detection and debouncing processing, and generate Hall transition edges;

[0012] The current period is obtained by measuring the time interval between adjacent valid Hall transition edges based on the system clock.

[0013] Based on the current period and the dynamic adjustment coefficient, calculate the lower and upper bounds of the dynamic time window;

[0014] Pulse discrimination is performed based on the relationship between the arrival time of the Hall transition edge and the dynamic time window. When a pulse is determined to be valid, the number of cycles accumulated is incremented. When a pulse is determined to be a glitch, the pulse is blocked. When a signal is determined to be lost, a compensation pulse is generated and the number of cycles accumulated is incremented.

[0015] Preferably, the formula for calculating the lower bound of the window is: lower bound of the window = current period × (1 - dynamic adjustment coefficient), and the formula for calculating the upper bound of the window is: upper bound of the window = current period × (1 + dynamic adjustment coefficient).

[0016] Preferably, the dynamic adjustment coefficient is adjusted in stages according to the speed range of the BLDC motor's operating speed. The lower the speed, the larger the dynamic adjustment coefficient, and the higher the speed, the smaller the dynamic adjustment coefficient. The value range of the dynamic adjustment coefficient is 0.05 to 0.5.

[0017] Preferably, in the pulse discrimination step, the parameters of the current period and the dynamic time window are updated only when the pulse is determined to be valid; when the pulse is determined to be a glitch, the parameters of the current period and the dynamic time window are kept unchanged and the pulse is blocked; when the pulse is determined to be lost, the parameters of the current period and the dynamic time window are kept unchanged and the compensation pulse is generated.

[0018] Preferably, the edge detection is performed by performing a logical OR operation on each phase of the Hall sensor signal, and the pulse discrimination is triggered when any phase signal changes.

[0019] Preferably, it also includes an initialization phase, in which the pulse discrimination is not performed within the first complete pulse cycle after the system is powered on or reset, and the first complete pulse cycle is used as the initial value of the current cycle.

[0020] Preferably, the method further includes setting an upper limit threshold for the number of consecutive triggers of the compensation pulse. When the number of consecutively generated compensation pulses exceeds the upper limit threshold, the BLDC motor is determined to stop and the generation of compensation pulses is stopped.

[0021] Preferably, the method is implemented based on an FPGA hardware parallel processing architecture. The edge detection and debouncing processing, the measurement of the current cycle, the calculation of the dynamic time window, and the pulse discrimination are each executed in parallel by independent hardware logic units. Each hardware logic unit shares a system clock, and the frequency of the system clock is not less than 50MHz.

[0022] This invention also discloses a BLDC motor revolution count anti-interference calculation system based on dynamic time window verification, comprising:

[0023] The signal acquisition module is used to acquire Hall sensor signals from the BLDC motor, perform edge detection and debouncing, and generate Hall transition edges.

[0024] The time measurement module is used to measure the time interval between two adjacent valid Hall transition edges based on the system clock to obtain the current period;

[0025] The window calculation module is used to calculate the dynamic time window based on the current period and the dynamic adjustment coefficient;

[0026] The decision logic module is used to determine whether the Hall transition edge is a valid pulse, a glitch pulse, or a signal loss based on the relationship between the arrival time of the Hall transition edge and the dynamic time window.

[0027] The pulse compensation module is used to generate a compensation pulse when the signal is determined to be lost.

[0028] The counting and accumulating module is used to trigger the incrementing of the cycle count register when the pulse is determined to be valid or when the compensation pulse is generated.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) By using a dynamic time window verification mechanism, the pulse discrimination time range is adaptively adjusted according to the current cycle, which can accurately distinguish between effective pulses and interference signals under variable speed conditions such as motor acceleration and deceleration. Compared with the fixed threshold method, it significantly improves the anti-interference capability under variable speed conditions.

[0031] (2) By using a three-level pulse discrimination logic to classify Hall transition edges into valid pulses, glitch pulses and signal loss, a differentiated response strategy for different types of interference is realized, avoiding the accuracy loss caused by simply shielding or accepting all interference signals.

[0032] (3) By using the compensation pulse generation mechanism, virtual pulses are actively generated to compensate for the number of revolutions when signal loss is detected, so as to prevent permanent deviation in the number of revolutions caused by a single signal loss and ensure the continuity of the number of revolutions calculation.

[0033] (4) By updating the parameters of the dynamic time window only during valid pulses, interference signals and compensation signals are avoided from polluting the window parameters, thus preventing the error from spreading in subsequent discrimination processes. Attached Figure Description

[0034] Figure 1 This is a flowchart illustrating a preferred embodiment of the BLDC motor revolution count anti-interference calculation method based on dynamic time window verification provided by the present invention.

[0035] Figure 2 This is a schematic diagram of the structure of a BLDC motor revolution anti-interference calculation system based on dynamic time window verification provided in a preferred embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the scope of protection of the present invention.

[0037] Example 1

[0038] like Figure 1 As shown, this embodiment provides a method for calculating the anti-interference effect of BLDC motor revolution count based on dynamic time window verification. The core idea of ​​this method is: to accurately measure the pulse interval of the Hall sensor signal using a high-frequency system clock, dynamically calculate an expected time window based on the current pulse period, and then use this window to determine the validity of subsequently detected pulses—pulses falling within the window are identified as valid signals and their revolution counts are accumulated; pulses arriving before the lower boundary of the window are identified as electromagnetic interference glitches and shielded; and pulses arriving after exceeding the upper boundary of the window are determined to be signal loss and trigger a compensation mechanism. The method includes the following steps:

[0039] Step S1: Signal Acquisition and Preprocessing. Acquire the Hall sensor signal from the BLDC motor, perform edge detection and debouncing processing, and generate Hall transition edges.

[0040] Hall sensor signals can be two-phase, three-phase, or more phase signals, depending on the motor's structure and application requirements. In this embodiment, the BLDC motor is equipped with three-phase Hall sensors, corresponding to the motor's three phases (typically labeled Hall_W, Hall_V, and Hall_U). The three-phase Hall sensor signals are input to the signal acquisition module via the FPGA's GPIO pins. To obtain sufficient time resolution, this embodiment uses a 100MHz system clock as the time base, corresponding to a time resolution of 10 nanoseconds.

[0041] Edge detection is implemented by comparing the current Hall signal value with the previous Hall signal value at the rising edge of each system clock. When they differ, it indicates a level transition in the Hall signal of that phase, and a Hall transition edge pulse is generated. In some preferred embodiments, edge detection further includes performing a logical OR operation on each phase of the Hall sensor signal, triggering pulse discrimination when any phase signal transitions. This method has the advantage of capturing transition events in all phases, improving the integrity of signal detection, and is not limited by the number of Hall sensor phases. In this embodiment, the BLDC motor is equipped with a three-phase Hall sensor. The three-phase Hall sensor signals (Hall_W, Hall_V, Hall_U) are each independently edge-detected, and the transition detection pulses of the three phases are combined into a unified Hall transition edge signal through a logical OR operation. In other application scenarios, for motors equipped with two-phase or four-phase Hall sensors, the above logical OR operation method can also be used to perform edge detection on each phase signal. It should be understood that, in addition to logic or method, edge detection can also be performed only on single-phase Hall signals, or multi-phase signals can be detected after weighted combination. The specific choice depends on the application scenario's requirements for balancing detection sensitivity and anti-interference performance.

[0042] Debouncing is a pre-processing step in edge detection. In real-world electromagnetic interference environments, Hall sensor signals may experience brief jitters during level transitions, manifesting as the signal rapidly switching between high and low levels several times before stabilizing. To avoid misinterpreting these jitters as multiple transitions, debouncing requires that the detected level change be sustained for several system clock cycles before being recognized as a valid transition. At a 100MHz system clock, a typical debouncing time is set to 2-5 clock cycles (i.e., 20-50 nanoseconds). This time window is sufficient to filter out most false transitions caused by signal jitter without significantly delaying the detection of normal signals.

[0043] Step S2: Current cycle measurement. The current cycle is obtained by measuring the time interval between adjacent valid Hall transition edges based on the system clock.

[0044] After detecting a valid Hall effect transition edge, the signal acquisition module reads the current value of a continuously incrementing time counter. This time counter is driven by the system clock and increments by 1 every clock cycle. By subtracting the counter value recorded at the time of the last valid Hall effect transition edge from the currently read counter value, the time interval between two valid transitions, i.e., the current period, can be obtained.

[0045] Taking a 100MHz system clock as an example, the time counter uses a 32-bit width, with a maximum count value of 4,294,967,295, corresponding to a maximum measurable time of approximately 42.9 seconds. In typical BLDC motor applications, even at extremely low speeds (e.g., 1 RPM), a single Hall pulse cycle will not exceed 10 seconds (taking 6 Hall pulses per revolution as an example, 1 RPM corresponds to approximately 10 seconds / pulse), therefore a 32-bit counter fully meets the requirements.

[0046] It is important to note that a "valid Hall transition edge" refers to a transition edge that is confirmed as a valid pulse after pulse discrimination in subsequent step S4. During the execution of step S2, the system uses the previously determined valid transition edge as the time reference. This means that if a transition edge is determined to be a glitch in the middle, that glitch transition edge will not be used as the time reference, thereby avoiding interference signals from contaminating the period measurement.

[0047] Step S3: Calculate the dynamic time window. Based on the current period and the dynamic adjustment coefficient, calculate the lower and upper bounds of the dynamic time window.

[0048] The dynamic time window is one of the core innovations of this invention. Traditional fixed-threshold debouncing methods use a pre-set fixed time value as the criterion for judging pulse validity, but this fixed value cannot adapt to real-time changes in motor speed. In contrast, the dynamic time window of this invention is calculated based on the currently measured pulse period, allowing the judgment criterion to adaptively adjust with changes in motor speed.

[0049] The formulas for calculating the lower and upper bounds of a window are:

[0050] Lower bound of the window = current period × (1 - dynamic adjustment coefficient)

[0051] Upper bound of the window = current period × (1 + dynamic adjustment coefficient)

[0052] The dynamic adjustment coefficient is a parameter ranging from 0 to 1, used to control the width of the dynamic time window. A larger dynamic adjustment coefficient results in a wider window, increasing tolerance for pulse arrival time fluctuations but decreasing sensitivity to interference detection; conversely, a smaller dynamic adjustment coefficient results in a narrower window, increasing sensitivity to interference detection but decreasing tolerance to normal pulse period fluctuations.

[0053] In some preferred embodiments, the dynamic adjustment coefficient is further adjusted in stages according to the speed range of the BLDC motor's operating speed. The lower the speed, the larger the dynamic adjustment coefficient, and the higher the speed, the smaller the dynamic adjustment coefficient. The value range of the dynamic adjustment coefficient is 0.05 to 0.5. The technical reason for this design is that when running at low speed, the Hall pulse period is relatively long, and the motor speed fluctuation is relatively large (e.g., caused by load changes). Therefore, a larger dynamic adjustment coefficient is needed to obtain a wider window and avoid misjudging normal periodic fluctuations as interference. When running at high speed, the Hall pulse period is short, and the motor speed is relatively stable. At this time, a smaller dynamic adjustment coefficient is needed to obtain a narrower window and improve the sensitivity to interference signals.

[0054] In this embodiment, a three-level adjustment strategy is adopted: a dynamic adjustment coefficient of 0.3 is used in low-speed mode (speed below 1000 RPM), a dynamic adjustment coefficient of 0.2 is used in medium-speed mode (speed between 1000 RPM and 5000 RPM), and a dynamic adjustment coefficient of 0.1 is used in high-speed mode (speed above 5000 RPM). The specific values ​​are selected based on the following: 0.3 corresponds to a window width of 60% of the current cycle, which can fully accommodate the maximum ±30% speed fluctuation caused by sudden load changes at low speeds; 0.2 corresponds to a window width of 40% of the current cycle, which is suitable for the typical ±15% speed fluctuation range under medium-speed conditions; and 0.1 corresponds to a window width of 20% of the current cycle, which can effectively identify interference pulses outside the window under high-speed steady-state conditions. It should be understood that the above three-level gearing strategy and specific coefficient values ​​and speed thresholds are only preferred implementation methods. In practical applications, they can be flexibly adjusted according to motor characteristics and interference environment. For example, a gearing strategy with more gears (such as five or seven gears) can be adopted, or a continuous adaptive algorithm can be used instead of discrete gearing, as long as the trend relationship of the coefficient being larger at lower speeds and smaller at higher speeds is satisfied, and the coefficient value is kept within the range of 0.05 to 0.5.

[0055] Let's take a specific numerical example to illustrate the behavior of the dynamic time window at different speeds:

[0056] Under low-speed conditions, assuming a motor speed of 300 RPM and 6 Hall pulses per revolution, the theoretical period of a Hall pulse is approximately 33,333 microseconds. In this case, the dynamic adjustment coefficient is set to 0.3 (low-speed mode), the lower bound of the window is 33,333 × (1 - 0.3) = 23,333 microseconds, and the upper bound is 33,333 × (1 + 0.3) = 43,333 microseconds. The window width is 20,000 microseconds. This wider window can accommodate pulse period changes caused by load fluctuations during low-speed operation, avoiding misinterpreting normal speed fluctuations as interference.

[0057] Under medium-speed conditions, assuming a motor speed of 2000 RPM, the theoretical period of the Hall pulse is approximately 5000 microseconds. With a dynamic adjustment coefficient of 0.2 (medium-speed mode), the lower bound of the window is 5000 × (1 - 0.2) = 4000 microseconds, and the upper bound is 5000 × (1 + 0.2) = 6000 microseconds. The window width is 2000 microseconds. This moderately wide window strikes a balance between anti-interference capability and speed fluctuation tolerance.

[0058] Under high-speed conditions, assuming a motor speed of 6000 RPM, the theoretical period of the Hall pulse is approximately 1667 microseconds. With a dynamic adjustment coefficient of 0.1 (high-speed mode), the lower bound of the window is 1667 × (1 - 0.1) = 1500 microseconds, and the upper bound is 1667 × (1 + 0.1) = 1834 microseconds. The window width is only 334 microseconds. This narrower window allows for accurate identification of interference pulses during high-speed operation because the periodic fluctuation range of normal pulses is already very small at high speeds, eliminating the need for an excessively wide window.

[0059] As can be seen from the three numerical examples above, the adaptive adjustment mechanism of the dynamic time window enables the system to automatically obtain appropriate discrimination sensitivity at different rotational speeds, without manual intervention or pre-configuration of fixed parameters. This is precisely the fundamental advantage of this invention over the fixed threshold method.

[0060] Step S4: Pulse discrimination and processing. Pulse discrimination is performed based on the relationship between the arrival time of the Hall transition edge and the dynamic time window. This step is the decision-making center of the entire method.

[0061] In some preferred embodiments, during the pulse discrimination step, the parameters of the current period and dynamic time window are updated only when the pulse is determined to be valid. When the pulse is determined to be a glitch, the parameters of the current period and dynamic time window remain unchanged and the pulse is masked. When the pulse is determined to be lost, the parameters of the current period and dynamic time window remain unchanged and a compensation pulse is generated. This selective parameter update rule is the key mechanism of this invention to prevent error propagation. In the prior art, some debouncing schemes update the reference parameters every time a transition is detected. This causes interference signals to contaminate the reference data, making subsequent discrimination increasingly inaccurate and creating an error propagation effect. This invention, by restricting parameter updates to valid pulse scenarios, fundamentally cuts off the influence path of interference signals on the discrimination reference.

[0062] Specifically, the judgment logic in this step is divided into the following three cases:

[0063] Case 1: Valid Pulse. When the arrival time of the detected Hall effect edge is greater than or equal to the lower bound of the window and less than or equal to the upper bound of the window, the Hall effect edge is determined to be a valid pulse. In this case, the system performs the following operations: the trigger cycle count accumulator register is incremented by 1 (in a typical configuration where 6 Hall pulses are generated per revolution, every 6 valid pulses correspond to one revolution of the motor); the currently measured time interval is updated to the new current cycle; based on the new current cycle, the lower and upper bounds of the dynamic time window are recalculated to provide a reference for the next pulse determination.

[0064] The second scenario: glitch pulses. When the time interval between the arrival time of a detected Hall effect edge and the previous valid Hall effect edge is less than the lower bound of the window, the Hall effect edge is determined to be a glitch pulse. Glitch pulses are usually caused by electromagnetic interference, characterized by an arrival time significantly earlier than expected. For example, in the drive circuit of a BLDC motor, the switching action of power switching devices (such as MOSFETs or IGBTs) can induce transient interference on the signal lines. This interference manifests as short, high-frequency pulses that appear much earlier than the expected time of a normal Hall effect pulse.

[0065] When a glitch pulse is detected, the system keeps the parameters of the current period and dynamic time window unchanged and masks the pulse: it does not trigger the increment of the cycle count register, does not update the current period, and does not recalculate the dynamic time window. The Hall transition edge is treated as non-existent, and the system continues to wait for the arrival of the next transition edge.

[0066] The third scenario: signal loss. If the system clock continues to count for more than the upper limit of the window without detecting a new Hall effect edge, it is considered a signal loss. Signal loss can be caused by various reasons: temporary failure of the Hall sensor, strong interference on the signal line causing the signal to be completely submerged, poor connector contact, etc.

[0067] When a signal loss is detected, the system maintains the parameters of the current period and dynamic time window unchanged and triggers a compensation mechanism: a compensation pulse is generated, which triggers the cycle count accumulation register to increment by 1 to maintain the continuity of cycle count calculation. The compensation pulse does not update the parameters of the current period and dynamic time window because the compensation pulse does not come from the actual signal from the Hall sensor, and its timing information is not of reference value.

[0068] In some preferred embodiments, the method further includes: after generating the compensation pulse, recording the compensation event to a diagnostic register for querying by the host computer. The information recorded in the diagnostic register may include the time when the compensation occurred (time counter value) and the cumulative number of compensations. The host computer periodically reads the diagnostic register through the communication interface, which can monitor the operational health status of the system and promptly detect potential hardware faults or environmental interference problems.

[0069] In some preferred embodiments, the method further includes setting an upper limit threshold for the number of consecutive triggers of compensation pulses. When the number of consecutively generated compensation pulses exceeds this upper limit threshold, the BLDC motor is determined to have stopped, and the generation of compensation pulses is stopped. The technical significance of this mechanism is that if the motor has actually stopped rotating, the Hall sensor no longer generates a signal, and the system will continue to trigger signal loss detection and generate compensation pulses, causing the revolution register to continuously increase, resulting in serious counting errors. By setting an upper limit for the number of consecutive compensations (e.g., 10 times), the system can identify the motor stop state within a reasonable time and automatically stop compensation, avoiding the continuous accumulation of false counts. The specific value of the upper limit threshold can be configured according to the application scenario—a smaller threshold can be set in scenarios with high reliability requirements to identify the stop as soon as possible, while a larger threshold can be set in environments with poor signal quality to improve the tolerance for occasional signal loss.

[0070] Step S5: Revolving Count Accumulation and Output. After pulse discrimination in Step S4, pulses confirmed as valid or compensation pulses generated by the compensation mechanism trigger the revolving count accumulator register to increment. The revolving count accumulator register is 32 bits wide, with a maximum count value of 4,294,967,295. With a configuration of 6 Hall pulses per revolution, this register can record approximately 716 million cumulative rotations, meeting the long-term operating requirements of most industrial applications.

[0071] In actual hardware implementation, the increment operation of the cycle count accumulator register needs to consider the synchronization issue of concurrent access. Since the valid pulse acknowledgment signal and the compensation pulse signal may be generated by different logic paths, to avoid counting errors caused by race conditions, this embodiment sets a priority arbitration logic at the input of the counting accumulator module: the valid pulse acknowledgment signal has higher priority, and the compensation pulse signal has lower priority. If both signals are valid simultaneously within the same clock cycle (a situation extremely rare in actual operation), only the valid pulse acknowledgment signal is responded to. This priority design ensures the determinism and uniqueness of the counting.

[0072] The rotation count is output to the host computer control system via a communication interface (such as SPI, UART, or parallel bus). Based on the rotation count and the displacement corresponding to each rotation, the host computer can calculate the absolute position or cumulative movement distance of the motor shaft, thereby achieving precise motion control. To ensure data consistency during communication, this embodiment employs a double-buffering mechanism on the rotation count reading interface: the value of the rotation count accumulation register is synchronously copied to an output buffer register after each pulse discrimination cycle. The host computer always reads data from the output buffer register, thus avoiding the possibility of rotation count jumps during the reading process.

[0073] In some preferred embodiments, an initialization phase is also included. No pulse discrimination is performed within the first complete pulse cycle after system power-on or reset; this first complete pulse cycle is used as the initial value for the current cycle. The necessity of the initialization phase lies in the fact that the calculation of the dynamic time window depends on the data of the "previous valid pulse cycle," which is not available when the system is first started. Therefore, the system needs to wait for the first complete pulse interval to be measured before establishing a meaningful time reference and beginning normal window calculation and pulse discrimination. During the initialization phase, all detected transition edges are unconditionally accepted and used for establishing the time reference.

[0074] Furthermore, the initialization phase can also include a system self-check function: after establishing a time reference, it checks whether the first measured current cycle falls within a preset reasonable range (e.g., the pulse cycle range corresponding to the rated speed range of the motor). If the first cycle value is significantly abnormal (too short or too long), the system can discard the value and continue waiting for the next complete cycle until a reliable initial reference is obtained. This mechanism can effectively avoid erroneous initialization caused by power fluctuations or signal instability at the moment of system startup.

[0075] Example 2

[0076] like Figure 2 As shown, this embodiment provides a BLDC motor revolution count anti-interference calculation system based on dynamic time window verification. This system is used to implement the method described in Embodiment 1.

[0077] The system includes a signal acquisition module, a time measurement module, a window calculation module, a decision logic module, a pulse compensation module, and a counting accumulation module.

[0078] In some preferred embodiments, the system further includes an FPGA hardware parallel processing architecture. Edge detection and debouncing, current cycle measurement, dynamic time window calculation, and pulse discrimination are each executed in parallel by independent hardware logic units. Each hardware logic unit shares a system clock with a frequency not less than 50MHz. The advantage of this parallel processing architecture is that each functional module operates simultaneously as an independent hardware logic unit, eliminating the need for sequential execution of steps as in software solutions, thus achieving nanosecond-level processing latency and deterministic timing response. In this embodiment, all six functional modules are implemented within the same FPGA chip, and each module operates in parallel as an independent hardware logic unit driven by a shared system clock.

[0079] The signal acquisition module receives Hall sensor signals from the BLDC motor, performs independent edge detection and debouncing on each phase signal, and generates a Hall transition edge signal. In this embodiment, the BLDC motor is equipped with three-phase Hall sensors (Hall_W, Hall_V, Hall_U). The signal acquisition module configures a set of registers for each phase signal to store the signal values ​​at the current and previous moments. When the values ​​of the two registers are inconsistent, a transition detection pulse is generated. The three-phase transition detection pulses are combined into a unified Hall transition edge signal through a logical OR operation and sent to subsequent modules for processing. In other application scenarios, if the motor is equipped with two-phase or four-phase Hall sensors, the signal acquisition module can also perform edge detection on each phase signal separately and combine them through a logical OR operation.

[0080] The time measurement module's function is to accurately measure the time interval between two consecutive valid Hall effect transitions. At its core is a 32-bit incrementing counter driven by the system clock. Whenever the decision logic module determines a valid pulse, the time measurement module records the current counter value and calculates the difference between it and the previous valid pulse time to obtain the current period. The time measurement module then outputs the current period to the window calculation module.

[0081] The window calculation module calculates the lower and upper bounds of the dynamic time window based on the current period and the dynamic adjustment coefficient. In FPGAs, multiplication is implemented using hardware multipliers and can be completed within a single clock cycle. To avoid the complexity of floating-point operations, the dynamic adjustment coefficient is typically represented as a fixed-point number in the actual hardware implementation. For example, a dynamic adjustment coefficient of 0.1 can be represented as 1 / 10, and the calculation of the lower bound becomes: Lower bound = Current period - Current period / 10 = Current period × 9 / 10. This integer division operation can be efficiently implemented in FPGAs using a combination of shifting and addition.

[0082] Furthermore, the window calculation module can also employ a pipelined architecture to optimize computational latency. In the first-stage pipeline, a hardware multiplier performs the multiplication operation between the current cycle and the dynamic adjustment coefficient; in the second-stage pipeline, addition and subtraction operations are performed respectively to obtain the upper and lower bounds of the window. This two-stage pipelined architecture can complete all window calculations within two clock cycles without becoming a timing bottleneck for the system. When the dynamic adjustment coefficient needs to be switched according to the speed range, the window calculation module reads the currently effective coefficient value from a configurable coefficient register. The update of this register is automatically completed by the decision logic module based on the speed range corresponding to the current cycle.

[0083] The decision logic module is the central decision-making unit of the entire system. This module receives the Hall effect transition signal output from the signal acquisition module and the time interval data output from the time measurement module. Combining this with the lower and upper bounds of the window provided by the window calculation module, it performs a three-level classification decision: classifying the Hall effect transition as a valid pulse, a glitch pulse, or a signal loss. The decision result triggers the corresponding actions of the counting accumulation module or the pulse compensation module. For glitch pulses, the decision logic module does not issue any action commands to any downstream modules, achieving a shielding effect.

[0084] The pulse compensation module is activated when the decision logic module determines that a signal is lost. This module generates a compensation pulse signal, which is sent to the counter accumulation module's trigger register for incrementing. Simultaneously, the pulse compensation module maintains a compensation event counter and a diagnostic register, recording the occurrence time and cumulative number of compensation events. The pulse compensation module also monitors the upper limit of continuous compensation attempts: when the number of consecutive compensation triggers exceeds a preset threshold, the module automatically enters a suppression state, stops generating compensation pulses, and reports the motor stop status to the host computer via the diagnostic register. When the decision logic module determines a valid pulse again, the pulse compensation module's continuous counter is automatically reset to zero, and it exits the suppression state, resuming normal compensation function. This self-recovery mechanism allows the system to automatically resume normal operation after a motor restart, without manual intervention.

[0085] The counting and accumulating module maintains a 32-bit cycle count accumulator register. This module receives a valid pulse confirmation signal from the decision logic module and a compensation pulse signal from the pulse compensation module. Upon receiving either signal, the cycle count accumulator register is incremented by 1. The cycle count is output to the host computer via the communication interface module.

[0086] Taking the Xilinx Artix-7 XC7A35T FPGA chip as an example: This chip provides abundant programmable logic resources and hardware multipliers. The system clock is driven by a 100MHz external crystal oscillator, and the three-phase Hall sensor signals are connected to the P1, P2, and P3 pins of the FPGA, respectively. The logic resource usage of all six functional modules mentioned above is approximately: about 500 lookup tables (LUTs), about 300 flip-flops (FFs), and 2 hardware multipliers (DSP48), occupying only about 2% of the total resources of this FPGA model, demonstrating good resource efficiency. It should be understood that the system of this invention is not limited to the specific FPGA chip mentioned above; any FPGA chip that provides sufficient logic resources and a clock frequency of at least 50MHz can be used to implement this system. Furthermore, the core logic of this system can also be implemented using ASICs (Application-Specific Integrated Circuits) or other programmable logic devices.

[0087] The following section further explains the data interaction relationships and timing coordination between the modules. During normal operation, the system's workflow is as follows: After detecting a Hall transition edge, the signal acquisition module simultaneously sends a transition detection notification signal to both the time measurement module and the decision logic module. Upon receiving the notification, the time measurement module completes the latching of the current counter value and the calculation of the time interval within the next clock cycle, and outputs the obtained time interval value to the decision logic module. Simultaneously, the window calculation module, based on the current cycle value updated during the last valid pulse, has pre-calculated the lower and upper bounds of the window and continuously outputs these two values ​​to the decision logic module. Upon receiving the time interval value from the time measurement module, the decision logic module compares it with the lower and upper bounds of the window, completes the decision within a single clock cycle, and sends corresponding action signals to the counting accumulation module or pulse compensation module based on the decision result.

[0088] For signal loss detection, the decision logic module maintains a timeout counter. This counter is reset to zero and then increments after each valid pulse is detected. When the timeout counter value exceeds the number of clock cycles corresponding to the upper bound of the window, the decision logic module automatically determines that a signal has been lost, without waiting for the next Hall transition edge. This proactive timeout detection mechanism ensures that signal loss can be detected and handled promptly, preventing system stagnation due to waiting for a signal that will never arrive. After the timeout detection is complete, the timeout counter restarts counting from the current cycle, preparing for the next possible signal loss event.

[0089] In the timing design of the entire system, the total delay from the detection of the Hall transition edge to the generation of the decision result does not exceed 5 clock cycles (50 nanoseconds at 100MHz). This extremely low processing delay enables the system to maintain reliable real-time response capabilities even at high speeds. Taking a motor speed of 10000RPM and 6 Hall pulses per revolution as an example, the Hall pulse period is approximately 1000 microseconds, and the system's 50 nanosecond processing delay accounts for only 0.005% of the pulse period, which is negligible.

[0090] Experimental Example

[0091] To verify the actual effectiveness of the technical solution of this invention, tests were conducted under the following conditions:

[0092] Test platform configuration: The FPGA chip is a Xilinx Artix-7 XC7A35T with a system clock of 100MHz; the BLDC motor is a three-phase four-pole brushless DC motor with a rated speed of 3000RPM and equipped with a three-phase Hall sensor installed at 120°; the dynamic adjustment coefficient adopts a graded strategy (0.3 for low speed / 0.2 for medium speed / 0.1 for high speed), with speed grade thresholds of 1000RPM and 5000RPM; the upper limit of continuous triggering of compensation pulse is set to 10 times.

[0093] Test Scenario 1: Anti-interference Test. Under an electromagnetic interference environment of 1000V / m, the motor operates at various speeds. The accuracy of the revolution count calculation using the method of this invention is greater than 99.9%, and the signal loss compensation response time is less than 1 millisecond. Compared with the traditional fixed threshold debouncing method, the method of this invention can adaptively distinguish between effective pulses and interference glitches through a dynamic time window mechanism, avoiding misjudgments caused by threshold mismatch in variable speed conditions under fixed threshold conditions.

[0094] Test Scenario 2: Long-Term Continuous Operation Stability Test. The motor ran continuously for 1000 hours, during which normal industrial background noise was maintained. The test results show that the method of this invention has no cumulative deviation in the number of revolutions calculation throughout the entire test cycle. Naturally occurring signal loss events during operation were correctly handled by the compensation pulse mechanism, and the dynamic time window remained stably tracked throughout the entire operation, without any window parameter divergence or drift.

[0095] Test Scenario 3: Variable Speed ​​Operation Test. The motor operates at varying speeds from low to high. Because the dynamic time window updates in real time according to the current cycle, it automatically widens at low speeds and narrows at high speeds, ensuring the system correctly identifies valid pulses and blocks interference signals across the entire speed range. Compared to the fixed time window method, this invention eliminates the need for manual parameter tuning for different speed ranges.

[0096] The above test results demonstrate that the BLDC motor revolution count anti-interference calculation method and system based on dynamic time window verification of the present invention can achieve accurate and reliable revolution count calculation under various operating conditions such as constant speed, variable speed, signal loss, and electromagnetic interference. The adaptive adjustment mechanism of the dynamic time window, the three-level pulse discrimination logic, and the compensation pulse generation mechanism work together to outperform traditional fixed threshold debouncing methods and fixed time window methods in terms of anti-interference capability, variable speed adaptability, and counting reliability.

[0097] The method and system of this invention are not only applicable to BLDC motors, but can also be extended to other scenarios requiring high-precision pulse counting. For example, in the position calculation of stepper motors, Hall sensor signals can be replaced with encoder signals, and the same dynamic time window verification logic can be used to identify and compensate for interference in encoder pulses. In the incremental encoder signal processing of servo motors, the three-level pulse discrimination logic of this invention can also effectively identify and shield false pulses caused by electromagnetic interference. The dynamic time window verification method of this invention also has broad application prospects in flow meters, tachometers, and other measuring instruments that rely on pulse counting in the field of industrial automation.

[0098] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A method for calculating the anti-interference effect of BLDC motor revolutions based on dynamic time window verification, characterized in that, include: Collect Hall sensor signals from the BLDC motor, perform edge detection and debouncing processing, and generate Hall transition edges; The current period is obtained by measuring the time interval between adjacent valid Hall transition edges based on the system clock. Based on the current period and the dynamic adjustment coefficient, calculate the lower and upper bounds of the dynamic time window; Pulse discrimination is performed based on the relationship between the arrival time of the Hall transition edge and the dynamic time window. When the pulse is determined to be valid, the number of cycles accumulated is incremented. When the pulse is determined to be a glitch, the pulse is blocked. When the pulse is determined to be lost, a compensation pulse is generated and the number of cycles accumulated is incremented. The formula for calculating the lower bound of the window is: Lower bound of window = Current period × (1 - Dynamic adjustment coefficient), and the formula for calculating the upper bound of the window is: Upper bound of window = Current period × (1 + Dynamic adjustment coefficient). The dynamic adjustment coefficient is adjusted in stages according to the speed range of the BLDC motor's operating speed. The lower the speed, the larger the dynamic adjustment coefficient, and the higher the speed, the smaller the dynamic adjustment coefficient. The value range of the dynamic adjustment coefficient is 0.05 to 0.

5.

2. The method for calculating the anti-interference number of BLDC motor turns based on dynamic time window verification according to claim 1, characterized in that, In the pulse discrimination step, the parameters of the current period and the dynamic time window are updated only when the pulse is determined to be valid; when the pulse is determined to be a glitch, the parameters of the current period and the dynamic time window are kept unchanged and the pulse is blocked; when the pulse is determined to be lost, the parameters of the current period and the dynamic time window are kept unchanged and the compensation pulse is generated.

3. The method for calculating the anti-interference number of BLDC motor turns based on dynamic time window verification according to claim 1, characterized in that, The edge detection is performed by performing a logical OR operation on each phase of the Hall sensor signal, and the pulse discrimination is triggered when any phase signal changes.

4. The method for calculating the anti-interference number of BLDC motor turns based on dynamic time window verification according to claim 1, characterized in that, It also includes an initialization phase in which the pulse discrimination is not performed during the first complete pulse cycle after the system is powered on or reset, and the first complete pulse cycle is used as the initial value of the current cycle.

5. The method for calculating the anti-interference number of BLDC motor turns based on dynamic time window verification according to claim 1, characterized in that, It also includes setting an upper limit threshold for the number of consecutive triggers of the compensation pulse. When the number of consecutively generated compensation pulses exceeds the upper limit threshold, the BLDC motor is determined to stop and the generation of compensation pulses is stopped.

6. The method for calculating the anti-interference number of BLDC motor turns based on dynamic time window verification according to claim 1, characterized in that, The method is implemented based on an FPGA hardware parallel processing architecture. The edge detection and debouncing processing, the measurement of the current cycle, the calculation of the dynamic time window, and the pulse discrimination are each executed in parallel by independent hardware logic units. Each hardware logic unit shares the system clock, and the frequency of the system clock is not less than 50MHz.

7. A BLDC motor revolution count anti-interference calculation system based on dynamic time window verification, characterized in that, include: The signal acquisition module is used to acquire Hall sensor signals from the BLDC motor, perform edge detection and debouncing, and generate Hall transition edges. The time measurement module is used to measure the time interval between two adjacent valid Hall transition edges based on the system clock to obtain the current period; The window calculation module is used to calculate the dynamic time window based on the current period and the dynamic adjustment coefficient; The formula for calculating the lower bound of the dynamic time window is: Lower bound = Current period × (1 - Dynamic adjustment coefficient), and the formula for calculating the upper bound of the dynamic time window is: Upper bound = Current period × (1 + Dynamic adjustment coefficient). The dynamic adjustment coefficient is adjusted in stages according to the speed range of the BLDC motor's operating speed. The lower the speed, the larger the dynamic adjustment coefficient, and the higher the speed, the smaller the dynamic adjustment coefficient. The value range of the dynamic adjustment coefficient is 0.05 to 0.

5. The decision logic module is used to determine whether the Hall transition edge is a valid pulse, a glitch pulse, or a signal loss based on the relationship between the arrival time of the Hall transition edge and the dynamic time window. The pulse compensation module is used to generate a compensation pulse when the signal is determined to be lost. The counting and accumulating module is used to trigger the incrementing of the cycle count register when the pulse is determined to be valid or when the compensation pulse is generated.

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