High-anti-interference bus adaptive decoding circuit and high-anti-interference bus adaptive decoding equipment
By introducing a signal feedback branch and an NMOS transistor into the two-bus receiver circuit, an adaptive dynamic reference generation mechanism is constructed, which solves the contradiction between load capacity and anti-interference capability in traditional circuits and achieves stable decoding under different load and noise environments.
Patent Information
- Application Number
- CN202610127588.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-29
- Publication Date
- 2026-05-08
AI Technical Summary
Existing dual-bus receiver circuits struggle to simultaneously balance bus load capacity and anti-interference capabilities when facing complex and ever-changing application scenarios, and the inherent contradictions caused by traditional decoding mechanisms are difficult to reconcile.
A signal feedback branch is connected in series on the signal sampling branch, including parallel NMOS transistors and resistors, to form an adaptive dynamic reference generation mechanism. The dynamic adjustment of Vdrop is achieved by the linear resistance region of the NMOS transistors, and the decoding threshold is automatically adjusted according to the bus load and noise environment.
It achieves stable and reliable signal decoding under wide load range and harsh noise environment, alleviates the contradiction between load capacity and anti-interference capability in traditional circuits, and improves the adaptability and reliability of the receiver.
Smart Images
Figure CN122001394A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of two-bus communication technology, and more specifically, to a high anti-interference bus adaptive decoding circuit and device. Background Technology
[0002] Two-wire bus is a bus technology that simultaneously carries communication and power supply functions, and the performance of its receiver is crucial; in existing technology, a mature and widely used receiver front-end circuit is such as Figure 1 As shown, the core design idea of this circuit is to receive the attenuated signal through the bus input terminal (BUS) and use the unidirectional conduction characteristic of the diode to quickly charge the capacitor of node SC under light load (i.e., less bus load), thereby storing a reference voltage Vsc representing the bus logic high level "VH".
[0003] Typically, Vsc ≈ VH - Vdrop, where Vdrop is the fixed voltage drop across the diode. This reference voltage Vsc, together with the real-time bus voltage Vbus (i.e., the actual potential of node SC), is fed into the back-end comparator for differential comparison. When the comparison result meets the flip condition, its output RX will generate a digital signal for the downstream controller (MCU) to decode. Figure 2 The waveform diagram clearly illustrates this process. Under ideal conditions, although the amplitude of the bus input waveform (BUS) is attenuated due to factors such as line impedance and load (the high level is lower than the nominal VH, and the low level is higher than GND), the receiving end can still accurately recover the regular digital waveform (RX) by comparing it with the dynamic reference of the "SC storage high level plane line".
[0004] However, this decoding mechanism, designed to adapt to bus voltage attenuation, introduces an inherent and irreconcilable contradiction: bus load capacity and anti-interference capability cannot be optimized simultaneously. The specific contradiction is analyzed as follows: To ensure decoding capability (load capacity) under heavy load: When the bus load is large, the actual high level VH on the bus will drop to its minimum value VHmin due to the larger voltage drop across the bus resistor caused by the supply current. Simultaneously, the difference between the high and low levels (VH-VL) will decrease. To ensure the comparator can still reliably toggle under these conditions, Vsc - VL > Vth must be satisfied, i.e., VHmin - Vdrop - VL > Vth. This can be derived as follows: VHmin VL>Vdrop+Vth (Equation 1) This indicates that to accommodate heavier loads (i.e., allow for lower VHmin), the value of (VHmin - VL) should be as small as possible. To ensure interference immunity under light load conditions: when the bus load is light, the capacitive reactance formed by the distributed capacitance of the lines is small, making the bus more susceptible to coupling with external electromagnetic interference. For example... Figure 2 As shown, this kind of interference often appears as superimposed sine wave noise (peak-to-peak value is Vpp_noise) on the bus; during the high level of the bus, the interference may cause the instantaneous voltage Vbus to be pulled down to VH - Vpp_noise / 2; at this time, if Vsc - Vbus = VH - Vdrop - (VH - Vpp_noise / 2) = Vpp_noise / 2 - Vdrop > Vth, the comparator will flip erroneously, resulting in decoding errors. After simplification, the condition to avoid error codes is: Vpp_noise / 2 < Vdrop + Vth (Equation 2) Combining Equation (1) and Equation (2), it can be obtained that the limit condition for the system to work stably is Vpp_noise / 2 < VHmin – VL. This means that to resist greater noise (that is, to allow Vpp_noise to be larger), the value of (VHmin - VL) should be as large as possible. On the one hand, to improve the bus load-carrying capacity (its measurement index is (VHmax - VHmin) / Iq, when VHmax and the static current Iq are fixed, it mainly depends on how low VHmin can be reduced), it is expected that (VHmin - VL) is as small as possible; on the other hand, to enhance the anti-interference ability of the bus under light load, it is expected that (VHmin - VL) is as large as possible.
[0005] This fundamental contradiction makes the traditional receiving circuit based on "SC stores high level" difficult to meet the performance requirements of both large-load driving and strong noise suppression while ensuring stable decoding in the face of complex and changeable application scenarios. Therefore, a high anti-interference bus adaptive decoding circuit is needed that can achieve different anti-interference capabilities under different bus load conditions to balance the bus load-carrying capacity requirements and communication quality (signal integrity) requirements. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to provide a high anti-interference bus adaptive decoding circuit, a high anti-interference bus device, and a method for applying a high anti-interference bus adaptive decoding circuit in view of the above-mentioned defects of the prior art.
[0007] The technical solution adopted by the present invention to solve its technical problems is: Construct a high anti-interference bus adaptive decoding circuit, including a signal sampling branch connected between the bus input end and the comparator. Among them, a signal feedback branch is connected in series on the signal sampling branch; the signal feedback branch includes a first resistor and an NMOS transistor connected in parallel; the NMOS transistor operates in its linear resistance region.
[0008] The high anti-interference bus adaptive decoding circuit of the present invention further includes a second resistor, a third resistor and a fourth resistor in the signal feedback branch; The gate (G) of the NMOS transistor is connected to the second resistor and the third resistor, the source (S) is grounded, and the drain (D) is connected to the fourth resistor. The other end of the second resistor is connected to one end of the first resistor, the other end of the fourth resistor is connected to the other end of the first resistor, and the other end of the third resistor is grounded.
[0009] The high anti-interference bus adaptive decoding circuit of the present invention includes a signal sampling branch comprising a fifth resistor, a diode, and a capacitor storage node connected in sequence; and a signal feedback branch connected in series between the capacitor storage node and the comparator.
[0010] A high interference immunity bus device, wherein the high interference immunity bus device is provided with the high interference immunity bus adaptive decoding circuit as described above.
[0011] The beneficial effects of this invention are as follows: a signal feedback branch consisting of a first resistor and an NMOS transistor connected in parallel is connected in series on the original signal sampling branch. The original fixed decoding reference generation mechanism (fixed voltage drop Vdrop) is transformed into an adaptive dynamic reference generation mechanism. Vdrop is no longer a fixed compromise value in the design, but can be intelligently adjusted according to the actual operating conditions of the bus (high or low VH). Thus, it can automatically lower the threshold when "sensitivity" (heavy load) is needed, and automatically raise the threshold when "robustness" (light load noise immunity) is needed. This dynamic characteristic effectively alleviates the inherent contradiction between load capacity and anti-interference capability in traditional circuits, enabling the two-bus receiver to work stably and reliably in a wider load range and in harsher noise environments. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort: Figure 1 It is an existing two-bus circuit schematic; Figure 2 It is the existing two-wire line waveform; Figure 3 This is a circuit diagram of a high anti-interference bus adaptive decoding circuit according to a preferred embodiment of the present invention. Detailed Implementation
[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, a clear and complete description will be provided below in conjunction with the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.
[0014] The preferred embodiment of the present invention includes a high anti-interference bus adaptive decoding circuit, such as... Figure 3 As shown, it includes a signal sampling branch connected between the bus input and the comparator, and a signal feedback branch connected in series on the signal sampling branch; the signal feedback branch includes a first resistor R2 and an NMOS transistor Q1 connected in parallel; the NMOS transistor Q1 operates in its linear resistance region; A signal feedback branch consisting of a first resistor R2 and an NMOS transistor Q1 connected in parallel was connected in series on the original signal sampling branch. The original fixed decoding reference generation mechanism (fixed voltage drop Vdrop) was transformed into an adaptive dynamic reference generation mechanism. Vdrop is no longer a fixed compromise value in the design, but can be intelligently adjusted according to the actual bus conditions (high or low VH). Thus, it can automatically lower the threshold when "sensitivity" (heavy load) is needed, and automatically raise the threshold when "robustness" (light load noise immunity) is needed. This dynamic characteristic effectively alleviates the inherent contradiction between load capacity and anti-interference capability in traditional circuits, enabling the two-bus receiver to work stably and reliably in a wider load range and harsher noise environments.
[0015] The specific circuit can be: The signal feedback branch also includes a second resistor, a third resistor, and a fourth resistor; the gate (G) of the NMOS transistor is connected to the second and third resistors, the source (S) is grounded, and the drain (D) is connected to the fourth resistor; the other end of the second resistor is connected to one end of the first resistor, the other end of the fourth resistor is connected to the other end of the first resistor, and the other end of the third resistor is grounded; the signal sampling branch includes a fifth resistor, a diode, and a capacitor storage node (SC point) connected in sequence; the signal feedback branch is connected in series between the capacitor storage node (SC point) and the comparator; The principle is explained as follows: As described in the background section: In traditional receiver circuits that store high-level references based on capacitors (SC points), the decoding threshold Vdrop + Vth is fixed. This fixed threshold is independent of the bus dynamic voltage VH, leading to a fundamental contradiction between load capacity and noise immunity: to handle heavy loads, a lower VHmin must be tolerated, thus sacrificing noise margin; to improve noise immunity, VHmin must be increased, thus limiting load capacity.
[0016] To overcome this limitation, this invention proposes an innovative circuit that incorporates feedback regulation, the core principle of which is as follows: Figure 3 As shown.
[0017] 1. Structure and principle of feedback regulation circuit: This circuit adds a parallel feedback branch consisting of an NMOS transistor Q1 and a first resistor R2 to the original path of diodes and energy storage capacitors.
[0018] Core component: NMOS transistor Q1 operates in its linear resistance region (or transistor region). In this operating region, the on-resistance Rds(on) of Q1 is controlled by its gate-source voltage Vgs, which is directly provided by Vsc (i.e., VH - Vdrop1). Therefore, Q1 is equivalent to a voltage-controlled variable resistor that is controlled in real time by the bus high level VH.
[0019] Regulation mechanism: The current Ifc flowing through Q1 and R2 constitutes a positive feedback regulation current. The additional voltage drop it generates across R2 is Vdrop2 = Ifc * R2.
[0020] Dynamic changes in total voltage drop: At this point, the total voltage drop Vdrop from the bus BUS to the storage node SC is no longer a fixed value, but consists of two parts: Vdrop=Vdrop1+Vdrop2=Vdrop1+(Ifc R2); Vdrop1 is the inherent voltage drop of diode D1 (relatively fixed), while Vdrop2 is a dynamically adjustable part.
[0021] 2. How dynamic feedback resolves conflicts: The ingenuity of this circuit lies in establishing a positive proportional relationship between Ifc (and thus Vdrop2) and the bus voltage VH through Q1: When the bus load is heavy and VH decreases, Vsc (≈ VH - Vdrop) also decreases. This causes the voltage Vgs applied to the gate of Q1 to decrease, which increases the on-resistance of Q1 and decreases the feedback current Ifc, thereby reducing the dynamic voltage drop Vdrop2. Finally, the total voltage drop Vdrop decreases automatically. This helps to prevent Vsc from being pulled too low under heavy load, thus ensuring that equation (1) VHmin - VL > Vdrop + Vth still holds true at a lower VHmin, improving the load-carrying capacity.
[0022] When the bus load is light, VH is high and there is superimposed noise: Vsc is high, the Vgs of Q1 increases, its on-resistance decreases, the feedback current Ifc increases, and thus the dynamic voltage drop Vdrop2 increases; finally, the total voltage drop Vdrop automatically increases; according to Equation (2), Vpp_noise / 2 < Vdrop + Vth, the increased Vdrop directly raises the anti-interference threshold, making it less likely for the circuit to have false flips in a light-load and high-noise environment, enhancing the anti-interference ability.
[0023] A high anti-interference bus device is provided with the high anti-interference bus adaptive decoding circuit as described above; it can be understood that the high anti-interference bus device of the present application can cover all existing devices using two-wire buses.
[0024] It should be understood that those of ordinary skill in the art can make improvements or transformations based on the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.
Claims
1. A high-interference-resistant bus adaptive decoding circuit, comprising a signal sampling branch connected between the bus input terminal and a comparator, characterized in that, A signal feedback branch is connected in series on the signal sampling branch; the signal feedback branch includes a first resistor and an NMOS transistor connected in parallel; the NMOS transistor operates in its linear resistance region.
2. The high anti-interference bus adaptive decoding circuit according to claim 1, characterized in that, The signal feedback branch also includes a second resistor, a third resistor, and a fourth resistor; The gate (G) of the NMOS transistor is connected to the second resistor and the third resistor, the source (S) is grounded, and the drain (D) is connected to the fourth resistor. The other end of the second resistor is connected to one end of the first resistor, the other end of the fourth resistor is connected to the other end of the first resistor, and the other end of the third resistor is grounded.
3. The high anti-interference bus adaptive decoding circuit according to claim 1, characterized in that, The signal sampling branch includes a fifth resistor, a diode, and a capacitor storage node connected in sequence; the signal feedback branch is connected in series between the capacitor storage node and the comparator.
4. A high anti-interference bus device, characterized in that, The high interference immunity bus device is provided with a high interference immunity bus adaptive decoding circuit as described in any one of claims 1-3.