Digitized integrated circuit fault diagnosis method and system

Abstract

The invention relates to the technical field of digital integrated circuit pre-diagnosis and health management, and discloses a digital integrated circuit fault diagnosis method and system. The method comprises the following steps: acquiring voltage fluctuation, current instantaneous change data and transmission delay duration of an integrated circuit, and performing space-time integration and dynamic denoising to obtain a purified signal sequence; time-frequency features are extracted, phase correction is completed, abnormal signal significant feature distribution is obtained, and when a threshold value is exceeded, a potential overload event is judged, and abnormal time is marked; tracing a fault propagation path, and locking a preliminary interval of a fault source in combination with a module dependency relationship and a historical fault mode; and calculating a comprehensive matching probability through multi-path comparison, and screening an optimal backtracking path to accurately position the source position of the circuit fault. According to the method, efficient and accurate diagnosis of integrated circuit faults can be realized, and the core requirements of operation and maintenance safety, timeliness and reliability are met.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit pre-diagnosis and health management technology, and in particular to a digital integrated circuit fault diagnosis method and system. Background Technology

[0002] Currently, in the field of digital integrated circuit pre-diagnosis and health management, with the continuous improvement of integrated circuit integration and the continuous expansion of complex application scenarios, the stable operation of digital integrated circuits, as the core component of electronic systems, is directly related to equipment reliability and operation and maintenance cost control.

[0003] Existing fault diagnosis methods for digital integrated circuits in the industry mainly rely on single signal detection or offline analysis. For example, they may use single-point sensors to monitor voltage fluctuations, rely on simple waveform comparisons to determine fault states, or ignore the spatiotemporal correlation of signals and fault propagation patterns. However, these methods are clearly insufficient in complex operating environments. Single signal detection has limited coverage, making it difficult to capture anomalies across the entire spectrum; offline analysis suffers from latency and is susceptible to environmental noise interference, easily missing minor faults or misinterpreting interference signals; furthermore, it lacks the ability to dynamically trace fault propagation paths, making it particularly difficult to quickly locate the root cause of faults in high-density, multi-module complex integrated circuits.

[0004] In summary, existing technologies are insufficient for accurate and efficient diagnosis of faults in digital integrated circuits, and cannot meet the core requirements of the pre-diagnosis and health management field for the safety, timeliness, and reliability of integrated circuit operation and maintenance. Summary of the Invention

[0005] This invention provides a method and system for diagnosing faults in digital integrated circuits, enabling accurate and efficient diagnosis of faults in digital integrated circuits and meeting the core requirements of the field of pre-diagnosis and health management for the safety, timeliness and reliability of integrated circuit operation and maintenance.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for diagnosing faults in digital integrated circuits, comprising:

[0007] Acquire voltage fluctuation data, instantaneous current change data, and data transmission delay time of digital integrated circuits;

[0008] The voltage fluctuation data and the instantaneous change data of the current are timestamped and integrated with the preset sensor spatial distribution information for spatiotemporal data integration. After the integrated data is denoised, a purified signal sequence is formed.

[0009] The time-domain and frequency-domain features of the purified signal sequence are extracted, and phase correction is performed in combination with the delay duration. The distribution of significant features of the abnormal signal is obtained by clustering and calculating the feature similarity of the corrected features.

[0010] If the distribution of the significant features exceeds the preset fluctuation judgment threshold, it is determined to be a potential circuit overload event. The discrete points of the signal pulses corresponding to the potential circuit overload event are extracted to obtain the time stamp of the abnormal event.

[0011] Based on the time stamp, trace the path nodes of the fault propagation in the purification signal sequence, construct the spatial topology of the path nodes, determine the boundary of the fault impact range, and combine the sensor spatial distribution information to determine the propagation direction and key impact area of ​​the abnormal signal.

[0012] Analyze the module dependencies and path node weights corresponding to the propagation direction and the key affected area, and combine them with the previously acquired historical fault modes to determine the preliminary location range of the fault source.

[0013] Based on multiple backtracking paths within the initial position range, the path deviation value and positioning time accuracy between the real-time signal and the preset standard reference waveform are calculated, and the comprehensive matching probability is calculated by combining the path deviation value and the positioning time accuracy.

[0014] The path with the highest overall matching probability and the smallest path deviation value is selected as the optimal backtracking path. The coordinates of the starting node of the optimal backtracking path are extracted to obtain the location of the root cause of the circuit fault.

[0015] Secondly, the present invention provides a digital integrated circuit fault diagnosis system, comprising:

[0016] The data acquisition module is used to acquire voltage fluctuation data, instantaneous current change data, and data transmission delay time of the digital integrated circuit.

[0017] The preprocessing module is used to timestamp-align the voltage fluctuation data and the instantaneous current change data, integrate the spatiotemporal data with the preset sensor spatial distribution information, and perform noise reduction processing on the integrated data to form a purified signal sequence.

[0018] The feature extraction module is used to extract the time-domain and frequency-domain features of the purified signal sequence, and perform phase correction in combination with the delay duration. By performing clustering processing and feature similarity calculation on the corrected features, the significant feature distribution of the abnormal signal is obtained.

[0019] An anomaly determination module is used to determine a potential circuit overload event if the distribution of the significant features exceeds a preset fluctuation determination threshold, extract the discrete points of the signal pulses corresponding to the potential circuit overload event, and obtain the time stamp of the anomaly event.

[0020] The path tracing module is used to trace the path nodes of the fault propagation in the purification signal sequence according to the time stamp, construct the spatial topology of the path nodes, determine the boundary of the fault impact range, and combine the sensor spatial distribution information to determine the propagation direction and key impact area of ​​the abnormal signal.

[0021] The source location module is used to analyze the module dependencies and path node weights corresponding to the propagation direction and the key impact area, and in combination with the pre-acquired historical fault modes, to determine the preliminary location range of the fault source.

[0022] The probability calculation module is used to calculate the path deviation value and positioning time accuracy between the real-time signal and the preset standard reference waveform based on multiple backtracking paths within the initial position interval, and to calculate the comprehensive matching probability by combining the path deviation value and the positioning time accuracy.

[0023] The path filtering module is used to filter the path with the highest comprehensive matching probability and the smallest path deviation value as the optimal backtracking path, extract the starting node coordinates of the optimal backtracking path, and obtain the location of the root cause of the circuit fault.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] (1) This invention acquires voltage fluctuations, instantaneous current changes and transmission delays of digital integrated circuits through a sensor array, performs timestamp alignment and spatiotemporal integration on the voltage and current data, dynamically adjusts the noise reduction parameters to preserve signal details, and forms a purified signal sequence. This breaks through the limitations of traditional single signal detection coverage, explores the spatiotemporal correlation characteristics of circuit operation, eliminates environmental noise and equipment jitter interference, provides high-precision basic data support for fault diagnosis, effectively improves the capture rate of small abnormal signals, and solves the problem of missing potential faults from a single signal source.

[0026] (2) This invention extracts the time and frequency domain features of the purification signal sequence, performs phase correction in combination with the transmission delay duration, obtains the distribution of significant features of abnormal signals through clustering and similarity calculation, determines potential overload events and marks time nodes when the threshold is exceeded, breaks through the limitation of traditional single feature analysis that cannot distinguish between faults and interference, accurately captures the exclusive signal features of circuit faults, provides multi-dimensional basis for anomaly judgment, significantly improves the accuracy of fault identification under complex working conditions, and makes up for the high misjudgment rate of existing technologies.

[0027] (3) Based on time stamping, this invention traces the fault propagation path nodes, constructs a spatial topology to determine the propagation direction and key areas, and combines module dependencies, historical fault modes and multi-path comparison to screen the optimal backtracking path to locate the fault root cause. This solves the limitations of traditional fault propagation tracing and accurate location capabilities, provides fault root cause location information for operation and maintenance, solves the problems of difficult fault location and low troubleshooting efficiency in complex integrated circuits, balances diagnostic accuracy and operation and maintenance timeliness, and meets the core requirements of reliability and security in the field of integrated circuit pre-diagnosis. Attached Figure Description

[0028] Figure 1 This is a schematic flowchart of a digital integrated circuit fault diagnosis method provided in the first embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of a digital integrated circuit fault diagnosis system provided in the second embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Reference Figure 1 The first embodiment of the present invention provides a method for diagnosing faults in digital integrated circuits, comprising the following steps:

[0032] S101, acquire voltage fluctuation data, instantaneous current change data, and data transmission delay of the digital integrated circuit;

[0033] S102, the voltage fluctuation data and the instantaneous change data of the current are timestamped and integrated with the preset sensor spatial distribution information to form a purified signal sequence after the integrated data is denoised.

[0034] S103, extract the time domain features and frequency domain features of the purified signal sequence, and perform phase correction in combination with the delay duration. By performing clustering processing and feature similarity calculation on the corrected features, the significant feature distribution of the abnormal signal is obtained.

[0035] S104, if the significant feature distribution exceeds the preset fluctuation judgment threshold, it is determined to be a potential circuit overload event, and the discrete points of the signal pulse corresponding to the potential circuit overload event are extracted to obtain the time stamp of the abnormal event.

[0036] S105, trace the path nodes of the fault propagation in the purification signal sequence according to the time stamp, construct the spatial topology of the path nodes, determine the boundary of the fault influence range, and combine the sensor spatial distribution information to determine the propagation direction and key influence area of ​​the abnormal signal.

[0037] S106, Analyze the module dependencies and path node weights corresponding to the propagation direction and the key influence area, and determine the preliminary location range of the fault source by combining the previously acquired historical fault modes;

[0038] S107, Based on the multiple backtracking paths within the initial position interval, calculate the path deviation value and positioning time accuracy between the real-time signal and the preset standard reference waveform, and calculate the comprehensive matching probability by combining the path deviation value and the positioning time accuracy;

[0039] S108, the path with the highest comprehensive matching probability and the smallest path deviation value is selected as the optimal backtracking path, and the starting node coordinates of the optimal backtracking path are extracted to obtain the location of the root cause of the circuit fault.

[0040] In step S101, acquiring the voltage fluctuation data, instantaneous current change data, and data transmission delay of the digital integrated circuit includes:

[0041] The system acquires raw data on the operating status of digital integrated circuits at high frequency through a sensor array. The raw data includes voltage signal fluctuation range, instantaneous change information of current signal, and data transmission timing data.

[0042] The raw data of the operating status is processed to standardize the format, and to unify the data sampling granularity and numerical range;

[0043] Invalid records and random interference data are removed from the original running status data to obtain preliminary processed data;

[0044] Voltage fluctuation data and instantaneous current change data are extracted from the preliminary processed data, and the time difference of the data transmission timing data is calculated to obtain the data transmission delay.

[0045] It should be noted that, firstly, a sensor array consisting of a surface-mount voltage sensor, a Hall effect current sensor, and a high-speed timing acquisition chip is used to collect raw data on the operating status of the digital integrated circuit at high frequency. The collected data includes voltage signal fluctuation range, instantaneous current signal changes, and data transmission timing data. The sampling frequency is set based on the integrated circuit's clock frequency and the minimum duration of fault signals. Statistical analysis of fault characteristics of various digital integrated circuits over the past two years shows that over 90% of effective fault signals have a duration of no less than 10ns. Therefore, the basic sampling frequency is set to 100MHz, corresponding to a sampling interval of 10ns. For high-precision chip scenarios, this can be increased to 200MHz, while for general consumer-grade chip scenarios, it can be reduced to 50MHz.

[0046] Next, the raw operational data undergoes format standardization to unify the data sampling granularity and numerical range. The sampling granularity is standardized to the basic sampling interval, and missing data is supplemented using linear interpolation to ensure a continuous sequence without breaks. The numerical range is mapped to the [0,1] interval for voltage and current data using a minimum-maximum normalization method, eliminating magnitude deviations caused by differences in the ranges of different sensors. The format standardization process simultaneously verifies the continuity of data timestamps, eliminating redundant records with duplicate timestamps to ensure the uniqueness of the data sequence.

[0047] For example, in a set of original data, the voltage range is 0-5V and the current range is 0-2A. After minimum-maximum normalization, the value corresponding to 3V voltage is 0.6 and the value corresponding to 1A current is 0.5. The sampling granularity is unified to 10ns, forming a standardized dataset.

[0048] Subsequently, invalid records and random interference data in the original operational status data are removed to obtain preliminary processed data. Invalid records include all-zero data caused by sensor offline and out-of-range data caused by acquisition overflow, which are directly removed. Random interference data is identified using the 3-standard-deviation principle. First, the mean and standard deviation of 1000 consecutive sampling points are calculated. Single-point data that exceed the mean ± 3 standard deviations and have no continuous temporal correlation are marked as random interference and removed. This identification rule is based on statistics from nearly 100,000 sets of normal operation data. More than 99.7% of normal data fall within the mean ± 3 standard deviations, which can effectively distinguish random noise from real fault signals. In high-noise industrial scenarios, the range can be relaxed to mean ± 4 standard deviations, and in low-noise laboratory scenarios, it can be tightened to mean ± 2 standard deviations. For example, if the mean of a voltage data segment is 1.0V and the standard deviation is 0.02V, the range of mean ± 3 standard deviations is 0.94V to 1.06V. If a single point value in the sequence is 0.8V and has no continuous correlation, it is judged as random interference data and removed.

[0049] Finally, voltage fluctuation data and instantaneous current change data are extracted from the preliminary processed data, and the time difference of the data transmission timing data is calculated to obtain the data transmission delay. The separation process is carried out according to the sensor type of the data acquisition: data acquired by the patch voltage sensor is classified as voltage fluctuation data, and data acquired by the Hall current sensor is classified as instantaneous current change data. Both retain their corresponding timestamps.

[0050] It should be noted that the delay duration is obtained by calculating the difference between the timestamps of the same signal event at the sending and receiving ends. The time bases of the sending and receiving ends are unified through a globally synchronized clock to ensure the accuracy of the difference calculation. For example, if the timestamp of a data signal at the sending end is 1000ns and the timestamp at the receiving end is 1005ns, the calculated data transmission delay duration is 5ns.

[0051] In step S102, the voltage fluctuation data and the instantaneous current change data are timestamped and integrated with preset sensor spatial distribution information to form a purified signal sequence after denoising the integrated data, including:

[0052] Extract the timestamps from the voltage fluctuation data and the instantaneous change data of the current, and associate and bind the voltage data and current data corresponding to the same timestamp;

[0053] Based on the preset sensor spatial distribution coordinates, the associated signal data is mapped to the physical space coordinate system to form spatiotemporal fusion data;

[0054] Calculate the signal-to-noise ratio of the spatiotemporal fusion data to determine the environmental noise interference level;

[0055] The denoising parameters are dynamically adjusted according to the noise interference level to smooth the spatiotemporal fusion data and remove environmental noise.

[0056] By preserving signal details through resolution compensation technology, the processed signal segments are spliced ​​together in chronological order to form a purified signal sequence.

[0057] It should be noted that, firstly, nanosecond-level timestamps are extracted from voltage fluctuation data and instantaneous current change data, and data association and binding are completed using time difference matching rules. The maximum allowable time difference for the matching rules is based on the global synchronization accuracy statistics of the sensor array. Analysis of data collected over the past two years revealed that 98% of the synchronized data acquisitions have a time difference of no more than 2ns. Therefore, the basic maximum allowable time difference is set to 2ns. For high-precision chip detection scenarios, this can be lowered to 1ns, and for general consumer-grade chip scenarios, it can be increased to 3ns. When the timestamp difference between two sets of data is within the maximum allowable range, they are determined to be corresponding data from the same moment, and the association and binding are completed.

[0058] For example, if the timestamp of a voltage data is 1000ns and the timestamp of the corresponding current data is 1001ns, the difference of 1ns is within the allowable range of 2ns, and the two are associated and bound together.

[0059] Next, based on the preset sensor spatial distribution coordinates, the correlated signal data is mapped to the physical space coordinate system, forming spatiotemporal fusion data. The sensor spatial distribution coordinates are pre-calibrated two-dimensional plane coordinates of the circuit board, with the unit uniformly in millimeters. During the mapping process, each correlated data point is matched with the physical coordinates of the corresponding sensor, so that each data point simultaneously contains information in four dimensions: timestamp, voltage value, current value, and spatial coordinates, fully reflecting the spatiotemporal correlation characteristics of the signal. For example, the correlated voltage and current data correspond to the sensor's calibration coordinates of 25mm and 40mm, and after mapping, spatiotemporal fusion data is formed that includes a 1000ns timestamp, 1.0V voltage, 0.5A current, and 25mm and 40mm coordinates.

[0060] Subsequently, the signal-to-noise ratio (SNR) of the spatiotemporal fusion data was calculated to determine the environmental noise interference level. The SNR calculation employed a sliding window method with a window length of 100 sampling points, corresponding to a duration of 1 μs. The signal power was taken as the mean square value of the effective signal within the window, and the noise power was taken as the mean square value of the sensor's floor noise when there was no signal input. The calculation results were expressed in dB. The environmental noise interference level was mapped to a range of 0 to 1 using the minimum-maximum normalization method; a higher SNR value corresponds to a lower environmental noise interference level.

[0061] In this embodiment, the denoising parameters need to be dynamically adjusted according to the noise interference level to smooth the spatiotemporal fusion data and remove environmental noise. The denoising process employs db4 wavelet transform technology. The parameter adjustment rules are as follows: when the noise interference level is below 0.3, a 3-level wavelet decomposition and soft thresholding are used; when the noise interference level is between 0.3 and 0.7, a 5-level wavelet decomposition is used; and when the noise interference level is above 0.7, a 7-level wavelet decomposition and hard thresholding are used. The processing first performs multi-level wavelet decomposition on the signal, then performs thresholding on the high-frequency coefficients after decomposition, and finally reconstructs the signal through inverse wavelet transform to complete the filtering of environmental noise.

[0062] For example, the environmental noise interference level of a certain spatiotemporal fusion data is 0.6. The corresponding signal is reconstructed after using 5-layer db4 wavelet decomposition and soft thresholding of the high-frequency coefficients, which effectively filters out the high-frequency environmental noise superimposed on the effective signal.

[0063] Subsequently, bilinear interpolation resolution compensation technology is used to preserve signal detail features. The processed signal segments are then stitched together in chronological order to form a purified signal sequence. Resolution compensation addresses the sampling resolution differences of different sensor specifications by uniformly mapping all signal data to a standard voltage resolution of 0.1mV and a standard current resolution of 0.1mA. During compensation, interpolation algorithms preserve transient detail features such as rising and falling edges of the signal. Signal segment stitching is performed in ascending order of timestamps. A weighted average method is used for overlapping portions of adjacent segments to achieve a smooth transition and avoid signal jumps at the stitching points.

[0064] For example, data collected by a 12-bit resolution sensor is compensated by bilinear interpolation and then unified with 16-bit resolution data to a standard resolution of 0.1mV. All processed segments are then spliced ​​together in chronological order to form a continuous and uninterrupted purified signal sequence.

[0065] In step S103, the extraction of the time-domain and frequency-domain features of the purified signal sequence, combined with the delay duration for phase correction, and the obtaining of the salient feature distribution of the abnormal signal through clustering and feature similarity calculation of the corrected features, include:

[0066] Extract time-domain and frequency-domain features from the purified signal sequence;

[0067] The delay duration is compared with a preset delay threshold. If the delay duration exceeds the delay threshold, the frequency domain feature is phase aligned and corrected.

[0068] Clustering is performed on the corrected time-domain and frequency-domain features to divide them into feature clusters;

[0069] Calculate the feature similarity between each feature cluster, filter clusters with similarity higher than a preset similarity threshold, integrate the filtered feature clusters, construct a feature mapping matrix, and obtain the salient feature distribution of the abnormal signal.

[0070] It should be noted that, firstly, time-domain and frequency-domain features are extracted from the purified signal sequence. Time-domain features include signal peaks, valleys, fluctuation period, rising slope, falling slope, and root mean square value, calculated directly from continuous sampling points of the time series. Frequency-domain features are extracted using Fast Fourier Transform (FFT) technology. The time-domain signal is first converted to the frequency domain, and then the spectral energy distribution, fundamental amplitude, harmonic component proportion, and dominant frequency position are calculated. All extracted features are mapped to the [0,1] interval using the min-max normalization method to eliminate the magnitude differences between different features.

[0071] For example, from the purification voltage signal sequence of a certain FPGA chip, a time domain peak of 1.05V and a fluctuation period of 20ns were extracted. After fast Fourier transform, a frequency domain feature with a main frequency of 50MHz and a harmonic component ratio of 12% was extracted.

[0072] Next, the delay duration is compared with a preset delay threshold. If the delay duration exceeds the threshold, phase alignment correction is performed on the frequency domain characteristics. The delay threshold is statistically set based on the clock cycle of the integrated circuit and the signal transmission path length. The minimum clock cycle of integrated circuits is generally in the 10ns range, and the signal transmission delay on the PCB trace is approximately 3.3ns per millimeter. Statistical analysis of the normal transmission delay of various chips over the past two years shows that more than 90% of compliant delays do not exceed 1ns. Therefore, the basic delay threshold is set to 1ns. For high-precision, high-frequency chip scenarios, the threshold can be lowered to 0.5ns, and for low-frequency, general-purpose chip scenarios, it can be raised to 2ns. During phase correction, the corresponding phase offset is calculated based on the delay duration, and the phase spectrum of the frequency domain characteristics is shifted to compensate for the shift, achieving precise phase alignment of voltage and current signals. For example, if the transmission delay of a signal is 3ns, exceeding the basic threshold of 1ns, the calculated phase offset is 54 degrees. The phase spectrum of the frequency domain characteristics is then shifted accordingly to complete the phase alignment correction.

[0073] Subsequently, the corrected time-domain and frequency-domain features are clustered to form feature clusters. First, the corrected time-domain and frequency-domain features are concatenated into a unified multi-dimensional feature vector, and then the K-Means++ algorithm is used for clustering. The initial number of cluster centers is determined using the elbow rule; based on historical fault feature datasets, the optimal number of clusters is set to 5, corresponding to five categories: normal signals, minor anomalies, moderate anomalies, severe anomalies, and random noise. The algorithm's iteration limit is set to 100 times, and the convergence threshold is set to 0.001. Iteration stops when the offset of the cluster centers is less than the convergence threshold for three consecutive rounds, ultimately yielding the divided feature clusters. For example, concatenating the corrected 6-dimensional time-domain and frequency-domain features into a feature vector, after K-Means++ clustering, results in 5 feature clusters, one of which corresponds to the feature set of severe anomaly signals.

[0074] Next, the feature similarity between each feature cluster is calculated. Clusters with similarity higher than a preset similarity threshold are selected, and the selected feature clusters are integrated to construct a feature mapping matrix, obtaining the salient feature distribution of the abnormal signal. Feature similarity is obtained by calculating the cosine similarity between feature vectors, with a value ranging from 0 to 1. The closer the value is to 1, the higher the feature overlap between clusters. The similarity threshold is set based on the statistical matching effect of the historical fault feature database. Statistical analysis of fault diagnosis data from the past year shows that clusters with similarity exceeding 0.7 have a fault feature matching accuracy of over 88%, therefore the basic similarity threshold is set to 0.7. For high-precision fault diagnosis scenarios, the threshold can be increased to 0.75, and for rapid screening scenarios, it can be decreased to 0.65.

[0075] It should be noted that when integrating clusters, clusters with similarity higher than a threshold are merged, and the mean, variance and distribution range of each cluster are retained. A feature mapping matrix is ​​constructed with rows corresponding to feature dimensions and columns corresponding to clusters. Finally, the feature distribution patterns of abnormal clusters are extracted from the matrix to obtain the significant feature distribution of abnormal signals.

[0076] For example, the similarity between the current abnormal cluster and the historical fault feature cluster is calculated to be 0.82, which exceeds the basic threshold of 0.7. After integrating the two, a feature mapping matrix is ​​constructed, and the significant feature distribution of the abnormal signal with a voltage drop amplitude of 50mV and a duration of 0.5ns is extracted.

[0077] In step S104, if the significant feature distribution exceeds a preset fluctuation judgment threshold, it is determined to be a potential circuit overload event. The discrete points of the signal pulses corresponding to the potential circuit overload event are extracted to obtain the time stamp of the abnormal event, including:

[0078] Calculate the energy density of the salient features distributed in the multidimensional feature space;

[0079] The energy density is compared with a preset fluctuation judgment threshold. If the energy density exceeds the fluctuation judgment threshold, it is determined to be a potential circuit overload event.

[0080] Extract the signal pulse corresponding to the potential circuit overload event from the purification signal sequence, and determine the discrete sampling points of the pulse;

[0081] The time stamp of the abnormal event is calculated based on the sampling time of the discrete sampling points.

[0082] It should be noted that, firstly, when calculating the energy density of salient feature distribution in a multidimensional feature space, the multidimensional feature vectors corresponding to the salient feature distribution are first normalized. The min-max normalization method is used to map all feature dimensions to the interval between 0 and 1, eliminating the influence of different feature magnitudes on the calculation results. The energy density is obtained by dividing the sum of the squares of the values ​​of each feature dimension by the total number of feature dimensions. The calculated result ranges from 0 to 1; a higher value indicates a stronger signal fluctuation and a greater deviation from normal signals. For example, the salient feature distribution of an abnormal signal corresponds to a 6-dimensional normalized feature vector, the sum of the squares of the values ​​of each dimension is 2.88, and the total number of feature dimensions is 6, resulting in an energy density of 0.48.

[0083] It's worth noting that the fluctuation judgment threshold is set based on statistical data of characteristic events from the normal operation and overload events of digital integrated circuits over the past two years. The lowest energy density of all confirmed circuit overload events is statistically analyzed and used as the base threshold of 0.25. For high-precision automotive-grade chips, this threshold can be increased to 0.2 to avoid missing potential faults. For consumer-grade general-purpose chips, it can be decreased to 0.3 to reduce false positives. This threshold has been verified with tens of thousands of sets of chip operating data, achieving an overload event identification accuracy of over 90%. The energy density is compared with the preset fluctuation judgment threshold. If the energy density exceeds the threshold, it is judged as a potential circuit overload event. For example, if the calculated energy density of a chip signal is 0.48, exceeding the base threshold of 0.25, the system determines that the signal corresponds to a potential circuit overload event.

[0084] Subsequently, the signal pulses corresponding to potential circuit overload events are extracted from the purification signal sequence. When determining the discrete sampling points of the pulses, the purification signal sequence of the corresponding time period is first extracted according to the time interval of energy density exceeding the threshold. Then, the mean and standard deviation of the signal during normal operation are calculated, and the sampling points in the sequence whose amplitude exceeds the mean of the normal signal plus or minus three times the standard deviation are identified and marked as the discrete sampling points of the signal pulses.

[0085] For example, the purification signal sequence during the period from 100ns to 150ns when the energy density exceeds the threshold is extracted, and 12 sampling points whose amplitudes exceed the normal range are identified and marked as discrete sampling points of the signal pulse corresponding to the overload event.

[0086] It should be noted that when calculating the timestamp of an abnormal event based on the sampling times of discrete sampling points, the earliest sampling time among the discrete sampling points is taken as the start time of the abnormality, and the latest sampling time is taken as the end time of the abnormality. Simultaneously, the sampling time corresponding to the pulse peak is recorded as the peak time of the abnormality, forming a complete timestamp of the abnormal event. The sampling time is calculated by multiplying the sampling sequence number by the sampling interval, which is determined by the sampling frequency set during the acquisition phase. For example, if the earliest sampling time among the discrete sampling points is 102ns, the latest sampling time is 148ns, and the sampling time corresponding to the peak is 120ns, the final timestamp of the abnormal event is: start 102ns, peak 120ns, and end 148ns.

[0087] In step S105, the step of tracing the path nodes of the fault propagation in the purification signal sequence according to the time stamp, constructing the spatial topology of the path nodes, determining the boundary of the fault impact range, and determining the propagation direction and key impact area of ​​the abnormal signal in conjunction with the spatial distribution information of the sensors includes:

[0088] Based on the time stamp, extract local waveform data from the purification signal sequence, identify amplitude jump points in the waveform, and mark them as fault propagation path nodes;

[0089] The path nodes are projected onto a preset sensor spatial distribution coordinate system to form a set of spatial nodes with timestamps;

[0090] Based on the coordinate distribution of the spatial node set, a spatial topology is constructed, and the spatial topology is analyzed using a density clustering algorithm to determine the boundary of the fault impact range.

[0091] Extract the timestamp sequence of the spatial node set and construct a vector trajectory from the earliest timestamp node to the latest timestamp node;

[0092] By combining the spatial distribution information of the sensors with the vector trajectory, the propagation direction and key affected area of ​​the abnormal signal are determined.

[0093] It should be noted that, firstly, local waveform data from the purified signal sequence is extracted based on time stamps, and amplitude jump points in the waveforms are identified and marked as fault propagation path nodes. The extraction range extends 200ns forward from the start time of the abnormal event and 200ns backward from the end time to ensure coverage of the complete propagation process of the fault signal. Amplitude jump points are identified by calculating the first-order difference of the signal, and the difference result represents the instantaneous rate of change of the signal amplitude. The jump judgment threshold is set based on the statistical setting of signal fluctuations during normal operation of the integrated circuit. Under normal operating conditions, the absolute value of the first-order difference of the signal does not exceed 0.05V / ns for more than 99% of the time. Therefore, the basic jump threshold is set to 0.05V / ns. For high-precision automotive-grade chip scenarios, it can be lowered to 0.03V / ns, and for consumer-grade general-purpose chip scenarios, it can be increased to 0.07V / ns. When the absolute value of the first-order difference of a sampling point exceeds the jump threshold, the sampling point is marked as an amplitude jump point and simultaneously marked as a fault propagation path node.

[0094] For example, if an abnormal event is time-stamped as starting at 102ns and ending at 148ns, and local waveform data from 80ns to 348ns is extracted, the absolute value of the first-order difference at a certain sampling point is calculated to be 0.08V / ns, which exceeds the basic threshold of 0.05V / ns. This sampling point is then marked as a node in the fault propagation path.

[0095] Next, the path nodes are projected onto a preset sensor spatial distribution coordinate system, forming a set of time-stamped spatial nodes. The sensor spatial distribution coordinate system is a pre-calibrated two-dimensional Cartesian coordinate system for the circuit board, with the coordinate unit uniformly in millimeters. Each path node corresponds to the calibrated physical coordinates of the sensor that acquired the signal. The projection process matches the corresponding spatial coordinates for each path node and simultaneously binds the sampling timestamp of that node, so that each spatial node contains three types of information: x-axis coordinate, y-axis coordinate, and sampling timestamp. After all the projected nodes are summarized, a set of time-stamped spatial nodes is formed.

[0096] For example, the sensor calibration coordinates corresponding to a certain fault propagation path node are 25mm and 40mm, and the sampling timestamp is 105ns. After projection, a spatial node containing 25mm, 40mm, and 105ns is formed. All similar nodes are summarized to form a complete set of spatial nodes.

[0097] Subsequently, based on the coordinate distribution of the spatial node set, a spatial topology is constructed, and the spatial topology is analyzed using a density clustering algorithm to determine the boundary of the fault impact range. The clustering algorithm used is the DBSCAN algorithm, which can effectively identify high-density clustered regions and discrete noise points in space. The neighborhood radius ε of the algorithm is statistically set based on the average spacing of the sensor array. The average spacing of sensors on the circuit board is 5mm, so the basic neighborhood radius ε is set to 5mm, and the minimum number of samples MinPts is set to 2. For high-density pin chip scenarios, ε can be lowered to 3mm, and for large-area industrial control circuit board scenarios, ε can be increased to 8mm. After the algorithm completes the clustering of the spatial node set, it identifies the connected high-density node regions, and the bounding rectangle of these regions is defined as the boundary of the fault impact range. For example, after the spatial node set is clustered by the DBSCAN algorithm, the connected high-density nodes are distributed within the range of 10mm to 50mm on the x-axis and 20mm to 60mm on the y-axis. This rectangular region is defined as the boundary of the fault impact range.

[0098] Next, the timestamp sequence of the spatial node set is extracted to construct a vector trajectory pointing from the earliest timestamp node to the latest timestamp node. First, all nodes in the spatial node set are sorted in ascending order of timestamp, and the sorted timestamp sequence and the corresponding spatial coordinates of the nodes are extracted. Using the coordinates of the earliest timestamp node as the vector starting point and the coordinates of the latest timestamp node as the vector ending point, a vector trajectory in a two-dimensional plane is constructed. The direction of the vector represents the spatial propagation path of the abnormal signal, and the magnitude of the vector represents the straight-line distance of signal propagation. For example, the earliest timestamp of 102ns corresponds to coordinates of 12mm and 21mm, and the latest timestamp of 148ns corresponds to coordinates of 45mm and 60mm. Finally, a vector trajectory is constructed pointing from 12mm and 21mm to 45mm and 60mm.

[0099] Finally, by combining the spatial distribution information of the sensors with the vector trajectory, the propagation direction of the abnormal signal and the critical impact area are determined. The direction of the vector trajectory indicates the propagation direction of the abnormal signal. The critical impact area is determined through buffer analysis of the vector trajectory. Using the vector trajectory as the center line, a strip-shaped area extending outwards with a width consistent with the average spacing between the sensors forms the basic critical impact area. Simultaneously, by combining the spatial distribution information of the sensors, the corresponding circuit functional modules within the area are included in the critical impact range, ensuring that the area covers all circuit units affected by the fault.

[0100] For example, the vector trajectory points from the power module toward the FPGA chip, and extends 5mm to both sides of the trajectory as the center line to form a strip-shaped area. The power regulation module and the circuit area corresponding to the decoupling capacitor array within this area are identified as the key areas affected by abnormal signals.

[0101] In step S106, the analysis of the module dependencies and path node weights corresponding to the propagation direction and the key influence area, combined with pre-acquired historical fault modes, determines the preliminary location range of the fault source, including:

[0102] Based on the propagation direction and the key influence area, retrieve the circuit topology data and construct a module dependency matrix;

[0103] Map the fault propagation path nodes to the module dependency matrix and calculate the weight value of each node;

[0104] The distribution map features formed by the weight values ​​are extracted and matched with the pre-acquired historical fault modes. Cluster analysis is performed on the matched historical fault source coordinates to generate high-density coordinate clusters.

[0105] Using the high-density coordinate cluster as the core, the initial location range of the fault source is delineated.

[0106] It should be noted that, firstly, based on the propagation direction and key affected areas, the circuit topology data of the integrated circuit is retrieved. This data includes the physical coordinates, electrical connections, signal flow, and control command links of each functional module. The rows and columns of the module dependency matrix correspond to all circuit functional modules within the key affected areas. The matrix element values ​​represent the signal dependency strength between two modules. The dependency strength is calculated by weighting the number of electrical connections between modules and the signal transmission frequency. Elements corresponding to modules without direct connections are set to 0.

[0107] For example, the key affected areas include the power conditioning module, the decoupling capacitor array, and the FPGA main module. By retrieving the electrical connection relationship between the three, the dependency strength between the power conditioning module and the decoupling capacitor array is calculated to be 0.9, and the dependency strength between the decoupling capacitor array and the FPGA main module is 0.85, thus constructing a 3×3 module dependency matrix.

[0108] Subsequently, the nodes of the fault propagation path are mapped to the module dependency matrix, and the weight values ​​of each node are calculated. First, the fault propagation path nodes are matched to the corresponding functional modules in the matrix according to their physical coordinates, completing the node mapping. The node weight value is obtained by weighted summation of module dependency strength, node anomaly amplitude, and node timestamp chronological order. The weight allocation is: module dependency strength 0.5, node anomaly amplitude 0.3, and node timestamp chronological order 0.2. This weight combination is based on the accuracy statistics of historical fault tracing. Module dependency strength directly reflects the critical position of the node in the fault propagation link and is assigned the highest weight. Node anomaly amplitude reflects the strength of the fault signal and is assigned a medium weight. Nodes with earlier timestamps are closer to the fault source and are assigned lower weights. Before calculation, all three indicators are mapped to the 0-1 range using min-max normalization to eliminate differences in magnitude. For example, a fault propagation path node is mapped to the power regulation module. The normalized module dependency strength is 0.9, the abnormal amplitude is 0.85, and the timestamp coefficient is 0.9. The weighted sum of these values ​​gives the node a weight of 0.9×0.5 + 0.85×0.3 + 0.9×0.2 = 0.885.

[0109] Subsequently, the distribution map features formed by the weight values ​​are extracted, including the weight gradient change rate, spatial clustering, peak coordinates, and distribution range. Feature matching employs a CNN convolutional neural network model with an architecture of 2 convolutional layers, 2 pooling layers, and 1 fully connected layer. The convolutional kernel size is set to 3×3, the stride is 1, the activation function is ReLU, and the pooling method is max pooling. The training set contains over 20,000 annotated integrated circuit fault case maps accumulated over the past 3 years, divided into training and validation sets in an 8:2 ratio. The optimizer is Adam, with an initial learning rate of 0.001, decreasing by 0.1 every 15 epochs until reaching 0.0001. The loss function is cross-entropy loss. During training, the matching accuracy of the validation set is monitored in real time, and iteration stops when the accuracy fluctuation is less than 0.002 for 10 consecutive epochs. The model outputs the similarity between features and historical fault patterns, filters historical fault patterns with similarity exceeding a preset matching threshold, and extracts the coordinates of the corresponding historical fault source.

[0110] It is worth noting that the matching threshold was set based on historical matching performance statistics. Specifically, over 5000 independent test samples covering various typical scenarios, including high-density logic chips, mixed-signal chips, and high-frequency RF circuits, were imported into the simulation test platform. The optimization objective was to maximize the harmonic mean of precision and recall (F1 score), and a grid search was performed within the [0,1] interval with a step size of 0.05. Statistical results show that when the basic threshold is set to 0.75, the model achieves the global optimum in terms of overall F1 score across various scenarios, effectively filtering out most false matches caused by accidental noise, and maintaining a stable matching accuracy of over 85%. For high-precision chip scenarios with extremely low tolerance for false alarms, the threshold can be increased to 0.8 to ensure absolute reliability of the matching results; for general-purpose chip scenarios requiring improved detection of potential faults, it can be decreased to 0.7. Those skilled in the art can adjust this flexibly according to the specific chip type. The extracted historical fault source coordinates were analyzed using the DBSCAN density clustering algorithm to generate high-density coordinate clusters. The algorithm neighborhood radius was set to 3 mm, and the minimum number of samples was set to 3 to adapt to the coordinate distribution scale of the circuit board.

[0111] For example, the current weight distribution map, calculated by the CNN model, has a similarity of 0.88 with the historical power module failure mode, which exceeds the basic threshold of 0.75. The coordinates of 12 historical failure sources corresponding to this mode are extracted and generated into a high-density coordinate cluster centered at 12.8mm and 21.2mm after DBSCAN clustering.

[0112] Finally, using the high-density coordinate cluster as the center, a preliminary location range for the fault source is defined. Using the center coordinates of the high-density coordinate cluster as the center and the maximum cluster radius obtained from the clustering algorithm as the base radius, a circular preliminary location range for the fault source is defined by extending outwards by 2mm of redundancy. This extended redundancy range is based on the placement accuracy of the circuit board sensors and can cover minor deviations in coordinate positioning. In high-precision chip scenarios, the extended range can be reduced to 1mm, and in large-area industrial control board scenarios, it can be expanded to 3mm. After the range is defined, the circuit functional modules included within the range are simultaneously confirmed to ensure coverage of all potential fault source locations.

[0113] For example, the center coordinates of the high-density coordinate cluster are 12.8mm and 21.2mm, and the maximum radius of the cluster is 2.5mm. After expanding outward by 2mm, a circular area with a radius of 4.5mm and a center of 12.8mm and 21.2mm is defined as the initial location range of the fault source.

[0114] In step S107, the step of calculating the path deviation value and positioning time accuracy between the real-time signal and the preset standard reference waveform based on multiple backtracking paths within the initial position interval, and calculating the comprehensive matching probability by combining the path deviation value and the positioning time accuracy, includes:

[0115] Based on the initial location range and circuit topology, multiple candidate backtracking paths are generated.

[0116] Calculate the Euclidean distance between the real-time signal and the preset standard reference waveform on each candidate backtracking path to obtain the path deviation value;

[0117] The positioning time accuracy is obtained by analyzing the time difference between the signal anomaly trigger time and the control command issuance time.

[0118] Preset weighting coefficients are assigned to the path deviation value and the positioning time accuracy, and the comprehensive matching probability of each candidate backtracking path is calculated by weighting.

[0119] It should be noted that, firstly, when generating multiple candidate backtracking paths based on the initial location interval and circuit topology, the underlying circuit topology data within the initial location interval is retrieved first. This data includes conductive trace connections, via locations, signal flow directions, and component pin mapping information. A depth-first search algorithm is employed, starting from all circuit nodes within the initial location interval and performing a fully connected traversal along the reverse path of the fault signal propagation. During the traversal, valid paths containing key nodes of the fault propagation path are retained, while invalid paths without electrical connections are eliminated, ultimately generating multiple consecutive candidate backtracking paths. The maximum traversal depth for path generation is set based on the physical size of the circuit board. For conventional industrial control circuit boards, the maximum traversal depth is set to 20 nodes. For high-density chip packaging scenarios, this can be reduced to 10 nodes, and for large-area motherboard scenarios, it can be increased to 30 nodes, ensuring coverage of all potential fault source paths.

[0120] For example, the initial location interval contains 5 key nodes of the power regulation module. After a depth-first search reverse traversal, 8 valid candidate backtracking paths containing key nodes of fault propagation are generated.

[0121] Next, the Euclidean distance between the real-time signal and the preset standard reference waveform on each candidate backtracking path is calculated to obtain the path deviation value. The preset standard reference waveform is the standard voltage and current waveform collected at the corresponding path nodes under normal fault-free operation of this integrated circuit model, which has been pre-calibrated and stored in the waveform database. The real-time signal is the purified signal sequence corresponding to each node on the candidate backtracking path. First, the real-time signal and the standard reference waveform are aligned on the time axis, and numerical sequences of equal length are truncated at the same sampling interval. Then, the Euclidean distance between the two sequences is calculated. Finally, the distance value is mapped to the interval of 0 to 1 using the minimum-maximum normalization method to obtain the path deviation value. The higher the value, the greater the deviation of the real-time signal from the normal waveform. For example, after aligning the real-time signal sequence on a candidate backtracking path with the standard reference waveform, the calculated Euclidean distance is 0.22, and after normalization, the path deviation value is 0.22.

[0122] Subsequently, the positioning time is obtained by analyzing the time difference between the signal anomaly trigger time and the control command issuance time. The control command issuance time is extracted from the runtime sequence log of the integrated circuit main control unit and is the precise timestamp of the command that triggered the circuit state change. The signal anomaly trigger time is the start timestamp of the previously calibrated anomaly event. The absolute value of the difference between the two times is calculated; the smaller the time difference, the higher the timing match. The positioning time accuracy is normalized and mapped to the range of 0 to 1. The maximum allowable time difference for normalization is based on the clock cycle setting of the integrated circuit. For chips with a standard 100MHz clock, the maximum allowable time difference is set to 20ns. For high-precision, high-frequency chips, this can be lowered to 10ns, and for low-frequency, general-purpose chips, it can be increased to 30ns. When the time difference exceeds the maximum allowable value, the accuracy is 0; when the time difference is 0, the accuracy is 1. For example, if the signal anomaly trigger time for a candidate backtracking path is 102ns and the control command issuance time is 105ns, the absolute value of the time difference is 3ns, which is less than the maximum allowable value of 20ns. After normalization, the positioning time accuracy is calculated to be 0.85.

[0123] Subsequently, preset weighting coefficients are assigned to the path deviation value and positioning time accuracy, and the comprehensive matching probability of each candidate backtracking path is calculated using a weighted average. The weight combination is set based on the accuracy statistics of historical fault tracing. The path deviation value directly reflects the degree of deviation of the signal from the normal operating state and has a stronger correlation with the source of the fault; its weight is set to 0.6. The positioning time accuracy reflects the temporal matching degree of the fault signal; its weight is set to 0.4. The comprehensive matching probability is calculated by subtracting the normalized path deviation value from 1, multiplying it by the corresponding weight, and adding the normalized positioning time accuracy multiplied by the corresponding weight. The final result ranges from 0 to 1; a higher value indicates a better matching degree between the path and the source of the fault. For example, if the normalized path deviation value of a candidate backtracking path is 0.22 and the positioning time accuracy is 0.85, the calculated comprehensive matching probability is 0.808.

[0124] In step S108, the path with the highest comprehensive matching probability and the smallest path deviation value is selected as the optimal backtracking path, and the starting node coordinates of the optimal backtracking path are extracted to obtain the location of the circuit fault root cause.

[0125] It should be noted that, firstly, a two-dimensional screening process is performed on all candidate backtracking paths. First, the set of paths with the highest comprehensive matching probability is selected. Then, the path with the smallest path deviation value is selected from this set, ultimately determining the optimal backtracking path. The priority of the screening dimensions is based on statistical results from integrated circuit fault tracing cases over the past three years. The comprehensive matching probability has a higher correlation with the fault source, therefore it is used as the first screening dimension. The path deviation value is used as the second supplementary screening dimension. This screening rule has been verified through over 20,000 actual fault cases, with the fault source location accuracy consistently above 92%. For example, among the eight candidate backtracking paths, the highest comprehensive matching probability is 0.808, corresponding to two paths. One of these paths has the smallest deviation value of 0.22, and this path is determined to be the optimal backtracking path.

[0126] Next, the coordinates of the starting node of the optimal backtracking path are extracted. The coordinate system is consistent with the preset two-dimensional plane coordinate system of the sensor spatial distribution, and the unit is uniformly millimeters. The starting node of the optimal backtracking path is the final starting point of the reverse tracing of the fault signal, and it is also the physical location where the fault signal first appears in the circuit. The calibrated coordinates of this node are the location of the root cause of the circuit fault. During the coordinate extraction process, the correspondence between the node and the circuit topology is verified simultaneously to confirm the circuit functional module and component information to which the node belongs, ensuring that the positioning result completely matches the physical layout of the circuit.

[0127] For example, the starting node coordinates of the optimal backtracking path are 12.7mm and 21.1mm, which correspond to the via position of the power regulation module feedback loop in the circuit topology. These coordinates are the root cause of the circuit fault.

[0128] In summary, this invention discloses a digital integrated circuit fault diagnosis method, which includes acquiring integrated circuit voltage fluctuations, instantaneous current changes, and transmission delay data; obtaining a purified signal sequence through spatiotemporal integration and dynamic denoising; extracting time-frequency features and performing phase correction to obtain the distribution of significant abnormal signal features; identifying potential overload events and marking abnormal times when thresholds are exceeded; tracing the fault propagation path and locking the initial fault source range by combining module dependencies and historical fault modes; and accurately locating the root cause of the circuit fault by screening the optimal backtracking path through multi-path comparison. This achieves efficient and accurate diagnosis of integrated circuit faults, meeting the core requirements of operational safety, timeliness, and reliability.

[0129] Reference Figure 2The second embodiment of the present invention provides a digital integrated circuit fault diagnosis system, comprising:

[0130] The data acquisition module is used to acquire voltage fluctuation data, instantaneous current change data, and data transmission delay time of the digital integrated circuit.

[0131] The preprocessing module is used to timestamp-align the voltage fluctuation data and the instantaneous current change data, integrate the spatiotemporal data with the preset sensor spatial distribution information, and perform noise reduction processing on the integrated data to form a purified signal sequence.

[0132] The feature extraction module is used to extract the time-domain and frequency-domain features of the purified signal sequence, and perform phase correction in combination with the delay duration. By performing clustering processing and feature similarity calculation on the corrected features, the significant feature distribution of the abnormal signal is obtained.

[0133] An anomaly determination module is used to determine a potential circuit overload event if the distribution of the significant features exceeds a preset fluctuation determination threshold, extract the discrete points of the signal pulses corresponding to the potential circuit overload event, and obtain the time stamp of the anomaly event.

[0134] The path tracing module is used to trace the path nodes of the fault propagation in the purification signal sequence according to the time stamp, construct the spatial topology of the path nodes, determine the boundary of the fault impact range, and combine the sensor spatial distribution information to determine the propagation direction and key impact area of ​​the abnormal signal.

[0135] The source location module is used to analyze the module dependencies and path node weights corresponding to the propagation direction and the key impact area, and in combination with the pre-acquired historical fault modes, to determine the preliminary location range of the fault source.

[0136] The probability calculation module is used to calculate the path deviation value and positioning time accuracy between the real-time signal and the preset standard reference waveform based on multiple backtracking paths within the initial position interval, and to calculate the comprehensive matching probability by combining the path deviation value and the positioning time accuracy.

[0137] The path filtering module is used to filter the path with the highest comprehensive matching probability and the smallest path deviation value as the optimal backtracking path, extract the starting node coordinates of the optimal backtracking path, and obtain the location of the root cause of the circuit fault.

[0138] It should be noted that the digital integrated circuit fault diagnosis system provided in this embodiment of the invention is used to execute all the process steps of the digital integrated circuit fault diagnosis method in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0139] It should be noted that the system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the system embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0140] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method for fault diagnosis of digital integrated circuits, characterized in that, include: Acquire voltage fluctuation data, instantaneous current change data, and data transmission delay time of digital integrated circuits; The voltage fluctuation data and the instantaneous change data of the current are timestamped and integrated with the preset sensor spatial distribution information for spatiotemporal data integration. After the integrated data is denoised, a purified signal sequence is formed. The time-domain and frequency-domain features of the purified signal sequence are extracted, and phase correction is performed in combination with the delay duration. The distribution of significant features of the abnormal signal is obtained by clustering and calculating the feature similarity of the corrected features. If the distribution of the significant features exceeds the preset fluctuation judgment threshold, it is determined to be a potential circuit overload event. The discrete points of the signal pulses corresponding to the potential circuit overload event are extracted to obtain the time stamp of the abnormal event. Based on the time stamp, trace the path nodes of the fault propagation in the purification signal sequence, construct the spatial topology of the path nodes, determine the boundary of the fault impact range, and combine the sensor spatial distribution information to determine the propagation direction and key impact area of ​​the abnormal signal. Analyze the module dependencies and path node weights corresponding to the propagation direction and the key affected area, and combine them with the previously acquired historical fault modes to determine the preliminary location range of the fault source. Based on multiple backtracking paths within the initial position range, the path deviation value and positioning time accuracy between the real-time signal and the preset standard reference waveform are calculated, and the comprehensive matching probability is calculated by combining the path deviation value and the positioning time accuracy. The path with the highest overall matching probability and the smallest path deviation value is selected as the optimal backtracking path. The coordinates of the starting node of the optimal backtracking path are extracted to obtain the location of the root cause of the circuit fault.

2. The digital integrated circuit fault diagnosis method according to claim 1, characterized in that, The acquisition of voltage fluctuation data, instantaneous current change data, and data transmission delay of the digital integrated circuit includes: The system acquires raw data on the operating status of digital integrated circuits at high frequency through a sensor array. The raw data includes voltage signal fluctuation range, instantaneous change information of current signal, and data transmission timing data. The raw data of the operating status is processed to standardize the format, and to unify the data sampling granularity and numerical range; Invalid records and random interference data are removed from the original running status data to obtain preliminary processed data; Voltage fluctuation data and instantaneous current change data are extracted from the preliminary processed data, and the time difference of the data transmission timing data is calculated to obtain the data transmission delay.

3. The digital integrated circuit fault diagnosis method according to claim 1, characterized in that, The process involves aligning the voltage fluctuation data and the instantaneous current change data with timestamps, integrating the data with preset sensor spatial distribution information, and then denoising the integrated data to form a purified signal sequence, including: Extract the timestamps from the voltage fluctuation data and the instantaneous change data of the current, and associate and bind the voltage data and current data corresponding to the same timestamp; Based on the preset sensor spatial distribution coordinates, the associated signal data is mapped to the physical space coordinate system to form spatiotemporal fusion data; Calculate the signal-to-noise ratio of the spatiotemporal fusion data to determine the environmental noise interference level; The denoising parameters are dynamically adjusted according to the noise interference level to smooth the spatiotemporal fusion data and remove environmental noise. By preserving signal details through resolution compensation technology, the processed signal segments are spliced ​​together in chronological order to form a purified signal sequence.

4. The digital integrated circuit fault diagnosis method according to claim 1, characterized in that, The process involves extracting the time-domain and frequency-domain features of the purified signal sequence, performing phase correction based on the delay duration, and then clustering and calculating feature similarity on the corrected features to obtain the significant feature distribution of the abnormal signal, including: Extract time-domain and frequency-domain features from the purified signal sequence; The delay duration is compared with a preset delay threshold. If the delay duration exceeds the delay threshold, the frequency domain feature is phase aligned and corrected. Clustering is performed on the corrected time-domain and frequency-domain features to divide them into feature clusters; Calculate the feature similarity between each feature cluster, filter clusters with similarity higher than a preset similarity threshold, integrate the filtered feature clusters, construct a feature mapping matrix, and obtain the salient feature distribution of the abnormal signal.

5. The digital integrated circuit fault diagnosis method according to claim 1, characterized in that, If the significant feature distribution exceeds a preset fluctuation judgment threshold, it is determined to be a potential circuit overload event. The discrete points of the signal pulses corresponding to the potential circuit overload event are extracted to obtain the time stamp of the abnormal event, including: Calculate the energy density of the salient features distributed in the multidimensional feature space; The energy density is compared with a preset fluctuation judgment threshold. If the energy density exceeds the fluctuation judgment threshold, it is determined to be a potential circuit overload event. Extract the signal pulse corresponding to the potential circuit overload event from the purification signal sequence, and determine the discrete sampling points of the pulse; The time stamp of the abnormal event is calculated based on the sampling time of the discrete sampling points.

6. The digital integrated circuit fault diagnosis method according to claim 1, characterized in that, The process of tracing the path nodes of the fault propagation in the purification signal sequence based on the time stamp, constructing the spatial topology of the path nodes, determining the boundary of the fault impact range, and combining the sensor spatial distribution information to determine the propagation direction and key impact area of ​​the abnormal signal includes: Based on the time stamp, extract local waveform data from the purification signal sequence, identify amplitude jump points in the waveform, and mark them as fault propagation path nodes; The path nodes are projected onto a preset sensor spatial distribution coordinate system to form a set of spatial nodes with timestamps; Based on the coordinate distribution of the spatial node set, a spatial topology is constructed, and the spatial topology is analyzed using a density clustering algorithm to determine the boundary of the fault impact range. Extract the timestamp sequence of the spatial node set and construct a vector trajectory from the earliest timestamp node to the latest timestamp node; By combining the spatial distribution information of the sensors with the vector trajectory, the propagation direction and key affected area of ​​the abnormal signal are determined.

7. The digital integrated circuit fault diagnosis method according to claim 1, characterized in that, The analysis of the propagation direction and the module dependencies and path node weights corresponding to the key impact areas, combined with pre-acquired historical fault patterns, determines the preliminary location range of the fault source, including: Based on the propagation direction and the key influence area, retrieve the circuit topology data and construct a module dependency matrix; Map the fault propagation path nodes to the module dependency matrix and calculate the weight value of each node; The distribution map features formed by the weight values ​​are extracted and matched with the pre-acquired historical fault modes. Cluster analysis is performed on the matched historical fault source coordinates to generate high-density coordinate clusters. Using the high-density coordinate cluster as the core, the initial location range of the fault source is delineated.

8. The digital integrated circuit fault diagnosis method according to claim 1, characterized in that, The step of calculating the path deviation value and positioning time accuracy between the real-time signal and the preset standard reference waveform based on multiple backtracking paths within the initial position interval, and combining the path deviation value and the positioning time accuracy to calculate the comprehensive matching probability includes: Based on the initial location range and circuit topology, multiple candidate backtracking paths are generated. Calculate the Euclidean distance between the real-time signal and the preset standard reference waveform on each candidate backtracking path to obtain the path deviation value; The positioning time accuracy is obtained by analyzing the time difference between the signal anomaly trigger time and the control command issuance time. Preset weighting coefficients are assigned to the path deviation value and the positioning time accuracy, and the comprehensive matching probability of each candidate backtracking path is calculated by weighting.

9. A digital integrated circuit fault diagnosis system, characterized in that, include: The data acquisition module is used to acquire voltage fluctuation data, instantaneous current change data, and data transmission delay time of the digital integrated circuit. The preprocessing module is used to timestamp-align the voltage fluctuation data and the instantaneous current change data, integrate the spatiotemporal data with the preset sensor spatial distribution information, and perform noise reduction processing on the integrated data to form a purified signal sequence. The feature extraction module is used to extract the time-domain and frequency-domain features of the purified signal sequence, and perform phase correction in combination with the delay duration. By performing clustering processing and feature similarity calculation on the corrected features, the significant feature distribution of the abnormal signal is obtained. An anomaly determination module is used to determine a potential circuit overload event if the distribution of the significant features exceeds a preset fluctuation determination threshold, extract the discrete points of the signal pulses corresponding to the potential circuit overload event, and obtain the time stamp of the anomaly event. The path tracing module is used to trace the path nodes of the fault propagation in the purification signal sequence according to the time stamp, construct the spatial topology of the path nodes, determine the boundary of the fault impact range, and combine the sensor spatial distribution information to determine the propagation direction and key impact area of ​​the abnormal signal. The source location module is used to analyze the module dependencies and path node weights corresponding to the propagation direction and the key impact area, and in combination with the pre-acquired historical fault modes, to determine the preliminary location range of the fault source. The probability calculation module is used to calculate the path deviation value and positioning time accuracy between the real-time signal and the preset standard reference waveform based on multiple backtracking paths within the initial position interval, and to calculate the comprehensive matching probability by combining the path deviation value and the positioning time accuracy. The path filtering module is used to filter the path with the highest comprehensive matching probability and the smallest path deviation value as the optimal backtracking path, extract the starting node coordinates of the optimal backtracking path, and obtain the location of the root cause of the circuit fault.

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