Memory control method and memory system
By dynamically configuring the mapping granularity of multiple sequential write regions in a DRAM-less SSD, the performance deficiency in large-scale storage arrays is solved, achieving efficient data storage and extending device lifespan.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU FEISHU TECH CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-12
AI Technical Summary
Traditional DRAM-less SSDs are underperforming in large-scale storage arrays, especially during sequential writes where the actual bandwidth cannot approach the hardware peak. Furthermore, frequent small-granularity random write operations exacerbate garbage collection pressure and write amplification, affecting lifespan.
By mapping the physical blocks of the memory module into multiple sequential write regions and dynamically configuring the mapping granularity according to the load type, multiple sequential write regions are written concurrently. By utilizing the multi-level parallel hardware architecture of the memory module, channel-level, chip-level, and plane-level concurrent writes are achieved, and the data is migrated as a whole during garbage collection to reduce the amount of effective data movement.
It significantly improves sequential write bandwidth, optimizes data storage patterns, reduces write amplification during garbage collection, and extends the lifespan of storage devices.
Smart Images
Figure CN122018788A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, specifically to a memory control method and a storage system. Background Technology
[0002] In the storage technology field, traditional solid-state drives (SSDs) are typically equipped with independent dynamic random access memory (DRAM) chips to cache address mapping tables and user data, thereby improving read and write access speeds. The presence of external DRAM significantly increases the hardware cost, power consumption, and design complexity of SSDs. DRAM-less SSDs have significant advantages over DRAM-based SSDs in terms of cost and power consumption. However, in practical applications, especially in scenarios where multiple SSDs are combined into large-scale storage arrays to provide higher capacity and reliability, their shortcomings in performance, task processing capabilities, and lifespan become particularly prominent. Therefore, the field needs to address the performance challenges faced in large-scale array applications while maintaining the cost advantage of DRAM-less SSDs. This can be achieved by fully exploring and synergistically utilizing the parallel capabilities of hardware at all levels from the array to the device's internal components through innovative control methods, maximizing sequential write bandwidth, and optimizing data storage patterns.
[0003] However, in existing technologies, storage control methods fail to fully adapt to and effectively utilize the inherent multi-level parallel hardware architecture (multi-channel, multi-chip, multi-plane) within SSDs. This results in the actual bandwidth of the storage array during sequential writes often failing to approach the theoretical peak of the hardware. Furthermore, frequent small-granularity random write operations not only exacerbate garbage collection pressure at both the storage array and SSD device levels but also significantly increase write amplification, thereby further impacting the overall lifespan of the SSD. Summary of the Invention
[0004] This specification describes a memory control method through several embodiments.
[0005] In a first aspect, embodiments of this specification provide a memory control method applied to a memory controller, the memory controller being connected to at least one memory module, the method comprising:
[0006] The physical blocks of the memory module are mapped into multiple sequential write regions;
[0007] Configure the mapping granularity for the sequential write region based on the current load. The mapping granularity defines the number and distribution of physical blocks corresponding to a single sequential write region.
[0008] Receive write requests from the host for a logical address range, split the write data of the write request into multiple sub-data blocks, and concurrently allocate the multiple sub-data blocks to multiple sequential write regions. The number of sub-data blocks is customized according to the requirements.
[0009] Based on the mapping granularity configured in the sequential write region, the sub-data block is split into multiple data pages;
[0010] Multiple data pages are concurrently written to physical blocks of the target sequential write region.
[0011] Furthermore, the mapping granularity includes at least one of the following configurations:
[0012] First mapping granularity: One sequential write region corresponds to one physical block within a storage plane;
[0013] Second mapping granularity: A sequential write region corresponds to a set of logical blocks consisting of physical blocks in at least two different storage planes within the same memory chip;
[0014] The third mapping granularity: A sequential write region corresponds to a set of logical blocks consisting of physical blocks in all storage planes within the same memory chip.
[0015] Furthermore, configuring the mapping granularity for the sequential write region based on the current load includes:
[0016] When the load is continuous large-capacity data writing, the second mapping granularity or the third mapping granularity is used for configuration;
[0017] When the load consists of multiple random small-capacity data writes, the first mapping granularity is used for configuration.
[0018] Furthermore, concurrently writing the multiple sub-data blocks to multiple target sequential write regions includes:
[0019] The memory controller will issue multiple write commands to different memory modules in parallel;
[0020] For a single memory module, the received write command points to multiple sequential write regions within the device based on different memory chips.
[0021] Furthermore, the method includes:
[0022] Inside the memory module, for a command to write to a single sequential write region, if the region is configured with a second or third mapping granularity, the write data in that region is further split into data slices corresponding to the number of physical blocks in the logical block set, and written concurrently to each physical block in the logical block set.
[0023] Furthermore, the method also includes:
[0024] When the memory controller first writes to the starting logical address of a sequential write region, the memory module allocates one or more free physical blocks from one or more corresponding storage planes according to the mapping granularity of the region, and establishes a mapping relationship between the sequential write region and the allocated physical blocks.
[0025] Furthermore, the method includes:
[0026] In response to triggering garbage collection for a sequential write region, all valid data within the sequential write region is migrated to a newly allocated set of physical blocks.
[0027] Update the mapping relationship between the sequential write region and the physical block, while keeping the logical address presented by the sequential write region to the memory controller unchanged.
[0028] Secondly, embodiments of this specification provide a memory controller applied to a memory array comprising multiple memory modules, the memory controller being configured to:
[0029] Each physical block of a storage device is mapped to multiple sequential write regions, and the mapping granularity of the sequential write regions is dynamically configured according to the current input / output load. The mapping granularity defines the number of physical blocks corresponding to a single sequential write region and its distribution among different storage planes.
[0030] Receive write requests from the host;
[0031] Based on the dynamically configured mapping granularity, the write data of the write request is split into multiple sub-data blocks;
[0032] The plurality of sub-data blocks are concurrently mapped and written to a plurality of target sequential write regions, the plurality of target sequential write regions being distributed in one or more of the memory modules;
[0033] The memory controller issues write commands in parallel, while utilizing channel-level concurrency between memory modules and chip-level concurrency within a single memory module.
[0034] Thirdly, embodiments of this specification provide a storage device for communication connection with the memory controller, comprising:
[0035] Flash memory media includes multiple channels, multiple memory chips, each memory chip contains multiple memory planes, and each memory plane contains multiple physical blocks;
[0036] The device controller is configured as follows:
[0037] Receive a write command from the memory controller, the command instructing data to be written to a target sequential write region;
[0038] Based on the mapping granularity configured by the memory controller for the target sequential write region, a corresponding set of physical blocks is determined;
[0039] Write the data to be written into the determined physical block;
[0040] When the mapping granularity indicates that the target sequential write region corresponds to a set of logical blocks consisting of physical blocks in multiple storage planes within the same storage chip, the device controller controls the flash memory medium to concurrently write the data to be written to each physical block in the set of logical blocks to achieve plane-level concurrency.
[0041] Fourthly, embodiments of this specification provide a storage system, including:
[0042] The memory controller and the storage device are connected to the memory controller through multiple channels;
[0043] The memory controller splits a host's write request into multiple sub-data blocks and controls these sub-data blocks to be concurrently written to multiple sequential write regions distributed across the multiple storage devices, thereby enabling multi-level hardware concurrent writing between channels, between chips, and between intra-chip planes in the storage system.
[0044] The beneficial effects of the technical solutions provided in some embodiments of this specification include at least the following:
[0045] This invention uses a memory controller to parallelly split host write requests into multiple sub-data blocks, concurrently writing them to sequential write regions distributed across different storage devices and different memory chips within the same storage device. The mapping granularity defines the number of physical blocks corresponding to a single sequential write region and their distribution across different storage planes. The memory controller can flexibly select different mapping granularities based on the current input / output load. When sequential write regions are configured with a larger mapping granularity, plane-level concurrent writing can be achieved within a single storage device, significantly improving sequential write bandwidth. The mapping relationship between sequential write regions and a set of physical blocks can be dynamically established and migrated according to the load. When garbage collection is required, all valid data within a sequential write region can be migrated to a newly allocated set of physical blocks, and the mapping relationship updated, while maintaining the logical address presented to the controller for that region. This significantly reduces the amount of valid data moved during garbage collection, lowers write amplification effects, and thus reduces wear on the storage medium, helping to extend the lifespan of the entire storage system.
[0046] Other features and advantages of various embodiments of this specification will be further revealed in the following detailed description and accompanying drawings. Attached Figure Description
[0047] To more clearly illustrate the technical solutions in the embodiments of this specification, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0048] Figure 1 This is a schematic flowchart of the memory control method provided in the embodiments of this specification.
[0049] Figure 2 This is a schematic diagram of the system architecture provided for the embodiments of this specification.
[0050] Figure 3 This is one of the channel structure diagrams provided in the embodiments of this specification.
[0051] Figure 4 This is a schematic diagram of planar parallel write / read provided for embodiments of this specification.
[0052] Figure 5 This is a schematic diagram of concurrent writing provided for an embodiment of this specification. Detailed Implementation
[0053] The technical solutions of the embodiments of this specification will be explained and described below with reference to the accompanying drawings. However, the following embodiments are only preferred embodiments of this specification and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments in the implementation methods without creative effort are all within the protection scope of this specification.
[0054] The terms "first," "second," "third," etc., in the description, claims, and accompanying drawings are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.
[0055] In the following description, terms such as “inner,” “outer,” “upper,” “lower,” “left,” and “right” are used only to facilitate the description of the embodiments and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this specification.
[0056] All data involved in this application are information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data comply with the relevant laws, regulations and standards of the relevant countries and regions.
[0057] This embodiment provides a memory control method applied to a memory controller, the memory controller being connected to at least one DRAM-less storage device, the storage medium of which is NAND Flash. Please refer to the appendix. Figure 1 The method mainly includes the following steps:
[0058] Step S101: Map the physical blocks of the storage device into multiple sequential write regions.
[0059] Storage device 20 includes a memory controller 210 and a memory module 220 connected thereto, consisting of at least one storage device (such as a DRAM-less SSD). The flash memory medium inside the memory module 220 has a multi-layer parallel structure: it includes multiple channels, each channel connecting multiple dies, each die containing multiple independently operable planes, and each plane consisting of multiple erasable blocks.
[0060] The memory controller 210 logically divides the physical blocks in the physical flash memory medium that can be used for sequential writing into multiple sequential write zones. Each sequential write zone acts as a logical management unit and receives sequential write data from the host.
[0061] This embodiment uses NAND Flash as the storage medium. The internal physical structure of NAND Flash has multi-level parallelism, specifically:
[0062] Channel (CH): A channel is a set of physical pins on a NAND Flash chip, responsible for receiving and transmitting data and commands. Different channels are completely independent and can operate in parallel, which forms the hardware basis for achieving channel-level concurrency.
[0063] Chip Enable (CE): Each CE pin corresponds to an independent physical memory chip (Die). Within the same channel (CH), different memory chips are selected by enabling different CE pins. Different CEs (i.e., different memory chips) within the same channel cannot be selected simultaneously for data transmission, but access efficiency can be improved through methods such as interleaving.
[0064] Storage Plane: Each memory die contains multiple independently operable storage planes. Different storage planes within the same memory die (same CE) can perform write or read operations in parallel, which is key to achieving plane-level concurrency. However, it is usually required that multiple planes operating in parallel access the same physical block number to maintain the synchronization of operations.
[0065] Each storage device in memory module 220 contains multiple channels (CH), each channel can connect to multiple storage chips (Die), and each storage chip contains multiple storage planes (Plane). This hardware architecture provides physical support for subsequent implementation of multi-level concurrent writes.
[0066] Step S102: Configure the mapping granularity for the sequential write region based on the current load.
[0067] Mapping granularity defines the number of physical blocks corresponding to a single sequential write region and their distribution within the flash memory medium. Specifically, mapping granularity can be configured to at least one of the following:
[0068] First mapping granularity: A sequential write region corresponds to a physical block within a storage plane.
[0069] Second mapping granularity: A sequential write region corresponds to a set of logical blocks consisting of physical blocks in at least two different storage planes within the same memory die.
[0070] The third mapping granularity: A sequential write region corresponds to a set of logical blocks consisting of physical blocks in all storage planes within the same memory chip.
[0071] The current load refers to the real-time input / output (I / O) characteristics monitored by the memory controller 210. When a series of write requests with large data volumes and consecutive logical addresses are received, it is determined to be a continuous large-capacity data write load, and the second or third mapping granularity is used in this case. When a series of write requests with small data volumes and scattered logical addresses are received, it is determined to be a multiple random small-capacity data write load, and the first mapping granularity is used in this case to provide a more flexible garbage collection granularity.
[0072] Step S103: Receive write requests from the host and perform concurrent splitting and mapping.
[0073] The memory controller 210 receives a write request from the host for a specific logical address range. Based on the mapping granularity configured for the target region of the request in step S102 and the parallel structure of the storage array, the controller splits the write data of the write request into multiple sub-data blocks. The controller concurrently allocates these sub-data blocks to multiple target sequential write regions. The memory controller 210 generates multiple write commands and sends them in parallel to different storage devices, utilizing channel-level concurrency between storage devices. For a single storage device, the received multiple write commands point to multiple sequential write regions within that device based on different storage chips, utilizing chip-level concurrency.
[0074] Step S104: Perform data page splitting and concurrent writing within the storage device.
[0075] After each storage device receives a write command pointing to a specific sequential write region, it performs the write operation according to the mapping granularity configured for that region. Specifically:
[0076] If the region is configured with the first mapping granularity, the sub-data blocks are directly written to the corresponding single physical block.
[0077] If the region is configured with the second or third mapping granularity, the sub-data block to be written will be further divided into multiple data pages corresponding to the number of physical blocks in the logical block set. These data pages will be written concurrently to each physical block in the logical block set to achieve planar concurrency within the storage chip.
[0078] S105: Dynamically establish and maintain the mapping relationship of sequential write regions.
[0079] When the memory controller 210 first writes to the starting logical address of a sequential write region, the storage device allocates one or more free physical blocks from one or more corresponding storage planes according to the mapping granularity configured for the region, and establishes an initial mapping relationship between the sequential write region and the allocated physical blocks, which is recorded in the internal L2P (Logic to Physical) mapping table.
[0080] The mapping is dynamic. In response to operations such as garbage collection, the storage device can migrate all valid data in a sequentially written region to a newly allocated set of physical blocks, and then update the internal mapping.
[0081] This embodiment provides a storage system for implementing the memory control method described in the preceding embodiments. Figure 2As shown, the overall architecture of the storage system includes a host 10 and a storage device 20. The host 10 is electrically connected to the storage device 20, and the storage device 20 receives read and write commands sent by the host 10 to access data.
[0082] The storage device 20 is the core device for implementing the technical solution of this invention. The storage device 20 mainly includes a memory controller 210 and a memory module 220. The memory module 220 can be composed of multiple DRAM-less SSD member disks. The memory controller 210 includes a processor 211 and an interface control circuit 212. The processor 211 processes read and write instructions received from the host 10, executes the read and write instructions according to the memory control method provided in this embodiment, and generates execution instructions to control the execution of the memory module 220. The execution instructions are converted into electrical signals that the memory module can respond to through the interface control circuit 212.
[0083] During the operation of the storage system, when host 10 initiates a write request, the interaction and data processing flow is as follows:
[0084] After the memory controller 210 starts up, it initializes each SSD and maps its physical block into multiple sequential write zones. A zone is a logically contiguous address space and serves as the basic unit for concurrent writes.
[0085] The controller dynamically configures the mapping granularity of the Zone based on the current load type:
[0086] For continuous large-capacity write scenarios: a third mapping granularity is adopted, that is, one Zone corresponds to a logical block set consisting of all physical blocks in the Plane (memory plane) within a Die (memory chip).
[0087] Random small-capacity write scenario: The first mapping granularity is adopted, that is, one Zone corresponds to one physical block within one Plane, with a capacity of 64 KB.
[0088] like Figure 3 As shown, the host sends a 1MB sequential write request.
[0089] Upon receiving the request, the memory controller 210 splits the write data into four 256KB sub-data blocks. The memory controller 210 then distributes these four sub-data blocks in parallel to four different SSDs via four channels, with each SSD responsible for writing one 256KB sub-data block.
[0090] Each SSD receives a write command pointing to a sequential write region within it (configured in third granularity). Each SSD concurrently processes 4 regions, corresponding to 4 dies.
[0091] Inside each SSD, as shown in the attached document Figure 4 As shown, the memory controller 210 further divides the 256KB sub-data block into four 64KB data slices, which correspond to four physical blocks (one for each plane) in the set of logical blocks mapped to the target sequential write region.
[0092] Subsequently, these four data slices are controlled to be written concurrently to four different planes. (See attached image.) Figure 5 As shown, this invention triggers 4-channel concurrency at the system level through a 1MB write operation, and triggers 1-channel chip concurrency and 4-channel planar concurrency within each SSD, fully exploiting the hardware parallel capabilities.
[0093] Meanwhile, the write zones are aligned with the physical structure, ensuring that data is neatly arranged on the flash memory, facilitating subsequent garbage collection, effectively reducing write amplification, and thus extending the SSD's lifespan. This allows 1MB of data to be written to the flash memory in an extremely short time, with sequential write bandwidth approaching the theoretical peak of the hardware.
[0094] Garbage Collection (GC): When the controller first writes to the starting LBA of a Zone, the SSD allocates free physical blocks from the corresponding Plane according to the Zone granularity and establishes an L2P (Logical-Physical) mapping relationship. When invalid data in a Zone reaches a threshold, GC is triggered. The SSD migrates all valid data in that Zone to a newly allocated set of physical blocks, updates the L2P table, and keeps the Zone's logical address unchanged, transparent to the controller.
[0095] This embodiment achieves the following technical effects through dynamic Zone mapping and multi-level concurrent write mechanism: the sequential write bandwidth is greatly improved to meet the needs of high-bandwidth application scenarios; the data is neatly arranged in the flash memory, the GC efficiency is high, and the lifespan of the SSD is extended; it supports multiple mapping granularities to adapt to different load types; and the Zone mapping and GC are transparent to the host and controller, requiring no modification to the upper-layer application.
Claims
1. A memory control method applied to a memory controller, the memory controller being connected to at least one storage device, characterized in that, The method includes: The physical blocks of the storage device are mapped into multiple sequential write regions; Configure the mapping granularity for the sequential write region based on the current load. The mapping granularity defines the number and distribution of physical blocks corresponding to a single sequential write region. Receive a write request from the host for a logical address range, split the write data of the write request into multiple sub-data blocks, and concurrently distribute the multiple sub-data blocks to multiple sequential write regions; Based on the mapping granularity configured in the sequential write region, the sub-data block is split into multiple data pages; Multiple data pages are concurrently written to physical blocks of the target sequential write region.
2. The memory control method according to claim 1, characterized in that, The mapping granularity includes at least one of the following configurations: First mapping granularity: One sequential write region corresponds to one physical block within a storage plane; Second mapping granularity: A sequential write region corresponds to a set of logical blocks consisting of physical blocks in at least two different storage planes within the same memory chip; The third mapping granularity: A sequential write region corresponds to a set of logical blocks consisting of physical blocks in all storage planes within the same memory chip.
3. The memory control method according to claim 2, characterized in that, The step of configuring the mapping granularity for the sequential write region based on the current load includes: When the load is continuous large-capacity data writing, the second mapping granularity or the third mapping granularity is used for configuration; When the load consists of multiple random small-capacity data writes, the first mapping granularity is used for configuration.
4. The memory control method according to claim 1, characterized in that, Writing the multiple sub-data blocks concurrently to multiple target sequential write regions includes: The memory controller will issue multiple write commands to different storage devices in parallel; For a single storage device, the received write command points to multiple sequential write areas within the device based on different storage chips.
5. A memory control method according to claim 4, characterized in that, The method includes: Inside the storage device, for a command to write to a single sequential write region, if the region is configured with a second or third mapping granularity, the write data in that region is further split into data slices corresponding to the number of physical blocks in the logical block set, and written concurrently to each physical block in the logical block set.
6. A memory control method according to claim 1, characterized in that, The method also includes: When the memory controller first writes to the starting logical address of a sequential write region, the storage device allocates one or more free physical blocks from one or more corresponding storage planes according to the mapping granularity of the region, and establishes a mapping relationship between the sequential write region and the allocated physical blocks.
7. A memory control method according to claim 6, characterized in that, The method includes: In response to triggering garbage collection for a sequential write region, all valid data within the sequential write region is migrated to a newly allocated set of physical blocks. Update the mapping relationship between the sequential write region and the physical block, while keeping the logical address presented by the sequential write region to the memory controller unchanged.
8. A memory controller applied to a memory array comprising multiple memory devices, characterized in that, The memory controller is configured to: Each physical block of a storage device is mapped to multiple sequential write regions, and the mapping granularity of the sequential write regions is dynamically configured according to the current input / output load. The mapping granularity defines the number of physical blocks corresponding to a single sequential write region and its distribution among different storage planes. Receive write requests from the host; Based on the dynamically configured mapping granularity, the write data of the write request is split into multiple sub-data blocks; The plurality of sub-data blocks are concurrently mapped and written to a plurality of target sequential write regions, the plurality of target sequential write regions being distributed in one or more of the storage devices; The memory controller issues write commands in parallel, while utilizing channel-level concurrency between the storage devices and chip-level concurrency within a single storage device.
9. A storage device for communicatively connecting to a memory controller as claimed in claim 8, characterized in that, include: Flash memory media includes multiple channels, multiple memory chips, each memory chip contains multiple memory planes, and each memory plane contains multiple physical blocks; The device controller is configured as follows: Receive a write command from the memory controller, the command instructing data to be written to a target sequential write region; Based on the mapping granularity configured by the memory controller for the target sequential write region, a corresponding set of physical blocks is determined; Write the data to be written into the determined physical block; When the mapping granularity indicates that the target sequential write region corresponds to a set of logical blocks consisting of physical blocks in multiple storage planes within the same storage chip, the device controller controls the flash memory medium to concurrently write the data to be written to each physical block in the set of logical blocks to achieve plane-level concurrency.
10. A storage system, characterized in that, include: The memory controller as described in claim 8; And multiple storage devices as described in claim 9, connected to the memory controller via multiple channels; The memory controller splits a host's write request into multiple sub-data blocks and controls these sub-data blocks to be concurrently written to multiple sequential write regions distributed across the multiple storage devices, thereby enabling multi-level hardware concurrent writing between channels, between chips, and between intra-chip planes in the storage system.