Reconfigurable processor fusing neuromorphic and general computing and execution method

Abstract

The application discloses a reconfigurable processor and an execution method fusing neuromorphic and general computing, and comprises a total control module and an on-chip network module, wherein the on-chip network module comprises a control module, a pulse storage module, a weight storage module, a pulse time module, a LIF neuron module and a classification comparison module. The execution method comprises the following steps: acquiring an input data set; selecting a working mode of the on-chip network module according to the input data set; and performing data recognition processing on the input data set according to the working mode, and outputting a data recognition output result. The application realizes the working of a central processing unit (CPU) and a spiking neural network (SNN) in a single core, thereby improving the utilization rate of a heterogeneous core and reducing the delay of core-to-accelerator communication. The application can be widely applied to the technical field of neural network accelerator as a reconfigurable processor and an execution method fusing neuromorphic and general computing.

Description

Technical Field

[0001] This invention relates to the field of neural network accelerator technology, and in particular to a reconfigurable processor and execution method that integrates neuromorphic and general computing. Background Technology

[0002] With the continuous development of deep neural networks, their computational complexity makes us urgently need more storage resources and larger computing resources. This makes us urgently need a low-overhead neural network accelerator. Spiking neural networks, due to their discreteness and binary nature, and their computation and processing of binary data, are regarded as the third generation of neural networks. They have the advantages of low power consumption and low overhead. More and more neuromorphic hardware architectures are focusing on the implementation of spiking neural networks.

[0003] RISC-V, a reduced instruction set computer architecture (ISA), is widely used in microprocessor and embedded system design as a highly efficient ISA. RISC-V adopts the design philosophy of RISC computers, aiming to provide a simple, flexible, and scalable architecture. It features a customizable instruction set, optional privilege levels, and scalable instruction set extensions, making it suitable for various application scenarios. RISC-V's characteristics include: open standards, modular design, strong compatibility, ease of implementation, and customization. It has gained widespread attention and adoption from academia and industry worldwide, becoming the preferred architecture in many fields, including embedded systems, the Internet of Things (IoT), artificial intelligence, and cloud computing.

[0004] Heterogeneous architectures utilize multiple different types of processors or computing units within a single system to achieve higher performance and efficiency. In heterogeneous architectures combining neural network accelerators and general-purpose processors, these two types of processors are used to handle different tasks. Neural network accelerators are hardware accelerators that efficiently perform neural network computations. They typically employ custom hardware architectures and instruction sets, enabling parallel processing of large-scale matrix and vector operations to accelerate the training and inference processes of neural networks. The design focus of neural network accelerators is to provide highly optimized computational performance and low power consumption to meet the demands of deep learning applications. General-purpose processors, on the other hand, are versatile processors capable of performing various types of computational tasks. They possess flexible instruction sets and general-purpose computing capabilities, enabling them to handle a wide range of algorithms and applications. In heterogeneous architectures, neural network accelerators and general-purpose processors can collaborate, sharing tasks and resources. General-purpose processors can handle general computational tasks, while neural network accelerators can specialize in neural network-related computations. This fully leverages the high performance and low power consumption characteristics of neural network accelerators, improving the overall system performance and energy efficiency.

[0005] However, existing communication between CPUs and accelerators requires adherence to specific communication protocols involving data transfer, synchronization, and error handling. These additional communication operations increase latency, resulting in a core-to-accelerator communication latency issue in traditional heterogeneous architectures. Furthermore, heterogeneous architectures necessitate the rational allocation of tasks to different types of processors to fully utilize their characteristics and advantages. Improper task allocation can lead to idle processors and wasted resources. Integrating different types of processors into a single system can increase system complexity and cost; therefore, consideration must be given to inter-processor communication and collaboration mechanisms, as well as system-level scheduling and management. Summary of the Invention

[0006] To address the aforementioned technical problems, the present invention aims to provide a reconfigurable processor and execution method that integrates neuromorphic and general computing. By implementing the operation of a central processing unit (CPU) and a spiking neural network (SNN) in a single core, the utilization rate of heterogeneous cores is improved and the latency of core-to-accelerator communication is reduced.

[0007] The first technical solution adopted in this invention is: a reconfigurable processor integrating neuromorphic and general-purpose computing, comprising a main control module and an on-chip network module, wherein the main control module is connected to the on-chip network module, wherein:

[0008] The main control module is used to select the operating mode of the on-chip network module according to the input dataset. The operating modes of the on-chip network module include spiking neural network mode and CPU mode.

[0009] The on-chip network module performs data recognition processing on the input dataset according to the corresponding working mode and outputs the data recognition output result.

[0010] Furthermore, the on-chip network module includes a control module, a pulse storage module, a weight storage module, a pulse timing module, a LIF neuron module, and a classification comparison module. The first output of the control module is connected to the input of the pulse storage module; the second output of the control module is connected to the first input of the weight storage module; the third output of the control module is connected to the first input of the pulse timing module; the first output of the pulse storage module is connected to the first input of the control module; the second output of the pulse storage module is connected to the first input of the LIF neuron module; the output of the weight storage module is connected to the second input of the LIF neuron module; the first output of the pulse timing module is connected to the second input of the control module; the second output of the pulse timing module is connected to the third input of the LIF neuron module; the first output of the LIF neuron module is connected to the input of the classification comparison module; the second output of the LIF neuron module is connected to the second input of the weight storage module; and the third output of the LIF neuron module is connected to the second input of the pulse timing module. Wherein:

[0011] The control module is used to encode the input dataset and generate an input data pulse signal;

[0012] The pulse storage module is used to store the input data pulse signal and transmit it to the LIF neuron module;

[0013] The weight storage module is used to store the initial weights of the input data pulse signal and transmit them to the LIF neuron module;

[0014] The pulse timing module is used to select the corresponding operating mode and count the time intervals according to the input data pulse signal, as well as update the neuron state for each time interval. The operating modes include supervised gradient substitution operating mode and unsupervised time-dependent plasticity operating mode.

[0015] The LIF neuron module is used to perform multiplication and accumulation calculations based on the input data pulse signal and the weight of the input data pulse signal, and to determine whether to emit a pulse based on the calculation result;

[0016] The classification and comparison module is used to count the emitted pulses and select the neuron corresponding to the largest number of emitted pulses for data recognition processing.

[0017] The second technical solution adopted in this invention is: an execution method for a reconfigurable processor that integrates neuromorphic and general-purpose computing, comprising the following steps:

[0018] Obtain the input dataset;

[0019] The operating mode of the on-chip network module is selected based on the input dataset;

[0020] The input dataset is processed for data recognition according to the working mode, and the data recognition output result is output.

[0021] Furthermore, the step of selecting the operating mode of the on-chip network module based on the input dataset specifically includes:

[0022] The input dataset is split to obtain pattern data and make a judgment.

[0023] If the pattern data of the input dataset is "0", then the working mode of the on-chip network module is set to CPU mode;

[0024] If the pattern data of the input dataset is "1", then the working mode of the on-chip network module is set to spiking neural network mode.

[0025] Furthermore, the step of performing data recognition processing on the input dataset according to the working mode and outputting the data recognition output result specifically includes:

[0026] Based on the CPU mode, the input dataset is subjected to decoding, addition, calculation, and recognition processing to obtain the data recognition output result in CPU mode;

[0027] Based on the spiking neural network pattern, the data packets of the input dataset are judged and processed;

[0028] If the data packets of the input dataset are supervised labels, the input dataset is processed for data recognition through supervised gradient substitution running mode, and the data recognition output result under the first spiking neural network mode is output.

[0029] If the data packets of the input dataset are unsupervised labels, the input dataset is processed for data recognition through the unsupervised time-dependent plasticity operation mode, and the data recognition output result under the second spiking neural network mode is output.

[0030] The data recognition output results are integrated from the data recognition output results in the CPU mode, the data recognition output results in the first spiking neural network mode, and the data recognition output results in the second spiking neural network mode to obtain the data recognition output result.

[0031] Furthermore, the step of performing data recognition processing on the input dataset through a supervised gradient substitution operation mode and outputting the data recognition output result under the first spiking neural network mode specifically includes:

[0032] The input dataset is frequency encoded to obtain discrete pulse signals, and the supervised gradient substitution operation mode is added as a label to the discrete pulse signals to obtain the input data pulse signals.

[0033] The supervised gradient substitution operation mode label and the weight of the input data pulse signal are read from the input data pulse signal to determine the learning mode. Based on the pulse signal and label value of the input data pulse signal, the accumulation and updating of the membrane voltage are selected to obtain the updated membrane voltage.

[0034] The updated membrane voltage is compared with the threshold voltage. When the updated membrane voltage is greater than the threshold voltage, a pulse is emitted and counted to obtain the number of emitted pulses.

[0035] The difference between the number of transmitted pulses and the tag value of the input data pulse signal is calculated, and the result is multiplied by the pulse signal of the input data pulse signal based on the chain rule to obtain the gradient value.

[0036] A learning rate is introduced, the gradient value is multiplied by the learning rate, and the weights of the input data pulse signal are updated to obtain the updated weights of the input data pulse signal.

[0037] Based on the weights of the updated input data pulse signals, the time count is incremented by one until the time count meets the preset counting requirements. Frequency statistics processing is performed on the emitted pulses, and the neuron corresponding to the emitted pulse with the highest frequency is selected for data recognition processing. The data recognition output result under the first spiking neural network mode is then output.

[0038] Furthermore, the step of performing data recognition processing on the input dataset through an unsupervised time-dependent plasticity operating mode and outputting the data recognition output result under the second spiking neural network mode specifically includes:

[0039] The input dataset is frequency encoded to obtain discrete pulse signals, and the unsupervised time-dependent plasticity operation mode is added as a label to the discrete pulse signals to obtain the input data pulse signals.

[0040] The unsupervised time-dependent plasticity operating mode label in the input data pulse signal is read and the weight of the input data pulse signal is determined. The learning mode is determined and the membrane voltage is accumulated and updated based on the pulse signal and label value of the input data pulse signal to obtain the updated membrane voltage.

[0041] The updated membrane voltage is compared with a threshold voltage. If the updated membrane voltage is greater than the threshold voltage, a pulse is emitted.

[0042] The pulse emission times of the emitted pulses at the input and output neurons are obtained by a time counter, and the corresponding time difference is calculated. The weights of the input data pulse signals are updated according to the time difference to obtain the updated weights of the input data pulse signals.

[0043] Based on the weights of the updated input data pulse signals, the time count is incremented by one until the time count meets the preset counting requirements. Frequency statistics processing is performed on the emitted pulses, and the neuron corresponding to the emitted pulse with the highest frequency is selected for data recognition processing. The data recognition output result under the second pulse neural network mode is then output.

[0044] Furthermore, the specific expressions for the accumulation and updating of the membrane voltage are as follows:

[0045]

[0046] In the above formula, β represents the voltage decay constant, and α represents the current decay constant. This represents the pulse emitted by the i-th neuron in the l-th layer. This represents the membrane voltage corresponding to the i-th neuron in the l-th layer. U represents the membrane current corresponding to the i-th neuron in the l-th layer. reset This represents the reset voltage, and n represents the discrete time n.

[0047] Furthermore, the specific expression for the weight update of the input data pulse signal in the supervised gradient substitution operation mode is as follows:

[0048]

[0049] In the above formula, The weights representing the changes are denoted by L, which represents the loss function. The loss function is the mean squared error of the output pulse frequency and the label. The final result, obtained through a three-layer network, is the target value minus the pulse counter count. σ′ represents the derivative of the gradient substitution function. This represents the input layer pulse, and target represents the preset target value. When a pulse is emitted, the count is obtained as cnt. i .

[0050] Furthermore, the specific expression for the weight update of the input data pulse signal in the unsupervised time-dependent plasticity operation mode is as follows:

[0051]

[0052] In the above formula, Apre and A post τ represents the synaptic learning constant. pre τ represents the presynaptic membrane voltage decay constant. post Let denot be the postsynaptic membrane voltage decay constant, and Δt be the time difference before and after the pulse arrives at the synapse. The change in training weights ΔW(Δt) is obtained through exponential operation.

[0053] The beneficial effects of the processor and execution method of this invention are as follows: By selecting the working mode of the on-chip network module, which includes spiking neural network mode and CPU mode, the invention implements the operation of the central processing unit (CPU) and spiking neural network (SNN) in a single core. This avoids the problems caused by complex heterogeneous interface connections, realizes the function within a single core, and better reduces the communication latency between the core and the accelerator. Furthermore, by performing data recognition processing on the input dataset according to the corresponding working mode, the invention can flexibly allocate computing resources according to different application scenarios and task types, thereby achieving higher performance and energy efficiency, thus improving the utilization rate of heterogeneous cores and reducing the communication latency between the core and the accelerator. Attached Figure Description

[0054] Figure 1 This is a structural block diagram of a reconfigurable processor that integrates neuromorphic and general computing according to an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram illustrating the steps of an execution method for a reconfigurable processor that integrates neuromorphic and general computing according to an embodiment of the present invention.

[0056] Figure 3 This is a schematic diagram of the SNN network structure and corresponding RISC-V process in a specific embodiment of the present invention;

[0057] Figure 4 This is a schematic diagram illustrating SNN weight storage, RISC-V instructions, and data storage reuse in a specific embodiment of the present invention;

[0058] Figure 5 This is a schematic diagram illustrating the implementation of pulse storage and gradient storage using register file multiplexing in a specific embodiment of the present invention;

[0059] Figure 6 This is a circuit diagram of the LIF neuron module in a specific embodiment of the present invention;

[0060] Figure 7 This is a schematic diagram illustrating the input data packet and the meaning of each bit in a specific embodiment of the present invention;

[0061] Figure 8 This is a schematic diagram illustrating the steps of a supervised gradient substitution operation mode in a specific embodiment of the present invention;

[0062] Figure 9 This is a schematic diagram of the steps in the unsupervised STDP operation mode of a specific embodiment of the present invention. Detailed Implementation

[0063] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

[0064] Explanation of the technical terms used in this invention:

[0065] SNN (Spiking Neural Network) mode is a third-generation neural network model characterized by its higher level of biological neural simulation. In addition to neuronal and synaptic states, SNN mode introduces the concept of time, providing the most appropriate simulation of biological neuronal mechanisms. This neural network model uses spikes—discrete events occurring at specific points in time—rather than conventional continuous values. These spikes are often represented by differential equations that describe biological processes, particularly when the neuron's membrane potential reaches a specific threshold. In this mode, the network is typically sparsely connected and utilizes a special network topology.

[0066] CPU Modes: Primarily used in the computer field, CPU modes refer to the operating modes of the central processing unit (CPU) within a computer. CPU modes typically include kernel mode and user mode. In kernel mode, the CPU can access all system resources, including memory, I / O settings, and other system resources; therefore, the operating system and drivers usually run in this mode. Conversely, user mode provides a higher level of security, restricting user access to system resources to user space, which is the memory area available to processes. Switching between CPU modes is usually handled by the operating system. For example, when a program needs to access system resources, the operating system switches the CPU to kernel mode; when the operation is complete, the CPU switches back to user mode.

[0067] Spiking Neural Networks (SNNs): Spiking Neural Networks (SNNs) are a type of neural network model designed based on the workings of biological neurons and synapses. A key characteristic of SNNs is their simulation of the dynamics of brain neurons, using spikes for information processing. These spikes occur discretely at different points in time, corresponding to the differential equations of biological processes. SNNs are typically sparsely connected and employ a specific network topology.

[0068] Network on Chip (NoC): A network on a chip is a network that builds complex electronic systems on a single chip or System-on-a-Chip (SoC). NoC transmits information by distributing multiple processing units (or nodes) on a chip and using highly optimized communication protocols. The goal of NoC is to improve performance and energy efficiency through distributed computing and communication.

[0069] LIF neurons: LIF neurons are neurons with Leaky Integrate-and-Fire (LIF) properties. They are a neuron model that simulates the change in electrical potential and the firing of action potentials in neurons after receiving input signals. In the LIF neuron model, input signals are linearly superimposed and independent of other postsynaptic neurons. When the input signal exceeds a certain threshold, the neuron fires an action potential while simultaneously resetting its own potential to its resting potential. This process is independent and does not depend on the previous state. LIF neurons play an important role in some highly adaptive neurons, such as retinal ganglion cells and certain types of inhibitory neurons. Furthermore, LIF neurons can be used to study neural coding and the stability and dynamic behavior of neural networks.

[0070] STDP, or Sequence-Dependent Plasticity, is a type of neuronal connection plasticity that primarily depends on the relative timing of the action potentials of the presynaptic and postsynaptic neurons. In STDP, if two neurons are activated simultaneously, or if one neuron activates before the other, the connection strength between them increases. If one neuron activates after the other, the connection strength decreases. This plasticity is achieved by altering the connection strength between the presynaptic and postsynaptic neurons, a change dependent on their relative activation times. STDP plays a crucial role in neural network learning and memory; it is a way in which experience leads to plasticity in the connections between neurons, making it one of the key mechanisms for neural network adaptation and learning.

[0071] RISC-V Instructions: RISC-V is an instruction set architecture (ISA) known for its simple, modular, scalable, and open-source design. RISC-V includes a set of instructions that match the hardware circuitry and can be viewed as a collection of instructions. Its design aims to meet the needs of different application scenarios; therefore, different CPUs can have different instruction sets, which can be categorized into Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC) based on their complexity.

[0072] In existing embedded edge devices, their portability and small size severely limit hardware resources. Building deep learning capabilities in embedded devices often requires significant resource overhead for neural network training and computation, thus frequently employing heterogeneous architectures. However, traditional heterogeneous cores suffer from low utilization and substantial communication latency between the core and the accelerator. Our proposed method implements the operation of both the CPU and the SNN within a single core, avoiding the problems caused by complex heterogeneous interface connections. It achieves functionality within a single core while significantly reducing communication latency between the core and the accelerator. This invention combines supervised and unsupervised learning methods from SNNs, aiming to train neural networks under different datasets and training conditions, such as whether or not training labels are provided.

[0073] Based on this, refer to Figure 1 This invention provides a reconfigurable processor that integrates neuromorphic and general-purpose computing, comprising a main control module and an on-chip network module, wherein the main control module is connected to the on-chip network module, and:

[0074] The main control module is used to select the operating mode of the on-chip network module according to the input dataset. The operating modes of the on-chip network module include spiking neural network mode and CPU mode.

[0075] The on-chip network module performs data recognition processing on the input dataset according to the corresponding working mode and outputs the data recognition results.

[0076] Specifically, the reconfigurable processor's system modules mainly consist of a central control module and an on-chip network. The central control module is responsible for controlling the selection of processor modes, data input / output control, and on-chip and off-chip communication. The on-chip network consists of 64 cores, each of which comprises the following modules: a control module, a pulse storage module, a weight storage module, a pulse timing module, a LIF neuron module, and a classification and comparison module.

[0077] Furthermore, the on-chip network module includes a control module, a spike storage module, a weight storage module, a spike timing module, a LIF neuron module, and a classification comparison module. The first output of the control module is connected to the input of the spike storage module, the second output of the control module is connected to the first input of the weight storage module, and the third output of the control module is connected to the first input of the spike timing module. The first output of the spike storage module is connected to the first input of the control module, the second output of the spike storage module is connected to the first input of the LIF neuron module, the output of the weight storage module is connected to the second input of the LIF neuron module, the first output of the spike timing module is connected to the second input of the control module, the second output of the spike timing module is connected to the third input of the LIF neuron module, the first output of the LIF neuron module is connected to the input of the classification comparison module, the second output of the LIF neuron module is connected to the second input of the weight storage module, and the third output of the LIF neuron module is connected to the second input of the spike timing module.

[0078] The control module is used to encode the input dataset and generate input data pulse signals;

[0079] The pulse storage module is used to store input data pulse signals and transmit them to the LIF neuron module;

[0080] The weight storage module is used to store the initial weights of the input data pulse signal and transmit them to the LIF neuron module;

[0081] The pulse timing module is used to select the corresponding operating mode and count the time intervals based on the input data pulse signal, as well as update the neuron state for each time interval. The operating modes include supervised gradient substitution operating mode and unsupervised time-dependent plasticity operating mode.

[0082] like Figure 6 As shown, the LIF neuron module performs multiplication and accumulation calculations based on the input data pulse signal and its weights, and determines whether to emit a pulse based on the calculation result. A small module consists of three multiplexers and one 8-bit full adder. One multiplexer selects between two inputs to determine whether to accumulate the input weights w and the pulse. The other two multiplexers determine gradient changes and whether the previous layer neuron emits a pulse. Finally, the 8-bit full adder accumulates the membrane voltage. The full adders in the upper and lower modules perform the same function, completing a 16-bit addition calculation through two 8-bit full adders. Finally, we compare the accumulated membrane voltage with the threshold voltage. If the value is greater than the threshold voltage, a pulse is emitted, attenuated by a shifter, and then input into a 16-bit subtractor to update and reduce the membrane voltage.

[0083] The classification and comparison module is used to count the emitted pulses and select the neuron with the most emitted pulses for data recognition processing.

[0084] Specifically, the control module is responsible for the state machine changes within the kernel and controlling the data flow. The input pulses obtained from the image encoding of the dataset are stored in the pulse storage module, the weight storage module stores the initialized weights, and the pulse timing module counts the time intervals, guides the mode switching, and completes the neuron state update for each time interval. The pulse storage module and the weight storage module input the pulses and weights to be calculated into the LIF neuron module, respectively. After multiplication and accumulation, they determine whether to fire a pulse. The classification comparison module counts the pulses fired by the output layer neurons and compares them to determine the neuron that fires the most pulses to complete the image recognition and classification.

[0085] In the neural network accelerator, the input neuron module completes the RISC-V address fetching stage through multiplexing, and uses the weight memory address update multiplexing for PC address updates, completing PC+4 in CPU mode. The spiking neural network accelerator optimizes complex matrix operations and multiply-accumulate calculations into selectors and adders, greatly simplifying the computational resources required for complex multiplication operations. The computation of the neural network accelerator is concentrated in the hidden layer neurons, completing the accumulation of membrane voltages and gradient calculations, corresponding to the CPU execution stage, and multiplexing resources with the arithmetic logic unit (ALU) in RISC-V. Two hidden layer neurons can form a complete 32-bit adder. In the CPU memory access stage, mainly involving instruction storage and data storage, these resources can be reused in the neural network accelerator mode by reusing the weight memory, ensuring no waste of storage resources and greatly improving the heterogeneous memory utilization. The register file in RISC-V can be used in the neural network accelerator mode to store hidden layer emitted pulses and intermediate values. Through the above methods, the present invention maximizes resource reuse in the five main processes of the CPU: instruction fetch, instruction decoding, execution, memory access, and register write-back, while building a complete spiking neural network with input, hidden, and output layers.

[0086] Reference Figure 2 An execution method for a reconfigurable processor that integrates neuromorphic and general-purpose computing includes the following steps:

[0087] S1. Obtain the input dataset;

[0088] Specifically, by integrating the spiking neural network accelerator and RISC-V into a single core, complex heterogeneous interfaces are reduced. This invention completes mode determination, data input, and address input through a unified data packet input, setting up communication between cores and with external devices, and packaging this information into a data packet for input.

[0089] S2. Select the operating mode of the on-chip network module based on the input dataset;

[0090] Specifically, such as Figure 7 As shown, if the pattern data of the input dataset is "0", the working mode of the on-chip network module is set to CPU mode; if the pattern data of the input dataset is "1", the working mode of the on-chip network module is set to spiking neural network mode.

[0091] S3. Perform data recognition processing on the input dataset according to the working mode, and output the data recognition output results.

[0092] Specifically, refer to Figure 3 , Figure 4 and Figure 5 The method of this invention trains a network based on pulse-shaped firing neurons (LIF neurons). The state of the LIF neurons is represented by membrane voltage, and the charging process of the membrane voltage in continuous time is as follows:

[0093]

[0094] In the above formula, τ represents the time decay constant. U represents the membrane voltage corresponding to the i-th neuron in the l-th layer. reset This indicates the reset voltage; when the voltage exceeds the threshold voltage, it is reset to U. reset R represents the resistance in the circuit. This represents the membrane current corresponding to the i-th neuron in the l-th layer.

[0095] Spiking neurons possess memory; their membrane voltage is related not only to the current input but also to the state at the previous time step. The state of a spiking neuron can be simplified to charging, discharging, and resetting. In the discrete-time case of a spiking neural network, the membrane voltage changes at each moment. The formula for the change in membrane voltage in the discrete-time case is:

[0096]

[0097] In the above formula, β represents the voltage decay constant, and α represents the current decay constant. This represents the pulse emitted by the i-th neuron in the l-th layer. This represents the membrane voltage corresponding to the i-th neuron in the l-th layer. U represents the membrane current corresponding to the i-th neuron in the l-th layer. reset This represents the reset voltage, and n represents the discrete time n.

[0098] S31. Based on CPU mode, perform decoding, addition, calculation, and recognition processing on the input dataset;

[0099] Specifically, when the input mode is set to CPU mode, we will execute RISC-V instructions. Taking the ADD addition instruction as an example, the input data packet is set to CPU mode, the instruction is ADD, and the instruction enters the decoding module. Based on the decoding, the module accesses the register set in the command and sends the data from the register set to the next module. During the execution phase, the 8-bit adder resources of two neurons are reused, and the corresponding addition operation is performed based on the decoding result. The result is then written back to the destination register in the register set for storage.

[0100] S32, such as Figure 8 As shown, the supervised gradient substitution operation mode is based on the spiking neural network model;

[0101] Specifically, gradient substitution, as a supervised learning method, has the advantage of higher classification accuracy for images. When our neural network accelerator processes labeled datasets, we can adopt gradient substitution learning, which offers higher classification accuracy. The principle of gradient substitution is as follows: Traditional spiking neural networks use step functions as activation functions for neurons during forward propagation, and the derivative of the activation function is an impulse function, which cannot be represented numerically. In traditional recurrent neural networks, backpropagation is an essential part of training network weights. The inability to obtain gradients for activation functions affects the backpropagation training process and is a major challenge hindering the application of supervised learning in spiking neural networks. Our method effectively solves the problem of missing gradients. This invention uses the LeakyReLU function as the substitution function, which successfully substitutes the step function during the backpropagation process. After obtaining the substituted gradient function, the chain rule is used to obtain the updated weights as follows:

[0102]

[0103] In the above formula, The weights representing the changes are denoted by L, which represents the loss function. The loss function is the mean squared error of the output pulse frequency and the label. The final result, obtained through a three-layer network, is the target value minus the pulse counter count. σ′ represents the derivative of the gradient substitution function. This represents the input layer pulse, and target represents the preset target value. When a pulse is emitted, the count is obtained as cnt. i .

[0104] Finally, we obtain the training results for the weights. The complete process of the supervised algorithm is as follows, where lr is the learning rate:

[0105]

[0106] In the above formula, lr represents the learning rate.

[0107] S321. Perform frequency encoding processing on the input dataset to obtain discrete pulse signals and add the supervised gradient replacement running mode as a label to the discrete pulse signals to obtain the input data pulse signals.

[0108] Specifically, the input dataset is encoded into discrete pulse signals through frequency encoding. After adding patterns, addresses, and communication signals, the signals are packaged into input data packets and stored in the pulse storage module, which is used as the input module for the entire network.

[0109] S322. Read the supervised gradient substitution operation mode label and the weight of the input data pulse signal from the input data pulse signal, determine the learning mode, and select the accumulation and updating of the membrane voltage based on the pulse signal and the label value of the input data pulse signal to obtain the updated membrane voltage.

[0110] Specifically, the input data packet pattern bits are read, the control module identifies it as SNN mode, the identification rule is supervised gradient substitution, the learning mode is determined, pulse signals and label values ​​are read in, the pulse storage module outputs pulses, and the weight storage module provides corresponding weights to enter the LIF neuron module. The membrane voltage is accumulated and updated by selective accumulator.

[0111] S323. Compare the updated membrane voltage with the threshold voltage. If the updated membrane voltage is greater than the threshold voltage, emit pulses and count them to obtain the number of emitted pulses.

[0112] Specifically, the pulse emission judgment is completed within the LIF neuron module. By comparing the membrane voltage and the threshold voltage, when the membrane voltage is greater than the threshold voltage, the hidden layer neuron emits a pulse, which is stored, and the number of emitted pulses is obtained through a counter.

[0113] S324. Perform the difference calculation based on the number of transmitted pulses and the tag value of the input data pulse signal, and multiply the calculation result with the pulse signal of the input data pulse signal based on the chain rule to obtain the gradient value.

[0114] Specifically, the counter in the classification and comparison module counts the number of pulses emitted by hidden layer neurons, calculates the difference between the obtained value and the corresponding supervised label, and multiplies the result with the pulses in the pulse memory based on the chain rule to obtain the gradient value, which is used for subsequent weight updates.

[0115] S325. Introduce a learning rate, multiply the gradient value by the learning rate, and update the weights of the input data pulse signal to obtain the updated weights of the input data pulse signal.

[0116] Specifically, the weights are modified based on the gradient value. The weights are read from the weight storage module and multiplied by the learning rate using the gradient value. Here, we use a simple shift unit to calculate the learning rate. The weights change, thus achieving supervised learning.

[0117] S326. Based on the updated input data pulse signal weights, increment the time count by one until the time count meets the preset count requirement. Perform frequency statistical processing on the emitted pulses, select the neuron corresponding to the emitted pulse with the highest frequency for data recognition processing, and output the data recognition output result under the first pulse neural network mode.

[0118] Specifically, each update of the neuron state increments the pulse timing module count. After one round of training, the EPOCH count is incremented. When the network is trained to the EPOCH we set, the pulse emission frequency of the output layer neurons is counted. The pulse emission frequency data of all output layer classification neurons are entered into the classification comparison module for comparison. The maximum pulse frequency corresponds to the corresponding image classification category, thus completing the image inference process.

[0119] S33, such as Figure 9 As shown, this is an unsupervised time-dependent plasticity operation mode based on a spiking neural network model.

[0120] Specifically, when the input dataset does not contain labels, we employ an unsupervised learning method based on STDP (Synaptic Temporal Deposition and Detection). STDP is a mechanism for adjusting synaptic weights in biological neural networks, adjusting the strength of synapses based on the temporal difference between neurons. That is, when a neuron's synapse fires an action potential at its subsequent neuron, the synaptic weight changes. The basic principle of STDP is that if a neuron fires an action potential and its subsequent neuron at the synapse also fires an action potential, the synaptic weight will be strengthened. Conversely, if the subsequent neuron fires an action potential after the presynaptic neuron fires an action potential, the synaptic weight will be weakened. In short, STDP adjusts synaptic weights based on the temporal difference between two neurons to enhance or weaken the effect of synaptic signal transmission. The corresponding weight changes are as follows:

[0121]

[0122] In the above formula, A pre and A post τ represents the synaptic learning constant. pre τ represents the presynaptic membrane voltage decay constant. post Let Δt represent the postsynaptic membrane voltage decay constant, and let Δt represent the time difference before and after the pulse arrives at the synapse. The change value of the training weights, ΔW(Δt), is obtained through exponential operation.

[0123] When Δt is greater than zero, the presynaptic pulse arrives only after the postsynaptic pulse has been emitted, indicating a weak correlation and a decrease in the synaptic weight between the two. When Δt is less than zero, the postsynaptic pulse is emitted after the presynaptic pulse arrives, indicating a strong correlation and an increase in the synaptic weight between the two.

[0124] By leveraging the resource sharing and reuse of neural network accelerators and general-purpose processors, our method achieves higher performance, lower resource overhead, and lower latency, significantly reducing resource waste and latency.

[0125] S331. Perform frequency encoding processing on the input dataset to obtain discrete pulse signals and add the unsupervised time-dependent plasticity operation mode as a label to the discrete pulse signals to obtain the input data pulse signals.

[0126] Specifically, the input dataset is encoded into discrete pulse signals through frequency encoding. After adding pattern, address, and communication signals, it is packaged into an input data packet, which is used as the input module of the entire spiking neural network processor.

[0127] S332. Read the unsupervised time-dependent plasticity operation mode label and the weight of the input data pulse signal in the input data pulse signal, determine the learning mode, and select the summation to accumulate and update the membrane voltage based on the pulse signal and label value of the input data pulse signal, so as to obtain the updated membrane voltage.

[0128] Specifically, the input data packet pattern bits are read and identified as SNN mode, the identification rule is unsupervised STDP, the learning mode is determined, the pulse signal and label value are read in, the pulse enters the LIF neuron module, and the membrane voltage is accumulated and updated by selective accumulator.

[0129] S333. Compare the updated membrane voltage with the threshold voltage. If the updated membrane voltage is greater than the threshold voltage, emit a pulse.

[0130] Specifically, the membrane voltage is compared with the threshold voltage. When the membrane voltage is greater than the threshold voltage, the hidden layer neurons emit pulses and store the pulses.

[0131] S334. Obtain the pulse emission time of the emission pulse in the input neuron and the output neuron respectively through the time counter and calculate the corresponding time difference. Update the weight of the input data pulse signal according to the time difference to obtain the updated weight of the input data pulse signal.

[0132] Specifically, the pulse emission times of the input and output neurons are obtained through a time counter, and the time difference is calculated. Based on the time difference, it is determined whether the weight of the synapse is excitatory or inhibitory. The weight increment is calculated based on the time difference between the pulse emission of the input and output neurons, and the updated synaptic weights are obtained through a shift unit to achieve the learning effect.

[0133] S335. Based on the updated input data pulse signal weights, increment the time count by one until the time count meets the preset count requirement. Perform frequency statistical processing on the emitted pulses, select the neuron corresponding to the emitted pulse with the highest frequency for data recognition processing, and output the data recognition output result under the second pulse neural network mode.

[0134] Specifically, after completing one round of training, the EPOCH count is performed. When the network is trained to the EPOCH we set, the pulse emission frequency of the output layer neurons is counted. The pulse emission frequency data of all output layer classification neurons are entered into the classification comparison module for comparison. The maximum pulse frequency corresponds to the corresponding image classification category, thus completing the image inference process.

[0135] The content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0136] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A reconfigurable processor integrating neuromorphic and general-purpose computing, characterized in that, It includes a main control module and an on-chip network module, wherein the main control module is connected to the on-chip network module, wherein: The main control module is used to select the operating mode of the on-chip network module according to the input dataset. The operating modes of the on-chip network module include spiking neural network mode and CPU mode. The on-chip network module performs data recognition processing on the input dataset according to the corresponding working mode, and outputs the data recognition image output result. The on-chip network module includes a control module, a spike storage module, a weight storage module, a spike timing module, a LIF neuron module, and a classification comparison module. The first output of the control module is connected to the input of the spike storage module; the second output of the control module is connected to the first input of the weight storage module; the third output of the control module is connected to the first input of the spike timing module; the first output of the spike storage module is connected to the first input of the control module; the second output of the spike storage module is connected to the first input of the LIF neuron module; the output of the weight storage module is connected to the second input of the LIF neuron module; the first output of the spike timing module is connected to the second input of the control module; the second output of the spike timing module is connected to the third input of the LIF neuron module; the first output of the LIF neuron module is connected to the input of the classification comparison module; the second output of the LIF neuron module is connected to the second input of the weight storage module; and the third output of the LIF neuron module is connected to the second input of the spike timing module. Wherein: The control module is used to encode the input dataset and generate an input data pulse signal; The pulse storage module is used to store the input data pulse signal and transmit it to the LIF neuron module; The weight storage module is used to store the initial weights of the input data pulse signal and transmit them to the LIF neuron module; The pulse timing module is used to select the corresponding operating mode and count the time intervals according to the input data pulse signal, as well as update the neuron state for each time interval. The operating modes include supervised gradient substitution operating mode and unsupervised time-dependent plasticity operating mode. The LIF neuron module is used to perform multiplication and accumulation calculations based on the input data pulse signal and the weight of the input data pulse signal, and to determine whether to emit a pulse based on the calculation result; The classification and comparison module is used to count the emitted pulses and select the neuron corresponding to the largest number of emitted pulses for data recognition processing.

2. An execution method for a reconfigurable processor integrating neuromorphic and general-purpose computing, applied to the reconfigurable processor integrating neuromorphic and general-purpose computing as described in claim 1, characterized in that, Includes the following steps: Obtain the input dataset; The operating mode of the on-chip network module is selected based on the input dataset; The input dataset is processed for data recognition according to the working mode, and the data recognition output result is output.

3. The reconfigurable processor integrating neuromorphic and general computing as described in claim 2, characterized in that, The step of selecting the operating mode of the on-chip network module based on the input dataset specifically includes: The input dataset is split to obtain pattern data and make a judgment. If the pattern data of the input dataset is "0", then the working mode of the on-chip network module is set to CPU mode; If the pattern data of the input dataset is "1", then the working mode of the on-chip network module is set to spiking neural network mode.

4. The execution method of a reconfigurable processor integrating neuromorphic and general computing according to claim 2, characterized in that, The step of performing data recognition processing on the input dataset according to the working mode and outputting the data recognition output result specifically includes: Based on the CPU mode, the input dataset is subjected to decoding, addition, calculation, and recognition processing to obtain the data recognition output result in CPU mode; Based on the spiking neural network pattern, the data packets of the input dataset are judged and processed; If the data packets of the input dataset are supervised labels, the input dataset is processed for data recognition through supervised gradient substitution running mode, and the data recognition output result under the first spiking neural network mode is output. If the data packets of the input dataset are unsupervised labels, the input dataset is processed for data recognition through the unsupervised time-dependent plasticity operation mode, and the data recognition output result under the second spiking neural network mode is output. The data recognition output results are integrated from the data recognition output results in the CPU mode, the data recognition output results in the first spiking neural network mode, and the data recognition output results in the second spiking neural network mode to obtain the data recognition output result.

5. The execution method of a reconfigurable processor integrating neuromorphic and general computing according to claim 4, characterized in that, The step of performing data recognition processing on the input dataset through a supervised gradient substitution operation mode and outputting the data recognition output result under the first spiking neural network mode specifically includes: The input dataset is frequency encoded to obtain discrete pulse signals, and the supervised gradient substitution operation mode is added as a label to the discrete pulse signals to obtain the input data pulse signals. The supervised gradient substitution operation mode label and the weight of the input data pulse signal are read from the input data pulse signal to determine the learning mode. Based on the pulse signal and label value of the input data pulse signal, the accumulation and updating of the membrane voltage are selected to obtain the updated membrane voltage. The updated membrane voltage is compared with the threshold voltage. When the updated membrane voltage is greater than the threshold voltage, a pulse is emitted and counted to obtain the number of emitted pulses. The difference between the number of transmitted pulses and the tag value of the input data pulse signal is calculated, and the result is multiplied by the pulse signal of the input data pulse signal based on the chain rule to obtain the gradient value. A learning rate is introduced, the gradient value is multiplied by the learning rate, and the weights of the input data pulse signal are updated to obtain the updated weights of the input data pulse signal. Based on the weights of the updated input data pulse signals, the time count is incremented by one until the time count meets the preset counting requirements. Frequency statistics processing is performed on the emitted pulses, and the neuron corresponding to the emitted pulse with the highest frequency is selected for data recognition processing. The data recognition output result under the first spiking neural network mode is then output.

6. The execution method of a reconfigurable processor integrating neuromorphic and general computing according to claim 4, characterized in that, The step of performing data recognition processing on the input dataset through an unsupervised, time-dependent, plasticity-based operating mode and outputting the data recognition output result under the second spiking neural network mode specifically includes: The input dataset is frequency encoded to obtain discrete pulse signals, and the unsupervised time-dependent plasticity operation mode is added as a label to the discrete pulse signals to obtain the input data pulse signals. The unsupervised time-dependent plasticity operating mode label in the input data pulse signal is read and the weight of the input data pulse signal is determined. The learning mode is determined and the membrane voltage is accumulated and updated based on the pulse signal and label value of the input data pulse signal to obtain the updated membrane voltage. The updated membrane voltage is compared with a threshold voltage. If the updated membrane voltage is greater than the threshold voltage, a pulse is emitted. The pulse emission times of the emitted pulses at the input and output neurons are obtained by a time counter, and the corresponding time difference is calculated. The weights of the input data pulse signals are updated according to the time difference to obtain the updated weights of the input data pulse signals. Based on the weights of the updated input data pulse signals, the time count is incremented by one until the time count meets the preset counting requirements. Frequency statistics processing is performed on the emitted pulses, and the neuron corresponding to the emitted pulse with the highest frequency is selected for data recognition processing. The data recognition output result under the second pulse neural network mode is then output.

7. The execution method of a reconfigurable processor integrating neuromorphic and general computing according to claim 5, characterized in that, The specific expressions for the accumulation and updating of the membrane voltage are as follows: In the above formula, Represents the voltage decay constant. Represents the current decay constant. Indicates the first The first layer The pulse emitted by each neuron Indicates the first The first layer The membrane voltage corresponding to each neuron Indicates the first The first layer The membrane current corresponding to each neuron Indicates the reset voltage. Discrete time is time.

8. The execution method of a reconfigurable processor integrating neuromorphic and general computing according to claim 5, characterized in that, The specific expression for updating the weights of the input data pulse signal in the supervised gradient substitution operation mode is as follows: In the above formula, The weights representing the changes The loss function is the sum of the output pulse frequency and the mean square error of the tag. It is derived through a three-layer network, ultimately yielding the target value minus the pulse counter count. This represents the derivative of the gradient substitution function. Indicates the input layer pulse. This represents a preset target value; when a pulse is emitted, the count is obtained. .

9. The execution method of a reconfigurable processor integrating neuromorphic and general computing according to claim 6, characterized in that, The specific expression for updating the weights of the input data pulse signals in the unsupervised time-dependent plasticity operation mode is as follows: In the above formula, and Represents the synaptic learning constant. This represents the presynaptic membrane voltage decay constant. This represents the postsynaptic membrane voltage decay constant. This represents the time difference before and after the pulse arrives at the synapse, and the change in training weights is obtained through exponential operations. .

Images