Processing system for realizing waveform file storage and playback based on DDR3 (Double Data Rate 3)

Abstract

The invention provides a processing system for realizing storage and playback of a waveform file based on DDR3 (Double Data Rate 3). The system is realized on the basis of a ZYNQ architecture. A PS end reads a waveform file from an SATA disk and moves the waveform file to a DDR3 of a PL end through an AXI bus; during playback, the PL end continuously fetches data from the DDR3 according to an address pointer according to sampling rate, power and other parameters issued by the PS end in real time, and drives the DA chip to output a radio frequency signal. Handshake is carried out between PS and PL by adopting a frame header + length + data protocol, the PL end manages data in a FIFO-DDR3 second-level cache, and paragraph circulation, speed change and zero-interruption playback are supported. According to the system, the waveform file playing with the maximum sampling rate of 800M can be realized, the continuous playing of different maximum file sizes can be supported under different sampling rates, the waveform output amplitude, the playing times, the playing period and other functions can be controlled, the realization method is simple, the portability is high, and the system can be applied to various FPGA chip platforms.

Description

Technical Field

[0001] This invention relates to the field of waveform signal processing technology, and more specifically, to a processing system based on DDR3 for storing and playing back waveform files. Background Technology

[0002] In applications requiring complex electromagnetic environment simulation, such as radar, communications, and electronic warfare, real-time storage and playback of waveform files have become core components of system verification, field testing, and training evaluation. Traditional methods rely on laboratory-grade "signal source" instruments. While these instruments offer excellent performance with their built-in solid-state storage and RF channels, a single unit can cost hundreds of thousands of yuan, are bulky, consume high power, and only support fixed waveform file formats, making them difficult to deploy on mobile platforms, ships, or anywhere else. In recent years, with the improvement of FPGA computing power and the widespread adoption of SATA / PCIe interfaces, solutions have emerged in the industry that directly implement the NVMe protocol stack using FPGAs and perform waveform caching via M.2 NVMe solid-state drives, attempting to replace instruments with commercial-grade devices. However, the NVMe protocol itself has a complex command set, requiring FPGAs to handle numerous low-level details at the link layer, such as queue management, PRP list parsing, and power state switching, resulting in over 20,000 lines of code and development cycles lasting several months. Furthermore, NVMe drives frequently experience link drops and increased bit error rates under extreme conditions such as high and low temperatures, vibration, and low air pressure, further increasing logic resource consumption and system complexity in reliability design. Furthermore, neither the instrumentation solution nor the NVMe solution addresses the pain point of "high-speed random playback of large files": when the file size exceeds the FPGA's on-chip DDR capacity, the solid-state drive can only be used as a streaming data source, reading and playing simultaneously. If jumps, loops, or speed changes are needed during playback, re-addressing is required, leading to millisecond-level interruptions. This cannot meet the stringent continuity requirements of scenarios such as coherent processing, frequency hopping, and pulse trains. Therefore, a new storage-playback architecture that balances cost, reliability, and flexibility is urgently needed to achieve high-sampling-rate waveform file storage and playback processing on embedded platforms. Summary of the Invention

[0003] The present invention aims to solve at least one of the aforementioned technical problems existing in the prior art.

[0004] Therefore, the present invention provides a processing system for waveform file storage and playback based on DDR3.

[0005] The proposed system for waveform file storage and playback based on DDR3 is based on the ZYNQ architecture of FPGA. It combines waveform playback files and parameters issued by the display control software to read the waveform file from the SATA disk and transfer it to DDR3. When waveform playback is required, the DA chip connected to DDR3 outputs the waveform radio frequency signal. The ZYNQ architecture includes a processing system and a programmable logic unit; the processing system and the programmable logic unit are connected via an AXI bus. The processing system is used to store waveform files to a SATA disk, read the SATA disk file and send it to the AXI data interface of the programmable logic terminal via the AXI bus, and send waveform playback parameters to the AXI parameter interface of the programmable logic terminal. The programmable logic terminal is used to parse AXI bus transmitted data, including parameter data and waveform file data; as well as DDR3 chip driver read / write control and DA chip RF control.

[0006] The waveform file storage and playback processing system based on DDR3 according to the above-described technical solution of the present invention may further have the following additional technical features: In the above technical solution, the processing system end and the programmable logic end use a protocol structure of frame header bit + length bit + data bit for data interaction.

[0007] In the above technical solution, the frame header is used to identify the data transmission status; When the data transmission is complete, that is, after the data writing is finished on the processing system side, the first identifier value is filled in the frame header to indicate that the programmable logic side can receive the data. When data reception is complete, the programmable logic end can fill the second identifier value in the frame header after reading all the data, indicating that the processing system end is ready to perform the next data interaction.

[0008] In the above technical solution, the programmable logic terminal adopts a FIFO-DDR3 collaborative caching mechanism, which realizes data storage through FIFO caching and DDR3 storage secondary cache.

[0009] In the above technical solution, the processing system runs the Reworks system.

[0010] In the above technical solution, the waveform playback parameters include waveform playback flag parameters, waveform sampling rate parameters, power control parameters, and reset flag parameters.

[0011] In the above technical solution, the size of the waveform file that the processing system can play back is negatively correlated with the waveform sampling rate set in the waveform playback parameters.

[0012] In the above technical solution, the DDR3 fast read / write control is implemented using the MIG IP core, that is, DDR3 is connected to the programmable logic terminal through the MIG controller.

[0013] In the above technical solution, the method for storing waveform file data using the processing system includes: When the programmable logic detects that the frame header bit of the AXI bus data interface is filled with the first identifier value, it parses the waveform data of this packet according to the protocol, writes the data into the FIFO buffer, and generates a FIFO data buffer completion flag. When the DDR3 write control module detects the FIFO data buffer completion flag, it starts the DDR3 data writing process, reads data from the FIFO and writes it into the DDR3. When the FIFO is empty, the second identifier value is filled into the frame header bit of the AXI protocol. At this time, the processing system side performs the next packet data interaction. The entire waveform file is sent to the programmable logic terminal for DDR3 data storage by the processing system. At this point, the programmable logic terminal can obtain the storage address area of ​​the waveform file for data reading during waveform playback.

[0014] In the above technical solution, the method for playing back waveform file data using the processing system includes: When the programmable logic terminal detects that the frame header bit in the AXI bus parameter interface is filled with the first identifier value, it obtains the waveform playback parameters according to the protocol parsing; the waveform playback parameters include waveform playback flag parameters, waveform sampling rate parameters, power control parameters, and reset flag parameters; When the DDR3 read control module detects the waveform playback flag, it starts the DDR3 read data process, obtains the DDR3 data address range for data storage, and caches the read DDR3 data into the FIFO. Based on the waveform sampling rate parameter, control the FIFO data reading period to ensure that the data is continuously output according to the corresponding sampling rate. When the FIFO is not empty, the data output is enabled. Based on the power control parameters, the data output from the FIFO is transformed accordingly, and the transformed data and enable signal are sent to the DA control module to obtain the RF waveform signal with the corresponding sampling rate and the waveform signal with the corresponding power.

[0015] In summary, due to the adoption of the above-mentioned technical features, the beneficial effects of the present invention are: This invention designs a processing system for storing and playing back high-sampling-rate waveform files based on DDR3. The system can play waveform files with a maximum sampling rate of up to 800M, and can support continuous playback of different maximum file sizes at different sampling rates. It can also control the waveform output amplitude, playback times, and playback period. The implementation method is simple and highly portable, and can be applied to various FPGA chip platforms.

[0016] Specifically, this invention adopts ZYNQ's PS-PL architecture. After the waveform file is moved from the SATA disk to DDR3, the DDR3 directly supplies data to the DA chip, eliminating the need for expensive dedicated hardware of traditional signal sources and avoiding the complex development of implementing a complete NVMe protocol stack in the FPGA. The SATA disk is only used for cold storage and no longer participates in real-time streaming disk read / write, reducing the probability of protocol layer errors in outdoor environments. The PS side runs a general embedded system, responsible for file management and parameter distribution. The PL side uses a FIFO-DDR3 L2 cache and a MIG controller to complete the read / write timing. Data and control are separated, the handshake protocol is simple, and output continuity is guaranteed. The playback sampling rate, power level, and reset flag are configured in real time by the PS side via the AXI bus. The PL side outputs data according to the set sampling rate and completes the amplitude adjustment in the digital domain, eliminating the need for external programmable attenuation. The DDR3 capacity determines the maximum playable file length and is inversely proportional to the sampling rate. The system can freely choose the combination of the two within the capacity range. The entire system relies solely on conventional FPGAs, standard DDR3 chips, and ordinary SATA hard drives, eliminating the need for high-speed SerDes or PCIe switching chips. This results in a simple hardware structure, significantly reduced costs, and reliability ensured by industrial-grade DDR3 and a mature MIG controller. Upgrades and maintenance are concentrated at the PS software layer, requiring no changes to the PL logic, making it suitable for mass deployment on various mobile platforms.

[0017] Additional aspects and advantages of the invention will become apparent in the following description or may be learned by practice of the invention. Attached Figure Description

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the system framework of a waveform file storage and playback processing system based on DDR3 according to an embodiment of the present invention; Figure 2 This is a schematic diagram of waveform playback parameter configuration for a waveform file storage and playback processing system based on DDR3 according to an embodiment of the present invention. Figure 3 This is a flowchart illustrating the data storage implementation of a waveform file storage and playback processing system based on DDR3 according to an embodiment of the present invention. Figure 4 This is a flowchart illustrating the waveform playback process of a waveform file storage and playback processing system based on DDR3 according to an embodiment of the present invention. Detailed Implementation

[0019] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0020] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0021] The following reference Figures 1 to 4 This describes a processing system based on DDR3 for waveform file storage and playback, provided by some embodiments of the present invention.

[0022] Some embodiments of this application provide a processing system for waveform file storage and playback based on DDR3.

[0023] like Figure 1 As shown, the first embodiment of the present invention proposes a processing system for waveform file storage and playback based on DDR3. Based on the ZYNQ architecture of FPGA, the waveform playback file and parameters are sent by the display control software. The waveform file is read from the SATA disk and transferred to DDR3. When waveform playback is required, the waveform radio frequency signal is output based on the DA chip connected to DDR3. The ZYNQ architecture includes a processing system terminal (PS terminal) and a programmable logic terminal (PL terminal); the processing system terminal and the programmable logic terminal are connected via an AXI bus; The processing system is used to store waveform files to a SATA disk, read the SATA disk file and send it to the AXI data interface of the programmable logic terminal via the AXI bus, and send waveform playback parameters to the AXI parameter interface of the programmable logic terminal. The programmable logic terminal is used to parse AXI bus transmitted data, including parameter data and waveform file data; as well as DDR3 chip driver read / write control and DA chip RF control.

[0024] Specifically, this solution is based on the ZYNQ software architecture of domestically produced FPGA. Combined with the waveform playback file and parameters issued by the display and control software, the waveform file is read from the SATA disk and transferred to DDR3. Based on the fast read and write characteristics of DDR3, it can realize the storage and playback of waveform files of 16-bit IQ data with a maximum sampling rate of 800M; the maximum playback file size can reach 256M.

[0025] exist Figure 1In the illustrated embodiment, the PS terminal runs the Reworks system, primarily responsible for storing waveform files to a SATA disk and reading files from the SATA disk, sending them to the PL terminal via the AXI bus; and sending waveform playback parameters to the PL terminal. The PL terminal mainly handles AXI bus data parsing, parameter parsing, DDR3 chip driver read / write control, and DA chip RF control. Specifically, by selecting a waveform playback file through the display and control software, the corresponding waveform RF signal can be output at the RF terminal. This enables playback of any waveform with a sampling rate not exceeding 800MHz, supports continuous playback of different maximum file sizes at different sampling rates, and controls waveform output amplitude, playback count, and playback period.

[0026] In one specific embodiment, the waveform playback parameters are set in the display and control software as follows: Figure 2 As shown.

[0027] In some embodiments, the processing system and the programmable logic terminal use a protocol structure of frame header bits + length bits + data bits for data interaction.

[0028] The frame header is used to identify the data transmission status; When the data transmission is complete, that is, after the data writing is finished on the processing system side, the first identifier value is filled in the frame header to indicate that the programmable logic side can receive the data. When data reception is complete, the programmable logic end can fill the second identifier value in the frame header after reading all the data, indicating that the processing system end is ready to perform the next data interaction.

[0029] Specifically, in this embodiment, waveform file / playback parameter data is exchanged between the PS and PL via the AXI_BRAM interface (including a data interface and a parameter interface). The specific protocol is a frame header + length + data bit structure. The frame header is used to distinguish when the PS has finished writing data and when the PL has finished reading data. That is, when the PS fills the frame header with the first identifier value, such as "5A", the data writing is complete and the PL can receive the data. After the PL finishes receiving the data, it fills the frame header with the second identifier value, such as "00", and the PS can proceed with the next data exchange. DDR3 fast read / write control is implemented using the MIG IP core. That is, DDR3 is connected to the programmable logic terminal through the MIG controller. With a clock cycle of 800MHz and a data bit width of 32bit, a burst packet bandwidth of 51.2Gb / s can be achieved. The higher the burst packet rate, the higher the average read / write rate can be supported, thus enabling high sampling rate and large-capacity waveform file playback. This architecture can support continuous playback of waveform data with an IQ of 16 bits each at a sampling rate of 800M, with a maximum file size of 50M, or continuous playback of waveform data with an IQ of 16 bits each at a sampling rate of 100M, with a maximum file size of 400M. That is, the smaller the sampling rate, the larger the waveform file that can be supported.

[0030] In some embodiments, the programmable logic terminal adopts a FIFO-DDR3 collaborative caching mechanism, which uses a FIFO cache and a secondary cache of DDR3 storage to achieve data storage and ensure data flow continuity.

[0031] In one specific embodiment, the method for storing waveform file data using the processing system is as follows: Figure 3 As shown, it includes: When the programmable logic detects that the frame header bit of the AXI bus data interface is filled with the first identifier value, it parses the waveform data of this packet according to the protocol, writes the data into the FIFO buffer, and generates a FIFO data buffer completion flag. When the DDR3 write control module detects the FIFO data buffer completion flag, it starts the DDR3 data writing process, reads data from the FIFO and writes it into the DDR3. When the FIFO is empty, the second identifier value is filled into the frame header bit of the AXI protocol. At this time, the processing system side performs the next packet data interaction. Repeat the above process until the processing system sends the entire waveform file to the programmable logic terminal for DDR3 data storage. At this point, the programmable logic terminal can obtain the storage address area of ​​the waveform file for data reading operations during waveform playback.

[0032] In one specific embodiment, the method for playing back waveform file data using the processing system is as follows: Figure 4 As shown, it includes: When the programmable logic terminal detects that the frame header bit in the AXI bus parameter interface is filled with the first identifier value, it obtains the waveform playback parameters according to the protocol parsing; the waveform playback parameters include waveform playback flag parameters, waveform sampling rate parameters, power control parameters, and reset flag parameters, etc. When the DDR3 read control module detects the waveform playback flag, it starts the DDR3 read data process, obtains the DDR3 data address range for data storage, and caches the read DDR3 data into the FIFO. Based on the waveform sampling rate parameter, control the FIFO data reading period to ensure that the data is continuously output according to the corresponding sampling rate. When the FIFO is not empty, the data output is enabled. Based on the power control parameters, the data output from the FIFO is transformed accordingly, and the transformed data and enable signal are sent to the DA control module to obtain the RF waveform signal with the corresponding sampling rate and the waveform signal with the corresponding power.

[0033] The playback count and playback cycle functions in waveform playback are controlled by the display and control software based on parameter settings. The software periodically sends a waveform playback flag parameter; each time the PL terminal detects this flag, a DDR3 data playback operation is completed, thus controlling the playback count and playback cycle in waveform playback. The reset flag parameter function controls the clearing of DDR3 cache data. Specifically, when DDR3 read / write operations are in an idle state, if the reset flag parameter is detected as valid, the DDR3 read / write operation address starts from address "0", achieving a reset function.

[0034] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0035] Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention shall be included within the scope of protection of this invention.

Claims

1. A processing system for waveform file storage and playback based on DDR3, characterized in that, Based on the FPGA-based ZYNQ architecture, combined with the waveform playback file and parameters issued by the display control software, the waveform file is read from the SATA disk and transferred to the DDR3. When the waveform needs to be played back, the waveform radio frequency signal is output based on the DA chip connected to the DDR3. The ZYNQ architecture includes a processing system and a programmable logic unit; the processing system and the programmable logic unit are connected via an AXI bus. The processing system is used to store waveform files to a SATA disk, read the SATA disk file and send it to the AXI data interface of the programmable logic terminal via the AXI bus, and send waveform playback parameters to the AXI parameter interface of the programmable logic terminal. The programmable logic terminal is used to parse AXI bus transmitted data, including parameter data and waveform file data; as well as DDR3 chip driver read / write control and DA chip RF control.

2. The processing system for waveform file storage and playback based on DDR3 according to claim 1, characterized in that, The processing system and the programmable logic unit use a protocol structure of frame header bits + length bits + data bits for data interaction.

3. The processing system for waveform file storage and playback based on DDR3 according to claim 2, characterized in that, The frame header is used to identify the data transmission status; When the data transmission is complete, that is, after the data writing is finished on the processing system side, the first identifier value is filled in the frame header to indicate that the programmable logic side can receive the data. When data reception is complete, the programmable logic end can fill the second identifier value in the frame header after reading all the data, indicating that the processing system end is ready to perform the next data interaction.

4. The processing system for waveform file storage and playback based on DDR3 according to claim 3, characterized in that, The programmable logic terminal adopts a FIFO-DDR3 collaborative caching mechanism, which realizes data storage through FIFO caching and DDR3 storage secondary cache.

5. The processing system for waveform file storage and playback based on DDR3 according to claim 1, characterized in that, The processing system runs the Reworks system.

6. The processing system for waveform file storage and playback based on DDR3 according to claim 1, characterized in that, The waveform playback parameters include waveform playback flag parameters, waveform sampling rate parameters, power control parameters, and reset flag parameters.

7. The processing system for waveform file storage and playback based on DDR3 according to claim 6, characterized in that, The size of the waveform file that the processing system can play back is negatively correlated with the waveform sampling rate set in the waveform playback parameters.

8. The processing system for waveform file storage and playback based on DDR3 according to claim 1, characterized in that, The DDR3 fast read / write control is implemented using the MIG IP core, meaning that DDR3 is connected to the programmable logic terminal through the MIG controller.

9. The processing system for waveform file storage and playback based on DDR3 according to claim 4, characterized in that, The method for storing waveform file data using the processing system includes: When the programmable logic detects that the frame header bit of the AXI bus data interface is filled with the first identifier value, it parses the waveform data of this packet according to the protocol, writes the data into the FIFO buffer, and generates a FIFO data buffer completion flag. When the DDR3 write control module detects the FIFO data buffer completion flag, it starts the DDR3 data writing process, reads data from the FIFO and writes it into the DDR3. When the FIFO is empty, the second identifier value is filled into the frame header bit of the AXI protocol. At this time, the processing system side performs the next packet data interaction. The entire waveform file is sent to the programmable logic terminal for DDR3 data storage by the processing system. At this point, the programmable logic terminal can obtain the storage address area of ​​the waveform file for data reading during waveform playback.

10. The processing system for waveform file storage and playback based on DDR3 according to claim 9, characterized in that, The method for playing back waveform file data using the processing system includes: When the programmable logic terminal detects that the frame header bit in the AXI bus parameter interface is filled with the first identifier value, it obtains the waveform playback parameters according to the protocol parsing; the waveform playback parameters include waveform playback flag parameters, waveform sampling rate parameters, power control parameters, and reset flag parameters; When the DDR3 read control module detects the waveform playback flag, it starts the DDR3 read data process, obtains the DDR3 data address range for data storage, and caches the read DDR3 data into the FIFO. Based on the waveform sampling rate parameter, control the FIFO data reading period to ensure that the data is continuously output according to the corresponding sampling rate. When the FIFO is not empty, the data output is enabled. Based on the power control parameters, the data output from the FIFO is transformed accordingly, and the transformed data and enable signal are sent to the DA control module to obtain the RF waveform signal with the corresponding sampling rate and the waveform signal with the corresponding power.

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