Simulink code generation method and device based on instruction pipeline perception

Abstract

The invention provides a Simulink code generation method and device based on instruction pipeline perception, and relates to the technical field of embedded code generation, and the method comprises the steps: carrying out instruction dependency analysis and delay modeling on a target Simulink model, and generating a dependency graph for describing a dependency relationship between modules and an instruction delay model combined with target processor system structure parameters; based on the dependency graph and the instruction delay model, determining an optimal execution sequence of each module through assembly line perception scheduling, and performing assembly line scheduling based on the optimal execution sequence to obtain a scheduling result; and based on the scheduling result, utilizing a local pipeline optimization strategy to generate a target code. According to the method provided by the invention, the data dependence path between the modules is determined by utilizing topology analysis, and the execution sequence is adaptively selected through the minimum penalty priority algorithm to avoid unnecessary waiting and resource conflicts, so that the number of pauses of the instruction assembly line is effectively reduced on the premise of ensuring the semantic consistency of the model.

Description

Technical Field

[0001] This application relates to the field of embedded code generation technology, and in particular to a Simulink code generation method and apparatus based on instruction pipeline awareness. Background Technology

[0002] Model-Driven Design (MDD) is one of the core methodologies in the development of complex embedded systems today. Its basic idea is to center system design and implementation around a model. By establishing an abstract system model and performing simulations and verifications, early verification and optimization of system functionality and performance can be achieved. Within the MDD framework, Simulink is one of the most widely used tools. Simulink provides an intuitive graphical modeling interface, allowing engineers to build control algorithms and signal processing systems by dragging and dropping modules and signal lines.

[0003] In related technologies, code generators such as Simulink Embedded Coder typically generate code strictly based on the data dependencies between modules in the model. However, while this process ensures that the generated code is semantically consistent with the model, it also causes serialization in instruction execution. That is, the generated code usually requires the computation of the previous module to be completely completed before the instructions of the next module can begin to execute, resulting in a large number of instructions being unable to be scheduled in parallel, thus causing severe pipeline congestion during the processor execution phase. Summary of the Invention

[0004] The purpose of this application is to provide a Simulink code generation method and apparatus based on instruction pipeline awareness. It uses topology analysis to determine the data dependency paths between modules and adaptively selects the execution order through the least penalty first algorithm to avoid unnecessary waiting and resource conflicts, thereby effectively reducing the number of instruction pipeline pauses while ensuring the semantic consistency of the model.

[0005] This application provides a Simulink code generation method based on instruction pipeline awareness, including: Instruction dependency analysis and latency modeling are performed on the target Simulink model to generate a dependency graph describing the dependencies between modules and an instruction latency model incorporating the target processor architecture parameters. Based on the dependency graph and the instruction latency model, the optimal execution sequence of each module is determined through pipeline-aware scheduling, and pipeline scheduling is performed based on the optimal execution sequence to obtain the scheduling result. The pipeline-aware scheduling minimizes pipeline stalls through dynamic priority strategies and latency conflict prediction. Based on the scheduling result, target code is generated using local pipeline optimization strategies.

[0006] Optionally, the local pipeline optimization strategy includes at least one of the following: reordering instructions without breaking dependency constraints, renaming registers with spurious dependencies, inserting independent operations into the delay slots of branch instructions, and merging consecutive independent short instructions into compound instructions.

[0007] Optionally, the step of performing instruction dependency analysis and latency modeling on the target Simulink model to generate a dependency graph describing the dependencies between modules and an instruction latency model incorporating the target processor architecture parameters includes: performing static structural analysis on the target Simulink model to construct a dependency graph with modules of the model as nodes and data flow and control flow as directed edges; and establishing an instruction latency model for each module in the dependency graph based on the hardware feature information of the target processor; wherein the hardware feature information includes at least one of the following: pipeline stage number, register access latency, memory access latency, and number of execution units.

[0008] Optionally, determining the optimal execution sequence of each module based on the dependency graph and the instruction latency model through pipeline-aware scheduling includes: extracting the current set of executable modules from the dependency graph and calculating a comprehensive priority for each module in the set; the comprehensive priority is calculated based on at least one of the following: the depth of the module in the dependency graph, the overlapability of instruction latency, and the impact of the module output on subsequent critical paths; and determining the optimal execution sequence of each module based on the comprehensive priority of each module.

[0009] Optionally, the pipeline scheduling based on the optimal execution sequence to obtain the scheduling result includes: selecting the module with the highest overall priority for launch scheduling based on the overall priority of each module and the conflict prediction result of the instruction latency model corresponding to each module; wherein, before the module is launched, if the conflict prediction result corresponding to the module indicates the possibility of a pause, the launch of the module is delayed, and the next module that can be executed immediately is selected for launch to maintain the continuous operation of the pipeline.

[0010] Optionally, selecting the module with the highest overall priority for launch scheduling includes: if the conflict prediction result indicates that there is partial dependency between modules and that they are not completely blocked, then an idle compensation instruction is inserted into the scheduling sequence to fill potential idle periods in order to reduce resource waste caused by structural pauses; if the conflict prediction result indicates that there is an unavoidable conflict, then a scheduling rollback mechanism is triggered to recalculate the optimal execution sequence.

[0011] Optionally, the step of generating target code based on the scheduling result using a local pipeline optimization strategy includes: generating target code corresponding to each module according to the execution order determined by the scheduling result; wherein, during the code generation process, register allocation is performed, and synchronization instructions are inserted according to dependency information to ensure the correctness of the execution result.

[0012] Optionally, after generating target code using a local pipeline optimization strategy based on the scheduling result, the method further includes: analyzing the generated target code and obtaining performance indicators based on the analysis results; the performance indicators include at least one of the following: pipeline pause rate, average number of execution cycles, and instruction throughput; if the performance indicators of the target code do not reach a preset threshold, the parameters of the instruction latency model and / or the dynamic priority strategy are adjusted based on the analysis results, and a new round of optimized code generation is performed until the performance indicators of the target code reach the preset threshold.

[0013] This application also provides a Simulink code generation apparatus based on instruction pipeline awareness, comprising: The latency model construction module performs instruction dependency analysis and latency modeling on the target Simulink model, generating a dependency graph describing the dependencies between modules and an instruction latency model incorporating the target processor architecture parameters. The pipeline-aware scheduling module determines the optimal execution sequence for each module based on the dependency graph and the instruction latency model, and performs pipeline scheduling based on the optimal execution sequence to obtain the scheduling result. The pipeline-aware scheduling minimizes pipeline stalls through dynamic priority strategies and latency conflict prediction. The code generation module generates target code based on the scheduling result using local pipeline optimization strategies.

[0014] Optionally, the latency model construction module is specifically used to perform static structural analysis on the target Simulink model and construct a dependency graph with the modules of the model as nodes and the data flow and control flow as directed edges; the latency model construction module is also specifically used to establish an instruction latency model for each module in the dependency graph based on the hardware feature information of the target processor; wherein, the hardware feature information includes at least one of the following: pipeline stage number, register access latency, memory access latency, and number of execution units.

[0015] Optionally, the pipeline-aware scheduling module is specifically used to extract the current set of executable modules from the dependency graph and calculate a comprehensive priority for each module in the set; the comprehensive priority is calculated based on at least one of the following: the depth of the module in the dependency graph, the overlap of instruction latency, and the impact of the module output on subsequent critical paths; the pipeline-aware scheduling module is further used to determine the optimal execution sequence of each module based on the comprehensive priority of each module.

[0016] Optionally, the pipeline-aware scheduling module is specifically used to select the module with the highest overall priority for launch scheduling based on the overall priority of each module and the conflict prediction result of the instruction delay model corresponding to each module; wherein, before the module is launched, if the conflict prediction result corresponding to the module indicates that there is a possibility of a pause, the launch of the module is delayed, and the next module that can be executed immediately is selected for launch to maintain the continuous operation of the pipeline.

[0017] Optionally, the pipeline-aware scheduling module is specifically used to insert idle compensation instructions into the scheduling sequence to fill potential idle cycles if the conflict prediction result indicates that there is a partial dependency between modules and that they are not completely blocked, so as to reduce the resource waste caused by structural pauses; the pipeline-aware scheduling module is also specifically used to trigger a scheduling rollback mechanism to recalculate the optimal execution sequence if the conflict prediction result indicates that there is an unavoidable conflict.

[0018] Optionally, the code generation module is specifically used to generate target code corresponding to each module according to the execution order determined by the scheduling result; wherein, during the code generation process, register allocation is performed and synchronization instructions are inserted according to dependency information to ensure the correctness of the execution result.

[0019] Optionally, the apparatus further includes: an optimization feedback module; the optimization feedback module is used to analyze the generated target code and obtain performance indicators based on the analysis results; the performance indicators include at least one of the following: pipeline pause rate, average number of execution cycles, and instruction throughput; the optimization feedback module is also used to adjust the parameters of the instruction latency model and / or the dynamic priority strategy based on the analysis results if the performance indicators of the target code do not reach the preset threshold, and to perform a new round of optimized code generation until the performance indicators of the target code reach the preset threshold.

[0020] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the instruction pipeline-aware Simulink code generation method as described above.

[0021] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the above-described instruction pipeline-aware Simulink code generation methods.

[0022] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the instruction pipeline-aware Simulink code generation method as described above.

[0023] The Simulink code generation method and apparatus based on instruction pipeline awareness provided in this application first perform instruction dependency analysis and latency modeling on the target Simulink model to generate a dependency graph describing the dependencies between modules and an instruction latency model incorporating the target processor architecture parameters. Then, based on the dependency graph and the instruction latency model, the optimal execution sequence of each module is determined through pipeline awareness scheduling, and pipeline scheduling is performed based on the optimal execution sequence to obtain the scheduling result. The pipeline awareness scheduling minimizes pipeline pauses through dynamic priority strategies and latency conflict prediction. Finally, based on the scheduling result, target code is generated using local pipeline optimization strategies. In this way, topology analysis is used to determine the data dependency paths between modules, and the least-penalty-first algorithm adaptively selects the execution order to avoid unnecessary waiting and resource conflicts, thereby effectively reducing the number of instruction pipeline pauses while ensuring the semantic consistency of the model. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the architecture of the Simulink code generation system based on instruction pipeline awareness provided in this application; Figure 2 This is one of the flowcharts of the Simulink code generation method based on instruction pipeline awareness provided in this application; Figure 3 This is the second flowchart of the Simulink code generation method based on instruction pipeline awareness provided in this application; Figure 4 This is a schematic diagram of the Simulink code generation device based on instruction pipeline awareness provided in this application; Figure 5 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0028] Industrial-grade code generation tools in related technologies have incorporated various optimization techniques, such as local variable elimination, reusable data utilization, vectorized operations, SIMD (Single Instruction Multiple Data) instruction parallelism optimization, and expression folding. These techniques primarily focus on the syntactic and structural levels of the generated code to reduce redundant code and storage overhead. However, existing methods still have significant shortcomings in utilizing the underlying processor architecture. In particular, the lack of effective optimization at the processor's instruction pipeline level leads to frequent instruction pauses during execution, thereby reducing overall execution efficiency.

[0029] Instruction pipelining is a performance enhancement mechanism widely used in modern processor architectures. Its core idea is to divide the instruction execution process into multiple stages, such as fetch, decode, execute, memory access, and write back. Each stage can process different instructions in parallel, thus ideally completing one instruction per clock cycle. To further improve processing performance, modern high-performance processors have also introduced architectural features such as multiple issue, out-of-order execution, and speculative execution, allowing multiple independent instructions to enter the pipeline execution unit simultaneously within the same clock cycle, thereby significantly improving throughput.

[0030] However, the efficient operation of an instruction pipeline is highly dependent on the data independence between instructions. When a subsequent instruction needs to use the result of a previous instruction that has not yet been computed, the processor must pause issuing the new instruction and wait for the data dependency to be resolved. This phenomenon is called a pipeline stall or data hazard. Typical types of hazards include read-after-write (RAW), write-after-read (WAR), and write-after-write (WAW). These hazards can cause parts of the instruction pipeline to idle, reducing processor resource utilization. For resource-constrained embedded devices, frequent pipeline stalls will directly lead to increased execution latency, increased power consumption, and decreased system real-time performance.

[0031] To address the aforementioned technical problems in related technologies, this application provides a Simulink code generation method based on instruction pipeline awareness. This method constructs a closed-loop mechanism of "dependency extraction – latency modeling – pipeline scheduling optimization," effectively reducing pauses caused by instruction-level data dependencies and improving code execution parallelism and efficiency while maintaining model semantic consistency. The method introduces instruction-level latency modeling, module dependency topology analysis, and priority-based scheduling strategies during the model code generation stage. By extracting and estimating the execution instruction sets of modules in the model, this method can dynamically evaluate the execution timing characteristics of different modules during the generation stage. The system uses topology analysis to determine the data dependency paths between modules and adaptively selects the execution order using a "Least Penalty Priority" algorithm to avoid unnecessary waiting and resource conflicts, thereby effectively reducing the number of instruction pipeline pauses while ensuring model semantic consistency.

[0032] Furthermore, this method dynamically updates the module execution state during the generation process through asynchronous task allocation and dependency release mechanisms, enabling priority solving of high-value paths and pruning of invalid dependencies. This method can generate code with good pipeline adaptability on different architectures (including Intel, ARM, etc.), significantly improving the utilization of instruction issue units, thereby achieving higher execution efficiency and energy utilization on embedded devices.

[0033] The system used in the Simulink code generation method based on instruction pipeline awareness in this application embodiment can be divided into three units, such as... Figure 1 As shown, the system includes: an instruction dependency analysis and latency modeling unit, a pipeline-aware scheduling unit, and a code generation and feedback optimization unit.

[0034] The Simulink code generation method based on instruction pipeline awareness provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0035] like Figure 2 As shown in the figure, this application provides a Simulink code generation method based on instruction pipeline awareness, which may include the following steps 201 to 203: Step 201: Perform instruction dependency analysis and latency modeling on the target Simulink model to generate a dependency graph describing the dependencies between modules and an instruction latency model that incorporates the target processor architecture parameters.

[0036] For example, the core objective of the instruction dependency analysis and latency modeling unit is to extract the dependencies and execution order features between modules from the Simulink model, and to establish an instruction latency model in combination with the architecture parameters of the target processor, so as to provide an accurate performance basis for subsequent pipeline scheduling.

[0037] Specifically, step 201 above may also include the following steps 201a1 and 201a2: Step 201a1: Perform static structural analysis on the target Simulink model and construct a dependency graph with the model's modules as nodes and the data flow and control flow as directed edges.

[0038] Step 201a2: Based on the hardware feature information of the target processor, establish an instruction latency model for each module in the dependency graph.

[0039] The hardware feature information includes at least one of the following: number of pipeline stages, register access latency, memory access latency, and number of execution units.

[0040] For example, the instruction dependency analysis and delay modeling unit first performs static analysis on the model structure and maps the input-output signal relationship of each module in the model into a directed dependency graph.

[0041] For example, each node represents a model module, and each directed edge represents the direction of data transmission. The above dependencies are divided into three categories: 1. Explicit data dependency: Dependency between modules that are directly connected by signal lines.

[0042] 2. Implicit data dependency: Cross-layer dependency formed through shared variables or storage blocks.

[0043] 3. Control Dependency: Execution path dependency determined by control logic such as conditional judgments and triggers.

[0044] For example, through the above analysis, the system can accurately identify the actual execution order between instructions in the model, providing semantic constraints for scheduling optimization.

[0045] Specifically, during the system initialization phase, the dependency analysis engine first performs a structural scan on the input Simulink model. The system traverses the model hierarchy, converting each module (such as arithmetic operations, logical judgments, signal selection, subsystems, etc.) into node objects and recording their input ports, output ports, and signal types. Each signal connection is mapped to a directed edge, forming a directed dependency graph, where: node Ni represents an executable module; edge Ei,j indicates that the output data of module Ni is the input of module Nj; control modules (such as Switch, Trigger, If / Else) are identified as control dependency nodes, and their outputs control the activation conditions of other branch modules.

[0046] For example, the output of this stage is a complete module dependency graph structure, providing a data foundation for subsequent delay modeling. After the dependency graph is constructed, the system further identifies three types of dependencies: explicit data dependencies: dependencies directly formed by signal lines, representing the explicit computational order of input and output; implicit state dependencies: temporal dependencies introduced by delay modules (Unit Delay), memory storage modules (Data Store Memory), etc.; and control dependencies: conditional execution paths generated by branch conditions and triggering modules. The system uses topological sorting and logical backtracking methods to generate a dependency matrix, where each element D(i,j) represents whether the execution of module i affects module j and its dependency strength. This matrix not only reflects the execution order but also marks module combinations that cannot be executed in parallel, providing constraint boundaries for pipeline optimization.

[0047] For example, based on the extracted dependency structure, this module combines the hardware characteristics of the target processor (such as pipeline stages, register access latency, memory access latency, number of execution units, etc.) to establish an instruction latency model for each module. The latency model records the time and resource consumption required by the module instructions at different stages (fetch, decode, execute, memory access, write back), which is used for pause prediction and overlap calculation during subsequent scheduling.

[0048] Specifically, after identifying logical dependencies, the dependency analysis engine, in conjunction with the target processor architecture parameters, establishes an instruction latency model for each module. The model is constructed as follows: the computational logic within the module is decomposed into a sequence of basic instructions (such as multiplication, addition, comparison, and access); the processor parameter table is called to query the average number of cycles for each instruction during the fetch (IF), decode (ID), execute (EX), memory access (MEM), and write-back (WB) stages; the module's memory access operation and register access latency are superimposed to obtain the total execution latency of the module; the earliest available time for subsequent modules to read the module's output is calculated for pause prediction in the subsequent scheduling stage.

[0049] For example, the system stores the latency models of all modules as a latency matrix (Latency Table) and dynamically adjusts the latency distribution according to the module type (e.g., the arithmetic module has a short execution latency, while the storage module has a long latency). Through this mechanism, the high-level model can be abstracted and mapped into quantifiable temporal features, achieving a unification of model semantics and underlying execution characteristics.

[0050] In one possible implementation, the system determines whether there is a possibility of parallel execution between modules based on a latency model. Specifically, if two modules have no data dependency, they are marked as "parallelizable candidates"; if partial dependency exists, the waiting period is recorded for subsequent latency compensation. This analysis directly affects the subsequent candidate set generation and priority calculation by the scheduler.

[0051] It should be noted that the output of the instruction dependency analysis and delay modeling unit is a dependency graph and a delay matrix, which constitute the basic input information for pipeline scheduling optimization and realize the mapping from the model semantic layer to the instruction-level performance layer.

[0052] Step 102: Based on the dependency graph and the instruction latency model, determine the optimal execution sequence of each module through pipeline-aware scheduling, and perform pipeline scheduling based on the optimal execution sequence to obtain the scheduling result.

[0053] The pipeline-aware scheduling uses dynamic priority strategies and delay conflict prediction to minimize pipeline stalls.

[0054] For example, the core objective of the pipeline-aware scheduling unit is to determine the optimal execution order of each module through a pipeline latency-aware dynamic scheduling strategy, while ensuring the semantic correctness of the model, thereby minimizing inter-instruction waiting and pauses and improving instruction-level parallelism efficiency. The pipeline optimization engine is the core execution unit in this embodiment. Its design goal is to generate an execution order that fully utilizes the processor pipeline capabilities based on the latency model and dependency constraints, reducing inter-instruction waiting and pauses and maximizing parallel issue efficiency. This engine includes two key sub-modules: a dynamic priority scheduler and a structured code generator, which form a closed-loop collaborative mechanism of "scheduling-generation-feedback".

[0055] Specifically, step 202 above, which determines the optimal execution sequence of each module based on the dependency graph and the instruction latency model through pipeline-aware scheduling, may further include the following steps 202a1 and 202a2: Step 202a1: Extract the current set of executable modules from the dependency graph and calculate the comprehensive priority for each module in the set.

[0056] The overall priority is calculated based on at least one of the following: the depth of the module in the dependency graph, the overlap of instruction delays, and the impact of the module output on subsequent critical paths.

[0057] Step 202a2: Determine the optimal execution sequence for each module based on the overall priority of each module.

[0058] For example, the pipeline-aware scheduling unit extracts the set of currently executable modules (i.e., all modules whose predecessor dependencies have been satisfied) from the dependency graph, and calculates the execution overhead and resource conflict probability of each module based on the latency model. Specifically, this includes the following: 1. The priority of each module consists of three parts: 2. The depth of the module in the dependency graph (the shallower the depth, the higher the priority); 3. The overlap of module delays (the higher the potential for parallelism with other instructions, the higher the priority); 4. The impact of the module output on subsequent critical paths (the higher the critical path dependency, the higher the priority).

[0059] For example, in the embodiments of this application, the core function of the dynamic priority scheduler is to determine the launch order and execution timing of modules based on dependency relationships and latency prediction results, so as to ensure that the pipeline remains in a saturated operating state.

[0060] Specifically, step 202 above, which involves performing pipeline scheduling based on the optimal execution sequence to obtain the scheduling result, may further include step 202b: Step 202b: Based on the overall priority of each module and the conflict prediction results of the instruction delay model corresponding to each module, select the module with the highest overall priority for launch scheduling.

[0061] If, before a module is launched, the conflict prediction result for that module indicates a possibility of a pause, the launch of that module is delayed, and the next module that can be executed immediately is selected for launch to maintain the continuous operation of the pipeline.

[0062] For example, the scheduler maintains a dynamically adjustable priority queue, from which the module with the highest overall priority is selected for launch each time. Before launch, the system predicts whether RAW (read-after-write) or WAW (write-after-write) dependency conflicts will occur in future cycles based on a latency model. If a potential pause is predicted, the system automatically delays the scheduling of that module and selects the next highest priority module that can be executed immediately to keep the pipeline running continuously.

[0063] For example, when there are partial dependencies but not complete blocking between modules, the system inserts idle compensation instructions or independent calculation instructions into the scheduling table to fill potential empty cycles, thereby reducing resource waste caused by structural pauses. If the delay prediction result shows that there are unavoidable conflicts in future cycles, the system triggers a rollback mechanism, cancels the previous scheduling step, and recalculates the priority to obtain a globally better execution sequence.

[0064] Specifically, step 202b above may also include step 202b1, or step 202b2: Step 202b1: If the conflict prediction result indicates that there is partial dependency between modules and that they are not completely blocked, then an idle compensation instruction is inserted into the scheduling sequence to fill the potential idle period in order to reduce the waste of resources caused by structural pauses.

[0065] Step 202b2: If the conflict prediction result indicates that there is an unavoidable conflict, then trigger the scheduling rollback mechanism to recalculate the optimal execution sequence.

[0066] For example, the system first represents each module task as a triple <module ID, execution latency, dependency>. Based on the dependency graph analysis results, all modules without predecessor dependencies are added to the initial task queue, and the initial priority is calculated according to the following heuristic rule: The shallower the dependency, the higher the priority (preferentially launching shallow modules can activate subsequent paths as soon as possible); the shorter the latency and the greater the parallel potential, the higher the priority; if the module is located on the critical path (i.e. the longest path that affects the output port), the priority is increased.

[0067] For example, the task queue uses a max-heap structure with dynamically adjustable priorities, supporting real-time updates of module weights. The system's main loop continuously pops the highest-priority module M from the queue: The system uses a delay matrix to determine whether the execution of M conflicts with resources already issued in the current pipeline (e.g., the same execution unit is occupied or RAW dependencies are not resolved). If a conflict is unavoidable, the system records the predicted pause length and attempts to select the next candidate module. If there is no conflict, M is immediately scheduled to be issued and the pipeline status table is updated, marking the resource occupancy of the corresponding execution stage.

[0068] For example, the scheduler dynamically evaluates the latency overlap of all candidate tasks in each cycle, optimizes the launch sequence in real time, and ensures maximum pipeline utilization. The scheduler can automatically adjust latency model parameters and priority weights according to different processor architectures. In superscalar or out-of-order execution architectures, the system enhances the scheduling ratio of parallel modules; in sequential execution architectures, the system automatically degenerates into topological sequential scheduling to ensure result compatibility.

[0069] For example, the scheduler dynamically adjusts task priorities based on execution feedback during execution: when a module completes execution and releases resources, the priority of its successor module is immediately increased; if a module's execution causes a partial pause, the priority of its similar modules is reduced to prevent duplicate resource consumption; if a new module is activated (predecessor dependencies are released), the priority offset value is calculated based on the current pipeline resource load. Through this feedback mechanism, the scheduler can continuously adapt to changes in execution state and achieve global load balancing.

[0070] For example, the core function of the pipeline-aware scheduling unit is to enable the instruction generation process to proactively adapt to the underlying pipeline behavior through delay prediction and dynamic priority control, thereby achieving the fusion of model semantics and hardware execution characteristics.

[0071] Step 203: Based on the scheduling results, generate target code using a local pipeline optimization strategy.

[0072] The local pipeline optimization strategy includes at least one of the following: reordering instructions without breaking dependency constraints, renaming registers with spurious dependencies, inserting independent operations into the delay slots of branch instructions, and merging consecutive independent short instructions into compound instructions.

[0073] For example, the core objective of the code generation and feedback optimization unit is to generate semantically equivalent executable code based on the pipeline scheduling results, and further eliminate local performance losses through a feedback mechanism during the generation phase to achieve closed-loop optimization.

[0074] Specifically, step 203 above may also include the following step 203a: Step 203a: Generate the target code corresponding to each module according to the execution order determined by the scheduling result.

[0075] During code generation, registers are allocated and synchronization instructions are inserted based on dependency information to ensure correct execution results.

[0076] For example, the code generation and feedback optimization unit generates the corresponding target code according to the execution order determined by the scheduler. During the generation process, independent register space is allocated to each module, and necessary synchronization instructions (such as data write-back or wait flags) are inserted according to dependency information to ensure correct execution results. The system automatically integrates control flow and data flow logic during generation to ensure that the output code is strictly consistent with the original model semantically.

[0077] Specifically, the generator generates code snippets corresponding to modules step by step according to the scheduling sequence: it creates a local variable area and register mapping for each module; it automatically inserts synchronization instructions or data forwarding flags when data dependencies are detected to ensure read-write consistency; it generates independent code blocks for branch modules and uses conditional jump structures to ensure logical integrity. The code generator supports multiple target language outputs (C, C++, assembly) through a template mechanism, adapting to different compilers and embedded platforms.

[0078] For example, during code generation, the code generation and feedback optimization unit automatically applies various local optimization strategies, including: 1. Instruction reordering: Reordering interchangeable instructions to fill idle cycles without breaking dependency constraints. That is, adjusting the order of operations without dependencies so that independent computation fills the idle stages of the pipeline. 2. Register renaming: Reallocating registers with spurious dependencies to eliminate WAR and WAW type pseudo-conflicts. 3. Delayed slot utilization: Inserting independent operations within the delay cycle for branch jump instructions to reduce pipeline idle time. That is, inserting non-dependent operations after jump instructions to reduce branch bubbles. 4. Instruction fusion: Combining consecutive, independent short instructions into a single compound instruction to improve instruction fetch efficiency. That is, detecting common compound patterns (such as multiply-accumulate, logical merging) and merging them into a single instruction.

[0079] Optionally, after code generation is complete, the system automatically performs static analysis and simulation verification, calculating metrics such as pipeline stall rate, average cycle count, and instruction throughput. If the analysis results are lower than a preset performance threshold, the system sends a performance report back to the scheduling module to readjust priority or delay parameters, forming an adaptive closed-loop optimization mechanism of "scheduling-generation-feedback".

[0080] For example, after step 203 above, the Simulink code generation method based on instruction pipeline awareness provided in this application embodiment may further include the following steps 204 and 205: Step 204: Analyze the generated target code and obtain performance indicators based on the analysis results.

[0081] The performance metrics include at least one of the following: pipeline stall rate, average number of execution cycles, and instruction throughput.

[0082] Step 205: If the performance metrics of the target code do not reach the preset threshold, the parameters of the instruction latency model and / or the dynamic priority strategy are adjusted based on the analysis results, and a new round of optimized code generation is performed until the performance metrics of the target code reach the preset threshold.

[0083] For example, the dependency analysis engine and the pipeline optimization engine collaborate in parallel through shared data structures (DependencyGraph, Latency Table, ParallelSet): 1. When the dependency analysis engine updates inter-module dependencies or latency characteristics, the pipeline optimization engine reads the updated data in real time and reschedules. 2. After scheduling is complete, the code generator automatically triggers latency feedback to optimize the next round of analysis parameters. 3. All data synchronization is based on lightweight memory mapping and message queue mechanisms to ensure low latency and thread safety.

[0084] Through this closed-loop feedback and parallel optimization mechanism, the embodiments of this application realize a fully automatic performance adaptation process from model semantics to instruction execution, enabling the generated embedded code to achieve near-manually optimized running efficiency under different hardware architectures.

[0085] For example, the code generation and feedback optimization unit supports generation templates for various processor platforms (such as ARM, RISC-V, x86, etc.). If the target platform does not have pipelined parallel execution capabilities, the system automatically downgrades to traditional sequential code generation to ensure the correctness and portability of the results. The code generation and feedback optimization unit ensures that the generated code maintains both the semantic correctness of the model and has efficient pipelined execution performance, providing the final output for overall system optimization.

[0086] like Figure 3The diagram illustrates a detailed flowchart of the Simulink code generation method based on instruction pipeline awareness. The system consists of a closed-loop feedback structure comprised of a dependency analysis engine and a pipeline optimization engine. Given any Simulink model, it can automatically complete dependency resolution, instruction-level latency modeling, pipeline-aware scheduling, and code generation, achieving automatic mapping from model semantics to high-performance code. The entire system operates through multi-threaded parallel scheduling, relying on shared core data structures such as the Dependency Graph, Latency Table, and ParallelSet to achieve real-time information synchronization, constructing an automated closed loop of "semantic extraction – performance modeling – optimization scheduling – feedback generation".

[0087] Specifically, such as Figure 3 As shown, the various stages and data flow are as follows: 1. Simulink Model Input The process begins with the Simulink Model on the left, which serves as the system input and provides basic model data for subsequent steps.

[0088] 2. Pipeline Sensitive Content Collection: This stage revolves around the Simulink model and consists of two sub-steps: Model Actor Identification: Identifies "Actors" (modules) in the model and outputs ActorProperty (module properties). Dataflow Traversal: Traverses the data flow and analyzes Data Dependency.

[0089] 3. Critical Actor Identification Receive the Actor Property and Data Dependency from the "Pipeline Sensitive Content Collection" stage, and combine them with the Model Actor Library and Processor Parameters to complete the following sub-steps: Instruction Fetch: Retrieves instructions and outputs the instruction set.

[0090] Execution Latency Estimation: Estimates execution latency and outputs Candidate Actors.

[0091] Dependency Analysis: Analyzes data dependencies to assist in the selection of candidate actors.

[0092] 4. Pipeline-Friendly Code Synthesis It receives Candidate Actors from the "Key Actor Identification" stage, combines Model ActorTranslation and Model Actor Selection, and finally outputs Embedded Code.

[0093] 5. Data dependency release and penalty value update The process includes feedback mechanisms such as Data Dependency Release and Penalty Value Update to optimize the code generation process.

[0094] The Simulink code generation method based on instruction pipeline awareness provided in this application first performs instruction dependency analysis and latency modeling on the target Simulink model to generate a dependency graph describing the dependencies between modules and an instruction latency model incorporating the target processor architecture parameters. Then, based on the dependency graph and the instruction latency model, the optimal execution sequence for each module is determined through pipeline awareness scheduling, and pipeline scheduling is performed based on the optimal execution sequence to obtain the scheduling result. The pipeline awareness scheduling minimizes pipeline pauses through dynamic priority strategies and latency conflict prediction. Finally, based on the scheduling result, target code is generated using local pipeline optimization strategies. In this way, topology analysis is used to determine the data dependency paths between modules, and the least-penalty-first algorithm adaptively selects the execution order to avoid unnecessary waiting and resource conflicts, thereby effectively reducing the number of instruction pipeline pauses while ensuring model semantic consistency.

[0095] It should be noted that the Simulink code generation method based on instruction pipeline awareness provided in this application embodiment can be executed by an instruction pipeline awareness-based Simulink code generation device, or a control module within that device for executing the method. This application embodiment uses the execution of the Simulink code generation method by an instruction pipeline awareness-based Simulink code generation device as an example to illustrate the instruction pipeline awareness-based Simulink code generation device provided in this application embodiment.

[0096] It should be noted that, in the embodiments of this application, the Simulink code generation methods based on instruction pipeline awareness shown in the accompanying drawings are all illustrated using one accompanying drawing from one of the embodiments of this application as an example. In specific implementation, the Simulink code generation methods based on instruction pipeline awareness shown in the accompanying drawings of the above methods can also be implemented in conjunction with any other accompanying drawings shown in the above embodiments, which will not be elaborated here.

[0097] The following describes the instruction pipeline-aware Simulink code generation apparatus provided in this application. The description below corresponds to the instruction pipeline-aware Simulink code generation method described above.

[0098] Figure 4 A schematic diagram of the structure of the Simulink code generation device based on instruction pipeline awareness provided in the embodiments of this application is shown below. Figure 4 As shown, it specifically includes: The latency model construction module 401 is used to perform instruction dependency analysis and latency modeling on the target Simulink model, generating a dependency graph describing the dependencies between modules and an instruction latency model incorporating the target processor architecture parameters; the pipeline-aware scheduling module 402 is used to determine the optimal execution sequence of each module based on the dependency graph and the instruction latency model, and to perform pipeline scheduling based on the optimal execution sequence to obtain the scheduling result; the pipeline-aware scheduling minimizes pipeline stalls through dynamic priority strategies and latency conflict prediction; the code generation module 403 is used to generate target code based on the scheduling result using local pipeline optimization strategies.

[0099] Optionally, the latency model construction module 401 is specifically used to perform static structural analysis on the target Simulink model and construct a dependency graph with the modules of the model as nodes and the data flow and control flow as directed edges; the latency model construction module 401 is also specifically used to establish an instruction latency model for each module in the dependency graph based on the hardware feature information of the target processor; wherein, the hardware feature information includes at least one of the following: pipeline stage number, register access latency, memory access latency, and number of execution units.

[0100] Optionally, the pipeline-aware scheduling module 402 is specifically used to extract the current set of executable modules from the dependency graph and calculate a comprehensive priority for each module in the set; the comprehensive priority is calculated based on at least one of the following: the depth of the module in the dependency graph, the overlap of instruction latency, and the impact of the module output on subsequent critical paths; the pipeline-aware scheduling module 402 is further used to determine the optimal execution sequence of each module based on the comprehensive priority of each module.

[0101] Optionally, the pipeline awareness scheduling module 402 is specifically used to select the module with the highest overall priority for launch scheduling based on the overall priority of each module and the conflict prediction result of the instruction delay model corresponding to each module; wherein, before the module is launched, if the conflict prediction result corresponding to the module indicates that there is a possibility of a pause, the launch of the module is delayed, and the next module that can be executed immediately is selected for launch to maintain the continuous operation of the pipeline.

[0102] Optionally, the pipeline-aware scheduling module 402 is specifically used to insert an idle compensation instruction into the scheduling sequence to fill potential idle cycles if the conflict prediction result indicates that there is a partial dependency between modules and that they are not completely blocked, so as to reduce the resource waste caused by structural pauses; the pipeline-aware scheduling module 402 is also specifically used to trigger a scheduling rollback mechanism to recalculate the optimal execution sequence if the conflict prediction result indicates that there is an unavoidable conflict.

[0103] Optionally, the code generation module 403 is specifically used to generate target code corresponding to each module according to the execution order determined by the scheduling result; wherein, during the code generation process, register allocation is performed and synchronization instructions are inserted according to dependency information to ensure that the execution result is correct.

[0104] Optionally, the apparatus further includes: an optimization feedback module; the optimization feedback module is used to analyze the generated target code and obtain performance indicators based on the analysis results; the performance indicators include at least one of the following: pipeline pause rate, average number of execution cycles, and instruction throughput; the optimization feedback module is also used to adjust the parameters of the instruction latency model and / or the dynamic priority strategy based on the analysis results if the performance indicators of the target code do not reach the preset threshold, and to perform a new round of optimized code generation until the performance indicators of the target code reach the preset threshold.

[0105] The Simulink code generation apparatus provided in this application, based on instruction pipeline awareness, firstly performs instruction dependency analysis and latency modeling on the target Simulink model, generating a dependency graph describing the dependencies between modules and an instruction latency model incorporating the target processor architecture parameters. Then, based on the dependency graph and the instruction latency model, it determines the optimal execution sequence for each module through pipeline awareness scheduling, and performs pipeline scheduling based on the optimal execution sequence to obtain the scheduling result. The pipeline awareness scheduling minimizes pipeline pauses through dynamic priority strategies and latency conflict prediction. Finally, based on the scheduling result, it generates target code using local pipeline optimization strategies. In this way, topology analysis is used to determine the data dependency paths between modules, and the least-penalty-first algorithm adaptively selects the execution order to avoid unnecessary waiting and resource conflicts, thereby effectively reducing the number of instruction pipeline pauses while ensuring model semantic consistency.

[0106] Figure 5 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 5As shown, the electronic device may include a processor 510, a communications interface 520, a memory 530, and a communication bus 540, wherein the processor 510, communications interface 520, and memory 530 communicate with each other via the communication bus 540. The processor 510 can call logical instructions in the memory 530 to execute a Simulink code generation method based on instruction pipeline awareness. This method includes: first, performing instruction dependency analysis and latency modeling on the target Simulink model to generate a dependency graph describing the dependencies between modules and an instruction latency model incorporating the target processor architecture parameters; then, based on the dependency graph and the instruction latency model, determining the optimal execution sequence for each module through pipeline awareness scheduling, and performing pipeline scheduling based on the optimal execution sequence to obtain a scheduling result; the pipeline awareness scheduling minimizes pipeline stalls through dynamic priority strategies and latency conflict prediction; finally, generating target code based on the scheduling result using a local pipeline optimization strategy. In this way, topology analysis is used to determine the data dependency paths between modules, and the execution order is adaptively selected through the least penalty first algorithm to avoid unnecessary waiting and resource conflicts, thereby effectively reducing the number of instruction pipeline pauses while ensuring the semantic consistency of the model.

[0107] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0108] On the other hand, this application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer can execute the instruction pipeline-aware Simulink code generation method provided by the above methods. This method includes: first, performing instruction dependency analysis and latency modeling on the target Simulink model to generate a dependency graph describing the dependencies between modules and an instruction latency model incorporating the target processor architecture parameters; then, based on the dependency graph and the instruction latency model, determining the optimal execution sequence of each module through pipeline-aware scheduling, and performing pipeline scheduling based on the optimal execution sequence to obtain a scheduling result; the pipeline-aware scheduling minimizes pipeline pauses through dynamic priority strategies and latency conflict prediction; finally, generating target code based on the scheduling result using a local pipeline optimization strategy. Thus, by using topology analysis to determine the data dependency paths between modules and adaptively selecting the execution order through a minimum penalty first algorithm, unnecessary waiting and resource conflicts are avoided, thereby effectively reducing the number of instruction pipeline pauses while ensuring model semantic consistency.

[0109] Furthermore, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the aforementioned instruction pipeline-aware Simulink code generation methods. This method includes: first, performing instruction dependency analysis and latency modeling on the target Simulink model to generate a dependency graph describing the dependencies between modules and an instruction latency model incorporating target processor architecture parameters; then, based on the dependency graph and the instruction latency model, determining the optimal execution sequence for each module through pipeline-aware scheduling, and performing pipeline scheduling based on the optimal execution sequence to obtain a scheduling result; the pipeline-aware scheduling minimizes pipeline pauses through dynamic priority strategies and latency conflict prediction; finally, generating target code based on the scheduling result using local pipeline optimization strategies. In this way, topology analysis is used to determine the data dependency paths between modules, and the execution order is adaptively selected using a minimum penalty first algorithm to avoid unnecessary waiting and resource conflicts, thereby effectively reducing the number of instruction pipeline pauses while ensuring model semantic consistency.

[0110] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0111] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A Simulink code generation method based on instruction pipeline awareness, characterized in that, include: Instruction dependency analysis and latency modeling are performed on the target Simulink model to generate a dependency graph describing the dependencies between modules and an instruction latency model that incorporates the target processor architecture parameters. Based on the dependency graph and the instruction latency model, the optimal execution sequence of each module is determined by pipeline-aware scheduling, and pipeline scheduling is performed based on the optimal execution sequence to obtain the scheduling result. The pipeline-aware scheduling minimizes pipeline downtime through dynamic priority strategies and delay conflict prediction. Based on the scheduling results, target code is generated using a local pipeline optimization strategy.

2. The method according to claim 1, wherein the local pipeline optimization strategy includes at least one of the following: reordering instructions without breaking dependency constraints, renaming registers with spurious dependencies, inserting independent operations into the delay slots of branch instructions, and merging consecutive independent short instructions into compound instructions.

3. The method according to claim 1, characterized in that, The process of performing instruction dependency analysis and latency modeling on the target Simulink model to generate a dependency graph describing the dependencies between modules and an instruction latency model incorporating the target processor architecture parameters includes: Static structural analysis is performed on the target Simulink model to construct a dependency graph with the model's modules as nodes and the data flow and control flow as directed edges. Based on the hardware feature information of the target processor, an instruction latency model is established for each module in the dependency graph; The hardware feature information includes at least one of the following: number of pipeline stages, register access latency, memory access latency, and number of execution units.

4. The method according to claim 1, characterized in that, The process of determining the optimal execution sequence of each module based on the dependency graph and the instruction latency model through pipeline-aware scheduling includes: Extract the current set of executable modules from the dependency graph and calculate a comprehensive priority for each module in the set; the comprehensive priority is calculated based on at least one of the following: the depth of the module in the dependency graph, the overlap of instruction latency, and the impact of the module output on subsequent critical paths; Based on the overall priority of each module, the optimal execution sequence of each module is determined.

5. The method according to claim 1 or 4, characterized in that, The pipeline scheduling based on the optimal execution sequence, to obtain the scheduling result, includes: Based on the overall priority of each module and the conflict prediction results of the instruction delay model corresponding to each module, the module with the highest overall priority is selected for launch scheduling. If, before a module is launched, the conflict prediction result for that module indicates a possibility of a pause, the launch of that module is delayed, and the next module that can be executed immediately is selected for launch to maintain the continuous operation of the pipeline.

6. The method according to claim 5, characterized in that, The selection of the module with the highest overall priority for launch scheduling includes: If the conflict prediction result indicates that there is partial dependency between modules and that they are not completely blocked, then an idle compensation instruction is inserted into the scheduling sequence to fill the potential idle period in order to reduce the waste of resources caused by structural pauses. If the conflict prediction results indicate that there is an unavoidable conflict, the scheduling rollback mechanism is triggered to recalculate the optimal execution sequence.

7. The method according to claim 1, characterized in that, The step of generating target code based on the scheduling result using a local pipeline optimization strategy includes: According to the execution order determined by the scheduling results, generate the target code corresponding to each module; During code generation, registers are allocated and synchronization instructions are inserted based on dependency information to ensure correct execution results.

8. The method according to claim 1, characterized in that, After generating the target code based on the scheduling result using a local pipeline optimization strategy, the method further includes: The generated target code is analyzed, and performance metrics are obtained based on the analysis results; the performance metrics include at least one of the following: pipeline stall rate, average number of execution cycles, and instruction throughput. If the performance metrics of the target code do not reach the preset threshold, the parameters of the instruction latency model and / or the dynamic priority strategy will be adjusted based on the analysis results, and a new round of optimized code generation will be performed until the performance metrics of the target code reach the preset threshold.

9. A Simulink code generation apparatus based on instruction pipeline awareness, characterized in that, The device includes: The latency model building module is used to perform instruction dependency analysis and latency modeling on the target Simulink model, generating a dependency graph describing the dependencies between modules and an instruction latency model that incorporates the target processor architecture parameters. The pipeline-aware scheduling module is used to determine the optimal execution sequence of each module based on the dependency graph and the instruction latency model, and to perform pipeline scheduling based on the optimal execution sequence to obtain the scheduling result; the pipeline-aware scheduling minimizes pipeline pauses through dynamic priority strategy and latency conflict prediction. The code generation module is used to generate target code based on the scheduling results using a local pipeline optimization strategy.

10. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of the instruction pipeline-aware Simulink code generation method as described in any one of claims 1 to 8.

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