EEPROM chip driving method and device

Abstract

The invention discloses an EEPROM (Electrically Erasable Programmable Read-Only Memory) chip driving method and device, and the EEPROM chip driving method comprises the following steps: determining a read / write / query process action sequence array: extracting a basic time sequence action from original driving time sequence actions for driving an EEPROM chip as a basic instruction; combining the plurality of basic instructions as a combined instruction; according to the read / write / query process of the EEPROM chip, the EEPROM chip is decomposed into a read process action sequence array, a write process action sequence array and a query process action sequence array which respectively comprise a plurality of combined instructions; according to the different process action sequence arrays, corresponding driving programs are formed and used for driving the EEPROM chip. According to the EEPROM chip driving method, code maintenance is facilitated, program readability is improved, timing of actions and timing sequences is distinguished, and the execution speed and sequence of the actions are easily adjusted according to different chips.

Description

Technical Field

[0001] This invention relates to the field of storage control technology, and in particular to an EEPROM chip driving method and apparatus. Background Technology

[0002] EEPROM (Electrically Erasable Programmable Read-Only Memory) is a type of memory chip that retains data even when power is off. EEPROM chips can be directly erased and written to on a computer or dedicated device via circuit control, eliminating the need for external devices. This means that data can be erased and written to at any time during device operation, and data can be modified byte-by-byte without erasing the entire chip. It is typically used to store configuration information that is loaded when the system is powered on again.

[0003] Many companies currently use I / O port simulation drivers when configuring and running EEPROM chip storage devices. Many related software programs do not comply with the I2C bus protocol in their handling of clock and data signals. Furthermore, when changing to different models or manufacturers, timing adjustments can easily lead to incompatibility issues and software accidents.

[0004] Traditional I / O port drivers for the I2C (Inter-Integrated Circuit) bus have fragmented and numerous software functions. I / O port operations and operation speeds are mixed in the same code segment. Maintenance and testing require a complete review and analysis of the code, resulting in low efficiency, poor readability, and a high risk of errors. Summary of the Invention

[0005] In response to the problems mentioned in the background art, this application provides an EEPROM chip driving method, which adopts an instruction-based driving architecture to decompose the EEPROM read and write process into an action sequence array composed of multiple instructions. This facilitates code maintenance, improves program readability, and separates the timing of actions from the timing of timing, making it easy to adjust the execution speed and order of each action according to different EEPROM chips.

[0006] To achieve the above-mentioned objectives, the present invention employs the following technical solution: Some embodiments of this application relate to an EEPROM chip driving method, including: Determine an array of read / write / query process action sequences, which includes: Extract basic timing actions from the original driving timing actions of the EEPROM chip as basic instructions. The basic instructions are single instructions that control the MCU port connected to the serial data line pin SDA, serial clock line pin SCL and write protection pin WP of the EEPROM chip. Multiple basic instructions are combined to form a combined instruction, which appears repeatedly in the driving timing action. Based on the read / write / query process of the EEPROM chip, it is decomposed into an array of read process action sequences, an array of write process action sequences, and an array of query process action sequences, each including multiple combined instructions; Based on different process action sequence arrays, corresponding driver programs are formed to drive the EEPROM chip.

[0007] The technical solutions involved in the above embodiments have the following beneficial effects or advantages: This technical solution decomposes basic instructions from the original driver timing actions and combines multiple basic instructions into combined instructions to form an instruction-based driver architecture. It abstracts the basic actions of EEPROM and the repetitive I2C bus timing actions, and encodes them centrally according to the read / write / query process, forming read process action sequence arrays, write process action sequence arrays, and query process action sequence arrays. This standardizes the actions, making them easier to understand and manage, simplifying the design, making it easier to find problems, reducing software complexity, improving software maintainability, facilitating future upgrades, and adding new functions.

[0008] Furthermore, this instruction-driven architecture separates the timing of actions from the timing of events, making it easier to adjust the interval (i.e., execution speed) and sequence of each action according to the timing requirements of different chips, facilitating the addition of new functions and improving software testing efficiency.

[0009] In some embodiments of this application, the basic instructions include at least: Modify the value of the pin's direction register, set or clear the pin, and read the pin's value.

[0010] The technical solutions involved in the above embodiments have the following beneficial effects or advantages: During the read / write / query process, modifying the value of the pin's direction register, setting or clearing the pin, and reading the pin's value are the simplest I2C bus actions. Selecting these actions as basic actions makes it easy to standardize the actions and facilitates later maintenance or upgrades.

[0011] In some embodiments of this application, the array of actions for determining the read / write / query process further includes: Set process variables, which are used to record and control the state of the driver execution process; The virtual instructions are set up to form a code segment that combines specific logic and computational tasks during the read / write process.

[0012] The technical solutions involved in the above embodiments have the following beneficial effects or advantages: During the process of reading / writing / querying EEPROM chips, parameter and logic judgments are also involved. Therefore, to create driver software that drives EEPROM chips, virtual instructions and process variables need to be added to assist the basic instructions in generating a driver software that is logically simple, clear, easy to understand, easy to maintain and port.

[0013] In some embodiments of this application, when forming basic instructions and combined instructions, each basic instruction and combined instruction is numbered.

[0014] The technical solutions involved in the above embodiments have the following beneficial effects or advantages: Each basic instruction and combination instruction is numbered to facilitate instruction management and make it easier to find problems.

[0015] In some embodiments of this application, the basic instructions include: The first basic instruction is used to set the value of the direction register of the SDA pin, so that the direction register of the SDA pin is an output; The second basic instruction is used to set the value of the direction register of pin SDA, so that the direction register of pin SDA is an input; The third basic instruction is used to set the value of the direction register of the SCL pin, so that the direction register of the SCL pin is an output; The fourth basic instruction is used to set the value of the direction register of the SCL pin, so that the direction register of the SCL pin is an input.

[0016] The technical solutions involved in the above embodiments have the following beneficial effects or advantages: The first, second, third, and fourth basic instructions are used to modify the value of the pin's direction register in order to enable the read and write process of the EEPROM.

[0017] In some embodiments of this application, the basic instructions further include: The fifth basic instruction is used to enable write protection, wherein the write protection pin WP is set; The sixth basic instruction is used to disable write protection by clearing the write protection pin WP to zero.

[0018] The technical solutions involved in the above embodiments have the following beneficial effects or advantages: The write protection pin WP is set and cleared using the fifth and sixth basic instructions, thereby enabling write protection and disabling writing during non-write operations, and disabling write protection and allowing normal writing during write operations.

[0019] In some embodiments of this application, the basic instructions further include: The seventh basic instruction is used to read the status of the SDA line connected to the SDA pin.

[0020] The technical solutions involved in the above embodiments have the following beneficial effects or advantages: The seventh basic instruction is used to read the status of the SDA line connected to the SDA pin. This reading must be done when the SDA pin is an input port and the SCL pin is high. The reading result is then saved.

[0021] In some embodiments of this application, the combination instructions include at least: The first set of instructions is used to set the I2C bus start signal; The second set of instructions is used to set the I2C bus stop signal; The third instruction combination is used to send a single data bit. The fourth combination instruction is used to receive a single data bit; The fifth combination instruction is used to check whether the ACK signal is valid when writing data or sending chip select data; The sixth instruction set is used to acknowledge the ACK signal on the I2C bus when reading data, and to send the NACK signal when the last piece of data has been read.

[0022] The seventh set of instructions is used to establish the normal state of pins SCL, SDA, and WP; The eighth combination instruction is used to set the EEPROM chip to an idle state.

[0023] The technical solutions involved in the above embodiments have the following beneficial effects or advantages: The actions performed by the above combined instructions are all necessary to complete during the read and write process, and each combined instruction is executed by a basic instruction. In this way, the actions corresponding to the combined instructions are also standardized, which facilitates maintenance and portability.

[0024] In some embodiments of this application, the seventh combination instruction shown is specifically used for: Set pins SCL and SDA as input ports, set the output register output to 0, and disable write protection during write operations. The eighth combined instruction is specifically used for: Set pins SCL and SDA as input ports, set the output of the output register to 0, and enable write protection.

[0025] The technical solutions involved in the above embodiments have the following beneficial effects or advantages: Before performing a read / write / query operation, it should be ensured that the SCL, SDA, and WP pins are in normal state and the EEPROM chip is in an idle state. Therefore, the seventh and eighth combination instructions are used to set the normal state of SCL, SDA, and WP and the idle state of the EEPROM chip.

[0026] Some embodiments of this application also relate to an EEPROM chip driver device, comprising: processor; and The memory stores processor-executable program code that, when executed by the processor, implements the driving method as described above.

[0027] The technical solutions involved in the above embodiments have the following beneficial effects or advantages: The driving method relies on a hardware carrier for implementation. Therefore, in terms of hardware, a processor is configured to execute the aforementioned EEPROM chip driving method stored in the memory, thereby enabling read / write / query operations on the EEPROM chip under an instruction-driven driving architecture.

[0028] Other features and advantages of the present invention will become clearer after reading the detailed embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 Here is a schematic diagram of an existing air conditioner. Figure 2 Based on the existing EEPROM chip driver software architecture; Figure 3 For EEPROM chip driver software architecture; Figure 4 The flowchart is a process for the EEPROM chip driving method proposed in this application; Figure 5This is a flowchart illustrating the determination of the read / write / query process action sequence array in the EEPROM chip driving method proposed in this application; Figure 6 This is a schematic diagram of the basic instructions involved in the EEPROM chip driving method proposed in this application; Figure 7 This is a schematic diagram of the combined instructions involved in the EEPROM chip driving method according to this application; Figure 8 A schematic diagram of the process variables involved in the EEPROM chip driving method proposed in this application; Figure 9 This is a schematic diagram of the virtual instructions involved in the EEPROM chip driving method proposed in this application; Figure 10 This is a block diagram of an EEPROM chip driver device according to this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0033] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0035] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0036] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0037] In household appliances, such as air conditioners, EEPROM chips are installed in their corresponding systems to store device configuration and operating data. The data is not lost when power is off. In this application, we are mainly concerned with the driving method of EEPROM chips, so that the driver software program is easy to manage and maintain, and the software program can be easily ported, modified and adjusted when the EEPROM chip in the air conditioner is replaced with different models and manufacturers.

[0038] The basic working principle of an air conditioner will be described below.

[0039] Air conditioners execute a refrigeration cycle using a compressor, condenser, expansion valve, and evaporator. The refrigeration cycle involves a series of processes, including compression, condensation, expansion, and evaporation, to cool or heat an indoor space.

[0040] Low-temperature, low-pressure refrigerant enters the compressor, which compresses it into a high-temperature, high-pressure refrigerant gas and discharges the compressed refrigerant gas. The discharged refrigerant gas flows into the condenser. The condenser condenses the compressed refrigerant into a liquid phase, and the heat is released to the surrounding environment through the condensation process.

[0041] The expansion valve expands the high-temperature, high-pressure liquid refrigerant that condenses in the condenser into a low-pressure liquid refrigerant. The evaporator evaporates the expanded refrigerant in the expansion valve and returns the low-temperature, low-pressure refrigerant gas to the compressor. The evaporator achieves its cooling effect by utilizing the latent heat of refrigerant evaporation to exchange heat with the material being cooled. Throughout the cycle, the air conditioner regulates the temperature of the indoor space.

[0042] See Figure 1 The outdoor unit of an air conditioner refers to the part of the refrigeration cycle that includes the compressor and the outdoor heat exchanger. The indoor unit of an air conditioner includes the indoor heat exchanger, and the expansion valve can be provided in either the indoor or outdoor unit.

[0043] The indoor and outdoor heat exchangers function as either condensers or evaporators. When the indoor heat exchanger is used as a condenser, the air conditioner functions as a heater in heating mode; when the indoor heat exchanger is used as an evaporator, the air conditioner functions as a cooler in cooling mode.

[0044] The following describes the EEPROM chip driving method.

[0045] See Figure 2 It shows the driver software architecture of EEPROM chips used by most manufacturers.

[0046] exist Figure 2 In the illustrated architecture, many similar operations are scattered across numerous fragmented functions, which poses difficulties for timing adjustments and logic upgrades during later code maintenance and is prone to omission, leading to bugs. Furthermore, adding new EEPROM read / write methods requires additional code, incurring coding and testing time and increasing labor costs.

[0047] Therefore, in some embodiments of this application, the traditional low-level I2C port input / output control and single-byte read / write functions are combined into one. The tedious, difficult-to-understand, and error-prone parts are decomposed and combined into a unified instruction set. Furthermore, the process of reading and writing data areas in the EEPROM chip is serialized into an array of externally modifiable action combinations. See [link to relevant documentation]. Figure 3 As shown.

[0048] In some embodiments of this application, the EEPROM chip adopts an instruction-driven architecture, which abstracts the basic operations of the EEPROM chip and the repetitive I2C bus timing operations, and generates driver software that is simple, clear, easy to understand, easy to maintain and port, based on the EEPROM chip read / write / query process.

[0049] See Figure 4 It shows a flowchart of the EEPROM chip driving method.

[0050] In some embodiments of this application, the EEPROM chip driving method includes determining an array of read / write / query process action sequences.

[0051] In some embodiments of this application, the basic operations of the EEPROM and the repetitive I2C bus timing operations need to be abstracted before writing the driver.

[0052] See Figure 5 It shows a flowchart for determining an array of action sequences for the read / write / query process.

[0053] Extract basic timing actions from the original driving timing actions of the EEPROM chip, and use them as basic instructions.

[0054] Among them, the original driving timing action refers to the use of Figure 2 The architecture shown in the diagram drives the read / write / query process of the EEPROM chip.

[0055] The driving process involved in this embodiment is also a reading / writing / querying process for the EEPROM chip. The difference from the traditional driving process is that this embodiment uses extracted instructions to write a driver program to implement the reading / writing / querying process for the EEPROM chip.

[0056] In some embodiments of this application, basic instructions and combined instructions are set.

[0057] The basic instruction is the simplest I2C bus operation. In some embodiments of this application, the basic instruction is a single instruction that controls the MCU port connected to the serial data line pin SDA, serial clock line pin SCL, and write protection pin WP of the EEPROM chip.

[0058] This single instruction includes at least modifying the value of the pin's direction register, setting or clearing the pin, and reading the pin's value.

[0059] In some embodiments of this application, the basic instructions can be numbered, for example, 1, 2, 3, ..., for ease of management.

[0060] See Figure 6It displays several basic instructions.

[0061] In some embodiments of this application, the basic instruction includes a first basic instruction (the instruction name may be clrsda).

[0062] The first basic instruction is used to set the value of the direction register of pin SDA, so that the direction register of pin SDA is an output.

[0063] In some embodiments of this application, the base instruction includes a second base instruction (the instruction name may be setsda).

[0064] This second basic instruction is used to set the value of the direction register of pin SDA, making the direction register of pin SDA an input.

[0065] In some embodiments of this application, the basic instruction includes a third basic instruction (the instruction name may be clrscl).

[0066] This third basic instruction is used to set the value of the direction register of the SCL pin, so that the direction register of the SCL pin is an output.

[0067] In some embodiments of this application, the basic instruction includes a fourth basic instruction (the instruction name may be setscl).

[0068] The fourth basic instruction is used to set the value of the direction register of the SCL pin, making the direction register of the SCL pin an input.

[0069] In some embodiments of this application, the basic instructions also include a fifth basic instruction (the instruction name may be enbwr).

[0070] The fifth basic instruction is used to enable write protection by setting the write protection pin WP (i.e., setting it to 1), which prevents writing.

[0071] In some embodiments of this application, the basic instructions also include a sixth basic instruction (the instruction name may be diswr).

[0072] The sixth basic instruction is used to disable write protection by clearing the write protection pin WP to zero (i.e., setting it to 0), at which point normal writing is possible.

[0073] In some embodiments of this application, the basic instructions also include a seventh basic instruction (the instruction name may be getsda).

[0074] The seventh basic instruction is used to read the status of the SDA line connected to the SDA pin. This reading must be performed when the SDA pin is an input port and the SCL pin is high. The data result of this reading can be stored.

[0075] The actions performed by the basic instructions described above all occur in the regular EEPROM read / write / query process. However, in some embodiments of this application, these actions are extracted as a single basic instruction.

[0076] In some embodiments of this application, multiple basic instructions are combined as combined instructions, and the instruction operations of the combined instructions are required to be repeated in multiple places in the EEPROM driver timing.

[0077] Replacing repetitive instructions with combined instructions makes them easier to understand, simpler and clearer in function, and more reusable.

[0078] See Figure 7 It displays a variety of combined instructions.

[0079] In some embodiments of this application, each combination instruction can be numbered, such as 16, 17, 18, ..., for ease of management.

[0080] In some embodiments of this application, the combined instruction includes a first combined instruction (the instruction name may be start).

[0081] The first set of instructions is used to set the I2C bus start signal, which involves the operation of the signals of pin SDA and pin SCL.

[0082] In some embodiments of this application, the MCU keeps SCL high and then transitions the SDA data signal from high to low to indicate a start signal. Simultaneously, devices on the I2C bus detect this start signal and know that the MCU is about to send data.

[0083] To perform the function of the first set of instructions, the first set of instructions may include the basic instructions setsda, setscl, clrsda and clrsc, which are executed sequentially.

[0084] In some embodiments of this application, the combined instruction includes a second combined instruction (the instruction name may be stop). The second set of instructions is used to set the I2C bus stop signal, which involves the operation of the signals of pin SDA and pin SCL.

[0085] In some embodiments of this application, the MCU keeps the SCL clock high and then transitions the SDA data signal from low to high to indicate a stop signal. Simultaneously, devices on the I2C bus detect this stop signal and know that the MCU has ended data transmission.

[0086] To accomplish the function of the second set of instructions, the second set of instructions may include the basic instructions clrsda, setscl, and setsda, which are executed sequentially.

[0087] In some embodiments of this application, the combination instruction includes a third combination instruction (the instruction name may be put).

[0088] The third set of instructions is used to send a data bit, and it also involves the operation of the signals on pin SDA and pin SCL.

[0089] In some embodiments of this application, in order to implement combined instructions, the execution function of combined instructions cannot be completed by simply relying on basic instructions. A process variable is also required. This process variable is used to record and control the state of the driver execution process and control the software to make correct judgments according to the calling requirements during the execution process.

[0090] In some embodiments of this application, process variables are variables used between basic instructions in the combination process to complete the function of the combination instructions, such as bit number, byte number, number of data, starting address, read / write status, etc.

[0091] In some embodiments of this application, the EEPROM chip driving method further includes setting virtual instructions, which are used to combine specific logic and computational tasks into code segments during the read and write process, such as generating chip select instruction words, initializing data buffers, starting, stopping, protecting, etc.

[0092] Virtual instructions do not occupy I2C bus operation time. When a virtual instruction is encountered, it is executed directly, and the process immediately proceeds to the next instruction after completion, until the basic instruction and combined instruction are encountered.

[0093] See Figure 8 The example shows multiple process variables.

[0094] In some embodiments of this application, the data result read by the seventh basic instruction getsda as described above is stored in bit_value.

[0095] In some embodiments of this application, the actions decomposed by the third combination instruction put may include the following: (1) 1.1 If the highest bit of byte_value is not equal to 0, then bit_value is set to 1; otherwise, bit_value is cleared to zero. 1.2 Left shift of byte_value by one bit 1.3 The bit_index increments by 1 1.4 If bit_value ≠ 0, then setsda; otherwise, clrsda. 1.5 setscl (2) clrscl.

[0096] Wherein, serial numbers (1) and (2) represent the first loop and the second loop, and 1.1, 1.2, 1.3, 1.4 and 1.5 in the first loop (1) represent the execution steps in the first loop.

[0097] Therefore, the third combination instruction is the basic instructions setsda, clrsda, setscl, and clrscl together with the process variables byte_value and bit_value to achieve the function of the combination instruction.

[0098] See Figure 9 The example provides several virtual instructions.

[0099] In some embodiments of this application, each virtual instruction can be numbered, for example, 32, 33, 34, ..., for ease of management.

[0100] In some embodiments of this application, the combination instruction further includes a fourth combination instruction (the instruction name may be get).

[0101] The fourth combination instruction is used to receive a data bit, and it also involves the operation of the signals of pin SDA and pin SCL.

[0102] In some embodiments of this application, the actions decomposed by the fourth combination instruction get may include the following: (1) setscl (2) 2.1 getsda 2.2 Left shift of byte_value by one bit 2.3 Place the bit_value in the least significant bit of the byte_value. 2.4 The bit_index is incremented by 1. 2.5 clrscl.

[0103] This shows that the fourth combination instruction is the basic instructions setscl, getsda, and clrscl together with the process variables byte_value and bit_value to achieve the function of the combination instruction.

[0104] In some embodiments of this application, the combination instruction further includes a fifth combination instruction (the instruction name may be check).

[0105] The fifth set of instructions is used to check whether the response signal ACK is valid when writing data or sending chip select data. It also involves the operation of the signals of pin SDA and pin SCL.

[0106] In some embodiments of this application, the actions decomposed by the fifth combination instruction check may include the following: (1)1.1 setsda 1.2 setscl (2)2.1 getsda 2.2 If bit_value ≠ 0, then process the exception 2.3 clrscl.

[0107] It can be seen from this that the fifth combined instruction is the basic instructions setsda, setscl, getsda, and clrscl together with the process variable bit_value that can realize the function of the combined instruction.

[0108] In some embodiments of the present application, the combined instruction further includes a sixth combined instruction (the instruction name can be ack).

[0109] The sixth combined instruction is used to respond to the response signal ACK on the I2C bus when reading data, and send a non-response signal NACK when reading the last data. It also involves the actions of the signals of pin SDA and pin SCL.

[0110] In some embodiments of the present application, the actions decomposed by the sixth combined instruction ack may include the following: (1)1.1 If byte_index + 1 < byte_size, then clrsda, otherwise setsda 1.2 setscl (2) clrscl.

[0111] It can be seen from this that the sixth combined instruction is the basic instructions clrsda, setsda, setscl, and clrscl together with the process variables byte_index and byte_size that can realize the function of the combined instruction.

[0112] In some embodiments of the present application, the combined instruction further includes a seventh combined instruction (the instruction name can be wakeup).

[0113] The seventh combined instruction is used to establish the normal states of pins SCL, SDA, and WP, that is, both SDA and SDL are set to input ports, the output registers are all set to 0, and the write protection is turned off during write operations.

[0114] In some embodiments of the present application, the combined instruction further includes an eighth combined instruction (the instruction name can be idle).

[0115] The eighth combined instruction is used to set the EEPROM chip to the idle state, that is, both SDA and SDL are set to input ports, the output registers are all set to 0, the write protection is turned on, and writing is prohibited.

[0116] As mentioned above, see return. Figure 5 After obtaining the basic instructions, combined instructions, process variables, and virtual instructions, the determination of the read / write / query process action sequence array also includes decomposing the read / write / query process of the EEPROM chip into read process action sequence arrays, write process action sequence arrays, and query process action sequence arrays, each containing multiple combined instructions.

[0117] That is, based on the EEPROM chip's read process, it is decomposed into an array of read process action sequences containing multiple combined instructions; based on the EEPROM chip's write process, it is decomposed into an array of write process action sequences containing multiple combined instructions; based on the EEPROM chip's query process, it is decomposed into an array of query process action sequences containing multiple combined instructions.

[0118] It should be noted that the read / write / query process of the EEPROM chip is still executed using the original driver timing action of the EEPROM chip, except that each step is implemented by writing multiple instructions into code.

[0119] In some embodiments of this application, in order to obtain the array of read process action sequences, simply relying on combined instructions cannot complete the read process; virtual instructions need to be added according to the read requirements.

[0120] See below for an array of action sequences for reading within a data block: wakeup, start, stop, start, prepwcs, loop, put, nextbit, check, prepaddr, loop, put, nextbit, check, nextbyte, start, preprcs, loop, put, nextbit, check, prepdata, loop, get, nextbit, ack, nextbyte, stop.

[0121] The above read process action sequence array includes combined instructions wakeup, start, stop, put, check, get, and ack, as well as virtual instructions prepwcs, loop, nextbit, prepaddr, nextbyte, and prepdata.

[0122] In some embodiments of this application, in order to obtain the array of write process action sequences, simply relying on combined instructions cannot complete the read process; it is also necessary to add basic instructions, process variables, and virtual instructions according to the write requirements.

[0123] See below for an array of write operation sequences within a data block: wakeup, diswr, start, stop, start, prepwcs, loop, put, nextbit, check, prepaddr, loop, put, nextbit, check, nextbyte, prepdata, loop, put, nextbit, check, nextbyte, stop, enbwr.

[0124] The above-mentioned sequence of actions includes basic instructions diswr and enbwr, combined instructions wakeup, start, stop, put, check, get and ack, and virtual instructions prepwcs, loop, nextbit, prepaddr, nextbyte and prepdata.

[0125] In some embodiments of this application, in order to obtain the query process action sequence array, simply relying on combined instructions cannot complete the reading process; it is also necessary to add basic instructions and virtual instructions according to the query requirements.

[0126] Since the read process is very fast, and the MCU can check whether the read is complete based on the ack in the combined instruction, the read completion action is generally not checked. Therefore, the query action involved in this embodiment is to check whether the write is complete.

[0127] See below for an array of action sequences for checking whether the write process is complete within a data block: wakeup, diswr, start, stop, start, prepwcs, loop, put, nextbit, check, stop, diswr.

[0128] The above query to see if the writing process is complete includes the basic instructions diswr and diswr, combined instructions wakeup, start, stop, put and check, and virtual instructions prepwcs, loop and nextbit.

[0129] In some embodiments of this application, it can be determined whether the read / write operation is complete simply by checking whether the bit_value read in the combined instruction check is equal to 0.

[0130] As mentioned above, the EEPROM read / write / query process can be broken down into multiple instructions, which are simple and clear in logic, easy to understand and maintain, and the instruction classification and management simplifies the design and makes it easier to find problems.

[0131] In some embodiments of this application, the action sequence array of the read / write / query process described above separates the timing of the actions from the timing sequence. The time interval (i.e., the execution speed) of the actions can be changed by adjusting the timing.

[0132] Furthermore, since the action sequence array for the read / write / query process is an externally modifiable array, it is convenient to add actions to the corresponding sequence array according to different chips, or change the order of actions, or increase the number of times actions are executed.

[0133] In some embodiments of this application, after obtaining the above action sequence array, implementation code is written to generate a driver program.

[0134] When writing the code, the code is based on reading and writing data in EEPROM within a data block, without handling cross-block access, and includes the implementation of the following functions: (1) Execution code of all basic instructions, combination instructions and virtual instructions; (2) Process variables are implemented in the stack and defined in the code; (3) Generate chip select word and address data; (4) Implement different read / write / query processes according to the definition of different process action sequence arrays; (5) Execution time control for each step; (6) Exception judgment and alarm; (7) Add watchdog code if necessary.

[0135] Next, write an EEPROM driver program, which is a synchronous and asynchronous read / write program for cross-block read / write, and arbitrary address and arbitrary number of bytes.

[0136] In some embodiments of this application, watchdog code can be embedded in the process action sequence array to avoid device restart problems caused by an action taking too long to execute.

[0137] Some embodiments of this application also relate to an EEPROM chip driver device, see [link to relevant documentation]. Figure 10 It shows a schematic diagram of the hardware structure of an embodiment of an EEPROM chip driver device.

[0138] The EEPROM chip driver includes a processor and a memory, and may also include input and output devices.

[0139] Processors, memory, input devices, and output devices can be connected via a bus or other means. Figure 10 Taking the example of a connection between China and Israel via a bus.

[0140] Memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the EEPROM chip driving method in the embodiments of this application. The processor executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory, thereby implementing the EEPROM chip driving method of the above method embodiments.

[0141] The input device can receive input digital or character information, and generate key signal inputs related to user settings and function control of the EEPROM chip driver. The output device may include display devices such as a display screen.

[0142] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0143] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for driving an EEPROM chip, characterized in that, include: Determine an array of read / write / query process action sequences, which includes: Extract basic timing actions from the original driving timing actions of the EEPROM chip as basic instructions. The basic instructions are single instructions that control the MCU port connected to the serial data line pin SDA, serial clock line pin SCL and write protection pin WP of the EEPROM chip. Multiple basic instructions are combined to form a combined instruction, which appears repeatedly in the driving timing action. Based on the read / write / query process of the EEPROM chip, it is decomposed into an array of read process action sequences, an array of write process action sequences, and an array of query process action sequences, each including multiple combined instructions; Based on different process action sequence arrays, corresponding driver programs are formed to drive the EEPROM chip.

2. The EEPROM chip driving method according to claim 1, characterized in that, The basic instructions include at least: Modify the value of the pin's direction register, set or clear the pin, and read the pin's value.

3. The EEPROM chip driving method according to claim 1, characterized in that, The array of actions for determining the read / write / query process also includes: Set process variables, which are used to record and control the state of the driver execution process; The virtual instructions are set up to form a code segment that combines specific logic and computational tasks during the read / write process.

4. The EEPROM chip driving method according to claim 1, characterized in that, When forming basic instructions and combined instructions, each basic instruction and combined instruction is numbered.

5. The EEPROM chip driving method according to claim 2, characterized in that, The basic instructions include: The first basic instruction is used to set the value of the direction register of the SDA pin, so that the direction register of the SDA pin is an output; The second basic instruction is used to set the value of the direction register of pin SDA, so that the direction register of pin SDA is an input; The third basic instruction is used to set the value of the direction register of the SCL pin, so that the direction register of the SCL pin is an output; The fourth basic instruction is used to set the value of the direction register of the SCL pin, so that the direction register of the SCL pin is an input.

6. The EEPROM chip driving method according to claim 2, characterized in that, The basic instructions also include: The fifth basic instruction is used to enable write protection by setting the write protection pin WP. The sixth basic instruction is used to disable write protection by clearing the write protection pin WP to zero.

7. The EEPROM chip driving method according to claim 2, characterized in that, The basic instructions also include: The seventh basic instruction is used to read the status of the SDA line connected to the SDA pin.

8. The EEPROM chip driving method according to claim 1, characterized in that, The combined instructions include at least: The first set of instructions is used to set the I2C bus start signal; The second set of instructions is used to set the I2C bus stop signal; The third instruction combination is used to send a single data bit. The fourth combination instruction is used to receive a single data bit; The fifth combination instruction is used to check whether the ACK signal is valid when writing data or sending chip select data; The sixth instruction set is used to acknowledge the ACK signal on the I2C bus when reading data, and to send the NACK signal when the last piece of data has been read. The seventh set of instructions is used to establish the normal state of pins SCL, SDA, and WP; The eighth combination instruction is used to set the EEPROM chip to an idle state.

9. The EEPROM chip driving method according to claim 8, characterized in that, The seventh combination of instructions shown is specifically used for: Set pins SCL and SDA as input ports, set the output register output to 0, and disable write protection during write operations. The eighth combined instruction is specifically used for: Set pins SCL and SDA as input ports, set the output of the output register to 0, and enable write protection.

10. An EEPROM chip driver device, characterized in that, include: processor; and The memory stores processor-executable program code that, when executed by the processor, implements the EEPROM chip driving method as described in any one of claims 1 to 9.

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