Heterogeneous many-core resource scheduling method, device, equipment, medium and product

Abstract

The invention relates to the technical field of data flow programming, and discloses a heterogeneous many-core resource scheduling method, device, equipment, medium and product, the method is applied to a host end, the method comprises the following steps: obtaining a target scheduling instruction of a target chip, the target scheduling instruction being obtained through a target programming interface, the target programming interface is used for configuring the number of the computing core arrays in the collaboration group and computing tasks of different computing core arrays in the collaboration group; determining collaboration group information, identification information of different target computing core arrays in a collaboration group and computing task information executed by each target computing core array based on the target scheduling instruction, wherein a plurality of target computing core arrays in the same collaboration group start and execute computing tasks at the same time; generating a target instruction based on the collaboration group information, the identification information of different target computing core arrays in the collaboration group and the computing task information executed by each collaboration group; and sending the target instruction to a target chip of the equipment end for execution.

Description

Technical Field

[0001] This invention relates to the field of dataflow programming technology, specifically to a heterogeneous many-core resource scheduling method, apparatus, equipment, medium, and product. Background Technology

[0002] Currently, Artificial Intelligence (AI) is continuously driving the in-depth development of digitalization and intelligentization, bringing wider applications and more profound technological changes to an increasing number of industries. With the increasing complexity of AI and model structures, and the continuous improvement in training and inference requirements, computing resources are facing unprecedented challenges. AI systems, represented by Large Language Models (LLMs), are experiencing explosive growth in their demand for computing resources, making heterogeneous many-core architectures the mainstream. However, existing mainstream resource scheduling methods have many shortcomings. In related technologies, a single computing core array is used as the primary scheduling object, with slave cores automatically mapped by the compiler. This lacks explicit multi-core scheduling and cooperative control semantics, does not support collaborative execution across multiple slave core arrays, and lacks a unified scheduling mechanism across heterogeneous cores. This makes it difficult to fully unleash the hardware's parallel computing power and cannot meet the dependency control requirements of complex parallel tasks. Summary of the Invention

[0003] This invention provides a heterogeneous many-core resource scheduling method, apparatus, device, medium, and product to solve the problems in related technologies that use a single computing core array as the main scheduling object, do not support collaborative execution of multiple slave core arrays, and lack a unified scheduling mechanism across heterogeneous cores, making it difficult to fully release the hardware parallel computing power and meet the dependency control requirements of complex parallel tasks.

[0004] In a first aspect, the present invention provides a heterogeneous many-core resource scheduling method, applied to a host end, wherein the host end is connected to a device end, and the device end integrates a target chip, the target chip including multiple computing core arrays, each computing core array including multiple computing cores, the method comprising: obtaining target scheduling instructions from the target chip, the target scheduling instructions being obtained through a target programming interface, the target programming interface being used to configure the number of computing core arrays in a collaborative group and the computing tasks of different computing core arrays in the collaborative group; determining collaborative group information, identification information of different target computing core arrays in the collaborative group, and computing task information executed by each target computing core array based on the target scheduling instructions, each collaborative group including multiple target computing core arrays to be scheduled, and multiple target computing core arrays in the same collaborative group simultaneously starting to execute computing tasks; generating target instructions based on collaborative group information, identification information of different target computing core arrays in the collaborative group, and computing task information executed by each collaborative group; and sending the target instructions to the target chip on the device end for execution.

[0005] The heterogeneous many-core resource scheduling method provided by this invention relies on the connection architecture between the host and the device integrating the target chip. Targeting the hardware characteristics of the multi-core arrays contained in the target chip, it obtains target scheduling instructions through a specially designed target programming interface. This interface can explicitly configure the number of core arrays in the cooperative group and the computing tasks of different core arrays, completely changing the passive automatic mapping scheduling mode in related technologies and supplementing the semantic support for explicit multi-core scheduling and cooperative control. Based on this, the host accurately determines the cooperative group information, the identification information of each target core array, and the corresponding computing task information based on the target scheduling instructions, explicitly including multiple core arrays that need to be scheduled into the same cooperative group and ensuring that multiple core arrays within the group start and execute tasks simultaneously, overcoming the limitations of related technologies. This addresses the technical bottleneck of ensuring that multiple computing core arrays can be simultaneously launched and executed, enabling the target chip's multiple computing core arrays to form a collaborative whole, fully releasing the parallel computing power inherent in the hardware. Simultaneously, the host end uniformly integrates the collaboration group, core array identifiers, and task information to generate target instructions and distribute them to the target chip on the device side for execution. This establishes a unified scheduling mechanism across heterogeneous computing core arrays, no longer limited to the scheduling dimension of a single core array. It can accurately adapt to the dependency control requirements of complex parallel tasks, effectively solving the problem that related technologies cannot meet the dependency control requirements of complex parallel tasks. Ultimately, it maximizes the computing power advantages of heterogeneous many-core architecture, adapting to the explosive growth in computing power demand of artificial intelligence systems such as large language models, alleviating the severe challenges to computing resources faced in the current AI development process, and promoting the in-depth development of AI technology in the digitalization and intelligentization of various industries.

[0006] In one optional implementation, the step of generating target instructions based on collaboration group information, identification information of different target computing core arrays in the collaboration group, and task information executed by each target computing core array includes: obtaining synchronization operation instructions of multiple target computing core arrays in the collaboration group based on a pre-built synchronization primitive interface, wherein the synchronization primitive interface is used to configure synchronization control rule information of different target computing core arrays in each collaboration group; and generating target instructions based on the synchronization operation instructions, collaboration group information, identification information of multiple target computing core arrays, and task information executed by each target computing core array.

[0007] In one alternative implementation, a heterogeneous many-core programming model is deployed on the host side. The heterogeneous many-core programming model includes a resource pool, a target programming interface, and a compiler. The resource pool is used to abstract and encapsulate the hardware resources of the target chip.

[0008] In one optional implementation, target instructions are generated based on synchronization operation instructions, cooperation group information, identification information of multiple target computing core arrays, and task information executed by each target computing core array. This includes: generating a computation function based on the synchronization operation instructions, cooperation group information, identification information of multiple target computing core arrays, and task information executed by each target computing core array, wherein the computation function is a carrier for carrying the computation logic of the target computing task; and compiling the computation function using a compiler to obtain the target instructions.

[0009] In one alternative implementation, the synchronization operation instructions include: blocking full synchronization instructions, non-blocking full synchronization instructions, blocking partial core synchronization instructions, and non-blocking partial core synchronization instructions.

[0010] In one optional implementation, after the step of sending the target instruction to the target chip at the device end for execution, the method further includes: obtaining the calculation result output by the target chip; and storing the calculation result in the target database.

[0011] Secondly, the present invention provides a heterogeneous many-core resource scheduling device for executing the method of the first aspect. The device includes: a first acquisition module for acquiring target scheduling instructions for a target chip, the target scheduling instructions being acquired through a target programming interface, the target programming interface being used to configure the number of computing core arrays in a collaborative group and the computing tasks of different computing core arrays in the collaborative group; a first determination module for determining collaborative group information, identification information of different target computing core arrays in the collaborative group, and computing task information executed by each target computing core array based on the target scheduling instructions, wherein each collaborative group includes multiple target computing core arrays that need to be scheduled, and multiple target computing core arrays in the same collaborative group simultaneously start executing computing tasks; a second determination module for generating target instructions based on collaborative group information, identification information of different target computing core arrays in the collaborative group, and computing task information executed by each collaborative group; and a sending module for sending the target instructions to the target chip at the device end for execution.

[0012] Thirdly, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the heterogeneous many-core resource scheduling method of the first aspect or any corresponding embodiment described above.

[0013] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the heterogeneous many-core resource scheduling method of the first aspect or any corresponding embodiment described above.

[0014] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the heterogeneous many-core resource scheduling method of the first aspect or any corresponding embodiment described above. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of an application scenario according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the first process of the heterogeneous many-core resource scheduling method according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the second process of the heterogeneous many-core resource scheduling method according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the implementation process of configuring the number of SPAs in the collaboration group in this embodiment of the invention; Figure 5 This is a structural block diagram of a heterogeneous many-core resource scheduling device according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0019] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0020] As an optional application scenario of this invention, considering the specific application environment architecture or specific hardware architecture upon which the heterogeneous many-core resource scheduling method depends, the specific application environment architecture or specific hardware architecture is described here. For example... Figure 1 As shown, the architecture system may include at least one terminal device and at least one server. Figure 1 The system is illustrated in the example, which includes a computer 101, a mobile terminal 102, and a server 103, and the terminal devices such as the computer 101 and the mobile terminal 102 are connected to the server 103 through a network 110.

[0021] Specifically, the terminal device can be a smartphone, tablet, laptop, PDA, desktop computer, game console, smart TV, smart wearable device, in-vehicle terminal, VR (Virtual Reality) device, AR (Augmented Reality) device, etc. Server 103 can be a standalone physical server, a server cluster, a distributed system, or a cloud server providing cloud services. Network 110 can be a wired or wireless network, examples of which include, but are not limited to, the Internet, corporate intranet, local area network, wide area network, mobile communication network, and combinations thereof.

[0022] Currently, Artificial Intelligence (AI) technology has deeply penetrated many key fields such as speech recognition, image analysis, intelligent manufacturing, financial risk control, and medical diagnosis, becoming a crucial engine for global technological transformation and industrial upgrading. AI technology is continuously driving the in-depth development of digitalization and intelligentization, bringing wider applications and more profound technological changes to an increasing number of industries. However, with the increasing complexity of AI model structures and the continuous improvement in training and inference requirements, computing resources are facing unprecedented challenges. AI systems represented by Large Language Models (LLMs) are experiencing explosive growth in their demand for computing resources, leading to the gradual emergence of a "computing power shortage." The computing power bottleneck has become a core factor restricting the development of AI, affecting the pace of industrial innovation and technological iteration.

[0023] Traditional CPU processing architectures, while highly versatile and flexible in control, suffer from significant shortcomings in computational density and energy efficiency, making it difficult to meet the high parallelism and low latency requirements of AI computing. To address this trend, computing architectures are evolving from traditional single-core or multi-core CPUs towards highly parallel heterogeneous processing architectures. These architectures integrate general-purpose processing cores with control and management functions, along with numerous streamlined slave cores for accelerated computation, all within the same chip. This achieves high computational density and high energy efficiency, providing fundamental support for artificial intelligence and other high-load applications. In related technologies, mainstream heterogeneous computing platforms provide programming models and development frameworks tailored to their own hardware architectures to achieve collaborative scheduling and data interaction between the master core and slave cores. However, these platforms primarily schedule single-core arrays, with slave cores automatically mapped by the compiler. They lack explicit multi-core scheduling and collaborative control semantics, do not support collaborative execution across multiple slave core arrays, and lack a unified scheduling mechanism across heterogeneous cores. This makes it difficult to fully unleash the hardware's parallel computing power and meet the dependency control requirements of complex parallel tasks.

[0024] In view of this, embodiments of this application provide a heterogeneous many-core resource scheduling method applied to a host-side server to achieve the scheduling of heterogeneous many-core resources. The method provided in this application relies on the connection architecture between the host and the device integrating the target chip. Targeting the hardware characteristics of the multi-core arrays contained in the target chip, it obtains target scheduling instructions through a specially designed target programming interface. This interface can explicitly configure the number of computing core arrays in the collaborative group and the computing tasks of different computing core arrays, completely changing the passive automatic mapping scheduling mode in related technologies and supplementing the semantic support for explicit multi-core scheduling and collaborative control. Based on this, the host accurately determines the collaborative group information, the identification information of each target computing core array, and the corresponding computing task information based on the target scheduling instructions, clearly including multiple computing core arrays that need to be scheduled into the same collaborative group and ensuring that multiple computing core arrays within the group start executing tasks simultaneously, overcoming the limitation in related technologies where multiple computing core arrays cannot be guaranteed to be scheduled simultaneously. By overcoming the technical bottleneck of simultaneous execution, the multi-core array of the target chip can form a collaborative whole, fully releasing the parallel computing power inherent in the hardware. Simultaneously, the host end uniformly integrates the collaboration group, core array identifier, and task information to generate target instructions and send them to the target chip on the device side for execution. This establishes a unified scheduling mechanism across heterogeneous computing core arrays, no longer limited to the scheduling dimension of a single core array. It can accurately adapt to the dependency control requirements of complex parallel tasks, effectively solving the problem that related technologies cannot meet the dependency control of complex parallel tasks. Ultimately, it can maximize the computing power advantages of heterogeneous many-core architecture, adapt to the explosive growth of computing power demand of artificial intelligence systems such as large language models, alleviate the severe challenges of computing power resources in the current AI development process, and promote the in-depth development of AI technology in the digitalization and intelligence of various industries.

[0025] According to an embodiment of the present invention, a heterogeneous many-core resource scheduling method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0026] This embodiment provides a heterogeneous many-core resource scheduling method, which can be used on the host side. The host side is connected to the device side, and the device side integrates a target chip. The target chip includes multiple computing core arrays, and each computing core array includes multiple computing cores. Figure 2 This is a flowchart of a heterogeneous many-core resource scheduling method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps: Step S201: Obtain the target scheduling instruction of the target chip. The target scheduling instruction is obtained through the target programming interface. The target programming interface is used to configure the number of computing core arrays in the collaboration group and the computing tasks of different computing core arrays in the collaboration group.

[0027] For example, the target chip refers to the core computing chip integrated on the device side, featuring a heterogeneous many-core architecture. It is the hardware carrier that carries computing tasks in this solution. Its physical structure includes multiple independent Synergistic Processor Element Arrays (SPAs), each containing multiple Synergistic Processor Element Elements (SPEs). Overall, it possesses high parallel computing power, specifically adapted to the computing power requirements of complex parallel tasks such as AI large-scale model training and inference. The target scheduling instruction refers to standardized instructions that guide the target chip in grouping, allocating tasks, and coordinating the execution of computing core arrays. It serves as the host-side instruction carrier for scheduling device-side computing resources. This instruction is not generated out of thin air but is transformed from configuration information input by the developer through the target programming interface. Its core function is to translate the developer's scheduling intent into execution instructions recognizable by the target chip, specifying how many core arrays are in the collaborative group and what tasks each computing core array performs. The target programming interface refers to the standardized programming interface provided to developers for explicitly configuring heterogeneous many-core scheduling logic. It is the core entry point for interaction between developers and the host-side scheduling system. Unlike related technologies where compilers automatically map and lack explicit configuration interfaces, this interface allows developers to directly define scheduling rules, avoiding the limitations of passively relying on the system's automatic scheduling. It is the core technology for implementing explicit multi-core scheduling and collaborative control. The target programming interface can also be used to configure the total number of Spatial Applications (SPAs) that need to be managed. For example, if a total of 10 SPAs need to be managed, and the number of SPAs in the collaborative group is 2, then it is equivalent to starting 2 SPAs simultaneously each time, requiring at most 5 scheduling operations to complete all computational tasks.

[0028] In this embodiment, the user only specifies that n SPAs are used to execute the kernel function in parallel, as shown in the example code below: __global__ void kernel() { printf(“hello\n”) } int main() { / / Other code kernel<<<10, 0, nullptr>>>(); / / Other code } In the example, the user calls the kernel function using the <<<…>>> syntactic sugar, where the first parameter indicates the number of SPAs to be launched, the second parameter is a reserved parameter, and the third parameter is the stream. This example shows that the user needs to execute the kernel function in parallel using 10 SPAs.

[0029] Users configure the collaboration group through the __cluster_dims__ property, specifying the number of SPAs that can be started simultaneously. Example code is as follows: __global____cluster_dims__(2) void kernel() { printf(“hello\n”) } int main() { / / Other code kernel<<<10, 0, nullptr>>>(); / / Other code } In the example, the user configures the number of collaboration groups to 2 through the __cluster_dims__ attribute, which means that when the kernel function starts, 2 SPAs will be started at the same time. The example itself starts a total of 10 SPAs through the <<<…>>> syntax sugar, starting 2 SPAs at a time, and at most 5 schedulings are needed to complete all computation tasks.

[0030] Step S202: Based on the target scheduling instructions, determine the cooperative group information, the identification information of different target computing core arrays in the cooperative group, and the computing task information executed by each target computing core array. Each cooperative group includes multiple target computing core arrays that need to be scheduled. Multiple target computing core arrays in the same cooperative group start executing computing tasks simultaneously.

[0031] For example, the collaboration group information refers to the structured information describing the overall configuration of the collaboration group. It is one of the core contents parsed from the target scheduling instruction. Specifically, it includes the scale information of the collaboration group, the unique number of each collaboration group, the total number of computing core arrays contained in a single collaboration group, and the identification information of different SPAs within the collaboration group. Its function is to clarify the division rules of collaborative units of multiple computing core arrays and provide a logical basis for subsequent synchronous startup and collaborative execution within the group. The identification information of the SPA may include, but is not limited to, the SPA number. In this embodiment, the target scheduling instruction is parsed to extract and clarify three types of key scheduling information: the overall configuration of the collaboration group, the unique identifier of each target computing core array participating in the scheduling, and the specific computing task corresponding to each core array. Each collaboration group must contain multiple target computing core arrays to be scheduled. Multiple core arrays within the same collaboration group start and execute tasks synchronously. This solves the problem that related technologies only support single computing core array scheduling and lack a collaborative execution mechanism, allowing the parallel collaboration of multiple core arrays to change from passive automatic mapping to active and precise control, ensuring that the scheduling logic is consistent with the developer's intention. Figure 1 This provides crucial information support for fully unleashing the parallel computing power of hardware.

[0032] Step S203: Generate target instructions based on the collaboration group information, the identification information of different target computing core arrays in the collaboration group, and the computing task information executed by each collaboration group.

[0033] For example, the host side uses a dedicated instruction generation module (belonging to the compilation toolchain layer of the heterogeneous many-core programming model) to convert collaboration group information, identification information, and task information into executable instructions in binary format according to the instruction set specifications of the target chip. This process simultaneously performs instruction validity verification and instruction optimization to ensure that the generated instructions not only conform to the hardware execution specifications but also adapt to the collaborative execution requirements of the collaboration group. The target instruction refers to the binary instruction package finally generated by the host side, which can be directly read and executed by the target chip on the device side. It is the final carrier for the scheduling intent to be implemented. This instruction package is not a single instruction but contains two core layers: one layer is the scheduling and control instruction, which enables SPA0 and SPA1 in the collaboration group to start and execute the specified tasks simultaneously; the other layer is the computation execution instruction, which can directly drive multiple computing core arrays of the target chip to collaboratively execute tasks according to the collaboration group rules.

[0034] Step S204: Send the target instruction to the target chip on the device side for execution.

[0035] For example, the target instruction is transmitted to the device through a standardized communication link between the host and the device, and is finally delivered precisely to the target chip integrated on the device. After receiving the instruction, the target chip will strictly follow the rules defined in the instruction to drive multiple computing core arrays to collaboratively execute computing tasks.

[0036] The heterogeneous many-core resource scheduling method provided in this embodiment relies on the connection architecture between the host and the device integrating the target chip. Targeting the hardware characteristics of the multi-core arrays contained in the target chip, it obtains target scheduling instructions through a specially designed target programming interface. This interface can explicitly configure the number of computing core arrays in the cooperative group and the computing tasks of different computing core arrays, completely changing the passive automatic mapping scheduling mode in related technologies and supplementing the semantic support for explicit multi-core scheduling and collaborative control. Based on this, the host accurately determines the cooperative group information, the identification information of each target computing core array, and the corresponding computing task information based on the target scheduling instructions, explicitly including multiple computing core arrays that need to be scheduled into the same cooperative group and ensuring that multiple computing core arrays within the group start and execute tasks simultaneously, breaking through the limitations of related technologies. Overcoming the technical bottleneck of not being able to guarantee that multiple computing core arrays can be launched and executed simultaneously, this mechanism enables the target chip's multiple computing core arrays to form a collaborative whole, fully releasing the parallel computing power inherent in the hardware. Simultaneously, the host end uniformly integrates the collaboration group, core array identifiers, and task information to generate target instructions and distribute them to the target chip on the device side for execution. This establishes a unified scheduling mechanism across heterogeneous computing core arrays, no longer limited to the scheduling dimension of a single core array. It can accurately adapt to the dependency control requirements of complex parallel tasks, effectively solving the problem that related technologies cannot meet the dependency control requirements of complex parallel tasks. Ultimately, it can maximize the computing power advantages of heterogeneous many-core architecture, adapt to the explosive growth in computing power demand of artificial intelligence systems such as large language models, alleviate the severe challenges to computing resources faced in the current AI development process, and promote the in-depth development of AI technology in the digitalization and intelligentization of various industries.

[0037] This embodiment provides a heterogeneous many-core resource scheduling method, which can be applied to the host side, where the host side is connected to the device side. The device side integrates a target chip, which includes multiple computing core arrays, and each computing core array includes multiple computing cores. Figure 3 This is a flowchart of a heterogeneous many-core resource scheduling method according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps: Step S301: Obtain the target scheduling instruction for the target chip. The target scheduling instruction is obtained through the target programming interface, which is used to configure the number of computing core arrays in the collaboration group and the computing tasks of different computing core arrays in the collaboration group. For details, please refer to [link to relevant documentation]. Figure 2 Step S201 of the illustrated embodiment will not be described again here.

[0038] In some alternative implementations, a heterogeneous many-core programming model is deployed on the host side. The heterogeneous many-core programming model includes a resource pool, a target programming interface, and a compiler. The resource pool is used to abstract and encapsulate the hardware resources of the target chip.

[0039] Step S302: Based on the target scheduling instructions, determine the cooperative group information, the identification information of different target computing core arrays in the cooperative group, and the computing task information executed by each target computing core array. Each cooperative group includes multiple target computing core arrays that need to be scheduled. Multiple target computing core arrays in the same cooperative group start executing computing tasks simultaneously.

[0040] Step S303: Generate target instructions based on the collaboration group information, the identification information of different target computing core arrays in the collaboration group, and the computing task information executed by each collaboration group.

[0041] Specifically, step S303 includes: Step S3031: Based on the pre-built synchronization primitive interface, obtain the synchronization operation instructions of multiple target computing core arrays in the collaboration group. The synchronization primitive interface is used to configure the synchronization control rule information of different target computing core arrays in each collaboration group.

[0042] For example, the synchronization operation instructions include: blocking full synchronization instructions, non-blocking full synchronization instructions, blocking partial kernel synchronization instructions, and non-blocking partial kernel synchronization instructions. In this embodiment, blocking full synchronization refers to the instruction that performs blocking full synchronization operations between all SPAs within a collaboration group when the number of collaboration groups is configured. Example code for blocking full synchronization is shown below: _global____cluster_dims__(2) void kernel() { / / Get the collaboration group where the current SPA is located cluster_cg cg = this_cluster_cg(); / / Full synchronization within the collaboration group cg.sync(); } int main() { / / Other code kernel<<<10, 0, nullptr>>>(); / / Other code } The example uses the `this_cluster_cg()` function to retrieve the current SPA's collaboration group, and the `sync()` member function of `cluster_cg` completes the synchronization operation for all SPAs within the collaboration group. The relevant interface definitions and functional descriptions are as follows: `cluster_cg this_cluster_cg()` / / Gets the collaboration group where the current block is located; void sync() / / Blocking synchronization of all blocks within a cooperative group.

[0043] In this embodiment, the blocking partial core synchronization instruction refers to an instruction that performs partial SPA blocking synchronization operations within a collaboration group when the number of collaboration groups is configured. An example of the code for the blocking partial core synchronization instruction is as follows: _global____cluster_dims__(4) void kernel() { / / Get the collaboration group where the current SPA is located cluster_cg cg = this_cluster_cg(); / / Specify some SPAs within the collaboration group to perform synchronization operations cg.sync(0b11); } int main() { / / Other code kernel<<<20, 0, nullptr>>>(); / / Other code } The example uses the `this_cluster_cg()` function to obtain the current SPA's collaboration group, and then uses the `sync(unsigned int)` member function of `cluster_cg` to perform synchronization operations on all SPAs within the collaboration group. In this example, the collaboration group contains 4 SPAs, but each synchronization only performs synchronization operations on the two SPAs with logical numbers 0 and 1. The relevant interface definitions and functions are as follows: `void sync(unsigned int) / / Blocking synchronization of a portion of the collaboration group`.

[0044] In this embodiment, the non-blocking fully synchronized instruction refers to performing non-blocking fully synchronized operations between all SPAs within a configured collaboration group. A code example of the non-blocking fully synchronized instruction is as follows: __global____cluster_dims__(4) void kernel() { / / Get the collaboration group where the current SPA is located cluster_cg cg = this_cluster_cg(); / / Non-blocking full synchronization within the collaboration group cg.barrier_arrive(); / / Initiates a hand-raising signal indicating synchronization is ready, without blocking subsequent code logic. … / / Other irrelevant logic code cg.barrier_wait(); / / Perform non-blocking synchronization operation … / / Data processing after synchronization } int main() { / / Other code kernel<<<20, 0, nullptr>>>(); / / Other code } The example uses the `this_cluster_cg()` function to obtain the current SPA's collaboration group, and uses the `barrier_arrive()` and `barrier_wait()` member functions of `cluster_cg` to complete the synchronization operation for all SPAs within the collaboration group. `barrier_arrive()` is a hand-raising operation; when an SPA reaches this interface, it can continue execution until it reaches `barrier_wait()` and then waits. When all SPAs in other collaboration groups have reached `barrier_arrive()` and initiated hand-raising operations, it indicates that the data dependency has been satisfied, and the SPAs in the collaboration group waiting at the `barrier_wait()` interface can continue execution. The relevant interface definitions and functions are as follows: `void barrier_arrive() / / Initiates synchronization ready signal;` void barrier_wait() / / Performs synchronization operations.

[0045] In this embodiment, the non-blocking partial kernel synchronization instruction refers to performing partial SPA non-blocking synchronization operations within a collaboration group when the number of collaboration groups is configured. A code example of the non-blocking partial kernel synchronization instruction is as follows: __global____cluster_dims__(4) void kernel() { / / Get the collaboration group where the current SPA is located cluster_cg cg = this_cluster_cg(); / / Only the first two blocks within the non-blocking synchronous cooperation group / / 3: 0b11 indicates that only the first two blocks within the collaboration group are synchronized. cg.barrier_arrive(3); / / Initiates a hand-raising signal indicating synchronization is ready, without blocking subsequent code logic. … / / Other irrelevant logic code cg.barrier_wait(3); / / Perform non-blocking synchronization operation … / / Data processing after synchronization } int main() { / / Other code kernel<<<20, 0, nullptr>>>(); / / Other code } The example uses the `this_cluster_cg()` function to obtain the current SPA's collaboration group, and uses the `barrier_arrive(unsigned int)` and `barrier_wait(unsigned int)` member functions of `cluster_cg` to complete the synchronization operation between specified SPAs within the collaboration group. `barrier_arrive(unsigned int)` is a hand-raising operation; when an SPA reaches this interface, it can continue execution until it reaches `barrier_wait(unsigned int)` and then waits. When all SPAs in other collaboration groups have reached `barrier_arrive(unsigned int)` and initiated hand-raising operations, it indicates that the data dependency has been satisfied, and the SPAs in the collaboration group waiting at the `barrier_wait(unsigned int)` interface can continue execution. The relevant interface definitions and functions are as follows: void barrier_arrive(unsigned int) / / Raises a hand to initiate a synchronization ready signal; void barrier_wait(unsigned int) / / Performs synchronization operation.

[0046] The number of SPAs in the current collaboration group can be obtained using the following code: __global____cluster_dims__(2) void kernel() { / / Get the collaboration group where the current SPA is located cluster_cg cg = this_cluster_cg(); / / Get the number of SPAs in the current collaboration group unsigned int cnt = cg.num_blocks(); } int main() { / / Other code kernel<<<10, 0, nullptr>>>(); / / Other code } The example uses the `this_cluster_cg()` function to retrieve the collaboration group to which the current SPA belongs, and the `num_blocks()` member function of `cluster_cg` to retrieve the number of SPAs within the current collaboration. The relevant interface definitions and functions are as follows: unsigned int num_blocks() / / Get the number of blocks in the current collaboration group.

[0047] The index of the current SPA within the collaboration group, which is the SPA number, can be determined using the following code: __global____cluster_dims__(4) void kernel() { / / Get the collaboration group where the current SPA is located cluster_cg cg = this_cluster_cg(); / / Get the index of the current SPA within the collaboration group unsigned int num = cg.block_rank (); } int main() { / / Other code kernel<<<20, 0, nullptr>>>(); / / Other code } The example uses the `this_cluster_cg()` function to retrieve the current SPA's collaboration group, and the `block_rank()` member function of `cluster_cg` to retrieve the SPA's index within the collaboration group. Indices start from 0. For example, if the collaboration group size is set to 4, the block index obtained through this interface would be [0, 1, 2, 3]. The relevant interface definitions and functions are as follows: unsigned int block_rank() / / Gets the index of the current block within the cooperative group, starting from 0.

[0048] Step S3032: Generate target instructions based on synchronization operation instructions, cooperation group information, identification information of multiple target computing core arrays, and task information executed by each target computing core array.

[0049] For example, in addition to the original collaboration group information, target computing core array identifier, and array task information, synchronization operation instructions are added. These four types of key information are integrated into a unified, executable target instruction according to the instruction set specification of the target chip. The final generated target instruction not only clarifies how many core arrays are started simultaneously to form a collaboration group and what tasks each performs, but also defines the synchronization execution rules of the core arrays within the collaboration group, ensuring that the target chip can drive the multi-core arrays to execute collaboratively according to explicit synchronization logic.

[0050] In some optional implementations, step S3032 above includes: Step a1: Generate a computation function based on the synchronization operation instructions, collaboration group information, identification information of multiple target computing core arrays, and task information executed by each target computing core array. The computation function serves as the carrier for the computation logic of the target computing task.

[0051] For example, the synchronization operation instructions that guide the collaborative rhythm of multi-core arrays, the collaborative group information that defines the grouping rules, the core array identifier that locates the hardware unit, and the task information that specifies the execution content are all integrated and transformed into a computation function. This computation function is no longer a code snippet that only contains pure computation logic, but a carrier that binds explicit synchronization and collaborative scheduling rules and can fully carry the core logic of the target computation task. It not only specifies the computation content to be executed, but also defines which core arrays execute the computation according to what synchronization rules.

[0052] Step a2: Compile the calculation function using a compiler to obtain the target instructions.

[0053] For example, the compiler not only translates the computational logic in the computation function into machine code that the target chip can recognize, but also verifies the legality of scheduling rules such as synchronization operations, cooperative group configurations, and core array identifiers, and optimizes the task allocation and synchronization logic of the multi-core array. Finally, it generates binary target instructions containing computational execution logic and explicit cooperative scheduling rules, transforming the developer's explicit scheduling intent into instructions that the hardware can directly execute. In this embodiment, the host side can specify the number of SPAs to be launched and the stream configuration through the runtime interface. The device-side kernel function configures the number of SPAs in the cooperative group through the __cluster_dims__ attribute, that is, it can specify how many SPAs can be launched simultaneously. The kernel function refers to the core computation function executed on the processor. The implementation process of the __cluster_dims__ attribute can be as follows: Figure 4 As shown, the specific process is as follows: The compiler first obtains the kernel function and determines whether it has the __cluster_dims__ attribute; if not, it directly generates the device-side binary file; if it does, it generates sdda_info to record the number of SPAs started at the same time during the assembly stage, and then binds the kernel function with sdda_info during the linking stage, finally generating the device-side executable binary file.

[0054] Step S304: The target instruction is sent to the target chip on the device side for execution. For details, please refer to [link to relevant documentation]. Figure 2 Step S204 of the illustrated embodiment will not be described again here.

[0055] Step S305: Obtain the calculation results output by the target chip.

[0056] For example, the computation result is the final data obtained after the target chip performs the task, such as the model inference result, the preprocessed feature array, etc., which is the core output of the computation task.

[0057] Step S306: Store the calculation results in the target database.

[0058] For example, the target database is a pre-specified database system used to store the results of such calculations. It is usually a dedicated database that matches business needs and is used to centrally manage the calculation results and support subsequent queries and analysis.

[0059] The heterogeneous many-core resource scheduling method provided in this application will be specifically described below through a specific embodiment.

[0060] Example: This application proposes an embodiment applicable to a target chip, which includes a main core and several SPAs. Each SPA is composed of several SPEs. Each SPE has independent computing, memory access and control functions and is an independent processor core that can independently complete a computing task.

[0061] The heterogeneous many-core programming model abstracts the underlying heterogeneous computing resources, shielding hardware differences and providing a unified programming interface for upper-layer developers. Through this model, users can simultaneously launch and schedule multiple Spatial Applications (SPAs) within the same application, enabling the scheduling of several SPAs and achieving parallel management and task allocation of heterogeneous many-core resources.

[0062] This method involves both host-side (CPU-side) and device-side kernel functions. The host-side kernel function can specify the number of SPAs to be launched and the stream configuration through the runtime interface. The device-side kernel function configures the number of collaboration groups through the `__cluster_dims__` attribute, allowing the specification of how many SPAs can be launched simultaneously. The heterogeneous many-core programming model under high parallelism completes the logical abstraction of SPAs, providing a set of keywords that allow users to directly obtain the logical number of the SPA, thereby customizing computational tasks for each SPA. Therefore, this programming model can launch SPAs exceeding the hardware's own resources. Simultaneously, this invention also designs a set of synchronization primitive interfaces, enabling unified synchronization control during asynchronous parallel execution of different SPAs. This mechanism ensures task consistency and execution safety in a high-parallelism environment, avoiding resource contention, execution order disorder, and other problems, while providing developers with controllable parallel scheduling capabilities.

[0063] The method provided in this application proposes a general programming model that abstracts underlying heterogeneous computing resources, shields hardware differences, and provides a unified programming interface for upper-layer developers. Through this model, users can simultaneously launch and schedule multiple Spatial Applications (SPAs) within the same application, achieving parallel management and task allocation of heterogeneous many-core resources. Unified abstraction shields heterogeneous hardware differences, reduces development complexity, and improves program portability and reusability. The general programming model proposed in this application introduces a unified abstraction layer between the architecture and the compilation layer, encapsulating underlying heterogeneous hardware resources into programmable logical computing units. Developers only need to describe the parallel computing logic using this abstract interface, without needing to concern themselves with the specific hardware core type, quantity, topology, or communication method. This model automatically completes the mapping and scheduling from high-level semantics to hardware execution units, enabling the same program to maintain consistent behavior on heterogeneous many-core platforms with different chip models or configurations. This unified abstraction mechanism significantly reduces the adaptation and portability costs for developers across multiple hardware platforms, improves program reusability and cross-platform portability, and also provides a unified abstraction basis for automatic optimization by compilers and runtime systems. This application proposes a general programming model that supports the simultaneous scheduling of multiple Spatial Applications (SPAs) through a cooperative group configuration mechanism, fully leveraging the performance potential of heterogeneous many-core architectures. This model allows for the simultaneous launching and scheduling of multiple SPAs within a single chip, achieving multi-array-level concurrent execution and resource coordination. Unlike existing programming models that only support scheduling at the "thread-block-grid" granularity, this model adapts and extends to the "SPA-SPE" two-level structure of heterogeneous many-core architectures, overcoming the limitation of related models being unable to adapt to the "SPA-SPE" two-level structure of domestic heterogeneous many-core architectures. This fully releases the parallel computing potential of the hardware, improving task-level parallelism and overall computational throughput. Furthermore, this invention utilizes synchronization primitives to achieve consistency control between multiple SPAs, ensuring correct dependencies between tasks. The invention designs a unified synchronization primitive mechanism to achieve efficient consistency control between multiple SPAs, ensuring correct dependencies and execution order between parallel tasks. The proposed general programming model provides a complete family of cooperative group interfaces, including: a full array synchronization interface within a cooperative group; a synchronization interface between partial SPAs; a query interface for obtaining the number of SPAs within a cooperative group; and an interface for obtaining the index of the current SPA within the cooperative group. Through these interfaces, programmers can flexibly implement synchronization, cooperation, and task partitioning among multiple arrays at a unified abstraction layer. This supports both global synchronization control and independent task customization for individual SPAs, thus balancing system concurrency performance with ease of programming. Under an asynchronous many-core architecture, it provides controllable scheduling and synchronization mechanisms to ensure the reliability and predictability of parallel execution.

[0064] This embodiment also provides a heterogeneous many-core resource scheduling device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0065] This embodiment provides a heterogeneous many-core resource scheduling device, such as... Figure 5 As shown, it includes: The first acquisition module 501 is used to acquire the target scheduling instructions of the target chip. The target scheduling instructions are acquired through the target programming interface. The target programming interface is used to configure the number of computing core arrays in the collaboration group and the computing tasks of different computing core arrays in the collaboration group. The first determining module 502 is used to determine the cooperative group information, the identification information of different target computing core arrays in the cooperative group, and the computing task information executed by each target computing core array based on the target scheduling instruction. Each cooperative group includes multiple target computing core arrays that need to be scheduled, and multiple target computing core arrays in the same cooperative group start to execute computing tasks at the same time. The second determining module 503 is used to generate target instructions based on the cooperative group information, the identification information of different target computing core arrays in the cooperative group, and the computing task information executed by each cooperative group. The sending module 504 is used to send the target instruction to the target chip on the device side for execution.

[0066] In some alternative implementations, the second determining module 503 includes: The acquisition submodule is used to acquire synchronization operation instructions of multiple target computing core arrays in the collaboration group based on the pre-built synchronization primitive interface. The synchronization primitive interface is used to configure the synchronization control rule information of different target computing core arrays in each collaboration group. The determination submodule is used to generate target instructions based on synchronization operation instructions, cooperation group information, identification information of multiple target computing core arrays, and task information executed by each target computing core array.

[0067] In some alternative implementations, a heterogeneous many-core programming model is deployed on the host side. The heterogeneous many-core programming model includes a resource pool, a target programming interface, and a compiler. The resource pool is used to abstract and encapsulate the hardware resources of the target chip.

[0068] In some alternative implementations, determining the submodule includes: The determination unit is used to generate a calculation function based on the synchronization operation instructions, cooperation group information, identification information of multiple target computing core arrays, and task information executed by each target computing core array. The calculation function is the carrier of the calculation logic of the target computing task. A compilation unit is used by a compiler to compile computation functions into target instructions.

[0069] In some alternative implementations, the synchronization operation instructions include: blocking full synchronization instructions, non-blocking full synchronization instructions, blocking partial core synchronization instructions, and non-blocking partial core synchronization instructions.

[0070] In some alternative embodiments, the above-described apparatus further includes: The second acquisition module is used to acquire the calculation results output by the target chip; The storage module is used to store the calculation results into the target database.

[0071] The heterogeneous many-core resource scheduling device provided in this embodiment of the invention can execute the heterogeneous many-core resource scheduling method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0072] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0073] The following is a detailed reference. Figure 6 This diagram illustrates a suitable structural design for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 601, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 602 or a program loaded from memory 608 into random access memory (RAM) 603. RAM 603 also stores various programs and data required for the operation of the electronic device. The processor 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0074] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0075] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 609, or installed from a memory 608, or installed from a ROM 602. When the computer program is executed by the processor 601, it performs the functions defined in the heterogeneous many-core resource scheduling method of the embodiments of the present invention.

[0076] Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0077] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the heterogeneous many-core resource scheduling method shown in the above embodiments is implemented.

[0078] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0079] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A heterogeneous many-core resource scheduling method, characterized in that, The method is applied to a host device connected to a device that integrates a target chip. The target chip includes multiple computing core arrays, each array including multiple computing cores. The method includes: Obtain the target scheduling instruction of the target chip. The target scheduling instruction is obtained through the target programming interface, which is used to configure the number of computing core arrays in the collaboration group and the computing tasks of different computing core arrays in the collaboration group. Based on the target scheduling instructions, the information of the collaboration group, the identification information of different target computing core arrays in the collaboration group, and the computing task information executed by each target computing core array are determined. Each collaboration group includes multiple target computing core arrays that need to be scheduled. Multiple target computing core arrays in the same collaboration group start executing computing tasks simultaneously. Target instructions are generated based on the information of the collaboration group, the identification information of different target computing core arrays in the collaboration group, and the computing task information executed by each collaboration group. The target instruction is sent to the target chip on the device side for execution.

2. The method according to claim 1, characterized in that, The steps for generating target instructions based on the cooperative group information, the identification information of different target computing core arrays in the cooperative group, and the task information executed by each target computing core array include: Based on a pre-built synchronization primitive interface, synchronization operation instructions for multiple target computing core arrays in a collaborative group are obtained. The synchronization primitive interface is used to configure synchronization control rule information for different target computing core arrays in each collaborative group. The target instruction is generated based on the synchronization operation instruction, the cooperation group information, the identification information of the multiple target computing core arrays, and the task information executed by each target computing core array.

3. The method according to claim 2, characterized in that, The host is equipped with a heterogeneous many-core programming model, which includes a resource pool, the target programming interface, and a compiler. The resource pool is used to abstract and encapsulate the hardware resources of the target chip.

4. The method according to claim 3, characterized in that, The generation of the target instruction based on the synchronization operation instruction, the cooperation group information, the identification information of the multiple target computing core arrays, and the task information executed by each target computing core array includes: A calculation function is generated based on the synchronization operation instruction, the cooperation group information, the identification information of the multiple target computing core arrays, and the task information executed by each target computing core array. The calculation function is the carrier that carries the calculation logic of the target computing task. The computation function is compiled using the compiler to obtain the target instructions.

5. The method according to claim 2, characterized in that, The synchronization operation instructions include: blocking full synchronization instructions, non-blocking full synchronization instructions, blocking partial core synchronization instructions, and non-blocking partial core synchronization instructions.

6. The method according to any one of claims 1 to 5, characterized in that, After the step of sending the target instruction to the target chip on the device for execution, the method further includes: Obtain the calculation results output by the target chip; The calculation results are stored in the target database.

7. A heterogeneous many-core resource scheduling device, characterized in that, The apparatus for performing the method of claim 1, comprising: The first acquisition module is used to acquire the target scheduling instruction of the target chip. The target scheduling instruction is acquired through the target programming interface. The target programming interface is used to configure the number of computing core arrays in the collaboration group and the computing tasks of different computing core arrays in the collaboration group. The first determining module is used to determine the cooperative group information, the identification information of different target computing core arrays in the cooperative group, and the computing task information executed by each target computing core array based on the target scheduling instruction. Each cooperative group includes multiple target computing core arrays that need to be scheduled, and multiple target computing core arrays in the same cooperative group start executing computing tasks simultaneously. The second determining module is used to generate target instructions based on the cooperative group information, the identification information of different target computing core arrays in the cooperative group, and the computing task information executed by each cooperative group. The sending module is used to send the target instruction to the target chip on the device side for execution.

8. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the heterogeneous many-core resource scheduling method according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the heterogeneous many-core resource scheduling method according to any one of claims 1 to 6.

10. A computer program product, characterized in that, It includes computer instructions for causing a computer to execute the heterogeneous many-core resource scheduling method according to any one of claims 1 to 6.

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