Task processing method and device, electronic equipment and storage medium

Abstract

The invention provides a task processing method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method is applied to the electronic equipment, a first processor of the electronic equipment comprises a plurality of computing cores, and the method comprises the steps that under the condition that a shader task is received, shared resources among thread bundles contained in the shader task are determined, and the shared resources are written into a shared storage space of the first processor; distributing each of the thread bundles to one or more target computing cores in the plurality of computing cores; and obtaining the shared resource from the shared storage space through each target computing core when a computing task in the shader task is executed, and performing computing based on the shared resource. The scheme can save a lot of computing core resources and improve the hardware resource utilization rate of the first processor.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more specifically, to a task processing method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the development of computer technology, processors with multi-core parallel computing architectures are widely used in graphics rendering, artificial intelligence inference, scientific computing, and general-purpose parallel computing. Examples of processors with multi-core parallel computing architectures include Graphics Processing Units (GPUs), Tensor Processing Units (TPUs), Neural Network Processing Units (NPUs), and AI accelerators. Internally, the shared data of each thread bundle is stored in shared registers within the computing core unit. This allows threads belonging to the same shader task within the computing core unit to access these shared registers, helping to reduce the register usage of each thread bundle.

[0003] In traditional task processing methods, when the processor is processing hardware instruction streams and distributing shader tasks to each computing core, the GPU front end cannot know in advance how many thread bundles the shader task will generate. Therefore, it is necessary to broadcast to all computing cores in the processor so that each computing core can initialize the shared registers in the thread bundle and complete the initialization of shared data.

[0004] However, in scenarios where the number of threads in a shader task is small, such as when there are few vertices to be rendered or few pixels to be rasterized, the threads in a shader task can only be allocated to one or a few computing cores for execution. In this case, all computing cores initialize shared registers, which causes the multi-core processor to execute a large number of invalid shared tasks, wasting a lot of computing core resources and resulting in low resource utilization of the multi-core processor.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a task processing method, apparatus, electronic device, and storage medium that can save a large amount of computing core resources and improve the resource utilization of the first processor.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0008] According to a first aspect of the present disclosure, a task processing method is provided, applied to an electronic device, wherein a first processor of the electronic device includes a plurality of computing cores, the method comprising: Upon receiving a shader task, determine the shared resources among the thread bundles contained in the shader task, and write the shared resources into the shared memory space of the first processor; Each of the aforementioned thread bundles is distributed to one or more target computing cores from the plurality of computing cores; When each of the target computing cores executes a computing task in the shader task, it obtains the shared resources from the shared storage space and performs computing based on the shared resources.

[0009] In some example embodiments of this disclosure, based on the foregoing scheme, the electronic device further includes a second processor; the step of writing the shared resources into the shared storage space of the first processor includes: The asynchronous sharing task of the shared resource is constructed through the second processor; In response to the execution instruction for the shader task, the asynchronous shared task is sent to the first processor; When the asynchronous shared task is executed by the first processor, the shared resources are written into the shared storage space of the first processor.

[0010] In some example embodiments of this disclosure, based on the foregoing scheme, the step of constructing the asynchronous sharing task of the shared resource through the second processor includes: The second processor creates a global memory write instruction for the shared resource; the global memory write instruction is used to instruct the shared resource to be written to the shared storage space of the first processor. An asynchronous shared task for the shared resource is constructed based on the global memory write instruction.

[0011] In some example embodiments of this disclosure, based on the foregoing scheme, when the asynchronous shared task is executed by the first processor, writing the shared resources into the shared storage space of the first processor includes: When the asynchronous shared task is executed through the shared computing core in the first processor, the shared resources are written into the shared storage space of the first processor; the shared computing core is a computing core that is different from the target computing core among the plurality of computing cores.

[0012] In some example embodiments of this disclosure, based on the foregoing scheme, the second processor runs a GPU driver, and the method further includes: The GPU driver generates synchronization instructions between the computing task and the corresponding asynchronous shared task, and sends the synchronization instructions to the first processor. The first processor executes the corresponding computation task after the asynchronous shared task is completed, based on the synchronous instructions.

[0013] In some example embodiments of this disclosure, based on the foregoing scheme, the step of obtaining the shared resources from the shared storage space when each of the target computing cores executes the computing tasks in the shader task includes: A preset register read instruction is determined from the computation task of the shader task; the register read instruction is the instruction of the computation task to read shared data from a shared register; The register read instruction is converted into a global memory read instruction for the shared storage space to obtain the updated computation task; When each of the target computing cores executes the updated computing task, it retrieves the shared resources from the shared storage space according to the global memory read instruction.

[0014] In some example embodiments of this disclosure, based on the foregoing scheme, the calculation based on the shared resources includes: For each target computing core, the shared resources are loaded into the cache of the target computing core; The shared resources in the cache are obtained from the computing units in the target computing core for computation.

[0015] In some example embodiments of this disclosure, based on the foregoing scheme, the electronic device further includes a second processor running a GPU driver and a GPU compiler. The step of determining the shared resources among the thread bundles contained in the shader task upon receiving a shader task includes: Upon receiving a shader task, the compilation request is sent to the GPU compiler via the user-space driver in the GPU driver; the compilation request includes the binary file of the shader task. The GPU compiler analyzes the binary file of the shader task to determine the shared resources among the thread bundles contained in the shader task.

[0016] According to a second aspect of the present disclosure, a task processing method is provided, applied to a second processor of an electronic device, the method comprising: Upon receiving a shader task, determine the shared resources among the thread bundles contained in the shader task, and construct an asynchronous shared task for the shared resources; The asynchronous sharing task is sent to the first processor; the asynchronous sharing task is used by the first processor to write the shared resources into the shared storage space of the first processor; Each of the thread bundles is distributed to one or more target computing cores of the first processor; the thread bundles are used by each of the target computing cores to obtain the shared resources from the shared storage space and perform calculations based on the shared resources when executing the computing tasks in the shader tasks.

[0017] According to a third aspect of the present disclosure, a task processing method is provided, applied to a first processor of an electronic device, the first processor including a plurality of target computing cores, the method comprising: In response to a received asynchronous shared task, the asynchronous shared task is executed, and the shared resources among the thread bundles contained in the shader task are written into the shared memory space of the first processor; the shared resources are determined by the second processor upon receiving the shader task. Each of the thread bundles received by each of the target computing cores obtains the shared resources from the shared storage space when executing the computing task corresponding to the thread bundle, and performs computing based on the shared resources.

[0018] According to a fourth aspect of the present disclosure, a task processing apparatus is provided, applied to an electronic device, wherein a first processor of the electronic device includes a plurality of computing cores, and the apparatus includes: A shared resource writing module is used to determine the shared resources among the thread bundles contained in the shader task when a shader task is received, and to write the shared resources into the shared memory space of the first processor. The thread bundle distribution module is used to distribute each of the thread bundles to one or more target computing cores among the plurality of computing cores; The computation task execution module is used to obtain the shared resources from the shared storage space and perform computations based on the shared resources when each of the target computation cores executes the computation tasks in the shader task.

[0019] According to a fifth aspect of the present disclosure, a task processing apparatus is provided, which is applied to a second processor of an electronic device, the apparatus comprising: An asynchronous shared task construction module is used to determine the shared resources among the thread bundles contained in the shader task when a shader task is received, and to construct an asynchronous shared task for the shared resources. A sending module is used to send the asynchronous shared task to a first processor; the asynchronous shared task is used by the first processor to write the shared resource into the shared storage space of the first processor; A thread beam distribution module is used to distribute each of the thread beams to one or more target computing cores of the first processor; the thread beams are used by each of the target computing cores to obtain the shared resources from the shared storage space and perform calculations based on the shared resources when executing the computing tasks in the shader tasks.

[0020] According to a sixth aspect of the present disclosure, a task processing apparatus is provided, which includes a first processor applied to an electronic device, the first processor including a plurality of target computing cores, the apparatus comprising: A shared resource writing module is used to respond to a received asynchronous shared task, execute the asynchronous shared task, and write the shared resources between the thread bundles contained in the shader task into the shared storage space of the first processor; the shared resources are determined by the second processor upon receiving the shader task; The computation task execution module is used to obtain the shared resources from the shared storage space and perform computation based on the shared resources when executing the computation task corresponding to the thread bundle received by each of the target computation cores.

[0021] According to a seventh aspect of the present disclosure, an electronic device is provided, comprising: a first processor; a second processor; and a memory storing computer-readable instructions that, when executed by the electronic device, implement the task processing method as described in the first aspect.

[0022] According to an eighth aspect of the present disclosure, a second processor is provided, wherein the first processor is configured to perform the task processing method as described in the second aspect.

[0023] According to a ninth aspect of the present disclosure, a first processor is provided, the first processor being configured to perform a task processing method as described in the third aspect.

[0024] According to a tenth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by an electronic device, implements the task processing method as described in the first aspect.

[0025] The technical solutions provided in this disclosure may have the following beneficial effects: In the task processing method of the example embodiments of this disclosure, when an electronic device receives a shader task, it determines the shared resources among the thread bundles included in the shader task and writes the shared resources into the shared memory space of the first processor. Then, the thread bundles are distributed to one or more target computing cores among multiple computing cores. The one or more target computing cores can obtain the shared resources from the shared memory space when executing the computing tasks in the shader task, and perform calculations based on the shared resources. That is, the shared resources are read from the shared memory space by the one or more target computing cores that actually undertake the computing tasks, without all computing cores in the first processor having to perform redundant shared initialization operations, which can save a lot of computing core resources and improve the resource utilization of the first processor.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0028] Figure 1 The schematic diagram illustrates a flowchart of a task processing method according to some embodiments of the present disclosure.

[0029] Figure 2 The illustration schematically shows a process diagram of writing shared resources into a shared storage space according to some embodiments of the present disclosure.

[0030] Figure 3 The illustration schematically shows the execution relationship between asynchronous shared tasks and computing tasks according to some embodiments of the present disclosure.

[0031] Figure 4 The illustration shows a flowchart of the steps for obtaining shared resources from a shared storage space according to some embodiments of the present disclosure.

[0032] Figure 5 A schematic flowchart of a task processing method according to other embodiments of the present disclosure is shown.

[0033] Figure 6 A schematic flowchart of a task processing method according to other embodiments of the present disclosure is shown.

[0034] Figure 7A schematic diagram of a task processing apparatus according to some embodiments of the present disclosure is shown.

[0035] Figure 8 A schematic diagram of a task processing apparatus according to other embodiments of the present disclosure is shown.

[0036] Figure 9 A schematic diagram of a task processing apparatus according to other embodiments of the present disclosure is shown.

[0037] Figure 10 An architectural diagram of a task processing system according to some embodiments of the present disclosure is illustrated.

[0038] Figure 11 The schematic diagram illustrates the structural schematic of a computer system of an electronic device according to some embodiments of the present disclosure.

[0039] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0040] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0041] Furthermore, the accompanying drawings are for illustrative purposes only and are not necessarily drawn to scale. The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0042] In this example embodiment, a task processing method is first provided, which can be applied to an electronic device, including a first processor and a second processor. The first processor refers to dedicated or general-purpose graphics / computing acceleration hardware with parallel computing capabilities, a multi-core architecture, a shared memory subsystem, and a task scheduling and execution pipeline, such as a graphics processing unit (GPU), tensor processor, neural network processor, or AI accelerator. The second processor is the main control processor, such as a central processing unit (CPU), used to run modules such as the operating system, GPU driver, and GPU compiler.

[0043] For example, the first processor can be the GPU hardware itself, while the second processor runs a GPU driver and a GPU compiler. The first processor and the GPU driver and GPU compiler on the second processor work together to form a complete heterogeneous computing system. The GPU driver is used to manage resource allocation, task submission, and hardware interaction; the GPU compiler is used to perform static analysis, instruction generation, and task refactoring of shader tasks.

[0044] For example, electronic devices can be built into or connected to various devices with graphics rendering or general-purpose parallel computing capabilities, including but not limited to: desktop computers, laptops, servers, workstations, game consoles, mobile terminals (such as smartphones and tablets), embedded computing platforms (such as smart cameras, industrial control terminals, in-vehicle infotainment systems, and autonomous driving domain controllers), artificial intelligence acceleration devices, data center acceleration cards, edge computing nodes, and heterogeneous computing systems that support graphics and computing APIs (Application Programming Interfaces) such as Vulkan, DirectX, Metal, OpenCL, or CUDA.

[0045] The aforementioned electronic devices can run operating systems that support collaborative task scheduling and shared memory management between the first and second processors, including but not limited to: Windows, Linux (including various distributions and real-time variants such as PREEMPT_RT), Android (based on the Linux kernel and integrating the GPU HAL layer), iOS / macOS (based on the XNU kernel and supporting the Metal framework), QNX, FreeRTOS (with GPU middleware), Zephyr, HarmonyOS, and customized embedded or real-time operating systems (RTOS) that support UEFI GPU initialization, DRM / KMS (Direct Rendering Manager / Kernel Mode Setting) subsystems, or dedicated GPU firmware interfaces. In these systems, the task processing method disclosed herein can improve the resource utilization of the first processor.

[0046] Figure 1 A schematic diagram illustrating a task processing flow according to some embodiments of the present disclosure is provided. References Figure 1 As shown, the task processing method may include the following steps: Step S110: Upon receiving a shader task, determine the shared resources among the thread bundles contained in the shader task, and write the shared resources into the shared memory space of the first processor. Step S120: Distribute each thread bundle to one or more target computing cores from multiple computing cores; In step S130, each target computing core obtains shared resources from the shared storage space when executing computing tasks in the shader task, and performs computing based on the shared resources.

[0047] According to the task processing method in this example embodiment, upon receiving a shader task, the shared resources among the thread bundles contained in the shader task are determined, and the shared resources are written into the shared memory space of the first processor. Then, each thread bundle is distributed to one or more target computing cores among multiple computing cores. When executing the computing tasks in the shader task, the one or more target computing cores can obtain the shared resources from the shared memory space and perform calculations based on the shared resources. That is, the shared resources are read from the shared memory space by the one or more target computing cores that actually undertake the computing tasks, without all computing cores in the first processor having to perform redundant shared initialization operations. This can save a lot of computing core resources and improve the resource utilization of the first processor.

[0048] The task processing method in this example embodiment will be further explained below, taking the first processor as the GPU hardware.

[0049] In step S110, upon receiving a shader task, the shared resources among the thread bundles contained in the shader task are determined, and the shared resources are written into the shared memory space of the first processor.

[0050] A shader is a program that runs on a graphics processing unit (GPU) and instructs the GPU on how to process graphics or compute data. A shader task is a running instance of a shader program that executes on the GPU. It can consist of one or more thread blocks, each of which can contain one or more thread bundles that execute the same shader logic on a specified dataset.

[0051] The shader task can contain a shader program (such as a vertex shader, fragment shader, compute shader, or OpenCL / CUDA kernel function) and its associated execution configuration parameters (such as the number of thread blocks, workgroup size, constant data, etc.) to trigger the first processor to process the specified dataset in parallel.

[0052] In some embodiments, when a shader task is received from an application, the shared resources among the thread bundles contained in the shader task can be determined.

[0053] For example, the application can be a 3D game engine that, when rendering a scene, can submit a shader task for calculating pixel colors to a second processor of an electronic device through a graphics interface. Upon receiving the shader task, the second processor determines the shared resources among the thread bundles contained in the shader task.

[0054] For example, the application could be a video editing tool that, when performing image filter processing, can initiate a computational shader task for parallel processing of image data through a computing interface and distribute the shader task to a second processor of the electronic device.

[0055] A thread bundle is the smallest scheduling and execution unit in a graphics processing unit (GPU) hardware. It can consist of one or more threads that can execute the same instructions synchronously within the same computing core using a Single Instruction Multiple Thread (SIMT) architecture, but each thread operates on different data. For example, a thread bundle can contain 32 or 64 threads, the specific number of which can be determined by the first processor architecture.

[0056] Shared resources refer to data that is accessed by multiple threads within a shader task and whose content remains consistent. Shared resources can include, but are not limited to, uniform transformation matrices, lighting parameters, texture sampling offsets, fragment data in constant buffers, or intermediate computation results that are reused across threads and identified by the compiler.

[0057] In some embodiments, the second processor of the electronic device runs a GPU compiler, which can determine the shared resources among the thread bundles contained in the shader task based on the shader task issued by the application.

[0058] Specifically, the electronic device also includes a second processor, which runs a GPU driver and a GPU compiler. Upon receiving a compilation request for a shader task, the second processor sends the compilation request to the GPU compiler through the user-mode driver in the GPU driver. The compilation request includes the binary file of the shader task. The GPU compiler analyzes the binary file of the shader task to determine the shared resources between the thread bundles contained in the shader task.

[0059] A compilation request is a request used to compile shader tasks. This compilation request can be received from the application via the User-Mode Driver (UMD) in the GPU driver. The User-Mode Driver is a graphics processor driver component running in the operating system's user space. Its main responsibility is to receive graphics or computing API calls from the application, perform high-level processing such as command construction, resource management, state tracking, and shader compilation, and submit the processing results to the kernel-mode driver for final scheduling by the primary processor.

[0060] Specifically, the binary file of the shader task is compiled using a GPU compiler to obtain the compiled shader task; the compiled shader task is then analyzed to determine the shared resources among the thread bundles contained in the shader task.

[0061] In some implementations, the GPU compiler can perform static program analysis on the compiled shader task, including data flow analysis, control flow graph construction, constant propagation, and invariant detection, to identify shared resources in each thread bundle contained in the shader task that meet preset conditions. These preset conditions can be set as needed.

[0062] In other implementations, the GPU compiler can combine the thread organization information of the shader tasks (such as the workgroup size local_size_x / y / z) during the analysis process to infer the division method and access mode of the thread bundles, thereby more accurately defining the shared boundaries and avoiding misjudging data used only by some thread bundles as shared resources.

[0063] In some other embodiments, the GPU compiler can also embed the identified shared resource information as metadata into the final generated executable instruction stream for use in subsequent steps (such as asynchronous shared task construction or resource writing) without modifying the original shader logic.

[0064] Understandably, by working together with the GPU compiler, the accurate identification of shared resources can be completed during the compilation phase, thus providing a reliable basis for the subsequent automated implementation of resource sharing mechanisms.

[0065] In other embodiments, the GPU driver can also dynamically extract shared resources between thread bundles at runtime based on shader reflection information, which can be applied to scenarios such as Just-In-Time Compilation (JIT) or delayed resource binding.

[0066] In other embodiments, other methods can be used to determine shared resources between thread bundles, such as dynamically identifying shared resources during the instruction stream parsing stage by the GPU front-end task analysis unit, or automatically labeling shared data using the GPU's hardware metadata tagging mechanism, etc., and are not limited to these.

[0067] Shared memory refers to a global memory buffer located within the graphics processor's global memory space, used to hold shared data. It's important to note that this shared memory space belongs to the globally addressable memory region, not the on-chip shared memory integrated into the GPU's internal computing units. For example, shared memory could be shared video memory.

[0068] In some embodiments, shared resources can be written to a pre-allocated buffer in the shared storage space. The location and size of the pre-allocated buffer can be set as needed and are not limited here.

[0069] In some embodiments, shared resources can be written into a shared storage space through one or more shared computing cores of the first processor.

[0070] In other embodiments, if the shared resources originate from constant data on the host (e.g., parameters passed via a Uniform Buffer Object (UBO)), the GPU driver can write the shared resources to the shared storage space area via the Direct Memory Access (DMA) engine during the task submission phase, without occupying any computing core execution resources.

[0071] Step S120: Distribute each thread bundle to one or more target computing cores from multiple computing cores.

[0072] The target computing core refers to the physical computing unit in the first processor that is actually allocated to execute some or all of the thread bundles in the shader task. Each target computing core can independently manage its internal thread scheduling, register file and on-chip storage resources.

[0073] In some embodiments, one or more target computing cores can be determined from the first processor, and thread bundles can be distributed to each target computing core. The target computing cores can be in a high-power state, while other computing cores in the first processor can be in a low-power state. That is, the power consumption of the target computing cores is higher than that of the other computing cores, which can ensure the processing efficiency of the target computing cores while reducing the power consumption of the other computing cores.

[0074] One or more target computing cores can be identified from the first processor by a second processor (such as a GPU driver running on the second processor), and thread bundles can be distributed to each target computing core.

[0075] In some implementations, a second processor (such as a GPU driver running on the second processor) can determine the number of thread bundles included in a shader task. If the number of thread bundles is less than or equal to the number of thread bundles that a computing core can accommodate, then the thread bundles are distributed to one computing core in the first processor, which is designated as the target computing core. If the number of thread bundles is greater than the number of thread bundles that a computing core can accommodate, then the thread bundles are distributed to at least two computing cores in the first processor, which are designated as the target computing cores.

[0076] In other implementations, a second processor (such as a GPU driver running on the second processor) can randomly select one or more computing cores from the computing cores in the first processor as the target computing core.

[0077] In other implementations, other methods can be used to determine the target computing core. For example, a second processor (such as a GPU driver running on the second processor) can select a computing core with a preset weight higher than a weight threshold or a preset confidence level higher than a confidence level threshold as the target computing core. This is not limited here.

[0078] For example, if a shader task contains 8 thread bundles, and each compute core can schedule 32 thread blocks simultaneously, then the 8 thread bundles are distributed to one compute core in the first processor. This compute core is the target compute core, and other compute cores do not need to participate in task execution or perform shared data initialization.

[0079] In other embodiments, after receiving the shader task, the dynamic scheduler of the first processor can combine the access patterns of shared resources with the dependencies between thread bundles to allocate each thread bundle to one or more target computing cores in a fine-grained manner. For example, if multiple thread bundles access the same shared resource and there is no data contention, they can be centrally scheduled to the same target computing core to improve cache locality; if there are parallelism requirements among the thread bundles, they can be distributed to multiple different target computing cores to improve throughput.

[0080] In some other embodiments, for a first processor architecture that supports fine-grained power gating of computing cores, computing cores other than the target computing core can be in a low-power state during task execution, that is, the clock can be completely turned off or the power supply can be cut off, thereby maximizing energy efficiency.

[0081] In step S130, each target computing core obtains shared resources from the shared storage space when executing computing tasks in the shader task, and performs computing based on the shared resources.

[0082] In this context, a computational task refers to the specific parallel computational work performed by a target computing core on its allocated thread bundle. This computational task is a local execution instance of the shader task on a single computing core.

[0083] For example, computational tasks may include loading input data from shared memory, performing arithmetic and logical operations defined by shader programs, and writing the computation results back to the output buffer.

[0084] It is understandable that shader tasks can include asynchronous shared tasks and computation tasks. Asynchronous shared tasks are used to write shared resources into shared memory. A shader task can contain one or more computation tasks, which can run on the same target compute core or different target compute cores, working together to complete the overall computation goal.

[0085] Once the thread bundles of a shader task are distributed to one or more target compute cores, each target compute core is responsible for executing the one or more thread bundles it receives. The computational operations carried out by these thread bundles, such as vertex coordinate transformation, pixel color interpolation, image filtering, matrix multiplication and addition, etc., constitute the computational tasks on that target compute core.

[0086] In some embodiments, each target computing core reads shared resources from the shared storage space according to global memory read instructions before the thread bundle begins executing the main computing logic. It is understood that since the shared resources have already been initialized and written to the shared storage space before task execution, each target computing core does not need to repeat the local initialization operation and can simply read them as needed.

[0087] In other embodiments, the shared resources can be cache-line aligned (e.g., aligned to 128-byte boundaries) in the storage layout of the shared memory space to improve memory bandwidth efficiency when multiple target compute cores access the same resource concurrently. When multiple target compute cores read the same shared resource simultaneously, the GPU's L1 / L2 cache subsystem can automatically cache the data of the shared resource, further reducing global memory space access latency.

[0088] Understandably, by obtaining shared resources from a unified shared storage space, each target computing core can significantly reduce redundant data loading and initialization overhead while ensuring computational correctness. Especially in light-load scenarios where shader tasks involve fewer thread bundles, this effectively avoids the resource waste caused by the need for independent initialization of each computing core in traditional solutions, thereby improving the overall energy efficiency and hardware utilization of the first processor.

[0089] The contents of steps S110 to S130 will be described in detail below.

[0090] In one example embodiment of this disclosure, the electronic device further includes a second processor, such as Figure 2 As shown, the step S110 of writing shared resources into the shared memory space of the first processor can be achieved through the following steps, specifically including steps S210 to S230: Step S210: Construct an asynchronous shared task for shared resources using the second processor.

[0091] In this context, an asynchronous shared task refers to a task that writes shared resources into shared storage space, independent of the computational task itself. This means that the asynchronous shared task can be responsible for preparing shared resources without participating in actual graphics rendering or general-purpose computation.

[0092] In some embodiments, constructing an asynchronous shared task of shared resources using a second processor includes: creating a global memory write instruction for the shared resources using the second processor; the global memory write instruction is used to instruct the shared resources to be written to the shared storage space of the first processor; and constructing an asynchronous shared task of shared resources based on the global memory write instruction.

[0093] A global memory write instruction refers to a single instruction or a set of low-level operation instructions conforming to the instruction set architecture of the first processor, which can be used to write shared resources to shared memory space. This global memory write instruction may include the target address of the shared memory space, the data length of the shared resource, and memory access semantics (such as local device write), and can be directly parsed and executed by the first processor.

[0094] Specifically, the second processor runs a GPU driver and a GPU compiler. After determining the shared resources between each thread bundle, the GPU compiler creates global memory write instructions for the shared resources and constructs asynchronous shared tasks for the shared resources based on the global memory write instructions. The GPU compiler sends the asynchronous shared task to the GPU driver, which can then send the asynchronous shared task to the first processor in response to the execution instructions for the shader task.

[0095] In some implementations, the GPU compiler can automatically generate corresponding global memory write instructions based on shared resources during the compilation of shader programs. The binary code of these global memory write instructions can then be directly used as an asynchronous shared task. This process occurs during the offline shader compilation phase or the runtime just-in-time (JIT) compilation phase, without application intervention.

[0096] In other implementations, the GPU compiler can organize global memory write instructions into a separate instruction sequence and attach necessary metadata (such as task dependency flags, memory alignment requirements, and synchronization signals) to encapsulate it into a complete asynchronous shared task.

[0097] In other implementations, asynchronous shared tasks can include write logic to shared resources, thus having extremely low instruction overhead and deterministic execution latency, making them suitable for efficient processing by the GPU's lightweight execution unit or DMA engine.

[0098] Understandably, by creating global memory write instructions through a second processor and using them to construct asynchronous shared tasks, the automatic generation of shared resource initialization logic and hardware readiness assurance can be achieved. This not only ensures the correctness and efficiency of write operations, but also provides compilation support for decoupling computational tasks and resource sharing operations, further improving the overall task scheduling flexibility and execution performance.

[0099] In step S220, in response to the execution instruction for the shader task, the asynchronous shared task is sent to the first processor.

[0100] In step S230, when the asynchronous shared task is executed by the first processor, the shared resources are written into the shared storage space of the first processor.

[0101] Among them, the execution instructions for shader tasks refer to the task submission requests initiated by the application through the graphics or general computing application programming interface, such as calling vkQueueSubmit in Vulkan, ExecuteCommandLists in DirectX 12, or cudaLaunchKernel in CUDA, which are used to trigger the first processor to schedule and execute the shader tasks.

[0102] In some embodiments, the GPU driver receives the execution instructions for the shader task issued by the application, and in response to the execution instructions, sends the asynchronous shared task to the first processor.

[0103] In other embodiments, the GPU driver receives the execution instructions for the shader tasks issued by the application. In response to these instructions, the asynchronous shared tasks and the computational tasks within the shader tasks are respectively dispatched to the first processor, whereby the first processor executes the asynchronous shared tasks and the computational tasks. The asynchronous shared tasks and computational tasks can be dispatched simultaneously or separately at different times. It is understood that dispatching the computational tasks within the shader tasks to the first processor means distributing the thread bundles contained in the shader tasks to one or more target computing cores of the first processor.

[0104] When the GPU driver receives the above execution instructions, it can simultaneously encapsulate the associated asynchronous shared tasks into a command stream. This command stream is organized according to the instruction format of the first processor and submitted to the command processor of the first processor through the Kernel Mode Driver (KMD).

[0105] Understandably, by introducing a second processor to construct an asynchronous shared task for shared resources, and then sending this asynchronous shared task to the first processor after receiving the execution instruction of the shader task, the write operation of the shared resources is decoupled from the computation task. When the first processor executes this asynchronous shared task, it can pre-write the shared resources into its shared memory space. In this way, each target computing core can directly read the pre-set shared resources from the shared memory space when executing subsequent computation tasks, without needing to load them synchronously during the computation process or have them repeatedly initialized by multiple computing cores. That is, by having the second processor uniformly plan and trigger the pre-set process of shared resources, the bandwidth contention and computational delays caused by repeated data loading during the task execution phase of the first processor are avoided. This not only improves the efficiency of resource sharing but also further reduces the redundancy overhead of the first processor, thereby improving the overall parallel efficiency and resource utilization of task processing.

[0106] Furthermore, in some embodiments, when executing an asynchronous shared task through the first processor, writing shared resources into the shared storage space of the first processor includes: when executing an asynchronous shared task through a shared computing core in the first processor, writing shared resources into the shared storage space of the first processor; the shared computing core is a computing core among multiple computing cores that is different from the target computing core.

[0107] In this context, the shared computing core refers to the computing core in the first processor used to execute asynchronous shared tasks. When executing asynchronous shared tasks, the shared computing core may include writing shared resources to shared memory space, as well as other related operations such as resource initialization.

[0108] Understandably, a shared computing core is a computing core that differs from the target computing core among multiple computing cores. The shared computing core and the target computing core are physically separated, for example, integrated into the GPU's command front-end, DMA controller bypass path, or dedicated coprocessor subsystem. This architectural design completely decouples resource sharing operations from the main computing logic (computing tasks) at the hardware level, avoiding the occupation of the main computing core's register files, caches, or scheduling slots due to resource initialization.

[0109] In other embodiments, the shared computing core is a lightweight processing unit that supports a general instruction set. It can parse and execute global memory write instructions issued by the second processor to write shared resources into the shared storage space of the first processor in accordance with the global memory write instructions.

[0110] When the first processor receives an asynchronous shared task, it can send the asynchronous shared task to the shared computing core; when the first processor receives a computing task, it can send the computing task to one or more target computing cores.

[0111] In other embodiments, when executing asynchronous shared tasks, the shared computing core can directly access host memory or a constant buffer to obtain shared resources, and efficiently transfer the shared resources to a pre-allocated area in the shared storage space in a batch write manner. The entire process does not require the participation of the target computing core, nor does it trigger its activation or context switching, thereby significantly reducing power consumption and latency in light-load scenarios.

[0112] Understandably, by introducing a shared computing core different from the target computing core to execute asynchronous shared tasks, hardware-level isolation between the resource sharing path and the main computing path can be achieved. This not only ensures the timeliness and reliability of shared resource writes but also further frees up the computing power of the target computing core, allowing it to focus on core graphics or general computing tasks, thereby improving the resource utilization efficiency and energy efficiency of the primary processor.

[0113] In other embodiments, the second processor runs a GPU driver, and the method further includes: generating synchronization instructions between the computing task and the corresponding asynchronous shared task through the GPU driver, and sending the synchronization instructions to the first processor; and executing the corresponding computing task by the first processor based on the synchronization instructions after the asynchronous shared task has been completed.

[0114] Synchronization instructions are hardware-recognizable control signals or commands used to establish execution order dependencies between asynchronous shared tasks and computational tasks. Their function is to ensure that the asynchronous shared task has successfully written the shared resource into the shared memory space before the computational task accesses it. Synchronization instructions may include, but are not limited to, fences, event signals, memory barriers, or task dependency tags.

[0115] In some embodiments, shared computing cores and target computing cores process in parallel, and for the same shader task, the corresponding computing task is executed after the asynchronous shared task in the shader task has been completed.

[0116] It is understandable that the shared computing core and each target computing core process in parallel. That is, after the shared computing core executes the asynchronous shared task of the current shader task, the target computing core executes the corresponding computing task. At the same time, after the shared computing core completes the current asynchronous shared task, it can continue to execute the asynchronous shared task of the next shader task without waiting for the target computing core to complete the current computing task, thus completing the shader task more quickly.

[0117] In some embodiments, when constructing the command stream, the first processor may insert a synchronization instruction between the asynchronous shared task and the computation task. This synchronization instruction includes a synchronization object identifier. During execution, the first processor's command processor first executes the asynchronous shared task, and then executes the computation task once the completion of the asynchronous shared task is detected.

[0118] In other embodiments, the synchronization mechanism can be implemented using status flags in the shared memory space. Specifically, after the asynchronous shared task completes writing the shared resources into the shared memory space, it writes a completion flag to a preset address; the computation task polls or waits for this completion flag before starting, ensuring that the data is ready before continuing execution. This method can be automatically injected with the necessary waiting logic by the first processor (such as a GPU driver running on the second processor) when generating the asynchronous shared task and the computation task, and encapsulated in the synchronization instructions.

[0119] In some other embodiments, the first processor may have a dedicated synchronization management unit for parsing synchronization instructions and coordinating the execution order between asynchronous shared tasks and computational tasks. For example, asynchronous shared tasks may be submitted to a task queue first, followed by computational tasks, with both linked by the same synchronization instruction. The first processor then ensures that the task queue executes asynchronous shared tasks before computational tasks.

[0120] Understandably, by generating and issuing synchronization instructions through the first processor, strict timing consistency between writing to shared resources and reading from computational tasks can be ensured without application intervention. This mechanism avoids computational errors caused by incomplete data and prevents performance losses from overly conservative global synchronization, thus maintaining high parallel efficiency while ensuring correctness. Furthermore, by splitting a single-stage shader task into two-stage asynchronous shared tasks and computational tasks in the GPU driver and GPU compiler, the execution of ineffective single-stage shared tasks under low load can be reduced, thereby maximizing the resource utilization efficiency of the first processor.

[0121] In some embodiments, such as Figure 3 As shown in the diagram, this illustrates the execution relationship and scheduling process between asynchronous shared tasks and computational tasks. Figure 3 In the first processor, three shader tasks are executed respectively: shader task 0, shader task 1 and shader task 2. Shader task 0 includes asynchronous shared task 0 and computation task 0, shader task 1 includes asynchronous shared task 1 and computation task 1, and shader task 2 includes asynchronous shared task 2 and computation task 2.

[0122] Asynchronous shared task 0 is executed through a shared computing core in the first processor. After the asynchronous shared task 0 is completed, the corresponding computing task 1 is executed through one or more target computing cores in the first processor. At the same time, after the shared computing core completes the execution of asynchronous shared task 0, it can continue to execute asynchronous shared task 1. After the execution of asynchronous shared task 1 is completed, the corresponding computing task 2 is executed through one or more target computing cores in the first processor. This process continues until all shader tasks are completed through the execution of the first processor.

[0123] In an example embodiment of this disclosure, such as Figure 4 As shown, step S130, where each target computing core obtains shared resources from the shared memory space while executing computing tasks in the shader task, can be achieved through the following steps: Steps S410 to S430. Step S410: Determine a preset register read instruction from the computation task of the shader task; the register read instruction is an instruction for the computation task to read shared data from a shared register. Step S420: Convert the register read instruction into a global memory read instruction for the shared memory space to obtain the updated computation task; In step S430, each target computing core obtains shared resources from the shared storage space according to the global memory read instruction when executing the updated computing task.

[0124] Register read instructions refer to instructions in the original computation task that read shared data from shared registers (or logically shared memory areas). In the traditional execution model, this shared data needs to be initialized locally by each computing core and written into its internal shared registers, and then read and used by the thread bundle.

[0125] Global memory read instructions are operation instructions in the graphics processor instruction set used to read shared resources from shared memory space.

[0126] Understandably, since shared resources have been uniformly written to the shared storage space and no longer depend on the local initialization of each computing core, the access methods in the original computing tasks need to be adapted.

[0127] In some embodiments, a preset register read instruction can be determined from the computational task of the shader task by a second processor (such as a GPU compiler running on the second processor), and the register read instruction can be converted into a global memory read instruction for the shared memory space to obtain an updated computational task.

[0128] Specifically, after receiving a compilation request from the GPU driver, the GPU compiler compiles the shader task in the compilation request to obtain the compiled shader task; it analyzes the shader task to obtain the compiled computation task; it identifies a preset register read instruction from the compiled computation task and redirects the preset register read instruction to a global memory read instruction, the target address of which points to the mapping location of the shared memory space in the global address space.

[0129] In other embodiments, preset register read instructions in the computing task can be identified through static analysis, the preset register read instructions can be replaced with virtual address offsets of shared memory space, and corresponding global memory read instructions can be generated.

[0130] In some embodiments, if the shader task is submitted in binary form and cannot be modified, the GPU driver can replace the register read instruction with a global memory read instruction at runtime through instruction rewriting or intermediate representation patching mechanisms during the command stream assembly phase.

[0131] In other embodiments, to improve access efficiency, global memory read instructions can adopt cache-friendly access modes, such as 128-byte alignment, merging multiple consecutive read requests, or enabling a read-only cache strategy to reduce bandwidth overhead and improve throughput performance when multiple target computing cores are read concurrently.

[0132] The updated computing task includes a global memory read instruction for the shared storage space. When one or more target computing cores execute the updated computing task, they obtain shared resources from the shared storage space where the target address is located, according to the target address of the global memory read instruction.

[0133] Understandably, by converting read operations that were originally directed to on-chip shared registers into global memory access to shared storage space, a seamless connection between computing tasks and centralized resource sharing mechanisms can be achieved. This not only preserves the semantic correctness of the original shader logic, but also avoids the resource waste caused by the repeated initialization of shared data by each computing core in traditional solutions. Thus, energy efficiency and hardware utilization can be optimized in a coordinated manner without changing the application code.

[0134] Furthermore, in some embodiments, computation based on shared resources includes: loading shared resources into the cache of each target computing core; and retrieving shared resources from the cache for computation through each computing unit in the target computing core.

[0135] Here, cache refers to a high-speed storage layer located within the target computing core of the first processor, which may include, but is not limited to, L1 data cache, read-only cache, or texture cache. This cache can be automatically managed by the first processor to temporarily store data frequently accessed from the shared storage space, thereby reducing access latency and improving bandwidth efficiency.

[0136] In some embodiments, for each target computing core, shared resources can be read from the shared storage space according to the global memory read instruction in the updated computing task. This global memory read instruction can be set to the cache scope of a single target computing core; that is, the shared resources obtained according to this global memory read instruction can be loaded into the cache of each target computing core, allowing each computing unit in each target computing core to quickly obtain shared resources from the cache.

[0137] In other embodiments, if multiple thread bundles repeatedly read the same shared resources (such as lighting parameters or transformation matrices) within the same thread block, the cache hit rate will be further improved, thereby avoiding each access from penetrating to the global storage space and effectively alleviating bandwidth pressure.

[0138] It is understandable that each target computing core has already acquired shared resources and loaded them into the cache. When each computing unit in the target computing core needs to perform calculations, it can directly obtain the shared resources from the cache within its respective target computing core. This avoids each computing unit obtaining shared resources from the shared storage space. Moreover, obtaining shared resources from the cache is faster than obtaining them from the shared storage space, which not only allows for faster acquisition of shared resources but also saves the resources of the first processor.

[0139] In some embodiments, such as Figure 5 As shown, another task processing method is also provided, applied to a second processor of an electronic device, the task processing method including the following steps S501 to S503: Step S501: Upon receiving a shader task, determine the shared resources among the thread bundles contained in the shader task, and construct an asynchronous shared task for the shared resources. Step S502: Send the asynchronous shared task to the first processor; the asynchronous shared task is used by the first processor to write the shared resources into the shared storage space of the first processor; Step S503: Distribute each thread bundle to one or more target computing cores of the first processor; the thread bundle is used by each target computing core to obtain shared resources from the shared memory space and perform calculations based on the shared resources when executing the computing tasks in the shader task.

[0140] According to the task processing method in this example embodiment, when the second processor receives a shader task, it determines the shared resources among the thread bundles included in the shader task and constructs a corresponding asynchronous shared task. This asynchronous shared task is then sent to the first processor, enabling the first processor to pre-write the shared resources into its shared storage space. Simultaneously, the second processor distributes each thread bundle to one or more target computing cores of the first processor. Thus, when the target computing cores actually undertaking the computational tasks execute the computational tasks in the shader task, they can directly obtain the shared resources from the shared storage space and perform computations based on these shared resources. In other words, the second processor uniformly constructs and distributes the shared resource writing tasks, avoiding the repetitive loading of the same shared resources by each target computing core when executing computational tasks. Furthermore, it eliminates the need for redundant initialization operations by computing cores in the first processor that are not involved in the task, thereby significantly reducing memory bandwidth usage and ineffective computational overhead, and improving the resource utilization and overall task processing efficiency of the first processor.

[0141] In some embodiments, constructing an asynchronous shared task for a shared resource includes: creating a global memory write instruction for the shared resource; the global memory write instruction is used to instruct the shared resource to be written to the shared memory space of a first processor; and constructing an asynchronous shared task for the shared resource based on the global memory write instruction.

[0142] Specifically, the second processor runs a GPU compiler, which can create global memory write instructions for shared resources and build asynchronous shared tasks for shared resources based on global memory write instructions.

[0143] In some embodiments, the second processor runs a GPU driver, and the above method further includes: generating synchronization instructions between the computing task and the corresponding asynchronous shared task through the GPU driver, and sending the synchronization instructions to the first processor. The synchronization instructions are used by the first processor to execute the corresponding computing task after the asynchronous shared task has been executed.

[0144] In some embodiments, distributing thread bundles to one or more target computing cores of the first processor includes: determining a preset register read instruction from the computing task of the shader task; the register read instruction is an instruction for the computing task to read shared data from a shared register; converting the register read instruction into a global memory read instruction for the shared storage space to obtain an updated computing task; distributing the thread bundles corresponding to the updated computing task to one or more target computing cores of the first processor, wherein the thread bundles corresponding to the updated computing task are used by each target computing core to obtain shared resources from the shared storage space and perform computation based on the shared resources when executing the updated computing task.

[0145] Specifically, the second processor runs a GPU driver and a GPU compiler. The GPU compiler determines the preset register read instructions from the computation tasks of the shader tasks, converts the register read instructions into global memory read instructions for the shared storage space, obtains the updated computation tasks, and sends the updated computation tasks to the GPU driver. The GPU driver then distributes the thread bundles corresponding to the updated computation tasks to one or more target computing cores of the first processor.

[0146] In some embodiments, the second processor runs a GPU driver and a GPU compiler; upon receiving a shader task, determining the shared resources among the thread bundles contained in the shader task includes: upon receiving a compilation request for the shader task, sending the compilation request to the GPU compiler via a user-mode driver in the GPU driver; the compilation request includes a binary file of the shader task; and analyzing the binary file of the shader task using the GPU compiler to determine the shared resources among the thread bundles contained in the shader task.

[0147] In some embodiments, such as Figure 6 As shown, another task processing method is also provided, applied to a first processor of an electronic device, the task processing method including the following steps S601 to S602: Step S601: In response to the received asynchronous shared task, execute the asynchronous shared task and write the shared resources between the thread bundles contained in the shader task into the shared memory space of the first processor; the shared resources are determined by the second processor upon receiving the shader task. In step S602, each thread bundle received by each target computing core obtains shared resources from the shared storage space when executing the computing task corresponding to the thread bundle, and performs computing based on the shared resources.

[0148] According to the task processing method in this example embodiment, after receiving the asynchronous shared task issued by the second processor, the first processor executes the asynchronous shared task and writes the shared resources between the thread bundles in the shader task into its own shared storage space. Subsequently, when each target computing core receives the allocated thread bundle and executes the corresponding computing task, it directly obtains the shared resources from the shared storage space and performs calculations based on the shared resources. That is, the first processor performs a unified write operation of the shared resources, so that all target computing cores participating in the calculation can reuse the same shared resources, without each target computing core needing to independently load the same shared resources from global memory when executing the computing task. This avoids repeated data transfer and redundant initialization overhead, thereby effectively saving memory bandwidth and computing resources, and improving the overall resource utilization and task execution efficiency of the first processor.

[0149] In some embodiments, the asynchronous shared task includes a global memory write instruction for a shared resource, the global memory write instruction being created by a second processor; in response to a received asynchronous shared task, executing the asynchronous shared task includes: in response to a received asynchronous shared task, executing the asynchronous shared task according to the global memory write instruction of the asynchronous shared task, and writing the shared resource into the shared storage space of the first processor.

[0150] In some embodiments, in response to a received asynchronous shared task, executing the asynchronous shared task and writing the shared resources among the thread bundles contained in the shader task into the shared memory space of the first processor includes: in response to a received asynchronous shared task, when executing the asynchronous shared task through a shared computing core in the first processor, writing the shared resources into the shared memory space of the first processor; the shared computing core is a computing core that is different from the target computing core among a plurality of computing cores.

[0151] In some embodiments, a synchronization instruction between a computation task and a corresponding asynchronous shared task sent by a second processor is received. This synchronization instruction is generated by a GPU driver running on the second processor. Based on the synchronization instruction, the corresponding computation task is executed after the asynchronous shared task has been completed.

[0152] In some embodiments, the first processor includes multiple computing cores; when executing a computing task corresponding to a thread bundle, it acquires shared resources from a shared memory space, including: receiving an updated computing task sent by a second processor; the updated computing task is obtained by the second processor converting a preset register read instruction into a global memory read instruction for the shared memory space, the preset register read instruction being determined by the second processor from the computing task of the shader task, the register read instruction being an instruction for the computing task to read shared data from a shared register; and acquiring shared resources from the shared memory space according to the global memory read instruction by one or more target computing cores respectively executing the updated computing task.

[0153] In some embodiments, computation based on shared resources includes: loading shared resources into the cache of each target computing core; and retrieving shared resources from the cache for computation through each computing unit in the target computing core.

[0154] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0155] Furthermore, in this example embodiment, a task processing device is also provided, applied to an electronic device, wherein the first processor of the electronic device includes multiple computing cores. (Refer to...) Figure 7 As shown, the task processing device 700 includes: a shared resource writing module 710, a thread bundle distribution module 720, and a computation task execution module 730. Wherein: The shared resource writing module 710 is used to determine the shared resources among the thread bundles contained in the shader task when a shader task is received, and write the shared resources into the shared memory space of the first processor. The thread bundle distribution module 720 is used to distribute each thread bundle to one or more target computing cores from multiple computing cores; The computation task execution module 730 is used to obtain shared resources from the shared storage space and perform computations based on the shared resources when each target computation core is executing computation tasks in the shader task.

[0156] In some example embodiments of this disclosure, the electronic device further includes a second processor, and based on the foregoing scheme, the shared resource writing module 710 is configured as follows: Asynchronous shared tasks with shared resources are constructed using a second processor; In response to the execution instructions for the shader task, the asynchronous shared task is sent to the first processor via the GPU driver; When an asynchronous shared task is executed by the first processor, the shared resources are written into the shared memory space of the first processor.

[0157] In some example embodiments of this disclosure, the GPU also includes a GPU driver, and based on the foregoing scheme, the shared resource writing module 710 is configured as follows: A global memory write instruction for the shared resource is created by the second processor; the global memory write instruction is used to instruct the shared resource to be written to the shared memory space of the first processor. An asynchronous shared task that builds shared resources based on global memory write instructions.

[0158] In some example embodiments of this disclosure, based on the foregoing scheme, the shared resource writing module 710 is configured as follows: When an asynchronous shared task is executed through a shared computing core in the first processor, the shared resources are written into the shared storage space of the first processor; the shared computing core is a computing core that is different from the target computing core among multiple computing cores.

[0159] In some example embodiments of this disclosure, the second processor runs a GPU driver. Based on the foregoing scheme, the above-mentioned device further includes a synchronization instruction generation module, which is configured to: The GPU driver generates synchronization instructions between computing tasks and corresponding asynchronous shared tasks, and then sends the synchronization instructions to the first processor. The first processor executes the corresponding computational task based on synchronous instructions after the asynchronous shared task has been completed.

[0160] In some example embodiments of this disclosure, based on the foregoing scheme, the computation task execution module 730 is configured as follows: Determine the preset register read instruction from the computation task of the shader task; the register read instruction is the instruction that the computation task reads shared data from the shared register; The register read instruction is translated into a global memory read instruction for the shared memory space, resulting in an updated computation task; Each target computing core retrieves shared resources from the shared storage space according to global memory read instructions when executing the updated computing task.

[0161] In some example embodiments of this disclosure, based on the foregoing scheme, the computation task execution module 730 is configured as follows: For each target computing core, the shared resources are loaded into the target computing core's cache; The computing units within the target computing core retrieve shared resources from the cache for computation.

[0162] In some example embodiments of this disclosure, based on the foregoing scheme, the electronic device further includes a second processor running a GPU driver and a GPU compiler, and the shared resource writing module 710 is configured as follows: Upon receiving a compilation request for a shader task, the compilation request is sent to the GPU compiler via the user-space driver in the GPU driver; the compilation request includes the binary file of the shader task. By analyzing the binary files of the shader tasks using a GPU compiler, the shared resources among the thread bundles contained in the shader tasks can be determined.

[0163] Furthermore, in this example embodiment, a task processing apparatus is also provided, which is a second processor applied to an electronic device. (Refer to...) Figure 8 As shown, the task processing device 800 includes: an asynchronous shared task construction module 810, a sending module 820, and a thread bundle distribution module 830. Wherein: The asynchronous shared task construction module 810 is used to determine the shared resources among the thread bundles contained in the shader task when a shader task is received, and to construct the asynchronous shared task of the shared resources. The sending module 820 is used to send the asynchronous shared task to the first processor; the asynchronous shared task is used by the first processor to write the shared resource into the shared storage space of the first processor; The thread bundle distribution module 830 is used to distribute each of the thread bundles to one or more target computing cores of the first processor; the thread bundles are used by each of the target computing cores to obtain the shared resources from the shared storage space and perform calculations based on the shared resources when executing the computing tasks in the shader tasks.

[0164] Furthermore, in this example embodiment, a task processing apparatus is also provided, including a first processor applied to an electronic device, the first processor comprising a plurality of target computing cores. (Refer to...) Figure 9 As shown, the task processing device 900 includes: a shared resource writing module 910 and a computing task execution module 920. Wherein: The shared resource writing module 910 is used to respond to a received asynchronous shared task, execute the asynchronous shared task, and write the shared resources between the thread bundles contained in the shader task into the shared storage space of the first processor; the shared resources are determined by the second processor upon receiving the shader task. The computation task execution module 920 is used to obtain the shared resources from the shared storage space and perform computation based on the shared resources when executing the computation task corresponding to the thread bundle received by each of the target computation cores.

[0165] The specific details of each module of the above task processing device have been described in detail in the corresponding task processing methods, so they will not be repeated here.

[0166] It should be noted that although several modules or units of the task processing apparatus have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0167] Furthermore, this example embodiment also provides an architecture diagram of a task processing system. For example... Figure 10 As shown, the task processing system 1000 includes a first processor and a second processor. The first processor is GPU hardware 1004, and the second processor runs a GPU driver 1002 and a GPU compiler 1003. The first processor and the second processor work together to achieve centralized management and efficient computing of shared resources.

[0168] GPU compiler 1003 is used to determine the shared resources among the thread bundles contained in the shader task based on the shader task submitted by application 1001, and generate an asynchronous shared task for writing the shared resources to the shared memory space.

[0169] GPU driver 1002 is used to distribute asynchronous shared tasks to shared computing cores in GPU hardware 1004, and to distribute the thread bundles corresponding to the computing tasks to one or more target computing cores in GPU hardware 1004.

[0170] GPU hardware 1004 is used to write shared resources into shared memory space when executing asynchronous shared tasks, and when executing computing tasks, each target computing core obtains shared resources from the shared memory space and performs computing based on the shared resources.

[0171] Furthermore, the GPU driver 1002 is also used to respond to the compilation request of the shader task issued by the application 1001, and send the compilation request to the GPU compiler 1003 through the user-mode driver; the compilation request includes the binary file of the shader task; the GPU compiler 1003 is also used to compile and analyze the binary file of the shader task, and determine the shared resources between the thread bundles contained in the shader task.

[0172] Furthermore, the GPU compiler 1003 is also used to construct asynchronous shared tasks for shared resources and send the asynchronous shared tasks to the GPU driver 1002; the GPU driver 1002 is also used to send the asynchronous shared tasks to the GPU hardware 1004 in response to the execution instructions for the shader tasks; the GPU hardware 1004 is also used to write the shared resources into the shared memory space when executing the asynchronous shared tasks.

[0173] Furthermore, the GPU compiler 1003 is also used to create global memory write instructions for shared resources; these global memory write instructions are used to instruct the writing of shared resources to shared storage space, and asynchronous shared tasks for shared resources are constructed based on these global memory write instructions. These asynchronous shared tasks include global memory write instructions.

[0174] Furthermore, the GPU hardware 1004 is also used to write shared resources into a shared storage space when executing asynchronous shared tasks through a shared computing core; the shared computing core is a computing core that is different from the target computing core among multiple computing cores.

[0175] Furthermore, the GPU driver 1002 is also used to generate synchronization instructions between the computing task and the corresponding asynchronous shared task, and to send the synchronization instructions to the GPU hardware 1004; the GPU hardware 1004 is also used to execute the corresponding computing task based on the synchronization instructions after the asynchronous shared task has been executed.

[0176] Furthermore, the GPU compiler 1003 is also used to determine preset register read instructions from the computation tasks of the shader tasks. These register read instructions are instructions for the computation tasks to read shared data from shared registers. The compiler converts these register read instructions into global memory read instructions for the shared memory space, resulting in an updated computation task, which is then sent to the GPU driver 1002. The GPU driver 1002 is also used to distribute the updated computation task to the GPU hardware 1004. The GPU hardware 1004 is further used to obtain shared resources from the shared memory space according to the global memory read instructions when each target computing core executes the updated computation task. This updated computation task includes global memory read instructions.

[0177] Furthermore, the GPU hardware 1004 is also used to load shared resources into the cache of the target computing core through each target computing core, and to obtain shared resources from the cache for computation through each computing unit in the target computing core.

[0178] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described task processing method is also provided.

[0179] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be embodied in the following forms: a completely hardware embodiment, a completely software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0180] The following reference Figure 11 To describe an electronic device 1100 according to such an embodiment of the present disclosure. Figure 11 The electronic device 1100 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0181] like Figure 11 As shown, the electronic device 1100 is manifested in the form of a general-purpose computing device. The components of the electronic device 1100 may include, but are not limited to: at least one processing unit 1110, at least one storage unit 1120, a bus 1130 connecting different system components (including storage unit 1120 and processing unit 1110), and a display unit 1140.

[0182] The storage unit stores program code that can be executed by the processing unit 1110, causing the processing unit 1110 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 1110 can perform actions such as... Figure 1 In step S110, upon receiving a shader task, the shared resources among the thread bundles contained in the shader task are determined, and the shared resources are written into the shared memory space of the first processor; in step S120, each thread bundle is distributed to one or more target computing cores among multiple computing cores; in step S130, each target computing core obtains shared resources from the shared memory space when executing the computing tasks in the shader task, and performs computing based on the shared resources.

[0183] Storage unit 1120 may include readable media in the form of volatile storage units, such as random access memory (RAM) 1121 and / or cache memory 1122, and may further include read-only memory (ROM) 1123.

[0184] Storage unit 1120 may also include a program / utility 1124 having a set (at least one) program module 1125, such program module 1125 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0185] Bus 1130 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0186] Electronic device 1100 can also communicate with one or more external devices 1170 (e.g., keyboard, pointing device, Bluetooth device, etc.), one or more devices that enable a user to interact with electronic device 1100, and / or any device that enables electronic device 1100 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1150. Furthermore, electronic device 1100 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1160. As shown, network adapter 1160 communicates with other modules of electronic device 1100 via bus 1130. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1100, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0187] In addition, a first processor is provided, which is configured to execute the task processing method applied to the first processor as described above.

[0188] In addition, a second processor is provided, wherein the first processor is configured to execute the task processing method applied to the second processor as described above.

[0189] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0190] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0191] The program product of the above-described task processing method can run on a terminal device, such as a personal computer. However, the program product disclosed herein is not limited thereto. In this document, the readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0192] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0193] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0194] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0195] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0196] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0197] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0198] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0199] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A task processing method, characterized in that, Applied to an electronic device, wherein the first processor of the electronic device includes multiple computing cores, the method includes: Upon receiving a shader task, determine the shared resources among the thread bundles contained in the shader task, and write the shared resources into the shared memory space of the first processor; Each of the aforementioned thread bundles is distributed to one or more target computing cores from the plurality of computing cores; When each of the target computing cores executes a computing task in the shader task, it obtains the shared resources from the shared storage space and performs computing based on the shared resources.

2. The task processing method according to claim 1, characterized in that, The electronic device further includes a second processor; the step of writing the shared resources into the shared storage space of the first processor includes: The asynchronous sharing task of the shared resource is constructed through the second processor; In response to the execution instruction for the shader task, the asynchronous shared task is sent to the first processor; When the asynchronous shared task is executed by the first processor, the shared resources are written into the shared storage space of the first processor.

3. The task processing method according to claim 2, characterized in that, The asynchronous sharing task of constructing the shared resource through the second processor includes: The second processor creates a global memory write instruction for the shared resource; the global memory write instruction is used to instruct the shared resource to be written to the shared storage space of the first processor. An asynchronous shared task for the shared resource is constructed based on the global memory write instruction.

4. The task processing method according to claim 2, characterized in that, When the asynchronous shared task is executed by the first processor, writing the shared resources into the shared storage space of the first processor includes: When the asynchronous shared task is executed through the shared computing core in the first processor, the shared resources are written into the shared storage space of the first processor; the shared computing core is a computing core that is different from the target computing core among the plurality of computing cores.

5. The task processing method according to claim 2, characterized in that, The second processor runs a GPU driver, and the method further includes: The GPU driver generates synchronization instructions between the computing task and the corresponding asynchronous shared task, and sends the synchronization instructions to the first processor. The first processor executes the corresponding computation task after the asynchronous shared task is completed, based on the synchronous instructions.

6. The task processing method according to any one of claims 1 to 5, characterized in that, The step of obtaining the shared resources from the shared storage space when each of the target computing cores executes the computing tasks in the shader task includes: A preset register read instruction is determined from the computation task of the shader task; the register read instruction is the instruction of the computation task to read shared data from a shared register; The register read instruction is converted into a global memory read instruction for the shared storage space to obtain the updated computation task; When each of the target computing cores executes the updated computing task, it retrieves the shared resources from the shared storage space according to the global memory read instruction.

7. The task processing method according to any one of claims 1 to 5, characterized in that, The calculation based on the shared resources includes: For each target computing core, the shared resources are loaded into the cache of the target computing core; The shared resources in the cache are obtained from the computing units in the target computing core for computation.

8. The task processing method according to any one of claims 1 to 5, characterized in that, The electronic device further includes a second processor running a GPU driver and a GPU compiler; the step of determining the shared resources among the thread bundles contained in the shader task upon receiving a shader task includes: Upon receiving a compilation request for a shader task, the compilation request is sent to the GPU compiler via the user-space driver in the GPU driver; the compilation request includes the binary file of the shader task; The GPU compiler analyzes the binary file of the shader task to determine the shared resources among the thread bundles contained in the shader task.

9. A task processing method, characterized in that, The method, applied to a second processor in an electronic device, includes: Upon receiving a shader task, determine the shared resources among the thread bundles contained in the shader task, and construct an asynchronous shared task for the shared resources; The asynchronous sharing task is sent to the first processor; the asynchronous sharing task is used by the first processor to write the shared resources into the shared storage space of the first processor; Each of the thread bundles is distributed to one or more target computing cores of the first processor; the thread bundles are used by each of the target computing cores to obtain the shared resources from the shared storage space and perform calculations based on the shared resources when executing the computing tasks in the shader tasks.

10. A task processing method, characterized in that, A first processor applied to an electronic device, the first processor comprising a plurality of target computing cores, the method comprising: In response to a received asynchronous shared task, the asynchronous shared task is executed, and the shared resources among the thread bundles contained in the shader task are written into the shared memory space of the first processor; the shared resources are determined by the second processor upon receiving the shader task. Each of the thread bundles received by each of the target computing cores obtains the shared resources from the shared storage space when executing the computing task corresponding to the thread bundle, and performs computing based on the shared resources.

11. A task processing device, characterized in that, Applied to an electronic device, the first processor of the electronic device includes multiple computing cores, and the device includes: A shared resource writing module is used to determine the shared resources among the thread bundles contained in the shader task when a shader task is received, and to write the shared resources into the shared memory space of the first processor. The thread bundle distribution module is used to distribute each of the thread bundles to one or more target computing cores among the plurality of computing cores; The computation task execution module is used to obtain the shared resources from the shared storage space and perform computations based on the shared resources when each of the target computation cores executes the computation tasks in the shader task.

12. A task processing device, characterized in that, A second processor applied to an electronic device, the device comprising: An asynchronous shared task construction module is used to determine the shared resources among the thread bundles contained in the shader task when a shader task is received, and to construct an asynchronous shared task for the shared resources. A sending module is used to send the asynchronous shared task to a first processor; the asynchronous shared task is used by the first processor to write the shared resource into the shared storage space of the first processor; A thread beam distribution module is used to distribute each of the thread beams to one or more target computing cores of the first processor; the thread beams are used by each of the target computing cores to obtain the shared resources from the shared storage space and perform calculations based on the shared resources when executing the computing tasks in the shader tasks.

13. A task processing device, characterized in that, A first processor for use in an electronic device, the first processor including a plurality of target computing cores, the device comprising: A shared resource writing module is used to respond to a received asynchronous shared task, execute the asynchronous shared task, and write the shared resources between the thread bundles contained in the shader task into the shared storage space of the first processor; the shared resources are determined by the second processor upon receiving the shader task; The computation task execution module is used to obtain the shared resources from the shared storage space and perform computation based on the shared resources when executing the computation task corresponding to the thread bundle received by each of the target computation cores.

14. An electronic device, characterized in that, include: First processor; Second processor; as well as A memory storing computer-readable instructions that, when executed by the electronic device, implement the task processing method as described in any one of claims 1 to 8.

15. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by an electronic device, implements the task processing method as described in any one of claims 1 to 8.

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