Multi-task scheduling method of multi-core processor architecture and scheduling control unit

Abstract

The invention discloses a multi-task scheduling method of a multi-core processor architecture and a scheduling control unit, and relates to the technical field of wireless communication and processor scheduling. The method comprises the following steps: initializing a system; task distribution judgment: the general RISC core starts a scheduling judgment process after receiving the wireless communication calculation task information, and issues the task information to a dynamic reconfigurable task instruction issuing unit after the judgment is completed; task queue management: the dynamic reconfigurable task instruction issuing unit writes the task information into a task queue memory according to the queue ID; multi-core task execution and response: external multi-core monitors the state of a corresponding task queue memory in real time, and reads and executes task information when a to-be-executed task is detected; and refreshing the state of the task queue memory after completion. According to the multi-core processor architecture for processing in the field of wireless communication, the programmable task scheduling unit is designed, and flexible expansion and combination among multiple cores are realized through instruction programming according to application scene requirements.

Description

Technical Field

[0001] This application relates to the fields of wireless communication and processor scheduling technology, and in particular to a multi-task scheduling method and scheduling control unit for a multi-core processor architecture. Background Technology

[0002] With the widespread adoption of 5G technology, wireless communication computing faces challenges in terms of computing power and real-time performance due to complex scenarios such as ultra-dense networking and multi-standard compatibility. Single-core architectures are no longer sufficient to meet the demands of massive concurrent data processing and differentiated tasks. While some existing multi-core architectures possess basic parallel processing capabilities, they often employ static scheduling or simple load balancing strategies, making it difficult to adapt to the dynamic characteristics of wireless communication tasks and to adjust task allocation in real-time based on task priority and core load status. Furthermore, insufficient fine-grained decomposition of computing tasks results in inadequate exploitation of parallelism and failure to overcome serial processing bottlenecks. These issues lead to low processor core resource utilization, resulting in an imbalance where some processor cores are overloaded while others remain idle, ultimately failing to meet the real-time and energy efficiency requirements of wireless communication scenarios and limiting the application performance of multi-core architectures in complex communication environments. Summary of the Invention

[0003] This application provides a multi-task scheduling method and scheduling control unit for a multi-core processor architecture to solve the problems in the prior art.

[0004] On one hand, embodiments of this application provide a multi-task scheduling method for a multi-core processor architecture, including: S1, System Initialization: After starting the general-purpose RISC (Reduced Instruction Set Computer) core, the peripheral modules are initialized; the dynamically reconfigurable task instruction issuing unit initializes the empty / full state of each task queue memory, sets the task queue status register to empty, and feeds back the initialization completion signal to the general-purpose RISC core through the system bus; the external processor core waits to receive task information from the task queue memory.

[0005] S2, Task Distribution Judgment: The host computer sends wireless communication computing task information to the Config_RF (configuration register group) of the general-purpose RISC core. After the general-purpose RISC core reads the task information into the RF (general-purpose register group), it starts the scheduling judgment process. After the judgment is completed, the general-purpose RISC core sends the task information to the dynamic reconfigurable task instruction issuing unit through the system bus. After the distribution is completed, the bus resources are released immediately.

[0006] In detail, the scheduling decision-making process includes: S2.1 Read the basic task information stored in Config_RF, including: the starting address of the task instruction in DDR (Double Data Rate Synchronous Dynamic Random Access Memory), the total number of instructions, and the task type.

[0007] S2.2, obtain the real-time status of the registers in the dynamic reconfigurable task instruction issuing unit through the system bus.

[0008] S2.3, dynamically determine the target task queue storage that is adapted to the complexity and queue status of this task based on the scheduling algorithm.

[0009] In detail, the scheduling algorithm includes: S2.3.1, Task Information Parsing and Status Acquisition: The general-purpose RISC core receives a task request from the APB (External Bus), extracts the total number of task instructions N and the task type T, and reads three key states from the registers in the dynamically reconfigurable task instruction issuing unit via the system bus: the instruction count threshold register stores the critical value TH for the number of instructions processed by a single processor core, and the queue task count register stores the current number of tasks in the FIFO (First-In-First-Out) task storage queues bound to the four external processor cores. The task queue status register stores the queue's idle or active status. S2.3.2, Instruction Count Threshold Judgment and Processing Path Selection: If N≤TH and T=0, i.e., the current task is a low / medium load task, check... ,like If the depth is less than the FIFO depth threshold, the task will be assigned to the CORE0 (external processor core) queue; if... Once the FIFO depth threshold is reached, iterate through CORE1-3 to filter for queues that are idle. If an idle queue is found, assign the task to that CORE queue; otherwise, check... If there is a FIFO with a depth less than the FIFO threshold, the task is assigned to the corresponding CORE queue. If all queues reach the threshold, the filtering process is repeated until an empty queue is found before task assignment. If N>TH or T=1, that is, the current task is a high-load task, the dynamic expansion mechanism is triggered to filter the idle queues in CORE1~3 and assign them to the CORE queue. If there are no idle queues, the filtering process is repeated until an empty queue is found before task assignment. S2.3.3, Task Allocation and Status Update: Write task information to the target FIFO, including: DDR initial address, total number of instructions N, and synchronously update the corresponding queue task count register.

[0010] S3, Task Queue Management: The dynamically reconfigurable task instruction issuing unit writes the task information into the corresponding task queue memory based on the queue ID in the task information issued by the general-purpose RISC core; the control unit updates the status of the task queue status register corresponding to the task queue memory in real time and synchronizes it to the general-purpose RISC core.

[0011] S4, Multi-core Task Execution and Response: When the external processor verifies the status of the corresponding task queue memory, it reads the task information from the queue and executes the computation task when it detects that there is a task to be executed in the task queue memory. After the execution is completed, the status of the task queue memory is refreshed, and the general-purpose RISC core sends new task information according to the real-time status of the task queue status register.

[0012] On the other hand, embodiments of this application also provide a multi-task scheduling and control unit with a multi-core processor architecture, including: A general-purpose RISC core is used for task allocation, load balancing, and operation status control of multi-core processors.

[0013] The dynamically reconfigurable task instruction issuing unit is used for task issuing and real-time load status sensing. The dynamically reconfigurable task instruction issuing unit includes: a task queue memory, which stores dedicated task information to be issued to external processor cores, containing four homogeneous task storage queues (FIFOs); a task information register group, which temporarily stores the raw task data issued by the general-purpose RISC core; a configuration register group, which parses read and write requests from the system bus, stores key parameters for task scheduling, and outputs FIFO control signals; and a control unit, which is used for scheduling and coordination during task instruction issuing.

[0014] In detail, the configuration register group includes: a task queue status register, used to store the empty / full status of each task queue; an instruction count threshold register, used to store the instruction count threshold for a single processor core to process a task; a queue task count register, used to store the current number of tasks in the four task storage queues (FIFOs); a task DDR start address register, used to store the starting address of the task to be executed in external DDR memory; a task instruction count register, used to store the total number of external processor core-customized instructions contained in the current task; a FIFO ID configuration register, used to store the target task queue number corresponding to the task to be dispatched; a FIFO write enable register, used to write task information to the task storage queue FIFOs; and a FIFO refresh register, used to force a refresh of the stored data in all task storage queue FIFOs for reset during task switching or exception handling.

[0015] Specifically, the data width of the task storage queue FIFO is 64 bits, and the depth is set to 16 items.

[0016] Peripheral modules include: RAM (Random Access Memory), used to cache raw data and intermediate results; CLINT (Core Local Interrupt), used for system timer interrupts and task queue clearing; UART (Universal Asynchronous Receiver / Transmitter) and GPIO (General Purpose Input / Output Ports) for debugging and peripheral control.

[0017] The multi-task scheduling control unit and scheduling algorithm of the multi-core processor architecture disclosed in this application have the following advantages: 1. By dynamically scheduling, flexible combination and expansion among multi-processor cores can be achieved, improving the real-time performance of computing and the system energy efficiency ratio; 2. Relying on the programmable scheduling unit and the instruction number threshold register that supports dynamic configuration, it can flexibly adapt to the specifications of different bandwidths and subcarrier spacings. There is no need to reconstruct the hardware interface or modify the core logic. Scene switching can be completed simply by instruction programming, reducing the cost of cross-standard adaptation. 3. By leveraging the queue task counter register to quantitatively perceive the load of each core, and combining a two-dimensional load judgment mechanism based on task type and instruction count, differentiated allocation is achieved, prioritizing single-core resource allocation for low / medium load tasks and dynamically triggering multi-core collaboration for high load tasks. This avoids idle computing power and computing power overload, significantly improving the overall computing power utilization and energy efficiency of the system. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a system architecture diagram for a multi-task scheduling unit.

[0020] Figure 2 This is a flowchart of a single task scheduling algorithm.

[0021] Figure 3 This is a general RISC core circuit structure diagram.

[0022] Figure 4 This is a diagram of the module architecture for the dynamic reconfigurable task instruction issuance unit.

[0023] Figure 5 A sequence diagram for issuing task information.

[0024] Figure 6 Sequence diagram for task information reading operation.

[0025] Figure 7The core circuit structure diagram of the dynamically reconfigurable task instruction issuing unit. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] Figure 1 This is a system architecture diagram of a multi-task scheduling unit provided in an embodiment of this application. This application provides a multi-task scheduling method for a multi-core processor architecture, including: S1, System Initialization: After starting the general-purpose RISC core, the peripheral modules are initialized; the dynamic reconfigurable task instruction issuing unit initializes the empty / full state of each task queue memory, sets the task queue status register to empty, and feeds back the initialization completion signal to the general-purpose RISC core through the system bus; the external processor core waits to receive task information from the task queue memory.

[0028] S2, Task Distribution Judgment: The host computer sends wireless communication computing task information to the Config_RF of the general-purpose RISC core. After reading the task information into the RF, the general-purpose RISC core starts the scheduling judgment process. After the judgment is completed, the general-purpose RISC core sends the task information to the dynamic reconfigurable task instruction issuing unit through the system bus. After the distribution is completed, the bus resources are released immediately.

[0029] In one possible implementation, the scheduling decision process includes: S2.1 Read the basic task information stored in Config_RF, including: the starting address of the task instruction in DDR, the total number of instructions, and the task type.

[0030] S2.2, obtain the real-time status of the registers in the dynamic reconfigurable task instruction issuing unit through the system bus.

[0031] S2.3, dynamically determine the target task queue storage that is adapted to the complexity and queue status of this task based on the scheduling algorithm.

[0032] In detail, to achieve efficient collaboration between the general-purpose RISC core and the dynamically reconfigurable task instruction delivery unit, solve problems such as uneven resource allocation and low energy efficiency during task delivery, and ensure rapid response and accurate distribution of multiple tasks under the homogeneous multi-core architecture, a task scheduling algorithm is designed, the interaction logic between the two is optimized, and the overall task processing efficiency of the system is improved.

[0033] Specifically, the scheduling algorithm is designed for homogeneous multi-core architecture, limited task information, and energy efficiency optimization requirements in wireless communication processing scenarios. The core achieves efficient task distribution and energy-saving scheduling through instruction number threshold partitioning, FIFO load perception, and dynamic sleep-wake control.

[0034] In one possible implementation, the scheduling algorithm includes: S2.3.1, Task Information Parsing and Status Acquisition: The general-purpose RISC core receives the task request issued by the APB, extracts the total number of task instructions N and the task type T, and reads three key states of the registers in the dynamically reconfigurable task instruction issuing unit through the system bus: the instruction count threshold register stores the critical value TH for the number of instructions processed by a single processor core, and the queue task count register stores the current number of tasks in the FIFO of the task storage queues bound to the four external processor cores. The task queue status register stores the queue's idle or active status.

[0035] Specifically, the number of current tasks stored in the FIFO task counter reflects the real-time load of the corresponding processor core. The task queue status register: 1 indicates idle, 0 indicates active; by default, only CORE0 is active, while other external processor core modules are in a sleep state.

[0036] S2.3.2, Instruction Count Threshold Judgment and Processing Path Selection: If N≤TH and T=0, i.e., the current task is a low / medium load task, check... ,like If the depth is less than the FIFO depth threshold, the task will be assigned to the CORE0 queue; if... Once the FIFO depth threshold is reached, iterate through CORE1-3 to filter for queues that are idle. If an idle queue is found, assign the task to that CORE queue; otherwise, check... If there is a FIFO with a depth less than the FIFO threshold, the task is assigned to the corresponding CORE queue. If all queues reach the threshold, the filtering process is repeated until an empty queue is found before the task is assigned. If N>TH or T=1, that is, the current task is a high-load task, the dynamic expansion mechanism is triggered to filter the idle queues in CORE1~3 and assign them to the CORE queue. If there are no idle queues, the filtering process is repeated until an empty queue is found before the task is assigned.

[0037] Specifically, low / medium load tasks prioritize using the default active CORE0 to reduce energy consumption.

[0038] S2.3.3, Task Allocation and Status Update: Write task information to the target FIFO, including: DDR initial address, total number of instructions N, and synchronously update the corresponding queue task count register.

[0039] In detail, such as Figure 2 The diagram shows the scheduling process for a single task. Through multi-level condition judgments, tasks are efficiently dispatched.

[0040] S3, Task Queue Management: The dynamically reconfigurable task instruction issuing unit writes the task information into the corresponding task queue memory based on the queue ID in the task information issued by the general-purpose RISC core; the control unit updates the status of the task queue status register corresponding to the task queue memory in real time and synchronizes it to the general-purpose RISC core.

[0041] S4, Multi-core Task Execution and Response: When the external processor verifies the status of the corresponding task queue memory, it reads the task information from the queue and executes the computation task when it detects that there is a task to be executed in the task queue memory. After the execution is completed, the status of the task queue memory is refreshed, and the general-purpose RISC core sends new task information according to the real-time status of the task queue status register.

[0042] On the other hand, embodiments of this application also provide a multi-task scheduling and control unit with a multi-core processor architecture, including: A general-purpose RISC core is used for task allocation, load balancing, and operation status control of multi-core processors.

[0043] In detail, the general-purpose RISC core establishes a connection with the dynamic reconfigurable task instruction delivery unit and the multi-core through the system bus. Its core function is to obtain the execution status information of each core recorded in the delivery unit in real time. Based on the preset scheduling algorithm and the dynamic requirements of the application scenario, it generates scheduling control signals by executing specific instruction sequences to realize task allocation, load balancing and operation status regulation of the multi-core processor.

[0044] Specifically, the general-purpose RISC core, as the main body for multi-task scheduling decisions, has a hardware architecture based on a three-stage pipeline design of instruction fetch (IF) – decode (ID) – execute (EX), such as... Figure 3 The diagram shows a general RISC core circuit structure. Through a core module deeply coupled with the scheduling function, lightweight and low-latency scheduling of wireless communication computing tasks is achieved, providing hardware support for the efficient operation of subsequent dynamic scheduling algorithms. The specific structure and functions are as follows: (1) Instruction Fetch Level (IF Level) The instruction fetch stage is implemented collaboratively by the IF module and the IM (instruction memory) module. Its core functions are to read the task instructions sent by the host computer, generate the program counter, pre-determine the branch direction, and provide the initial instruction and address reference for scheduling. The specific logic is as follows: Instruction Fetch: The IF module initiates a read request to the IM through the read instruction enable signal. The IM outputs a 32-bit task instruction based on the fetch address and sends it back to the IF through the instr signal. At the same time, the IM has built-in address out-of-bounds protection logic. When the address information exceeds the storage depth, it automatically outputs a NOP (no operation) instruction to avoid instruction fetching errors.

[0045] PC (Program Counter) Address Generation and Branch Prediction: The IF module has a built-in branch prediction submodule (Prediction), which predicts the branch jump direction based on the current PC address and the immediate value in the instruction, and generates a prefetch address to ensure the continuity of instruction prefetching and task scheduling and reduce pipeline congestion.

[0046] Pipeline interaction logic: The IF module synchronizes instruction validity with the decoding level through handshake signals—only when the ID level is ready to receive new instructions and there is no refresh will the prefetched instructions be latched and the current instruction PC address and the next instruction PC address be synchronized.

[0047] (2) Decoding level (ID level) The decoding level is implemented collaboratively by the Decode submodule, the Record submodule, and RF. Its core functions are to handle data bypassing and detect scheduling conflicts. The specific logic is as follows: Instruction parsing: The Decode module receives instructions from the IF module, parses the instruction information using opcode and func3, and extracts key parameters: source register, destination register, and immediate value.

[0048] Conflict detection: To avoid pipeline blockage, the Decode module uses the busa_bypass / busb_bypass signals to bypass data, prioritizing the reading of instruction results from the execution level and then reading register file data to ensure real-time parameter updates. Meanwhile, the Record module detects hard data conflicts based on the source register and the ls_mul_vld signal: if the source register is occupied by an incomplete instruction, the data conflict signal is set high, pausing instruction dispatch to avoid scheduling conflicts.

[0049] Task dispatch determination: The Decode module determines whether an instruction is dispatchable through the disp_alu / disp_mul / disp_ls signals: the corresponding dispatch signal is set only when there is no data conflict and the instruction is valid, providing the trigger condition for instruction execution for EX-level scheduling.

[0050] (3) Execution level (EX level) The execution level is implemented collaboratively by the Arithmetic Logic Execution (ALU), Multiplication Execution (MUL), and Memory Access Control submodules. Its core functions are instruction calculation, data loading / storage, and feedback of execution results. The specific logic is as follows: Arithmetic logic execution: The ALU module performs arithmetic logic calculations of the corresponding type based on the opcode and operands output by the Decode module and returns the calculation results.

[0051] Multiplication operation execution: The MUL module parses the instructions and obtains the operands, performs sign expansion, and completes the multiplication calculation through a two-stage pipeline.

[0052] Data Load / Storage Execution Logic: During the execution of data load / store operations, the instruction parameters passed at the decoding level are first received. The memory access address is calculated by the arithmetic logic unit, and address alignment checks are performed simultaneously. For load operations, a read request is sent to the memory controller. After receiving the returned raw data, data expansion is performed according to the instruction type. For store operations, data is read from the source register, truncated to the target width according to the instruction type, and a write request is sent to the memory controller, along with the address and data. During the process, exceptions such as address out-of-bounds errors and alignment errors are detected simultaneously and exception signals are generated. Finally, the load operation writes the processed data and the target register ID back to the register file, and the store operation generates a completion signal after completing the memory write, ensuring the correctness and timing of data interaction.

[0053] (4) Bus interface unit The bus interface unit receives instruction access requests at the fetch level and data load / store requests at the execution level, parses the request type, address, and data width, and converts the internal signal format into standard signals conforming to the external bus protocol. It coordinates the timing between the kernel and the external bus to ensure correct cross-clock domain interaction. During data transmission, it forwards external return data to the kernel for read operations and forwards kernel data to external storage for write operations, while also adapting the data width. Simultaneously, it monitors bus errors (such as address out-of-bounds errors and response timeouts), generates error status signals, and feeds them back to the kernel, ultimately achieving efficient and reliable data and instruction interaction between the kernel and external devices.

[0054] The dynamically reconfigurable task instruction issuing unit is used for task issuing and real-time load status sensing. The dynamically reconfigurable task instruction issuing unit includes: a task queue memory, which stores dedicated task information to be issued to external processor cores, containing four homogeneous task storage queues (FIFOs); a task information register group, which temporarily stores the raw task data issued by the general-purpose RISC core; a configuration register group, which parses read and write requests from the system bus, stores key parameters for task scheduling, and outputs FIFO control signals; and a control unit, which is used for scheduling and coordination during task instruction issuing.

[0055] In detail, the dynamically reconfigurable task instruction issuing unit, as the core execution unit, communicates with the general-purpose RISC core, the task queue memory, and various external cores. Its core innovation lies in its "dynamic reconfiguration capability." This includes a built-in task scenario configuration register, which can be written with scenario parameters for the current wireless communication computing task through the general-purpose RISC core, providing a parameter basis for dynamic reconfiguration. The task queue and each core are dynamically mapped, allowing the control unit to adjust the binding relationship between the queue and each core according to the characteristics of the computing task. For low-complexity tasks, a single processor core is invoked; for high-complexity tasks, multiple processor cores are invoked for collaborative processing. The dynamically reconfigurable task instruction issuing unit also has a built-in task queue status register, providing real-time feedback on the storage status of each task queue memory and dynamically adjusting queue priorities based on application scenario parameters.

[0056] Furthermore, Figure 4 The diagram shows the architecture of the dynamic reconfigurable task instruction delivery unit. Its core function is to enable task information and status interaction between the general-purpose RISC core and external multi-core processors. Specifically, it comprises three main functional modules: a task queue memory, a task information register group, and a configuration register group. These modules are interconnected via an internal data bus and control bus. The task queue memory caches dedicated task information to be delivered to the external processor core. The task information register group temporarily stores the raw task data delivered by the general-purpose RISC core. The configuration register group stores information such as the empty / full status of each task queue, the preset threshold for the number of instructions that the external processor core can process, and the number of tasks in the task queue memory. Through collaborative operation, the modules enable the dynamic reconfigurable task instruction delivery unit to complete task delivery, real-time load status monitoring, and threshold-based scheduling decisions, ensuring the accuracy of task information transmission and the efficiency of scheduling.

[0057] Specifically, the configuration register set is a 32-bit wide register set.

[0058] In one possible implementation, a task queue status register is used to store the empty / full status of each task queue; an instruction count threshold register is used to store the critical value of the number of instructions a single processor core can process for a task; a queue task count register is used to store the current number of tasks in the four task storage queues FIFO; a task DDR start address register is used to store the starting address of the task to be executed in external DDR memory; a task instruction count register is used to store the total number of external processor core customized instructions contained in the current task; a FIFO ID configuration register is used to store the target task queue number corresponding to the task to be issued; a FIFO write enable register is used to write task information to the task storage queue FIFO; and a FIFO refresh register is used to force a refresh of the stored data in all task storage queue FIFOs for reset during task switching or exception handling.

[0059] Specifically, the task queue status register stores the queue's empty / full status, allowing the scheduling algorithm to determine whether an external processor core is idle in order to allocate tasks. Its bit fields are defined as follows:

[0060] Bits 3 to 0 each represent the full state of a FIFO; a value of 1 indicates that the corresponding FIFO is full, and a value of 0 indicates that the FIFO is not full. Bits 7 to 4 each represent the empty state of a FIFO; a value of 1 indicates that the corresponding FIFO is empty, and a value of 0 indicates that the FIFO is not empty.

[0061] The instruction count threshold register stores the critical number of instructions a single processor core can process for a task. It serves as the criterion for distinguishing between low / medium load tasks and high load tasks in the scheduling algorithm, and supports dynamic configuration to adapt to load partitioning requirements in different scenarios. Its bit fields are defined as follows:

[0062] The queue task counter register provides quantitative data support for the scheduling algorithm to perceive the external processor core load status and achieve load balancing. Its bit fields are defined as follows:

[0063] Among them, bits 0-7, 8-15, 16-23, and 24-31 correspond to the current number of tasks in the four queues FIFO.

[0064] The task DDR start address register stores the starting address of the task to be executed in external DDR memory, for use by the system bus when reading task data from DDR. Its bit fields are defined as follows:

[0065] The Task Instruction Count Register stores the total number of custom instructions from the external processor core included in the current task. This is used by the external processor core to determine the task's execution progress and prevent instruction overflow. Its bit fields are defined as follows:

[0066] The FIFO ID configuration register stores the target task queue number corresponding to the task to be assigned. When the system bus writes task information, the control unit writes data to the target FIFO according to the value of this register. Its bit field definition is as follows:

[0067] The lower 4 bits correspond to queues 0-3 respectively.

[0068] The FIFO write enable register writes task information to the queue FIFO. Its bit fields are defined as follows:

[0069] The lower bit is valid; a value of 1 indicates that the bit is being written.

[0070] The FIFO refresh register is used to reset the FIFO during task switching or exception handling. Its bit fields are defined as follows:

[0071] The lower bit is valid; when the value is 1, all FIFO storage data is forcibly refreshed.

[0072] Furthermore, in the dynamically reconfigurable task instruction issuing unit, the input / output ports serve as the core interfaces for signal interaction and data transmission between the unit and external systems. Their port definitions, bit widths, and functional descriptions are as follows:

[0073] Furthermore, such as Figure 5 The diagram shows the timing of the task information distribution operation. Before task information distribution begins, the general-purpose RISC core first initiates a read operation on the task queue status register, queue task count register, and instruction count threshold register (TH) in the dynamically reconfigurable task instruction distribution unit via the internal bus. This obtains the current empty / full status of the four task queues, the number of tasks cached in each FIFO, and the preset instruction count threshold. The information is then transmitted back to the general-purpose RISC core via the internal bus. The general-purpose RISC core executes a scheduling algorithm based on the read-back data: first, it determines the current task load type (low / medium or high load) based on the comparison result between the current task instruction count in the task status register group and TH, and the task type. Then, it combines the empty / full flag of the task queue status register with the value of the queue task count register to filter out target candidate queues that meet the conditions, completing the status pre-detection before task distribution.

[0074] Once the general-purpose RISC core determines the target candidate queue, it initiates a write request to the dynamically reconfigurable task instruction issuing unit via the internal bus, sequentially writing the following information: task DDR start address (recording the task's starting position in DDR), task instruction count (recording the total number of instructions N for the current task), FIFO ID configuration (specifying the target queue number 0-3 to be issued), and FIFO write enable. A single task issuance requires three bus read operations (to acquire status register group data) and four bus write operations (to write task information and control signals).

[0075] Furthermore, such as Figure 6The timing diagram shown illustrates the task information reading operation. Before initiating the task information reading, the external processor core first determines two types of status signals from the task instruction controller: the first is the task valid signal (ASIP_O_valid), which is set by the controller when there is task information to be executed in a queue memory; the second is the queue empty status signal (Queue_Empty), which is set to 1 when there is no task data in a queue memory.

[0076] The external processor core determines whether a valid, readable task exists in the target task queue memory by checking the ASIP_O_valid and Queue_Empty signals. Only after confirming the presence of a valid task in the queue memory will a read request be triggered. If not, it continuously listens for status signals to avoid invalid reads. Once a valid task is found, the external processor core immediately initiates a read request signal (ASIP_Read). This read request signal uses a one-to-one mapping design with the task queue memory to ensure the directionality of the request signal and prevent simultaneous read operations from multiple queue memories.

[0077] After the dynamically reconfigurable task instruction issuing unit samples the read request signal from the external processor core, it first determines the ID of the target task queue memory based on the bit information; second, it reads 64-bit wide task information data from the queue memory; finally, it outputs the read task information to the corresponding data interface, where the high 32 bits of data are the starting position of the task instruction in DDR, and the low 32 bits of data are the number of task instructions.

[0078] In one possible implementation, the data width of the task storage queue FIFO is 64 bits, and the depth is set to 16 items.

[0079] In detail, the task queue memory comprises four identical storage units with a data width of 64 bits and a depth of 16 items, adapted to the data volume of wireless communication computing tasks, and used to store dedicated task information. Its storage content and mapping relationship are dynamically configured by the dynamic task instruction issuance unit according to the application scenario.

[0080] The peripheral modules include: RAM, used to cache raw data and intermediate results; CLINT, used for system timer interrupts and task queue clearing; and UART and GPIO, used for debugging and peripheral control.

[0081] Specifically, such as Figure 7 The core circuit structure diagram of the dynamically reconfigurable task instruction issuing unit shown above realizes the directional storage of task information to the queue memory through bus control signals; and triggers the reading and output of task information in the queue memory through externally input read request signals.

[0082] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0083] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A multi-task scheduling method for a multi-core processor architecture, characterized in that, include: S1, System Initialization: After starting the general-purpose RISC core, the peripheral modules are initialized; the dynamic reconfigurable task instruction issuing unit initializes the empty / full state of each task queue memory, sets the task queue status register to empty, and feeds back the initialization completion signal to the general-purpose RISC core through the system bus; the external processor core waits to receive the task information in the task queue memory. S2, Task distribution judgment: The host computer sends wireless communication computing task information to the Config_RF of the general RISC core. After the general RISC core reads the task information into the RF, it starts the scheduling judgment process. After the judgment is completed, the general RISC core sends the task information to the dynamic reconfigurable task instruction issuing unit through the system bus. After the distribution is completed, the bus resources are released immediately. S3, Task queue management: The dynamic reconfigurable task instruction issuing unit writes the task information into the corresponding task queue memory according to the queue ID in the task information issued by the general RISC core; The control unit updates the status of the task queue status register corresponding to the task queue memory in real time and synchronizes it to the general-purpose RISC core. S4, Multi-core task execution and response: When the external processor verifies the status of the corresponding task queue memory, it reads the task information from the queue and executes the computation task when it detects that there is a task to be executed in the task queue memory. After the execution is completed, the status of the task queue memory is refreshed, and the general-purpose RISC core sends new task information according to the real-time status of the task queue status register.

2. The multi-task scheduling method for a multi-core processor architecture as described in claim 1, characterized in that, The scheduling decision process includes: S2.1, Read the basic task information stored in the Config_RF, including: the starting address of the task instruction in DDR, the total number of instructions, and the task type; S2.2, Obtain the real-time status of the registers in the dynamically reconfigurable task instruction issuing unit through the system bus; S2.3, dynamically determine the target task queue storage that is adapted to the complexity and queue status of this task based on the scheduling algorithm.

3. The multi-task scheduling method for a multi-core processor architecture as described in claim 2, characterized in that, The scheduling algorithm includes: S2.3.1, Task Information Parsing and Status Acquisition: The general-purpose RISC core receives the task request issued by the APB, extracts the total number of task instructions N and the task type T, and reads three key states of the registers in the dynamically reconfigurable task instruction issuing unit through the system bus: the instruction count threshold register stores the critical value TH of the number of instructions processed by a single processor core, and the queue task count register stores the current number of tasks in the FIFO of the task storage queues bound to the four external processor cores. The task queue status register stores the queue's idle or active status. S2.3.2, Instruction Count Threshold Judgment and Processing Path Selection: If N≤TH and T=0, i.e., the current task is a low / medium load task, check... ,like If the depth is less than the FIFO depth threshold, the task will be assigned to the CORE0 queue; if... Once the FIFO depth threshold is reached, iterate through CORE1-3 to filter for queues that are idle. If an idle queue is found, assign the task to that CORE queue; otherwise, check... If there is a FIFO with a depth less than the FIFO threshold, the task is assigned to the corresponding CORE queue. If all queues reach the threshold, the filtering process is repeated until an empty queue is found before task assignment. If N>TH or T=1, that is, the current task is a high-load task, the dynamic expansion mechanism is triggered to filter the idle queues in CORE1~3 and assign them to the CORE queue. If there are no idle queues, the filtering process is repeated until an empty queue is found before task assignment. S2.3.3, Task Allocation and Status Update: Write task information to the target FIFO, including: DDR initial address, total number of instructions N, and synchronously update the corresponding queue task count register.

4. A multi-task scheduling and control unit with a multi-core processor architecture, characterized in that, The scheduling control unit applies the method as described in any one of claims 1-3, including: A general-purpose RISC core is used for task allocation, load balancing, and operation status control in multi-core processors. A dynamically reconfigurable task instruction issuing unit is used for task issuing and real-time load status sensing. The unit includes: a task queue memory for storing dedicated task information to be issued to an external processor core, comprising four homogeneous task storage queues (FIFOs); a task information register group for temporarily storing the raw task data issued by the general-purpose RISC core; a configuration register group for parsing system bus read / write requests, storing key parameters for task scheduling, and outputting FIFO control signals; and a control unit for scheduling and coordination during task instruction issuing. The peripheral modules include: RAM, used to cache raw data and intermediate results; CLINT, used for system timer interrupts and task queue clearing; and UART and GPIO, used for debugging and peripheral control.

5. A multi-task scheduling and control unit for a multi-core processor architecture as described in claim 4, characterized in that, The configuration register group includes: a task queue status register for storing the empty / full status of each task queue; an instruction count threshold register for storing the instruction count threshold for a single processor core to process a task; a queue task count register for storing the current number of tasks in the four task storage queues (FIFOs); a task DDR start address register for storing the starting address of the task to be executed in external DDR memory; a task instruction count register for storing the total number of external processor core-customized instructions contained in the current task; a FIFO ID configuration register for storing the target task queue number corresponding to the task to be issued; a FIFO write enable register for writing task information to the task storage queues (FIFOs); and a FIFO refresh register for forcibly refreshing the stored data of all task storage queues (FIFOs) for reset during task switching or exception handling.

6. A multi-task scheduling and control unit for a multi-core processor architecture as described in claim 4, characterized in that, The data width of the task storage queue FIFO is 64 bits, and the depth is set to 16 items.

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