A chip testing method based on multi-protocol burning and adaptive testing

Abstract

The present application relates to the technical field of chip testing, and particularly relates to a chip testing method based on multi-protocol burning and adaptive testing, which comprises the following steps: obtaining a communication establishment time and a communication stable rate based on a test mode corresponding to a physical interface of different types, determining a characteristic state of a chip based on the communication establishment time and the communication stable rate; extracting an equivalent impedance factor value of all chips in a first characteristic state to obtain an impedance threshold value for making the chips fall into the first characteristic state, determining a process drift index of a current batch of chips based on a comparison result of the equivalent impedance factor value and the impedance threshold value; determining whether a process fluctuation of the chip is a process drift based on the process drift index, and adjusting a critical upper limit value of the characteristic state of the chip. The present application realizes precise excitation of implicit defects and adaptive calibration of process drift through multi-protocol lateral comparison diagnosis, on-chip impedance backstepping and design tolerance-process line threshold dynamic closed loop.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip testing method based on multi-protocol programming and adaptive testing. Background Technology

[0002] With the rapid development of fields such as the Industrial Internet of Things (IIoT), smart cars, and high-performance computing, the application scenarios of chips have expanded from single, controllable environments to the complex, ever-changing, and harsh real-world physical world. A microcontroller may need to instantly initiate vehicle communication in -40°C temperatures, or it may need to simultaneously process multiple sensor data streams and high-speed network transmissions at 85°C temperatures. This poses unprecedented challenges to the dynamic stability and energy efficiency matching of chips throughout their entire lifecycle and under all operating conditions. As the last line of defense for ensuring product quality, chip testing has evolved from "selecting working chips" to "identifying chips that can reliably operate in complex scenarios." However, as chip application scenarios become increasingly complex, existing testing methods face two fundamental contradictions that are difficult to reconcile:

[0003] I. The contradiction between static testing and dynamic failure: Traditional testing is usually conducted under fixed load and normal temperature conditions, using "pass / fail" as a binary criterion. However, numerous field failure cases show that latent chip faults are often only triggered under specific combinations of sudden load changes and high-temperature stress. Such dynamic failures cannot be captured by static testing, leading to the quality dilemma of "production line qualified, field failure".

[0004] Second, the contradiction between uniform standards and individual deviations: Due to slight fluctuations in manufacturing processes, the electrical characteristics (such as dynamic voltage drop response and critical stability voltage) of each chip exhibit objective differences. However, current testing applies the exact same nominal test parameters to all chips. This results in: potential risks of chips with weaker characteristics going unidentified; and energy efficiency potential of chips with superior characteristics being wasted. This "one-size-fits-all" approach is essentially a compromise between testing accuracy and process deviations.

[0005] The fundamental cause of the above contradiction is that the existing testing system does not have the ability of "active excitation-quantitative diagnosis-individual compensation". It is unable to dynamically evaluate the stability margin of the chip under specific stress, nor can it assign each chip its own unique optimal operating parameters based on actual measurement differences.

[0006] Therefore, there is an urgent need for a new chip testing method that can actively construct dynamic stress scenarios, quantitatively extract individual characteristic boundaries, and achieve parameter-level personalized adaptation.

[0007] Chinese Patent Publication No. CN101008909A discloses a chip and a chip testing method. The chip is applied to a computer system, wherein the two ends of the chip are respectively connected to a high-speed bus and a low-speed bus. The chip includes a test control unit, a preset address data, receives an external signal transmitted from the low-speed bus, and determines whether to compare the address data of the external signal with the preset address data based on a control signal. An upstream component control unit is connected to the high-speed bus and the test control unit to transmit the external signal to the high-speed bus. A downstream component control unit is also connected to the high-speed bus and the test control unit to transmit the external signal to the low-speed bus. Therefore, the chip and chip testing method described herein have the following problems:

[0008] Traditional pass / fail tests struggle to capture latent faults that only occur under specific load and temperature combinations. Each chip has a different optimal operating point (such as minimum stable voltage) due to slight manufacturing differences, and testing with uniform nominal parameters can lead to performance waste or potential risks. Summary of the Invention

[0009] To address this, the present invention provides a chip testing method based on multi-protocol programming and adaptive testing, which overcomes the problems in the prior art where testing is difficult to capture latent faults that are triggered only under specific load and temperature combinations, and where testing with uniform nominal parameters can lead to performance waste or potential risks.

[0010] To achieve the above objectives, this invention provides a chip testing method based on multi-protocol programming and adaptive testing, comprising:

[0011] The communication establishment time and communication stability rate are obtained based on the test modes corresponding to different types of physical interfaces, and the characteristic state of the chip is determined based on the communication establishment time and the communication stability rate.

[0012] In response to the first stress scheme applied to the characteristic state, the chip junction temperature is adjusted to the high temperature characteristic temperature, the wake-up time temperature sensitivity coefficient and the load jump transient recovery time are obtained to determine the severity of the USB interface wake-up delay and to determine the required voltage boost and adjust the supply voltage.

[0013] In response to the characteristic state, a second stress scheme is applied, the electrical load of the SPI interface is adjusted to obtain several coefficients of variation of the actual transmission rate, and the severity of the insufficient SPI interface transmission rate is determined by combining the total number of readback data errors, and the SPI communication clock frequency is adjusted.

[0014] Based on the load state of the core load current of the control chip according to the first stress scheme, the core current and USB wake-up time corresponding to different load states are obtained in order to determine the first impedance factor and the second impedance factor to obtain the equivalent impedance factor.

[0015] The impedance characteristics of the chip are determined by obtaining the nonlinear exponent based on the first and second impedance factors, and the design value of the sensitivity coefficient is adjusted accordingly.

[0016] Extract the equivalent impedance factor values ​​of all chips in the first characteristic state, obtain the impedance threshold that makes the chip fall into the first characteristic state, and determine the process drift index of the current batch of chips based on the comparison results of the equivalent impedance factor values ​​and the impedance threshold.

[0017] The process drift index is used to determine whether chip process fluctuations are due to process drift, and the critical upper limit value for determining the characteristic state of the chip is adjusted accordingly.

[0018] Furthermore, the process of determining the characteristic state of the chip includes:

[0019] If the communication setup time of the USB interface exceeds the critical upper limit of the historical range, while the communication setup time of the JTAG interface and SPI interface, and the stable communication rate of the USB interface, JTAG interface and SPI interface are all within their respective historical ranges, then the chip is in the first characteristic state, and the chip characteristic is the USB interface wake-up delay.

[0020] If the stable communication rate of the SPI interface is lower than the critical lower limit of the historical range, while the communication setup time of the JTAG interface, SPI interface, and USB interface, as well as the stable communication rate of the USB interface and JTAG interface, are all within their respective historical ranges, then the chip is judged to be in the second characteristic state, and the chip characteristic is that the SPI interface transmission rate is insufficient.

[0021] Furthermore, if the communication setup time of all three interfaces is significantly longer and the stable communication rate of all three interfaces is significantly shorter, then the chip is judged to be in the third characteristic state, and the chip characteristic is that the overall clock is too slow or the global process deviation is too small.

[0022] Specifically, when the communication establishment time of the three sets of interfaces is greater than the critical upper limit of the corresponding historical range, it is determined that the communication establishment time of the three sets of interfaces is significantly too large; when the communication stability rate of the three sets of interfaces is lower than the critical lower limit of the corresponding historical range, it is determined that the communication stability rate of the three sets of interfaces is significantly too small.

[0023] Furthermore, the process of determining the severity of the USB interface wake-up delay includes:

[0024] If the wake-up time temperature sensitivity coefficient is greater than the first sensitivity coefficient threshold, and the load change transient recovery time is greater than the first load recovery threshold, then the severity of the USB interface wake-up delay is determined to be severe, and voltage compensation is required.

[0025] If the wake-up time temperature sensitivity coefficient is greater than the second sensitivity coefficient threshold, or the load jump transient recovery time is greater than the second load recovery threshold, then the severity of the USB interface wake-up delay is determined to be moderate, and a voltage compensation reference signal is issued.

[0026] Furthermore, the process of determining the severity of the insufficient SPI interface transmission rate includes:

[0027] Record the total number of readback data errors in several tests. If the proportion of the total number of errors in several tests is greater than the proportion threshold, the severity of the insufficient SPI interface transmission rate is judged as severe, and the chip is marked as unusable.

[0028] If the proportion of the total number of tests is less than the proportion threshold and the coefficient of variation is greater than or equal to the coefficient threshold, then the severity of the insufficient SPI interface transmission rate is judged to be moderate, and frequency reduction compensation is enabled to reduce the SPI communication clock frequency.

[0029] Furthermore, the core current corresponding to different load states includes idle core current, single-core core current, and dual-core core current;

[0030] The first impedance factor is calculated based on the USB wake-up time corresponding to the idle core current and the single-core core current, and the second impedance factor is calculated based on the USB wake-up time corresponding to the single-core current and the dual-core core current.

[0031] Obtain the equivalent impedance factor, which is the average of the first impedance factor and the second impedance factor.

[0032] Furthermore, the impedance deviation is calculated and denoted as a nonlinear exponent, whereby the impedance deviation is the absolute value of the difference between the first impedance factor and the second impedance factor.

[0033] If the nonlinearity index is greater than the difference evaluation value, it is determined that the chip has nonlinear impedance characteristics. Under the current chip sensitivity coefficient, the chip wake-up delay is caused by PDN process deviation, and the output suggests reducing the design value of the sensitivity coefficient.

[0034] Further, the impedance threshold of the equivalent impedance factor that causes the chip to fall into the first characteristic state is obtained.

[0035] If the proportion of the chip marked as the first characteristic state is greater than the proportion threshold when the equivalent impedance factor value is greater than any equivalent threshold, then the upper limit of the USB interface's tolerance to PDN impedance is determined to be the corresponding equivalent threshold.

[0036] Furthermore, when any equivalent impedance factor value is greater than the tolerance limit, the process drift index of the current batch of chips is calculated.

[0037] Furthermore, the process of determining whether chip process variations are due to process drift includes:

[0038] If the process drift index is less than or equal to the first index threshold, the process fluctuation is judged to be within the normal range, and the existing threshold is maintained unchanged.

[0039] If the process drift index is greater than the first index threshold and less than or equal to the second index threshold, then the chip process is determined to be drifting, and the critical upper limit value is adjusted.

[0040] If the process drift index is greater than the second index threshold, the chip process is judged to be seriously abnormal, and a process abnormality alarm is issued.

[0041] Compared with existing technologies, the beneficial effects of this invention are as follows: By establishing a three-level parameter mapping chain of interface communication parameters, on-chip physical parameters, and design tolerance parameters, this invention elevates chip testing from functional qualification screening to a new stage of quantitative extraction of physical characteristics and design feedback loop. In terms of testing, it utilizes testing equipment to non-destructively extract the equivalent impedance factor and nonlinearity index of the on-chip power distribution network without adding on-chip testing structures, transforming the chip's internal physical characteristics, which originally required destructive analysis, into continuously quantifiable indicators that can be obtained in real time. In terms of decision-making, it automatically establishes the correlation threshold between interface communication parameters and on-chip impedance parameters through statistical mapping, and achieves dynamic self-calibration of the judgment threshold based on batch-level process drift index, solving the problem of high misjudgment rate under process fluctuations in traditional fixed threshold methods. In terms of value, it transforms the testing system from a passive execution tool into an active feedback node, and the generated design sensitivity report can directly guide the interface circuit optimization of the next version of the chip, shortening the design defect discovery cycle from months of market returns to hours of mass production testing. This invention enables chip testing to simultaneously serve the triple goals of quality screening, process monitoring, and design improvement.

[0042] Furthermore, this invention performs horizontal comparative diagnosis in the field of chip testing. Through independent communication tests of three physical interfaces and cross-comparison of six parameters, it achieves precise localization of interface-level defects. This method does not rely on the chip's built-in self-test circuit; relying solely on the test system operation design, it can clearly diagnose ambiguous communication defects as three types of physical characteristic states: USB interface wake-up delay, insufficient SPI transmission rate, or global process deviation. Compared with traditional functional testing, this method can predict the risk of latent failures under high temperature and heavy load scenarios under normal temperature and no-load conditions, shifting the defect discovery window from the application end to the production line end. At the same time, through a database of historical qualified product parameter ranges and statistical tolerance thresholds, a quantifiable and traceable feature judgment standard is established, solving the subjective problem of relying on experience to set thresholds in traditional testing. It realizes a digital profile of the chip's hardware quality, providing accurate and reliable feature inputs for subsequent adaptive compensation.

[0043] Furthermore, this invention employs feature-driven dynamic stress precision excitation in chip testing. Unlike traditional testing that applies the same fixed stress to all chips, this method, based on the interface-level feature tags output from the first layer, customizes a directional stress scheme for each chip that is only related to its weakest module. It applies a combination of high temperature and dynamic load stress to USB wake-up delay chips and increased electrical load stress to SPI chips with insufficient speed. The test significantly amplifies latent defects that are completely normal under normal temperature and no load conditions, transforming them into quantifiable continuous parameter trajectories under specific stress. By extracting three core quantitative indicators—wake-up time temperature sensitivity coefficient, load jump transient recovery time, and rate variation coefficient—this method achieves non-destructive, continuous, and scalable measurement of interface timing margins, upgrading the traditional pass / fail binary judgment to a three-level quantitative classification of severe / moderate / mild defects.

[0044] Furthermore, traditional methods for measuring power supply impedance require specially designed test chips or probe stations directly attached to the power lines, which is not feasible for mass production testing. This invention utilizes the existing USB interface as a sensor, measuring the wake-up time variation under different loads to inversely deduce the on-chip PDN impedance without increasing any hardware cost. This invention precisely controls three quantized states of the core load current and measures the USB wake-up time under the corresponding states to inversely extract the equivalent impedance factor and nonlinearity index of the on-chip power distribution network. The consistency comparison between the first and second impedance factors is converted into a nonlinearity index to distinguish two different causes of USB wake-up delay: linear high impedance can be repaired through voltage compensation, while nonlinear defective types require design improvements. Through batch distribution statistics of the equivalent impedance factor, the sensitivity S-value of the current chip design to PDN process deviations is calculated, and suggestions to reduce the sensitivity coefficient are output.

[0045] Furthermore, this invention extracts the equivalent impedance factor distribution of the chip in the first characteristic state, establishing a direct mapping between the physical tolerance parameter PDN impedance threshold in the chip design stage and the judgment standard USB wake-up time threshold in the mass production testing stage; it introduces the batch-level process drift index into the threshold decision chain: when the process drift index is between 1.0 and 3.0, the system automatically updates the upper limit of the critical value to the current batch mean + 3 times the standard deviation, so that the test standard is adaptively adjusted with process fluctuations, completely solving the problem of high misjudgment rate of traditional fixed thresholds under process drift; when the drift index exceeds 3.0, the system immediately issues a process anomaly alarm, shifting the window for detecting systematic deviations in wafer manufacturing from after finished product testing to before packaging testing; this method evolves the test system from a passive execution tool to a process monitoring node, realizing dynamic alignment of quality screening standards, manufacturing process status, and chip design tolerances. Attached Figure Description

[0046] Figure 1This is a flowchart illustrating the chip testing method based on multi-protocol programming and adaptive testing in an embodiment of the present invention.

[0047] Figure 2 This is a flowchart illustrating the process of determining the severity of insufficient SPI interface transmission rate in an embodiment of the present invention.

[0048] Figure 3 This is a schematic diagram of the process for determining the impedance characteristics of a chip in an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram illustrating the process for determining whether chip process fluctuations are process drift in an embodiment of the present invention. Detailed Implementation

[0050] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0051] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0052] It should be noted that in the description of this invention, the terms "upper", "lower", "left", "right", "inner", "outer", etc., which indicate directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. This is only for the convenience of description and is not intended to indicate or imply that the device or element must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0053] Furthermore, it should be noted that, in the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0054] Please see Figures 1-4 As shown, Figure 1 This is a flowchart illustrating the chip testing method based on multi-protocol programming and adaptive testing in an embodiment of the present invention. Figure 2 This is a flowchart illustrating the process of determining the severity of insufficient SPI interface transmission rate in an embodiment of the present invention. Figure 3 This is a schematic diagram of the process for determining the impedance characteristics of a chip in an embodiment of the present invention; Figure 4This is a schematic diagram illustrating the process for determining whether chip process fluctuations are process drift in an embodiment of the present invention.

[0055] This invention provides a chip testing method based on multi-protocol programming and adaptive testing, comprising:

[0056] Step S1: Obtain the communication establishment time and communication stability rate based on the test modes corresponding to different types of physical interfaces, and determine the characteristic state of the chip based on the communication establishment time and the communication stability rate.

[0057] Step S2: In response to the first stress scheme applied to the characteristic state, the chip junction temperature is adjusted to the high temperature characteristic temperature, the wake-up time temperature sensitivity coefficient and the load jump transient recovery time are obtained to determine the severity of the USB interface wake-up delay and to determine the required voltage boost amount to adjust the power supply voltage.

[0058] Step S3: In response to the characteristic state, apply a second stress scheme, adjust the electrical load of the SPI interface to obtain several coefficients of variation of the actual transmission rate, combine the total number of readback data errors to determine the severity of the insufficient SPI interface transmission rate, and adjust the SPI communication clock frequency.

[0059] Step S4: Based on the load state of the core load current of the control chip according to the first stress scheme, obtain the core current and USB wake-up time corresponding to different load states, so as to determine the first impedance factor and the second impedance factor and obtain the equivalent impedance factor.

[0060] Step S5: Obtain the nonlinear exponent based on the first impedance factor and the second impedance factor to determine the impedance characteristics of the chip, and adjust the design value of the sensitivity coefficient.

[0061] Step S6: Extract the equivalent impedance factor values ​​of all chips in the first characteristic state, obtain the impedance threshold that makes the chip fall into the first characteristic state, and determine the process drift index of the current batch of chips based on the comparison results of the equivalent impedance factor values ​​and the impedance threshold.

[0062] Step S7: Determine whether the chip process fluctuation is due to process drift based on the process drift index, and adjust the critical upper limit value for determining the characteristic state of the chip.

[0063] Specifically, chip testing presents a contradiction between static testing and dynamic failure detection. Traditional pass / fail tests struggle to capture latent faults triggered only under specific load and temperature combinations. There is also a conflict between standardized testing and individual variations; each chip, due to slight manufacturing differences, has a different optimal operating point, such as a minimum stable voltage, making standardized parameter testing wasteful or potentially risky. This invention elevates chip testing from functional qualification screening to a new stage of quantitative extraction of physical characteristics and design feedback loop by establishing a three-level parameter mapping chain of interface communication parameters, on-chip physical parameters, and design tolerance parameters. In terms of testing dimensions, it utilizes testing equipment to non-destructively extract the equivalent impedance factor and non-equivalent impedance of the on-chip power distribution network without adding on-chip test structures. The linear index transforms the internal physical characteristics of chips, which previously required destructive analysis, into continuously quantifiable indicators that can be obtained in real time. In terms of decision-making, it automatically establishes threshold relationships between interface communication parameters and on-chip impedance parameters through statistical mapping, and achieves dynamic self-calibration of the judgment threshold based on batch-level process drift indices, solving the problem of high false positive rates in traditional fixed threshold methods under process fluctuations. In terms of value, it transforms the testing system from a passive execution tool into an active feedback node, and the generated design sensitivity report can directly guide the optimization of interface circuits in the next version of the chip, shortening the design defect discovery cycle from months of market returns to hours of mass production testing. This invention enables chip testing to simultaneously serve the triple goals of quality screening, process monitoring, and design improvement.

[0064] Standard test data blocks are written to the chip's internal SRAM sequentially through three physical interfaces: JTAG, SPI, and USB. This performs multi-protocol independent communication quality testing on the chip. After each communication, a readback verification is performed to record precise timing and electrical parameters.

[0065] Specifically, the test mode for the JTAG interface is the JTAG communication mode, which involves writing data blocks via the JTAG protocol for readback verification; the test mode for the SPI interface is the SPI communication mode, which involves writing data blocks via the SPI protocol for readback verification; and the test mode for the USB interface is the USB communication mode, which involves writing data blocks via the USB protocol for readback verification.

[0066] Obtain the communication establishment time and communication stability rate under the test modes corresponding to the three physical interfaces;

[0067] Specifically, the communication establishment time is the time taken from initiating a connection to receiving the first valid response under the test modes corresponding to the three physical interfaces, in microseconds; the communication stability rate is the actual data throughput per unit time under the stable transmission phase in the test modes corresponding to the three physical interfaces, in Mbps.

[0068] In practice, the data blocks written can have exactly the same content, such as 1024 bytes of 0x55, or they can be different, as long as the data block length is the same.

[0069] The communication establishment time and communication stability rate of the three physical interfaces under their respective test modes are compared one by one with the historical qualified product parameter range database of this chip model.

[0070] If the communication setup time of the USB interface exceeds the critical upper limit of the historical range, while the communication setup time of the JTAG interface and SPI interface, and the stable communication rate of the USB interface, JTAG interface and SPI interface are all within their respective historical ranges, then the chip is in the first characteristic state, and the chip characteristic is the USB interface wake-up delay.

[0071] The chip's digital logic core, clock network, and power network are generally healthy, but there is a slight deviation in the initialization circuit or reference clock of the USBPHY module, which causes the time from reset to readiness to be extended. This deviation does not affect the function under normal temperature and no-load conditions, but may worsen under high temperature or sudden load changes.

[0072] If the stable communication rate of the SPI interface is lower than the critical lower limit of the historical range, while the communication establishment time of the JTAG interface, SPI interface, and USB interface, as well as the stable communication rate of the USB interface and JTAG interface, are all within their respective historical ranges, then the chip is judged to be in the second characteristic state, and the chip characteristic is that the SPI interface transmission rate is insufficient.

[0073] The chip's overall process is normal, but the output drive capability of the SPI interface is weak or the input sampling timing margin is too small, which makes it impossible to complete high-speed data transmission at the standard clock frequency. This deviation may not cause errors in short-distance transmission at room temperature, but it is very easy to cause communication failure in long-trace, heavy-load or high-temperature scenarios.

[0074] If the communication setup time of all three interfaces is significantly longer and the communication stability rate of all three interfaces is significantly shorter, then the chip is judged to be in the third characteristic state, and the chip characteristic is that the overall clock is too slow or the global process deviation is too small.

[0075] The fact that all communication interfaces of the chip exhibit consistently low performance indicates that the problem is not limited to a specific module, but is global. Possible causes include: a slow main clock frequency, a low core voltage, or a slow overall wafer manufacturing process. Such chips require global compensation.

[0076] In practice, when the communication establishment time of the three sets of interfaces is greater than the critical upper limit of the corresponding historical range, it is determined that the communication establishment time of the three sets of interfaces is significantly too large; when the communication stability rate of the three sets of interfaces is lower than the critical lower limit of the corresponding historical range, it is determined that the communication stability rate of the three sets of interfaces is significantly too small.

[0077] If all six parameters are within the historical range, or if the communication establishment time and communication stability rate of the three sets of interfaces do not meet any of the characteristic states, then the chip is judged to have no significant characteristics, the chip enters the standard test process, and does not trigger subsequent adaptive compensation.

[0078] The historical range is a range of historical qualified product parameters consisting of the communication establishment time and communication stability rate of a number of historical qualified products corresponding to the three physical interfaces. The upper limit of the critical range is 115% of the upper limit of the historical range, and the lower limit of the critical range is 85% of the lower limit of the historical range.

[0079] The historical range of qualified product parameters is derived from the test data of at least 1,000 known good chips, including the mean μ and standard deviation σ of each parameter. The qualified range is defined as [μ-3σ, μ+3σ].

[0080] Specifically, this invention performs horizontal comparative diagnosis in the field of chip testing. Through independent communication tests of three physical interfaces and cross-comparison of six parameters, it achieves precise localization of interface-level defects. This method does not rely on the chip's built-in self-test circuit; relying solely on the test system operation design, it can clearly diagnose ambiguous communication problems as three types of physical characteristic states: USB interface wake-up delay, insufficient SPI transmission rate, or global process deviation. Compared with traditional functional testing, this method can predict the risk of latent failures under high temperature and heavy load scenarios under normal temperature and no-load conditions, shifting the defect discovery window from the application end to the production line end. At the same time, through a database of historical qualified product parameter ranges and statistical tolerance thresholds, a quantifiable and traceable feature judgment standard is established, solving the subjective problem of relying on experience to set thresholds in traditional testing. It realizes a digital profile of the chip's hardware quality, providing accurate and reliable feature inputs for subsequent adaptive compensation.

[0081] For each characteristic state, a dynamic stress combination that is most relevant to that characteristic state is designed. Under stress, the continuous change trajectory of key parameters is continuously monitored, and the severity of the characteristic is quantitatively assessed by trajectory shape and correlation ratio.

[0082] The chip is in a first characteristic state, and a first stress scheme is applied. The first stress scheme is to raise the chip junction temperature to a high temperature characteristic temperature and maintain it stably through a temperature control platform, and instruct the chip to execute a periodic load cycle. The load cycle is designed to create periodic, large current steps on the chip core power network, thereby generating periodic voltage drops.

[0083] The communication establishment time of the USB interface is repeatedly obtained according to the initial detection cycle, and the change trajectory of the communication establishment time of several USB interfaces over time is recorded.

[0084] In practice, the periodic load cycle is an idle-full-core full-frequency calculation-idle cycle with a period of 100ms and a duty cycle of 50%. The high-temperature characteristic temperature is 85°C, and the initial detection period is 10s.

[0085] The communication establishment time of the USB interface before the first stress scheme is applied is recorded as the baseline wake-up time. The average value of the communication establishment time of the USB interface during the three initial detection cycles after the first stress scheme is applied, when the chip junction temperature stabilizes at the high temperature characteristic temperature, is recorded as the high temperature steady-state wake-up time.

[0086] The temperature change caused by the rise of the chip junction temperature to the high temperature characteristic temperature is measured, and the change in the communication establishment time of the USB interface caused by the unit temperature change is recorded as the wake-up time temperature sensitivity coefficient, with the unit being μs / °C. The wake-up time temperature sensitivity coefficient = (high temperature steady-state wake-up time - reference wake-up time) / temperature change. In the implementation, the temperature change is 85-25.

[0087] In the periodic load cycle, the load transition transient recovery time is obtained. The load transition transient recovery time is the time required for the communication establishment time after the full-core full-frequency computing switches to idle to recover to within 90% of the baseline wake-up time, in milliseconds.

[0088] If the wake-up time temperature sensitivity coefficient is greater than the first sensitivity coefficient threshold, and the load change transient recovery time is greater than the first load recovery threshold, then the severity of the USB interface wake-up delay is determined to be severe, and voltage compensation is required.

[0089] If the wake-up time temperature sensitivity coefficient is greater than the second sensitivity coefficient threshold, or the load jump transient recovery time is greater than the second load recovery threshold, then the severity of the USB interface wake-up delay is determined to be moderate, and a voltage compensation reference signal is issued.

[0090] In practice, the first sensitivity threshold is 5.0 μs / °C, the second sensitivity threshold is 3.0 μs / °C, the first load recovery threshold is 50 ms, and the second load recovery threshold is 30 ms.

[0091] Specifically, when calibrating the sensitivity coefficient threshold, at least 1000 known good chips are selected, and their wake-up time temperature sensitivity coefficient is measured under standard test conditions. The distribution is statistically analyzed, and the 95th percentile is defined as the first sensitivity coefficient threshold, and the 75th percentile is defined as the second sensitivity coefficient threshold. When calibrating the load recovery threshold, at least 1000 known good chips are selected, and their load jump transient recovery time is measured under standard stress conditions. The distribution is statistically analyzed, and the maximum allowable value specified in the chip specification is defined as the first load recovery threshold, and the 90th percentile is defined as the second load recovery threshold.

[0092] Understandably, the first sensitivity threshold is preset to a relatively high value to characterize severely excessive temperature sensitivity, exceeding the wake-up time temperature sensitivity coefficient of 95% of good chips during preset calibration; the second sensitivity threshold is preset to a moderate value to characterize significantly high temperature sensitivity, exceeding the wake-up time temperature sensitivity coefficient of 75% of good chips during preset calibration; the first load recovery threshold is preset to a relatively high value to characterize severely excessive recovery time, using the maximum allowable value specified in the specification; the second load recovery threshold is preset to a moderate value to characterize significantly long recovery time, exceeding the load jump transient recovery time of 90% of good chips during preset calibration.

[0093] For chips whose USB interface wake-up latency is classified as moderate or above, a dynamic voltage compensation strategy is adopted.

[0094] Specifically, the wake-up delay of the USBPHY is negatively correlated with the supply voltage. For every ΔV increase in voltage, the wake-up time is shortened by Ki μs. Based on the measured wake-up time temperature sensitivity coefficient and the load transition transient recovery time, the required voltage rise is calculated.

[0095] Voltage rise = K1 × (base wake-up time - target wake-up time) + K2 × (load transition transient recovery time - target transient recovery time), where the target wake-up time is the average communication establishment time of several historical qualified products, the target transient recovery time is 30ms, and K1 and K2 are empirical coefficients for the voltage rise corresponding to the communication wake-up time and the load transition transient recovery time, which are determined through the engineering verification phase of this chip model, and the values ​​range from 0.001~0.01V / μs and 0.001~0.005V / ms.

[0096] It is understood that in this embodiment, K1 and K2 are empirical coefficients of the chip model of the embodiment. If the USB model is changed, the empirical coefficients of the voltage rise corresponding to the communication wake-up time and the load transition transient recovery time need to be re-determined.

[0097] The chip is in the second characteristic state, and a second stress scheme is applied. The second stress scheme is to increase the electrical load of the SPI interface and perform SPI data block write-readback tests several times in a row. The test rate is the highest SPI clock frequency specified in the chip's datasheet.

[0098] During implementation, a fixed 50pF load capacitor was connected in parallel on the SPI clock line, and 100 consecutive SPI data block write-readback tests were performed. The data block length was 256 bytes, and the chip datasheet specified a maximum SPI clock frequency of 50MHz.

[0099] Obtain the actual transmission rate of any test in several tests, and calculate the coefficient of variation of several actual transmission rates. It can be understood that the coefficient of variation is the ratio of the standard deviation to the mean. The coefficient of variation reflects the stability of the chip's SPI interface under heavy load, rather than the absolute value of the speed. The greater the fluctuation, the tighter the timing margin.

[0100] Record the total number of readback data errors in several tests. If the proportion of the total number of errors in several tests is greater than the proportion threshold, the severity of the insufficient SPI interface transmission rate is judged as severe, and the chip is marked as unusable.

[0101] If the proportion of the total number of tests is less than the proportion threshold and the coefficient of variation is greater than or equal to the coefficient threshold, then the severity of the insufficient SPI interface transmission rate is judged to be moderate, and frequency reduction compensation is enabled to reduce the SPI communication clock frequency.

[0102] During implementation, the SPI communication clock frequency is determined by consulting a pre-generated SPI frequency range table based on the coefficient of variation. When the coefficient of variation is in the range of 10%-15%, the SPI communication clock frequency is 40MHz with slight fluctuations and a small frequency reduction. When the coefficient of variation is in the range of 15%-20%, the SPI communication clock frequency is 33MHz with obvious fluctuations and a moderate frequency reduction.

[0103] The ratio threshold is 5%, and the coefficient threshold is 10%.

[0104] Specifically, this invention employs feature-driven dynamic stress precision excitation in chip testing. Unlike traditional testing that applies the same fixed stress to all chips, this method, based on the interface-level feature tags output from the first layer, customizes a directional stress scheme for each chip that is only related to its weakest module. It applies a combination of high temperature and dynamic load stress to USB wake-up delay chips and increased electrical load stress to SPI chips with insufficient speed. The test significantly amplifies latent defects that are completely normal under normal temperature and no load conditions, transforming them into quantifiable continuous parameter trajectories under specific stress. By extracting three core quantitative indicators—wake-up time temperature sensitivity coefficient, load jump transient recovery time, and rate variation coefficient—this method achieves non-destructive, continuous, and scalable measurement of interface timing margins, upgrading the traditional pass / fail binary judgment to a three-level quantitative classification of severe / moderate / mild defects.

[0105] After the chip is in the first characteristic state and the power supply voltage is adjusted, the core load current of the control chip operates in three different load states in sequence. The load states include idle mode, single-core full load mode and dual-core full load mode. The core load current corresponding to the idle mode is the idle core current, the core load current corresponding to the single-core full load mode is the single core current, and the core load current corresponding to the dual-core full load mode is the dual core current.

[0106] Under each load condition, the USB wake-up time was measured repeatedly. In practice, the measurement was repeated 10 times under each load condition and the average value was taken.

[0107] It is understandable that the internal power supply voltage of the chip = external power supply voltage - (load current × on-chip PDN impedance), and the change in wake-up time caused by load change = S × equivalent resistance of on-chip power distribution network × change in load current.

[0108] In the formula, S is the sensitivity coefficient of USB wake-up time to power supply voltage, is the chip-specific parameter that needs to be calibrated, the equivalent resistance of the on-chip power distribution network is the core unknown that needs to be deduced, and USB wake-up time is the communication setup time of the USB interface.

[0109] The first impedance factor is calculated based on the USB wake-up time corresponding to the idle core current and the single-core core current, and the second impedance factor is calculated based on the USB wake-up time corresponding to the single-core current and the dual-core core current.

[0110] The first impedance factor = the sensitivity coefficient of the supply voltage S × the equivalent resistance of the on-chip power distribution network = (USB wake-up time corresponding to single-core current - USB wake-up time corresponding to idle core current) / (idle core current - single-core core current), and the second impedance factor = (USB wake-up time corresponding to dual-core current - USB wake-up time corresponding to single-core current) / (single-core current - dual-core current).

[0111] Specifically, the equivalent impedance factor is obtained. The equivalent impedance factor is the average of the first impedance factor and the second impedance factor, which reflects the chip's sensitivity to changes in load current. The larger the equivalent impedance factor, the more severe the deterioration of USB wake-up time caused by the same load change.

[0112] The impedance deviation is calculated and denoted as the nonlinearity index. The impedance deviation is the absolute value of the difference between the first impedance factor and the second impedance factor. If the nonlinearity index is greater than the difference evaluation value, it is determined that the chip has nonlinear impedance characteristics. Under the current chip power supply voltage sensitivity coefficient S, the chip has a wake-up delay due to PDN process deviation. The output suggests reducing the design value of the power supply voltage sensitivity coefficient S.

[0113] For example, in implementation, the USBPHY design has a sensitivity coefficient S=3.2μs / mΩ to the supply voltage of the PDN impedance, causing 5% of the chips to have wake-up delay due to PDN process deviation. It is recommended to design to reduce the sensitivity coefficient S value of the supply voltage.

[0114] The difference evaluation value is 20%.

[0115] Specifically, traditional methods for measuring power supply impedance require specially designed test chips or probe stations directly attached to the power lines, which is impractical for mass production testing. This invention utilizes the existing USB interface as a sensor, measuring the wake-up time variation under different loads to inversely deduce the on-chip PDN impedance without increasing hardware costs. This invention precisely controls three quantized states of the core load current and measures the USB wake-up time under the corresponding states to inversely extract the equivalent impedance factor and nonlinearity index of the on-chip power distribution network. The consistency comparison between the first and second impedance factors is converted into a nonlinearity index to distinguish two different causes of USB wake-up delay: linear high impedance can be repaired through voltage compensation, while nonlinear defective types require design improvements. Through batch distribution statistics of the equivalent impedance factor, the sensitivity coefficient S value of the current chip design to the power supply voltage deviation of the PDN process is calculated, and suggestions to reduce the sensitivity coefficient are output.

[0116] Extract the equivalent impedance factor values ​​of all chips in the first characteristic state, plot the distribution histogram, and obtain the impedance threshold of the equivalent impedance factor that makes the chip fall into the first characteristic state.

[0117] In practice, if the proportion of the chip marked as the first characteristic state is greater than the proportion threshold when the equivalent impedance factor value is greater than any equivalent threshold, then the upper limit of the tolerance of the USB interface to the PDN impedance is determined to be the corresponding equivalent threshold. In this embodiment, the equivalent threshold is 1.2.

[0118] For example, when the equivalent impedance factor is greater than 1.2, the chip has a 90% probability of being marked as having USB wake-up delay, and when the equivalent impedance factor is greater than 1.5, the probability rises to 100%.

[0119] When any equivalent impedance factor value is greater than the tolerance limit, calculate the process drift index of the current batch of chips. Process drift index = |mean of USB wake-up time of the current batch of chips - mean of USB wake-up time of historical qualified products| / standard deviation of USB wake-up time of historical qualified products.

[0120] If the process drift index is less than or equal to the first index threshold, the process fluctuation is judged to be within the normal range, and the existing threshold is maintained unchanged.

[0121] If the process drift index is greater than the first index threshold and less than or equal to the second index threshold, then the chip process is determined to be drifting, and the critical upper limit value is adjusted.

[0122] Specifically, the critical upper limit value is adjusted to the sum of the average USB wake-up time of the current batch of chips and three times the standard deviation.

[0123] If the process drift index is greater than the second index threshold, the chip process is judged to be seriously abnormal, and a process abnormality alarm is issued.

[0124] During implementation, the mean and standard deviation of the USB wake-up time of the first 1,000 chips in the current batch are calculated, and the long-term qualified product statistical benchmark for this product model is read from the historical database. This benchmark is derived from the accumulation of at least 1,000 known good chips.

[0125] For example, the mean USB wake-up time of historical qualified products is 500μs, and the standard deviation is 50μs;

[0126] The average USB wake-up time of the first 1000 chips in this batch is 520μs, and the standard deviation is 60μs, which is within the normal range of process fluctuations.

[0127] The first index threshold is 1.0, and the second index threshold is 3.0.

[0128] Specifically, this invention extracts the equivalent impedance factor distribution of the chip in the first characteristic state and establishes a direct mapping between the physical tolerance parameter PDN impedance threshold in the chip design stage and the judgment standard USB wake-up time threshold in the mass production testing stage. It introduces the batch-level process drift index into the threshold decision chain: when the process drift index is between 1.0 and 3.0, the system automatically updates the upper limit of the critical value to the current batch mean + 3 times the standard deviation, allowing the test standard to adaptively adjust with process fluctuations, completely solving the problem of high false judgment rate under traditional fixed thresholds during process drift. When the drift index exceeds 3.0, the system immediately issues a process anomaly alarm, shifting the window for detecting systematic deviations in wafer manufacturing from after finished product testing to before packaging testing. This method evolves the test system from a passive execution tool into a process monitoring node, achieving dynamic alignment of quality screening standards, manufacturing process status, and chip design tolerances.

[0129] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

[0130] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip testing method based on multi-protocol burn-in and adaptive testing, characterized in that, include: Based on the test modes corresponding to different types of physical interfaces, the communication establishment time and communication stability rate are obtained to determine the characteristic state of the chip. The characteristic state of the chip includes three types of physical characteristic states: USB interface wake-up delay, insufficient SPI transmission rate, or global process deviation. Based on the aforementioned characteristic state, a first stress scheme is applied, wherein the first stress scheme involves adjusting the chip junction temperature to a high-temperature characteristic temperature, obtaining the wake-up time temperature sensitivity coefficient and the load jump transient recovery time to determine the severity of the USB interface wake-up delay, and adjusting the power supply voltage to determine the required voltage boost. A second stress scheme is applied based on the aforementioned characteristic state. The second stress scheme involves adjusting the electrical load of the SPI interface to obtain several coefficients of variation of the actual transmission rate, combining the total number of readback data errors to determine the severity of the insufficient SPI interface transmission rate, and adjusting the SPI communication clock frequency. Based on the first stress scheme, the load state of the core load current of the control chip is controlled, and the core current and USB wake-up time corresponding to different load states are obtained to determine the first impedance factor and the second impedance factor to obtain the equivalent impedance factor; wherein, the first impedance factor is calculated based on the USB wake-up time corresponding to the idle core current and the single-core core current, and the second impedance factor is calculated based on the USB wake-up time corresponding to the single-core core current and the dual-core core current. The impedance characteristics of the chip are determined by obtaining the nonlinear index based on the first impedance factor and the second impedance factor, and the design value of the sensitivity coefficient of the power supply voltage is adjusted. The nonlinear index is the absolute value of the difference between the first impedance factor and the second impedance factor. Extract the equivalent impedance factor values ​​of all chips in the first characteristic state, obtain the impedance threshold that makes the chip fall into the first characteristic state, and determine the process drift index of the current batch of chips based on the comparison results of the equivalent impedance factor values ​​and the impedance threshold. The chip characteristic of the first characteristic state is the USB interface wake-up delay. The process drift index is used to determine whether chip process fluctuations are due to process drift, and the critical upper limit value for determining the characteristic state of the chip is adjusted accordingly.

2. The chip testing method based on multi-protocol programming and adaptive testing according to claim 1, characterized in that, The process of determining the characteristic state of a chip includes: If the communication setup time of the USB interface exceeds the critical upper limit of the historical range, while the communication setup time of the JTAG interface and SPI interface, and the stable communication rate of the USB interface, JTAG interface and SPI interface are all within their respective historical ranges, then the chip is in the first characteristic state, and the chip characteristic is the USB interface wake-up delay. If the stable communication rate of the SPI interface is lower than the critical lower limit of the historical range, while the communication setup time of the JTAG interface, SPI interface, and USB interface, as well as the stable communication rate of the USB interface and JTAG interface, are all within their respective historical ranges, then the chip is judged to be in the second characteristic state, and the chip characteristic is that the SPI interface transmission rate is insufficient.

3. The chip testing method based on multi-protocol programming and adaptive testing according to claim 2, characterized in that, If the communication setup time of all three interfaces is significantly longer and the communication stability rate of all three interfaces is significantly shorter, then the chip is judged to be in the third characteristic state, and the chip characteristic is that the overall clock is too slow or the global process deviation is too small. Specifically, when the communication establishment time of the three sets of interfaces is greater than the critical upper limit of the corresponding historical range, it is determined that the communication establishment time of the three sets of interfaces is significantly too large; when the communication stability rate of the three sets of interfaces is lower than the critical lower limit of the corresponding historical range, it is determined that the communication stability rate of the three sets of interfaces is significantly too small.

4. The chip testing method based on multi-protocol programming and adaptive testing according to claim 3, characterized in that, The process of determining the severity of USB interface wake-up latency includes: If the wake-up time temperature sensitivity coefficient is greater than the first sensitivity coefficient threshold, and the load change transient recovery time is greater than the first load recovery threshold, then the severity of the USB interface wake-up delay is determined to be severe, and voltage compensation is required. If the wake-up time temperature sensitivity coefficient is greater than the second sensitivity coefficient threshold, or the load jump transient recovery time is greater than the second load recovery threshold, then the severity of the USB interface wake-up delay is determined to be moderate, and a voltage compensation reference signal is issued.

5. The chip testing method based on multi-protocol programming and adaptive testing according to claim 4, characterized in that, The process of determining the severity of insufficient SPI interface transmission rate includes: Record the total number of readback data errors in several tests. If the proportion of the total number of errors in several tests is greater than the proportion threshold, the severity of the insufficient SPI interface transmission rate is judged as severe, and the chip is marked as unusable. If the proportion of the total number of tests is less than the proportion threshold and the coefficient of variation is greater than or equal to the coefficient threshold, then the severity of the insufficient SPI interface transmission rate is judged to be moderate, and frequency reduction compensation is enabled to reduce the SPI communication clock frequency.

6. The chip testing method based on multi-protocol programming and adaptive testing according to claim 5, characterized in that, The core current corresponding to different load states includes idle core current, single-core core current, and dual-core core current. The first impedance factor is calculated based on the USB wake-up time corresponding to the idle core current and the single-core core current, and the second impedance factor is calculated based on the USB wake-up time corresponding to the single-core current and the dual-core core current. Obtain the equivalent impedance factor, which is the average of the first impedance factor and the second impedance factor.

7. The chip testing method based on multi-protocol programming and adaptive testing according to claim 6, characterized in that, The impedance deviation is calculated and denoted as a nonlinear exponent, whereby the impedance deviation is the absolute value of the difference between the first impedance factor and the second impedance factor. If the nonlinearity index is greater than the difference evaluation value, it is determined that the chip has nonlinear impedance characteristics. Under the current sensitivity coefficient of the chip's power supply voltage, the chip has a wake-up delay due to PDN process deviation, and it is recommended to reduce the design value of the sensitivity coefficient of the power supply voltage.

8. The chip testing method based on multi-protocol programming and adaptive testing according to claim 7, characterized in that, Obtain the impedance threshold of the equivalent impedance factor that causes the chip to fall into the first characteristic state. If the proportion of the chip marked as the first characteristic state is greater than the proportion threshold when the equivalent impedance factor value is greater than any equivalent threshold, then the upper limit of the USB interface's tolerance to PDN impedance is determined to be the corresponding equivalent threshold.

9. The chip testing method based on multi-protocol programming and adaptive testing according to claim 8, characterized in that, Calculate the process drift index of the current batch of chips when any equivalent impedance factor value is greater than the tolerance limit.

10. The chip testing method based on multi-protocol programming and adaptive testing according to claim 9, characterized in that, The process of determining whether chip manufacturing process variations are due to process drift includes: If the process drift index is less than or equal to the first index threshold, the process fluctuation is judged to be within the normal range, and the existing threshold is maintained unchanged. If the process drift index is greater than the first index threshold and less than or equal to the second index threshold, then the chip process is determined to be drifting, and the critical upper limit value is adjusted. If the process drift index is greater than the second index threshold, the chip process is judged to be seriously abnormal, and a process abnormality alarm is issued.

Images