Data access method and device, equipment, storage medium and chip
By introducing a Swizzle-based address remapping mechanism in shared memory and using XOR operations to generate the target physical address, the memory conflict problem is solved and data access efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-02-02
- Publication Date
- 2026-05-12
AI Technical Summary
Existing data access methods are ineffective in dealing with storage conflicts, resulting in low data access efficiency.
An address remapping mechanism based on Swizzle transformation is introduced, which generates the target physical address through XOR operation, avoiding data storage requests from different threads from being mapped to the same memory bank and optimizing access to shared memory.
It effectively reduces or even eliminates memory conflicts, improves the efficiency of multi-threaded parallel access, and enhances chip data access efficiency.
Smart Images
Figure CN122019407A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a data access method, apparatus, device, storage medium, and chip. Background Technology
[0002] In a chip, shared memory is a critical high-speed on-chip memory whose storage space can be shared by all threads within the same warp. To improve chip bandwidth, shared memory typically comprises multiple independent banks. Ideally, a warp includes multiple threads that can simultaneously access different banks within the shared memory, performing data access on different banks concurrently, thus enabling parallel access by multiple threads within a single cycle. For example, if the shared memory comprises 32 independent banks and the warp includes 32 threads, then within the same cycle, each thread can access a different bank, allowing all 32 threads to simultaneously access data on the shared memory.
[0003] However, when multiple threads access memory addresses or read addresses mapped to the same memory bank, bank conflicts occur in shared memory because only one thread can access a memory bank per cycle. These conflicting thread accesses must be serialized and executed asynchronously across multiple cycles. For example, if three threads simultaneously initiate data storage requests, and the target memory addresses carried in these requests all map to the same memory bank, a bank conflict will occur. In this case, the data storage requests initiated by the three threads need to be divided into three asynchronous cycles. Therefore, the existence of bank conflicts significantly reduces the chip's effective bandwidth and program performance.
[0004] To address memory conflicts, traditional data access methods primarily rely on programmers manually optimizing data layout (e.g., adjusting the data access order within memory) to avoid conflicts. However, this approach increases chip programming complexity and memory overhead, lacking versatility. Based on this, some related technologies have proposed dynamic scheduling of access requests. However, this data access method often suffers from complex hardware implementation and high memory overhead, resulting in low data access efficiency.
[0005] In summary, existing data access methods are ineffective in dealing with storage conflicts, resulting in low data access efficiency. Summary of the Invention
[0006] This invention provides a data access method, apparatus, device, storage medium, and chip to address the shortcomings of existing data access methods, which are unable to effectively cope with storage conflicts, resulting in low data access efficiency.
[0007] This invention provides a data access method, comprising: receiving a data storage request from a thread; the data storage request carrying data to be stored and a target storage address; determining a first address transformation rule corresponding to the target storage address based on a first data access granularity of the target storage address; performing an address transformation operation on the target storage address based on the first address transformation rule to generate a first target physical address; the first target physical address being used to specify the physical location of a first target memory in a shared memory; and storing the data to be stored in the first target memory based on the first target physical address.
[0008] According to a data access method provided by the present invention, a first address transformation rule includes a first bit sequence to be operated on, the first bit sequence to be operated on is determined based on multiple first target bits in the target storage address, and the address transformation operation is an XOR operation; based on the first address transformation rule, an address transformation operation is performed on the target storage address to generate a first target physical address, including: determining the first bit sequence to be transformed of the target storage address; the first bit sequence to be transformed includes multiple consecutive bits in the target storage address; performing an XOR operation on the first bit sequence to be transformed and the first bit sequence to be operated on to generate the first target physical address.
[0009] According to a data access method provided by the present invention, a first address transformation rule corresponding to a target storage address is determined based on a first data access granularity of the target storage address, including: if the first data access granularity of the target storage address is less than or equal to a preset threshold, then multiple first target bits are selected from the target storage address as a first bit sequence to be operated on in the first address transformation rule; if the first data access granularity of the target storage address is greater than the preset threshold, then multiple first target bits and at least one first sub-bit sequence are selected from the target storage address as a first bit sequence to be operated on in the first address transformation rule; wherein, the first sub-bit sequence includes multiple consecutive bits in the target storage address.
[0010] According to a data access method provided by the present invention, after storing the data to be stored into a target memory based on a target physical address, the method further includes: receiving a data read request from a receiving thread; the data read request carrying a target read address; determining a second address transformation rule corresponding to the target read address based on a second data access granularity of the target read address; performing an address transformation operation on the target read address based on the second address transformation rule to generate a second target physical address; the second target physical address being used to specify the physical location of a second target memory in a shared memory; and reading target data from the second target memory based on the second target physical address.
[0011] According to a data access method provided by the present invention, a second address transformation rule includes a second bit sequence to be operated on, which is determined based on multiple second target bits in the target read address, and the address transformation operation is an XOR operation; based on the second address transformation rule, an address transformation operation is performed on the target read address to generate a second target physical address, including: determining the second bit sequence to be transformed in the target read address; the second bit sequence to be transformed includes multiple consecutive bits in the target read address; and performing an XOR operation on the second bit sequence to be transformed and the second bit sequence to be operated on to generate the second target physical address.
[0012] According to a data access method provided by the present invention, a second address transformation rule corresponding to a target read address is determined based on a second data access granularity of the target read address. The method includes: if the second data access granularity of the target read address is less than or equal to a preset threshold, then selecting multiple second target bits from the target read address as a second bit sequence to be processed in the second address transformation rule; if the second data access granularity of the target read address is greater than the preset threshold, then selecting multiple second target bits and at least one second sub-bit sequence from the target read address as a second bit sequence to be processed in the second address transformation rule; wherein the second sub-bit sequence includes multiple consecutive bits in the target read address.
[0013] The present invention also provides a data access device, comprising: a receiving module for receiving a data storage request from a thread; the data storage request carrying data to be stored and a target storage address; a rule determination module for determining a first address transformation rule corresponding to the target storage address based on a first data access granularity of the target storage address; an address transformation module for performing an address transformation operation on the target storage address based on the first address transformation rule to generate a first target physical address; the first target physical address is used to specify the physical location of a first target memory in a shared memory; and an access module for storing the data to be stored into the first target memory based on the first target physical address.
[0014] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement any of the data access methods described above.
[0015] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the data access methods described above.
[0016] The present invention also provides a chip, the chip including a shared memory controller and a shared memory, the shared memory controller including a shared memory access device, the shared memory access device being used to execute any of the above data access methods.
[0017] The data access method, apparatus, device, storage medium, and chip provided by this invention introduce an address remapping mechanism based on Swizzle transformation during the data access process of shared memory. Swizzle transformation is a technique for optimizing shared memory access. After receiving a thread's data storage request, a first address transformation rule corresponding to the target storage address can be determined according to the first data access granularity of the target storage address carried in the data storage request. Then, according to the first address transformation rule, an address transformation operation is performed on the target storage address to generate a first target physical address. This first target physical address is used to specify the physical location of the first target memory in the shared memory. Finally, the data to be stored carried in the data storage request is stored in the first target memory specified by the first target physical address. Through this address remapping method based on Swizzle transformation, the target storage addresses corresponding to data storage requests from different threads can be mapped to the physical addresses of different memory banks in the shared memory according to their data access granularity. This avoids memory bank conflicts caused by mapping the target storage addresses corresponding to data storage requests from different threads to the same memory bank, effectively reducing or even eliminating memory bank conflicts in the chip, improving the efficiency of multi-threaded parallel access, and thus improving the efficiency of chip data access. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0019] Figure 1 This is a flowchart illustrating the data access method provided by the present invention.
[0020] Figure 2 This is a schematic diagram of the structure of the chip and shared memory controller provided by the present invention.
[0021] Figure 3 This is a schematic diagram illustrating the principle of memory bank conflict in the contiguous address access mode provided by the present invention.
[0022] Figure 4 This is a schematic diagram illustrating the principle of resolving memory conflicts provided by the present invention.
[0023] Figure 5 This is a schematic diagram of the data access device provided by the present invention.
[0024] Figure 6This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0026] Please see Figures 1 to 4 , Figure 1 This is a flowchart illustrating the data access method provided by the present invention. Figure 2 This is a schematic diagram of the structure of the chip and shared memory controller provided by the present invention. Figure 3 This is a schematic diagram illustrating the principle of memory bank conflicts under the contiguous address access mode provided by the present invention. Figure 4 This is a schematic diagram illustrating the principle of resolving memory conflicts provided by the present invention.
[0027] like Figure 1 As shown, in this embodiment, the data access method is applied to a shared memory access device. The data access method includes steps S110 to S140, and each step is as follows: S110: Receives data storage requests from threads.
[0028] The data storage request carries the data to be stored and the target storage address.
[0029] Specifically, a complete data access process includes a storage procedure and a retrieval procedure. During the storage procedure, the shared memory access device can receive data storage requests (i.e., Store requests) from threads. These data storage requests carry the data to be stored and the target storage address bit_addr1.
[0030] S120: Determine the first address transformation rule corresponding to the target storage address based on the first data access granularity of the target storage address.
[0031] Specifically, the shared memory access device predefines a variety of Swizzle transformation modes. After receiving a data storage request from a thread, the mode selector of the shared memory access device can select the first address transformation rule corresponding to the target storage address bit_addr1 from the predefine multiple Swizzle transformation modes according to the first data access granularity of the target storage address bit_addr1.
[0032] S130: Based on the first address transformation rule, perform address transformation operation on the target storage address to generate the first target physical address.
[0033] Specifically, after determining the first address transformation rule corresponding to the target storage address bit_addr1, the address shuffling module of the shared memory access device can perform address transformation operation on the target storage address bit_addr1 according to the first address transformation rule to generate the first target physical address swzl_bit_addr1 after completing the Swizzle transformation.
[0034] Optionally, the address transformation operation is an XOR operation; performing an address transformation operation on the target storage address bit_addr1 refers to performing an XOR operation on a specific bit of the target storage address bit_addr1.
[0035] The first target physical address swzl_bit_addr1 is used to specify the physical location of a specific first target memory in the shared memory.
[0036] S140: Based on the first target physical address, store the data to be stored in the first target storage.
[0037] Specifically, after determining the first target physical address swzl_bit_addr1, the data to be stored is stored in the first target memory specified by the first target physical address swzl_bit_addr1, that is, the data to be stored is stored in a specific physical location of the shared memory specified by the first target physical address swzl_bit_addr1, thus completing the data storage process.
[0038] To facilitate understanding, a specific application example is provided here.
[0039] like Figure 2 As shown, in this embodiment, the data access method is applied to a shared memory access device, which can be integrated into the chip's shared memory controller.
[0040] Optionally, the chip includes, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), and a data processing unit (DPU).
[0041] by Figure 2For example, a chip may include a thread block scheduler, a warp scheduler, multiple load / store units (LSUs), a shared memory controller, and shared memory.
[0042] The thread block scheduler is used to assign different tasks to different thread blocks.
[0043] The thread bundle scheduler is used to schedule smaller execution units, such as thread bundles (a thread bundle contains multiple threads), and is the core scheduling layer for parallel thread execution.
[0044] The load / store unit is used to handle data storage requests and data read requests from each thread in the thread bundle.
[0045] Shared memory is a physical memory array consisting of multiple independent memory banks, denoted as bank 0 to bank n.
[0046] The shared memory controller is a composite module that includes an address swizzle module based on swizzle transformation, a mode selector, a bank conflict detection and request scheduling module, and a physical bank arbitration and access control module. The shared memory controller is used to manage thread access to shared memory.
[0047] The shared memory access device is integrated into the shared memory controller, which includes an address shuffling module and a mode selector.
[0048] The address shuffling module receives data storage requests or data read requests from threads. Based on the logical address bit_addr carried in the data storage request or data read request (the logical address carried in the data storage request is the target storage address, and the logical address carried in the data read request is the target read address), it determines the corresponding data access granularity. According to the address transformation rules defined by the currently effective Swizzle transformation mode, it performs address transformation operations (such as XOR operations) to convert the logical address bit_addr carried in the data storage request or data read request into the corresponding target physical address swzl_bit_addr. The target physical address is used to specify the physical location of a specific memory bank in the shared memory. The addressing of each memory bank in the shared memory is controlled by the target physical address swzl_bit_addr.
[0049] The mode selector is used to generate a mode selection signal sel_mode based on the data access granularity corresponding to the logical address carried in the data storage request or data read request. The mode selection signal sel_mode is used to select and activate the corresponding Swizzle transformation mode.
[0050] Optionally, the address shuffling module consists of a set of configurable multiplexers and XOR logic gates, which can be configured with the input bits of the XOR operation by the signal of the mode selector.
[0051] It should be noted that the shared memory access device in this embodiment uses a data access method based on XOR operation and reversible Swizzle transformation mechanism. The core idea is as follows: when a thread writes data to be stored into the shared memory, the data access granularity of the target memory address carried in the data storage request is first determined. Then, according to the data access granularity, a specific low-order bit of the target memory address is XORed with some high-order bits of the target memory address to generate a target physical address with scrambled address information. The data to be stored carried in the data storage request is then stored in the specific memory specified by the target physical address. Similarly, when a thread reads data from the shared memory, the data access granularity of the target read address carried in the data read request is first determined. Then, according to the data access granularity, a specific low-order bit of the target read address is XORed with some high-order bits of the target read address to generate a target physical address with scrambled address information. The required data is then read from the specific memory specified by the target physical address. This address transformation operation is equivalent to shuffling the address space of the shared memory, mapping the originally continuous address sequence to scattered, conflict-free physical memory. For any thread, when initiating a data read request, only the exact same transformation operation as when initiating a data storage request needs to be applied. At this point, due to the reflexivity of the XOR operation, the following condition is met: (symbol This represents the XOR operation. and Since these are the two operands participating in the XOR operation, the physical address of the data storage can be accurately located, thus allowing the correct data to be read.
[0052] The storage conflict detection and request scheduling module is used to identify storage conflicts in order to determine whether the data storage requests or data read requests of threads need to be scheduled and optimized.
[0053] The physical memory arbitration and access control module is used to manage parallel access control of multiple independent memory banks in a shared memory.
[0054] Specifically, the complete data access process includes a storage procedure and a retrieval procedure. During the storage procedure, the address shuffling module of the shared memory access device can receive data storage requests (i.e., Store requests) from threads. The data storage request carries the data to be stored and the target storage address bit_addr1.
[0055] Furthermore, the mode selector of the shared memory access device predefines a variety of Swizzle transformation modes. After receiving a data storage request from a thread, the mode selector can select the first address transformation rule corresponding to the target memory address bit_addr1 from the predefined variety of Swizzle transformation modes based on the first data access granularity of the target memory address bit_addr1.
[0056] Furthermore, after determining the first address transformation rule corresponding to the target storage address bit_addr1, the address shuffling module of the shared memory access device can perform address transformation operation on the target storage address bit_addr1 according to the first address transformation rule to generate the first target physical address swzl_bit_addr1 after completing the Swizzle transformation.
[0057] Optionally, the address transformation operation is an XOR operation; performing an address transformation operation on the target storage address bit_addr1 refers to performing an XOR operation on a specific bit of the target storage address bit_addr1.
[0058] The first target physical address swzl_bit_addr1 is used to specify the physical location of a specific first target memory in the shared memory.
[0059] Furthermore, after determining the first target physical address swzl_bit_addr1, the data to be stored is stored in the first target memory specified by the first target physical address swzl_bit_addr1, that is, the data to be stored is stored in a specific physical location of the shared memory specified by the first target physical address swzl_bit_addr1, thus completing the data storage process.
[0060] The data access method provided in this embodiment introduces an address remapping mechanism based on Swizzle transformation during the data access process of shared memory. Swizzle transformation is a technique used to optimize shared memory access. After receiving a thread's data storage request, the method can determine the first address transformation rule corresponding to the target storage address based on the first data access granularity of the target storage address carried in the data storage request. Then, according to the first address transformation rule, the target storage address is subjected to address transformation operation to generate a first target physical address. This first target physical address is used to specify the physical location of the first target memory in the shared memory. Finally, the data to be stored carried in the data storage request is stored in the first target memory specified by the first target physical address. Through this address remapping method based on Swizzle transformation, the target storage addresses corresponding to data storage requests from different threads can be mapped to the physical addresses of different memory banks in the shared memory according to their data access granularity. This avoids memory bank conflicts caused by mapping the target storage addresses corresponding to data storage requests from different threads to the same memory bank, effectively reducing or even eliminating memory bank conflicts in the chip, improving the efficiency of multi-threaded parallel access, and thus improving the efficiency of chip data access.
[0061] In some embodiments, the first address transformation rule includes a first bit sequence to be operated on, which is determined based on multiple first target bits in the target storage address, and the address transformation operation is an XOR operation; based on the first address transformation rule, the target storage address is subjected to an address transformation operation to generate a first target physical address, including: determining the first bit sequence to be transformed in the target storage address; the first bit sequence to be transformed includes multiple consecutive bits in the target storage address; performing an XOR operation on the first bit sequence to be transformed and the first bit sequence to be operated on to generate the first target physical address.
[0062] In this embodiment, each predefined Swizzle transformation mode in the mode selector corresponds to a different address transformation rule, and the general formulas for these different address transformation rules are as follows: ; in, It is a positive integer greater than or equal to 3; For a number of bits in logical address bit_addr that are greater than or equal to The bit sequence to be operated on consists of multiple bits; The target physical address corresponding to the logical address bit_addr after the address translation operation is performed; This represents the second bit to the third bit of the target physical address swzl_bit_addr. One bit; This represents the second bit to the first bit of the logical address bit_addr. One bit; symbol This represents the XOR operation.
[0063] The above formula shows that the principle of address transformation in this embodiment is to transform multiple specific bits in the logical address bit_addr (for example, the second bit in the logical address bit_addr to the third bit). (1 bit) and a bit sequence to be operated on Perform an XOR operation to change the original logical address bit_addr, generating a new target physical address swzl_bit_addr. This new target physical address swzl_bit_addr contains several specific bits (e.g., bits 2 to 3 in the target physical address swzl_bit_addr). (a number of bits) is a sequence of specific bits in the logical address bit_addr and a bit sequence to be operated on. The result obtained after performing an XOR operation.
[0064] Specifically, for a storage procedure, the first address translation rule includes a first bit sequence to be operated on. The first bit sequence to be operated on It is determined based on multiple first target bits in the target storage address bit_addr1, and the address transformation operation is an XOR operation.
[0065] After determining the first address transformation rule corresponding to the target memory address bit_addr1, the address shuffling module of the shared memory access device can first determine the first bit sequence to be transformed for the target memory address bit_addr1. The first bit sequence to be transformed This includes multiple consecutive bits in the target storage address bit_addr1.
[0066] Furthermore, for the first bit sequence to be transformed... and the first bit sequence to be operated on Perform an XOR operation to generate the first target physical address. .
[0067] Among them, the first target physical address Satisfy the following formula: ; in, It is a positive integer greater than or equal to 3; For the number of bits at the target memory address bit_addr1 that are greater than or equal to The first bit sequence to be operated on consists of multiple first target bits; The first target physical address after the address transformation operation is performed on the target storage address bit_addr1; Indicates the first target physical address The second bit to the first bit One bit; This indicates the second bit to the first bit of the target memory address bit_addr1. One bit; symbol This represents the XOR operation.
[0068] In some embodiments, determining a first address transformation rule corresponding to a target storage address based on a first data access granularity of the target storage address includes: if the first data access granularity of the target storage address is less than or equal to a preset threshold, then selecting multiple first target bits from the target storage address as a first bit sequence to be operated on in the first address transformation rule; if the first data access granularity of the target storage address is greater than the preset threshold, then selecting multiple first target bits and at least one first sub-bit sequence from the target storage address as a first bit sequence to be operated on in the first address transformation rule; wherein, the first sub-bit sequence includes multiple consecutive bits in the target storage address.
[0069] In this embodiment, the selection of each predefined Swizzle transformation mode is determined based on the data access granularity of the logical address bit_addr. The data access granularity includes, but is not limited to, 16 bytes, 32 bytes, 64 bytes, 128 bytes, 256 bytes, 512 bytes, 1K bytes, 2K bytes, 4K bytes, and 8K bytes, and each Swizzle transformation mode has a corresponding base address alignment requirement.
[0070] Specifically, for a stored procedure, after receiving a data storage request from a thread, the mode selector of the shared memory access device can first determine the first data access granularity of the target storage address bit_addr1.
[0071] If the first data access granularity of the target storage address bit_addr1 is less than or equal to a preset threshold, then multiple first target bits are selected from the target storage address bit_addr1 as the first bit sequence to be operated on in the first address transformation rule. .
[0072] The preset threshold can be adjusted according to actual needs.
[0073] For example, a data access granularity of 32 bytes can be used as a preset threshold. If the first data access granularity of the target storage address bit_addr1 is less than or equal to 32 bytes, then multiple first target bits can be directly selected from the target storage address bit_addr1 as the first bit sequence to be operated on in the first address transformation rule. .
[0074] Optionally, if the first data access granularity of the target storage address bit_addr1 is 16 bytes, then the base address alignment requirement is 512 bytes, and the first address translation rule and the first bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the first target physical address The second to the third bit; This represents the second and third bits of the target memory address bit_addr1; symbol This represents the XOR operation; This represents the 7th bit of the target memory address bit_addr1; This represents the 8th bit of the target memory address bit_addr1.
[0075] Optionally, if the first data access granularity of the target storage address bit_addr1 is 32 bytes, then the base address alignment requirement is 1KB, and the first address transformation rule and the first bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the first target physical address The 2nd to 4th bits; This represents the second to fourth bits of the target memory address bit_addr1; symbol This represents the XOR operation; This represents the 7th bit of the target memory address bit_addr1; This represents the 8th bit of the target memory address bit_addr1; This represents the 9th bit of the target storage address bit_addr1.
[0076] If the first data access granularity of the target storage address bit_addr1 is greater than a preset threshold, then multiple first target bits and at least one first sub-bit sequence are selected from the target storage address bit_addr1 as the first bit sequence to be operated on in the first address transformation rule. .
[0077] The first sub-bit sequence includes multiple consecutive bits in the target storage address bit_addr1.
[0078] Optionally, if the first data access granularity of the target storage address bit_addr1 is 64 bytes, then the base address alignment requirement is 2K bytes, and the first address translation rule and the first bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the first target physical address The 2nd to 5th bits; This represents bits 2 through 5 of the target memory address bit_addr1; symbol This represents the XOR operation; The first sub-bit sequence represents the 7th to 8th bits of the target storage address bit_addr1; This represents the 9th bit of the target memory address bit_addr1; This represents the 10th bit of the target storage address bit_addr1.
[0079] Optionally, if the first data access granularity of the target storage address bit_addr1 is 128 bytes, then the base address alignment requirement is 4K bytes, and the first address translation rule and the first bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the first target physical address The 2nd to 6th bits; This represents bits 2 through 6 of the target memory address bit_addr1; symbol This represents the XOR operation; The first sub-bit sequence represents bits 7 to 9 of the target storage address bit_addr1; This represents the 10th bit of the target memory address bit_addr1; This represents the 11th bit of the target storage address bit_addr1.
[0080] Optionally, if the first data access granularity of the target storage address bit_addr1 is 256 bytes, then the base address alignment requirement is 8K bytes, and the first address translation rule and the first bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the first target physical address The 2nd to 6th bits; This represents bits 2 through 6 of the target memory address bit_addr1; symbol This represents the XOR operation; The first sub-bit sequence represents the 8th to 10th bits of the target storage address bit_addr1; This represents the 11th bit of the target memory address bit_addr1; This represents the 12th bit of the target storage address bit_addr1.
[0081] Optionally, if the first data access granularity of the target storage address bit_addr1 is 512 bytes, then the base address alignment requirement is 16K bytes, and the first address translation rule and the first bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the first target physical address The 2nd to 6th bits; This represents bits 2 through 6 of the target memory address bit_addr1; symbol This represents the XOR operation; The first sub-bit sequence represents bits 9 to 11 of the target storage address bit_addr1; This represents the 12th bit of the target memory address bit_addr1; This represents the 13th bit of the target memory address bit_addr1.
[0082] Optionally, if the first data access granularity of the target storage address bit_addr1 is 1K bytes, then the base address alignment requirement is 32K bytes, and the first address translation rule and the first bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the first target physical address The 2nd to 6th bits; This represents bits 2 through 6 of the target memory address bit_addr1; symbol This represents the XOR operation; This is the first sub-bit sequence, representing bits 10 to 12 of the target storage address bit_addr1; This represents the 13th bit of the target memory address bit_addr1; This represents the 14th bit of the target storage address bit_addr1.
[0083] Optionally, if the first data access granularity of the target storage address bit_addr1 is 2K bytes, then the base address alignment requirement is 64K bytes, and the first address translation rule and the first bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the first target physical address The 2nd to 6th bits; This represents bits 2 through 6 of the target memory address bit_addr1; symbol This represents the XOR operation; The first sub-bit sequence represents bits 11 to 13 of the target storage address bit_addr1; This represents the 14th bit of the target memory address bit_addr1; This represents the 15th bit of the target storage address bit_addr1.
[0084] Optionally, if the first data access granularity of the target storage address bit_addr1 is 4K bytes, then the base address alignment requirement is 128K bytes, and the first address translation rule and the first bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the first target physical address The 2nd to 6th bits; This represents bits 2 through 6 of the target memory address bit_addr1; symbol This represents the XOR operation; This is the first sub-bit sequence, representing bits 12 to 14 of the target storage address bit_addr1; This represents the 15th bit of the target memory address bit_addr1; This represents the 16th bit of the target memory address bit_addr1.
[0085] Optionally, if the first data access granularity of the target storage address bit_addr1 is 8K bytes, then the base address alignment requirement is 256K bytes, and the first address translation rule and the first bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the first target physical address The 2nd to 6th bits; This represents bits 2 through 6 of the target memory address bit_addr1; symbol This represents the XOR operation; The first sub-bit sequence represents bits 13 to 15 of the target storage address bit_addr1; This represents the 16th bit of the target memory address bit_addr1; This represents the 17th bit of the target memory address bit_addr1.
[0086] As can be seen from the above examples, for larger data access granularity, it is usually necessary to transform more low-order addresses (i.e., the first bit sequence to be transformed) in the target memory address. The high-order addresses involved in the XOR operation (i.e., the first bit sequence to be operated on) ensure that the Swizzle transformation mode is different under different base addresses, thereby avoiding global memory conflicts.
[0087] In some embodiments, after storing the data to be stored in the target memory based on the target physical address, the method further includes: receiving a data read request from a receiving thread; the data read request carrying a target read address; determining a second address transformation rule corresponding to the target read address based on a second data access granularity of the target read address; performing an address transformation operation on the target read address based on the second address transformation rule to generate a second target physical address; the second target physical address being used to specify the physical location of the second target memory in the shared memory; and reading target data from the second target memory based on the second target physical address.
[0088] Specifically, the complete data access process includes a storage process and a reading process. During the reading process, the address shuffling module of the shared memory access device can receive data read requests (i.e., load requests) from threads, and the data read requests carry the target read address bit_addr2.
[0089] Furthermore, the mode selector of the shared memory access device predefines a variety of Swizzle transformation modes. After receiving a data read request from a thread, the mode selector can select the second address transformation rule corresponding to the target read address bit_addr2 from the predefined variety of Swizzle transformation modes according to the second data access granularity of the target read address bit_addr2. The second address transformation rule is the same as the address transformation rule of the stored procedure.
[0090] Furthermore, after determining the second address transformation rule corresponding to the target read address bit_addr2, the address shuffling module of the shared memory access device can perform address transformation operation on the target read address bit_addr2 according to the second address transformation rule to generate the second target physical address swzl_bit_addr2 after Swizzle transformation.
[0091] Optionally, the address transformation operation is an XOR operation; performing an address transformation operation on the target read address bit_addr2 refers to performing an XOR operation on a specific bit of the target read address bit_addr2.
[0092] The second target physical address swzl_bit_addr2 is used to specify the physical location of a specific second target memory in the shared memory.
[0093] Furthermore, after determining the second target physical address swzl_bit_addr2, the target data is read from the second target memory specified by the second target physical address swzl_bit_addr2, that is, the target data is read from the specific physical location of the shared memory specified by the second target physical address swzl_bit_addr2, and the target data is returned to the corresponding thread to complete the data reading process.
[0094] In some embodiments, the second address transformation rule includes a second bit sequence to be operated on, which is determined based on multiple second target bits in the target read address, and the address transformation operation is an XOR operation; based on the second address transformation rule, the target read address is subjected to an address transformation operation to generate a second target physical address, including: determining the second bit sequence to be transformed in the target read address; the second bit sequence to be transformed includes multiple consecutive bits in the target read address; and performing an XOR operation on the second bit sequence to be transformed and the second bit sequence to be operated on to generate the second target physical address.
[0095] In this embodiment, each predefined Swizzle transformation mode corresponds to a different address transformation rule, and the general formulas for these different address transformation rules are as follows: ; in, It is a positive integer greater than or equal to 3; For a number of bits in logical address bit_addr that are greater than or equal to The bit sequence to be operated on consists of multiple bits; The target physical address corresponding to the logical address bit_addr after the address translation operation is performed; This represents the second bit to the third bit of the target physical address swzl_bit_addr. One bit; This represents the second bit to the first bit of the logical address bit_addr. One bit; symbol This represents the XOR operation.
[0096] The above formula shows that the principle of address transformation in this embodiment is to transform multiple specific bits in the logical address bit_addr (for example, the second bit in the logical address bit_addr to the third bit). (1 bit) and a bit sequence to be operated on Perform an XOR operation to change the original logical address bit_addr, generating a new target physical address swzl_bit_addr. This new target physical address swzl_bit_addr contains several specific bits (e.g., bits 2 to 3 in the target physical address swzl_bit_addr). (a number of bits) is a sequence of specific bits in the logical address bit_addr and a bit sequence to be operated on. The result obtained after performing an XOR operation.
[0097] Specifically, for the reading process, the second address transformation rule includes the second bit sequence to be processed. The second bit sequence to be operated on It is determined based on multiple second target bits in the target read address bit_addr2, and the address transformation operation is an XOR operation.
[0098] After determining the second address transformation rule corresponding to the target read address bit_addr2, the address shuffling module of the shared memory access device can first determine the second bit sequence to be transformed for the target read address bit_addr2. The second bit sequence to be transformed This includes multiple consecutive bits in the target read address bit_addr2.
[0099] Furthermore, for the second bit sequence to be transformed... Second bit sequence to be operated Perform an XOR operation to generate the second target physical address. .
[0100] Among them, the second target physical address Satisfy the following formula: ; in, It is a positive integer greater than or equal to 3; For the number of bits greater than or equal to the target address bit_addr2 to be read The second bit sequence to be operated on is composed of multiple second target bits; The second target physical address corresponding to the target address bit_addr2 after the address transformation operation is completed; Indicates the second target physical address The second bit of 2 to the 2nd bit One bit; This indicates that the target read address is bit_addr2, from the second bit to the... One bit; symbol This represents the XOR operation.
[0101] In some embodiments, determining a second address transformation rule corresponding to the target read address based on the second data access granularity of the target read address includes: if the second data access granularity of the target read address is less than or equal to a preset threshold, then selecting multiple second target bits from the target read address as the second bit sequence to be operated on in the second address transformation rule; if the second data access granularity of the target read address is greater than the preset threshold, then selecting multiple second target bits and at least one second sub-bit sequence from the target read address as the second bit sequence to be operated on in the second address transformation rule; wherein the second sub-bit sequence includes multiple consecutive bits in the target read address.
[0102] In this embodiment, the selection of each predefined Swizzle transformation mode is determined based on the data access granularity of the logical address bit_addr. The data access granularity includes, but is not limited to, 16 bytes, 32 bytes, 64 bytes, 128 bytes, 256 bytes, 512 bytes, 1K bytes, 2K bytes, 4K bytes, and 8K bytes, and each Swizzle transformation mode has a corresponding base address alignment requirement.
[0103] Specifically, for the reading process, after receiving a data read request from a thread, the mode selector of the shared memory access device can first determine the second data access granularity of the target read address bit_addr2.
[0104] If the second data access granularity of the target read address bit_addr2 is less than or equal to a preset threshold, then multiple second target bits are selected from the target read address bit_addr2 as the second bit sequence to be operated on in the second address transformation rule. .
[0105] The preset threshold can be adjusted according to actual needs.
[0106] For example, a data access granularity of 32 bytes can be used as a preset threshold. If the second data access granularity of the target read address bit_addr2 is less than or equal to 32 bytes, then multiple second target bits can be directly selected from the target read address bit_addr2 as the second bit sequence to be operated on in the second address transformation rule. .
[0107] Optionally, if the second data access granularity of the target read address bit_addr2 is 16 bytes, then the base address alignment requirement is 512 bytes, and the second address transformation rule and the second bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the second target physical address The second to the third bit; This indicates the second and third bits of the target read address bit_addr2; symbol This represents the XOR operation; This indicates the 7th bit of the target read address bit_addr2; This indicates the 8th bit of the target read address bit_addr2.
[0108] Optionally, if the second data access granularity of the target read address bit_addr2 is 32 bytes, then the base address alignment requirement is 1K bytes, and the second address transformation rule and the second bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the second target physical address The 2nd to 4th bits; This indicates the 2nd to 4th bits of the target read address bit_addr2; symbol This represents the XOR operation; This indicates the 7th bit of the target read address bit_addr2; This indicates the 8th bit of the target read address bit_addr2; This indicates the 9th bit of the target read address bit_addr2.
[0109] If the second data access granularity of the target read address bit_addr2 is greater than a preset threshold, then multiple second target bits and at least one second sub-bit sequence are selected from the target read address bit_addr2 as the second bit sequence to be operated on in the second address transformation rule. .
[0110] The second sub-bit sequence includes multiple consecutive bits in the target read address bit_addr2.
[0111] Optionally, if the second data access granularity of the target read address bit_addr2 is 64 bytes, then the base address alignment requirement is 2K bytes, and the second address transformation rule and the second bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the second target physical address The 2nd to 5th bits; This indicates the 2nd to 5th bits of the target read address bit_addr2; symbol This represents the XOR operation; The first sub-bit sequence represents the 7th to 8th bits of the target read address bit_addr2; This indicates the 9th bit of the target read address bit_addr2; This indicates the 10th bit of the target read address bit_addr2.
[0112] Optionally, if the second data access granularity of the target read address bit_addr2 is 128 bytes, then the base address alignment requirement is 4K bytes, and the second address transformation rule and the second bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the second target physical address The 2nd to 6th bits; This indicates that the target address bit_addr2 contains bits 2 through 6; symbol This represents the XOR operation; The second sub-bit sequence represents bits 7 to 9 of the target read address bit_addr2; This indicates the 10th bit of the target read address bit_addr2; This indicates the 11th bit of the target read address bit_addr2.
[0113] Optionally, if the second data access granularity of the target read address bit_addr2 is 256 bytes, then the base address alignment requirement is 8K bytes, and the second address transformation rule and the second bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the second target physical address The 2nd to 6th bits; This indicates that the target address bit_addr2 contains bits 2 through 6; symbol This represents the XOR operation; The second sub-bit sequence represents bits 8 to 10 of the target read address bit_addr2; This indicates the 11th bit of the target read address bit_addr2; This indicates the 12th bit of the target read address bit_addr2.
[0114] Optionally, if the second data access granularity of the target read address bit_addr2 is 512 bytes, then the base address alignment requirement is 16K bytes, and the second address transformation rule and the second bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the second target physical address The 2nd to 6th bits; This indicates that the target address bit_addr2 contains bits 2 through 6; symbol This represents the XOR operation; The second sub-bit sequence represents bits 9 to 11 of the target read address bit_addr2; This indicates the 12th bit of the target read address bit_addr2; This indicates the 13th bit of the target read address bit_addr2.
[0115] Optionally, if the second data access granularity of the target read address bit_addr2 is 1K bytes, then the base address alignment requirement is 32K bytes, and the second address transformation rule and the second bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the second target physical address The 2nd to 6th bits; This indicates that the target address bit_addr2 contains bits 2 through 6; symbol This represents the XOR operation; The second sub-bit sequence represents the 10th to 12th bits of the target read address bit_addr2; This indicates the 13th bit of the target read address bit_addr2; This indicates the 14th bit of the target read address bit_addr2.
[0116] Optionally, if the second data access granularity of the target read address bit_addr2 is 2K bytes, then the base address alignment requirement is 64K bytes, and the second address transformation rule and the second bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the second target physical address The 2nd to 6th bits; This indicates that the target address bit_addr2 contains bits 2 through 6; symbol This represents the XOR operation; This is the second sub-bit sequence, representing bits 11 to 13 of the target read address bit_addr2; This indicates the 14th bit of the target read address bit_addr2; This indicates the 15th bit of the target read address bit_addr2.
[0117] Optionally, if the second data access granularity of the target read address bit_addr2 is 4K bytes, then the base address alignment requirement is 128K bytes, and the second address transformation rule and the second bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the second target physical address The 2nd to 6th bits; This indicates that the target address bit_addr2 contains bits 2 through 6; symbol This represents the XOR operation; This is the second sub-bit sequence, representing bits 12 to 14 of the target read address bit_addr2; This indicates the 15th bit of the target read address bit_addr2; This indicates the 16th bit of the target read address bit_addr2.
[0118] Optionally, if the second data access granularity of the target read address bit_addr2 is 8K bytes, then the base address alignment requirement is 256K bytes, and the second address transformation rule and the second bit sequence to be operated on are... The expression is as follows: ; ; in, Indicates the second target physical address The 2nd to 6th bits; This indicates that the target address bit_addr2 contains bits 2 through 6; symbol This represents the XOR operation; This is the second sub-bit sequence, representing bits 13 to 15 of the target read address bit_addr2; This indicates the 16th bit of the target read address bit_addr2; This indicates the 17th bit of the target read address bit_addr2.
[0119] As can be seen from the above examples, for larger data access granularity, it is usually necessary to transform more low-order addresses (i.e., the second bit sequence to be transformed) in the target memory address. The high-order addresses involved in the XOR operation (i.e., the second bit sequence to be operated on) ensure that the Swizzle transformation mode is different under different base addresses, thereby avoiding global memory conflicts.
[0120] Compared with the prior art, the data access method provided in this embodiment has at least the following technical advantages: (1) Efficiently eliminate memory conflicts: The Swizzle transformation mode in this embodiment can predefine different address XOR rules according to different data access granularities of the request. By shuffling the mapping from the logical address of each request to the physical memory, it can transform the original multi-threaded regular access mode (such as continuous access, equal step access) that may cause memory conflicts into a uniformly distributed access mode, which can effectively avoid memory conflicts.
[0121] (2) Extremely low hardware overhead: The address shuffling module consists only of multiplexers and XOR logic gates, which hardly increases the critical path delay and chip area, and can effectively reduce hardware overhead.
[0122] (3) Software transparency: This solution does not require programmers to modify the chip code and can be automatically implemented through hardware settings, which lowers the threshold for use.
[0123] (4) High method correctness: Since the Swizzle transformation using XOR operation is reversible, the semantic correctness of the data access process can be ensured.
[0124] To further verify the effectiveness of the data access method provided in this embodiment, here we take... Figure 3and Figure 4 Let's take an example to illustrate.
[0125] exist Figure 3 and Figure 4 In this context, it is assumed that the shared memory includes 32 independent memory banks, denoted as memory bank 0 to memory bank 31, each memory bank includes multiple memory units, and the thread bundle includes 32 threads, denoted as thread 0 to thread 31.
[0126] like Figure 3 As shown, in contiguous address access mode, if the logical addresses bit_addr of 32 threads are mapped to different memory units in the same memory bank, for example, the logical addresses bit_addr of threads 0 to 31 are mapped to 32 memory units in memory bank 0 respectively (the logical address of thread 0 is mapped to memory unit 0 in memory bank 0, the logical address of thread 1 is mapped to memory unit 32 in memory bank 0, and so on for the remaining threads), then the access of threads 0 to 31 will be concentrated in memory bank 0. Since a memory bank can only be accessed by one thread in one cycle, the shared memory will experience a bank conflict due to the simultaneous access of 32 threads to memory bank 0. The requests initiated by these 32 threads need to be divided into 32 cycles for asynchronous execution, which seriously reduces the effective bandwidth of the chip and the shared memory and the program performance.
[0127] Figure 4 This demonstrates the effect of applying the data access method provided in this embodiment, such as... Figure 4 As shown, after address translation, the logical addresses of different threads are shuffled. The logical addresses bit_addr of threads 0 to 31 are mapped to 32 memory banks respectively. For example, the logical address of thread 0 is still mapped to memory cell 0 of memory bank 0, but the logical address of thread 1 is mapped to memory cell 33 of memory bank 1, the logical address of thread 2 is mapped to memory cell 66 of memory bank 2, and so on. The logical address of each thread is mapped to one of the memory cells in an independent memory bank, so that the access of 32 threads is evenly distributed across 32 independent memory banks, avoiding memory bank conflicts caused by 32 threads accessing the same memory bank at the same time. Since the access of 32 threads is evenly distributed across 32 independent memory banks, these threads can execute synchronously in the same cycle, realizing the parallel execution of multi-threaded single-cycle, which proves the technical effect of this embodiment.
[0128] The present invention also provides a data access device. Please refer to [link / reference]. Figure 5 , Figure 5This is a schematic diagram of the data access device provided by the present invention. In this embodiment, the data access device includes a receiving module 510, a rule determination module 520, an address translation module 530, and an access module 540.
[0129] The receiving module 510 is used to receive data storage requests from threads.
[0130] The data storage request carries the data to be stored and the target storage address.
[0131] The rule determination module 520 is used to determine the first address transformation rule corresponding to the target storage address based on the first data access granularity of the target storage address.
[0132] Address translation module 530 is used to perform address translation operations on the target storage address based on the first address translation rule to generate the first target physical address.
[0133] The first target physical address is used to specify the physical location of the first target memory in the shared memory.
[0134] The access module 540 is used to store the data to be stored into the first target storage based on the first target physical address.
[0135] In some embodiments, the first address transformation rule includes a first bit sequence to be operated on, which is determined based on a plurality of first target bits in the target storage address, and the address transformation operation is an XOR operation.
[0136] Address translation module 530 is used to determine a first bit sequence to be translated to a target storage address; the first bit sequence to be translated includes multiple consecutive bits in the target storage address; an XOR operation is performed on the first bit sequence to be translated and the first bit sequence to be processed to generate a first target physical address.
[0137] In some embodiments, the rule determination module 520 is configured to: if the first data access granularity of the target storage address is less than or equal to a preset threshold, select a plurality of first target bits from the target storage address as the first bit sequence to be operated on in the first address transformation rule; if the first data access granularity of the target storage address is greater than the preset threshold, select a plurality of first target bits and at least one first sub-bit sequence from the target storage address as the first bit sequence to be operated on in the first address transformation rule; wherein the first sub-bit sequence includes a plurality of consecutive bits in the target storage address.
[0138] In some embodiments, the receiving module 510 is used to receive data read requests from threads.
[0139] The data read request carries the target read address.
[0140] The rule determination module 520 is used to determine the second address transformation rule corresponding to the target read address based on the second data access granularity of the target read address.
[0141] Address translation module 530 is used to perform address translation operations on the target read address based on the second address translation rule to generate the second target physical address.
[0142] The second target physical address is used to specify the physical location of the second target memory in the shared memory.
[0143] Access module 540 is used to read target data from the second target storage based on the second target physical address.
[0144] In some embodiments, the second address transformation rule includes a second bit sequence to be operated on, which is determined based on a plurality of second target bits in the target read address, and the address transformation operation is an XOR operation.
[0145] Address translation module 530 is used to determine a second bit sequence to be translated in the target read address; the second bit sequence to be translated includes multiple consecutive bits in the target read address; an XOR operation is performed on the second bit sequence to be translated and the second bit sequence to be processed to generate a second target physical address.
[0146] In some embodiments, the rule determination module 520 is configured to: if the second data access granularity of the target read address is less than or equal to a preset threshold, select a plurality of second target bits from the target read address as the second bit sequence to be operated on in the second address transformation rule; if the second data access granularity of the target read address is greater than the preset threshold, select a plurality of second target bits and at least one second sub-bit sequence from the target read address as the second bit sequence to be operated on in the second address transformation rule; wherein the second sub-bit sequence includes a plurality of consecutive bits in the target read address.
[0147] The present invention also provides an electronic device. Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 6 As shown, the electronic device may include a processor 610, a communication interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 communicate with each other through the communication bus 640. The processor 610 can call logical instructions in the memory 630 to execute data access methods.
[0148] Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0149] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data access methods provided by the above methods.
[0150] The present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can perform the data access methods provided by the above methods.
[0151] The present invention also provides a chip, the chip including a shared memory controller and a shared memory, the shared memory controller including a shared memory access device, the shared memory access device being used to execute any of the above data access methods.
[0152] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0153] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A data access method, characterized in that, include: Receives data storage requests from threads; The data storage request carries the data to be stored and the target storage address; Based on the first data access granularity of the target storage address, determine the first address transformation rule corresponding to the target storage address; Based on the first address transformation rule, an address transformation operation is performed on the target storage address to generate a first target physical address; the first target physical address is used to specify the physical location of the first target storage bank in the shared memory; Based on the first target physical address, the data to be stored is stored in the first target storage.
2. The data access method according to claim 1, characterized in that, The first address transformation rule includes a first bit sequence to be operated on, which is determined based on multiple first target bits in the target storage address, and the address transformation operation is an XOR operation; The step of performing address transformation operations on the target storage address based on the first address transformation rule to generate a first target physical address includes: Determine a first bit sequence to be transformed from the target storage address; the first bit sequence to be transformed includes multiple consecutive bits in the target storage address; Perform an XOR operation on the first bit sequence to be transformed and the first bit sequence to be operated on to generate the first target physical address.
3. The data access method according to claim 2, characterized in that, The determination of the first address transformation rule corresponding to the target storage address based on the first data access granularity of the target storage address includes: If the first data access granularity of the target storage address is less than or equal to a preset threshold, then multiple first target bits are selected from the target storage address as the first bit sequence to be operated on in the first address transformation rule; If the first data access granularity of the target storage address is greater than the preset threshold, then multiple first target bits and at least one first sub-bit sequence are selected from the target storage address as the first bit sequence to be processed in the first address transformation rule. The first sub-bit sequence includes multiple consecutive bits in the target storage address.
4. The data access method according to claim 1, characterized in that, After storing the data to be stored in the target storage based on the target physical address, the process further includes: Receive the data read request from the thread; the data read request carries the target read address; Based on the second data access granularity of the target read address, determine the second address transformation rule corresponding to the target read address; Based on the second address transformation rule, an address transformation operation is performed on the target read address to generate a second target physical address; the second target physical address is used to specify the physical location of the second target memory in the shared memory; Based on the second target physical address, the target data is read from the second target storage.
5. The data access method according to claim 4, characterized in that, The second address transformation rule includes a second bit sequence to be operated on, which is determined based on multiple second target bits in the target read address, and the address transformation operation is an XOR operation; The step of performing address transformation operations on the target read address based on the second address transformation rule to generate a second target physical address includes: Determine a second bit sequence to be transformed from the target read address; the second bit sequence to be transformed includes multiple consecutive bits in the target read address; Perform an XOR operation on the second bit sequence to be transformed and the second bit sequence to be operated on to generate the second target physical address.
6. The data access method according to claim 5, characterized in that, The determination of the second address transformation rule corresponding to the target read address based on the second data access granularity of the target read address includes: If the second data access granularity of the target read address is less than or equal to a preset threshold, then multiple second target bits are selected from the target read address as the second bit sequence to be operated on in the second address transformation rule; If the second data access granularity of the target read address is greater than the preset threshold, then multiple second target bits and at least one second sub-bit sequence are selected from the target read address as the second bit sequence to be processed in the second address transformation rule; The second sub-bit sequence includes multiple consecutive bits in the target read address.
7. A data access device, characterized in that, include: The receiving module is used to receive data storage requests from threads. The data storage request carries the data to be stored and the target storage address; The rule determination module is used to determine the first address transformation rule corresponding to the target storage address based on the first data access granularity of the target storage address. The address translation module is used to perform address translation operations on the target storage address based on the first address translation rule to generate a first target physical address; the first target physical address is used to specify the physical location of the first target storage bank in the shared memory; The access module is used to store the data to be stored into the first target storage based on the first target physical address.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the data access method as described in any one of claims 1 to 6.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data access method as described in any one of claims 1 to 6.
10. A chip, characterized in that, The chip includes a shared memory controller and a shared memory, the shared memory controller including a shared memory access device, the shared memory access device being used to perform the data access method as described in any one of claims 1 to 6.