Data characterization processing method of functional unit, related equipment and storage medium
By combining timing arcs and conducting simulation tests on integrated circuit functional units, the problem of low efficiency in acquiring characteristic data of complex functional units was solved, thereby improving the efficiency of integrated circuit design.
Patent Information
- Application Number
- CN202512034398.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies are time-consuming and involve large amounts of data in the process of extracting characteristic data of complex functional units in integrated circuits, resulting in low overall design efficiency.
By merging the timing arcs of the target functional unit, the number of circuit state combinations that need to be simulated during the simulation test is reduced. Characterized data is obtained by using the timing arc merging method and simulation test.
It shortens the simulation testing time, improves the efficiency of acquiring characteristic data, and enhances the overall design efficiency of integrated circuits.
Smart Images
Figure CN122021541A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, specifically to a data feature processing method, related equipment, and storage medium for a functional unit. Background Technology
[0002] In the field of integrated circuit design, standard cell libraries are the cornerstone of physical design. Each standard cell in the library must provide a complete set of characteristic data, among which timing data and power consumption data are the most critical. The accuracy of the characteristic data directly affects the final performance and yield of the integrated circuit after tape-out.
[0003] As integrated circuit design continues to evolve towards high performance and high energy efficiency, customized functional units with higher integration and more complex logic functions are increasingly being adopted in design. The application of such complex functional units in the design process inevitably requires the support of characteristic data. However, functional units usually have numerous input / output ports and internal circuit states. In the process of extracting characteristic data of functional units, the number of circuit state combinations that need to be simulated will increase exponentially, resulting in extremely long characteristic processes and extremely large amounts of data. This makes it difficult to efficiently obtain characteristic data of functional units and reduces the overall design efficiency of integrated circuits. Summary of the Invention
[0004] In view of this, this application aims to provide a method, related equipment and storage medium for data feature processing of functional units, so as to solve the problem of low efficiency in extracting feature data of functional units in related technologies, which affects the overall design process of integrated circuits.
[0005] In a first aspect, this application provides a data feature processing method for functional units, including: Obtain a target functional unit, which is used to implement a preset function of an integrated circuit, and any timing arc in the target functional unit includes at most one timing logic unit; Perform a timing arc merging operation on each timing path in the target functional unit; The target functional unit is simulated and tested based on the merged time arc to obtain the characteristic data of the target functional unit.
[0006] In one optional implementation, a timing arc merging operation is performed on each timing path in the target functional unit, including: Each timing path in the target functional unit is sequentially taken as the target timing path; Determine the target-level gate circuit among the multi-level gate circuits included in the target timing path; Obtain the timing delay duration from the starting point of the target timing path to the target gate circuit; The timing arcs of the target timing path before the target gate circuit are merged according to the timing delay duration.
[0007] In one optional implementation, obtaining the timing delay duration from the starting point of the target timing path to the target gate circuit includes: Iterate through all combinations of input values for timing paths other than the target timing path; For each combination of input values, the timing delay duration from the starting point of the target timing path to the target gate circuit is obtained.
[0008] In one optional implementation, merging the timing arcs of the target timing path before the target-level gate circuit according to the timing delay duration includes: The timing delay fluctuation duration is determined based on the multiple timing delay durations corresponding to the target timing path; If the timing delay fluctuation duration is within a preset duration range, the timing arcs of the target timing path from the starting point of the timing path to the target gate circuit are merged into one timing arc. If the timing delay fluctuation duration is not within the preset duration range, the target level gate circuit is determined again in the multi-level gate circuits included in the target timing path, until the timing arcs from the starting point of the timing path to the target level gate circuit are merged into a single timing arc.
[0009] In one optional implementation, determining the timing delay fluctuation duration based on multiple timing delay durations corresponding to the target timing path includes: Determine the maximum and minimum timing delay durations from among the multiple timing delay durations corresponding to the target timing path; The difference between the maximum timing delay duration and the minimum timing delay duration is determined as the timing delay fluctuation duration.
[0010] In one optional implementation, determining a target-level gate circuit among the multi-level gate circuits included in the target timing path includes: Starting from the last gate circuit in the multi-level gate circuits included in the target timing path, each level of gate circuit is sequentially taken as the target level gate circuit in the direction towards the starting point of the timing path, wherein the last gate circuit is the gate circuit adjacent to the end point of the timing path in the multi-level gate circuits.
[0011] In one optional implementation, determining a target-level gate circuit among the multi-level gate circuits included in the target timing path includes: Take any one of the multi-level gate circuits included in the target timing path as the target-level gate circuit.
[0012] In one optional implementation, the simulation test of the target functional unit based on the merged timing arc to obtain the characteristic data of the target functional unit includes: Acquire simulation excitation data and simulation process angle data; Multiple simulation files are generated based on the simulation excitation data and the simulation process angle data; Simulation tests were performed on the target functional unit after merging timing arcs according to each of the aforementioned simulation files to obtain simulation test data. The characteristic data of the target functional unit are determined based on the simulation test data.
[0013] In one optional implementation, the target-level gate circuit includes at least one input terminal, the simulation test data includes timing delay data, dynamic power consumption data and leakage power consumption data, and the leakage power consumption data includes the leakage power consumption of each output terminal of the target functional unit. The characteristic data of the target functional unit are determined based on the simulation test data, including: The timing delay duration and dynamic power consumption of each timing path in the front-end circuit connected to the target input terminal are obtained, wherein the target input terminal is any one of the at least one input terminal; Based on the timing delay duration and dynamic power consumption of each timing path in the front-end circuit, the timing characteristic data and dynamic power consumption characteristic data of the target functional unit are determined. The average leakage power consumption of each of the output terminals is determined as the leakage power consumption characteristic data of the target functional unit.
[0014] In an optional implementation, the data characterization processing method for the functional unit provided in the first aspect of this application further includes: generating a standard library file for the target functional unit based on the timing characterization data, dynamic power consumption characterization data, and leakage power consumption characterization data.
[0015] Secondly, this application provides a data characterization processing apparatus for a functional unit, comprising: An acquisition unit is used to acquire a target functional unit, wherein the target functional unit is used to implement a preset function of the integrated circuit, and any timing arc in the target functional unit includes at most one timing logic unit. The timing arc merging unit is used to perform timing arc merging operations on each timing path in the target functional unit; The data processing unit is used to perform simulation tests on the target functional unit based on the merged time arc to obtain the characteristic data of the target functional unit.
[0016] Thirdly, this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein the processor executes the computer program to implement the steps of the data characterization processing method for the functional unit provided in any embodiment of the first aspect of this application.
[0017] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, it implements the steps of the data characterization processing method for the functional unit provided in any embodiment of the first aspect of this application.
[0018] Based on the above, this application provides a data feature processing method for functional units, used to perform data feature processing on target functional units. Any timing arc of the target functional unit includes at most one timing logic unit. After obtaining the target functional unit, a timing arc merging operation is performed on each timing path in the target functional unit. Simulation testing is performed on the target functional unit based on the merged timing arc to obtain the feature data of the target functional unit. Since the timing arc of the target functional unit is merged before obtaining the feature data, the number of circuit state combinations that need to be simulated during the simulation test can be greatly reduced, thereby shortening the simulation test time, improving the efficiency of obtaining feature data, and correspondingly improving the overall design efficiency of integrated circuits. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a flowchart of a data feature processing method for a functional unit provided in an embodiment of this application.
[0021] Figure 2 This is a flowchart of a timing arc merging method provided in an embodiment of this application.
[0022] Figure 3 This is a timing path diagram of a functional unit provided in an embodiment of this application.
[0023] Figure 4 This is a flowchart of the method for obtaining functional unit feature data provided in the embodiments of this application.
[0024] Figure 5 This is a timing path diagram of another functional unit provided in an embodiment of this application.
[0025] Figure 6 This is a structural block diagram of a data feature processing device for a functional unit provided in an embodiment of this application.
[0026] Figure 7 This is a structural block diagram of a data feature processing device for another functional unit provided in an embodiment of this application.
[0027] Figure 8 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation
[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0029] As mentioned earlier, existing integrated circuits widely adopt customized functional units with higher integration and more complex logic functions. The application of such complex functional units in the design process inevitably requires the support of characteristic data. However, functional units usually have numerous input / output ports and internal circuit states. In the process of extracting characteristic data of functional units, the number of circuit state combinations that need to be simulated will increase exponentially, resulting in extremely long characteristic processes and extremely large data volumes. It is difficult to efficiently obtain characteristic data of functional units and reduce the overall design efficiency of integrated circuits.
[0030] To address the aforementioned issues, this application provides a data feature processing method for functional units. By merging the timing arcs of the target functional unit before acquiring the feature data, the number of circuit state combinations that need to be simulated during simulation testing can be greatly reduced, thereby shortening the simulation testing time, improving the efficiency of acquiring feature data, and correspondingly improving the overall design efficiency of integrated circuits.
[0031] The data feature processing method for functional units provided in this application is applied to electronic devices, which may be laptops, personal computers (PCs), tablets, or other electronic devices capable of running applications corresponding to the data feature processing method provided in this application. These will not be listed here. In some cases, it can also be applied to network-side servers. See also... Figure 1As shown, the data feature processing method for functional units provided in this application includes the following steps.
[0032] S100, Obtain the target functional unit.
[0033] In current integrated circuit design, integrated circuits can be divided into different functional units. Each functional unit is built based on a large number of standard units, has numerous input / output ports and internal circuit states, and is used to implement the preset functions of the integrated circuit. In general, the preset functions of each functional unit are different from each other. Due to the complexity of the functions and implementation, the process of obtaining the characteristic data of these functional units is extremely difficult.
[0034] The data feature processing method provided in this application aims to reduce the difficulty of data feature processing for functional units and improve the efficiency of acquiring feature data of functional units. It should be noted that the data feature processing method provided in this application can not be applied to any functional unit in an integrated circuit. Specifically, according to the static timing analysis method, any timing path in an integrated circuit must complete the transmission and output of data within one clock cycle and complete the reception of data in the next clock cycle. Only functional units that include at most one timing logic unit (i.e., the timing logic unit includes one or zero units, and the remaining logic units are combinational logic units) in any timing arc can be used as the target functional unit mentioned in this application. In other words, if the functional unit in the integrated circuit does not meet this condition, it cannot be used as the target functional unit mentioned in this application.
[0035] S110. Perform timing arc merging operation on each timing path in the target functional unit.
[0036] As mentioned earlier, the target functional unit includes a large number of input / output ports and internal circuit states. These input / output ports can be combined based on the internal circuit states to obtain a large number of timing paths. Each timing path includes multiple timing arcs connected in sequence. This step requires performing timing arc merging operations on each timing path in the target functional unit.
[0037] See Figure 2 As shown, as an optional implementation, this application provides a timing arc merging method, which may specifically include the following steps.
[0038] S1101. Sequentially take each timing path in the target functional unit as the target timing path.
[0039] Each timing path in the target functional unit corresponds to multiple timing arcs. To minimize the number of timing arcs, it is necessary to merge the timing arcs of each timing path. Based on this, each timing path in the target functional unit can be sequentially taken as the target timing path. After traversing all timing paths, the timing arc merging process of the target functional unit is completed. It should be noted that this embodiment uses the target timing path as an example to illustrate the timing arc merging process. When merging the timing arcs of other timing paths, the relevant content of this embodiment can be referred to.
[0040] S1102. Determine the target-level gate circuit among the multi-level gate circuits included in the target timing path.
[0041] The timing path distribution within the target functional unit can be found in [reference]. Figure 3 As shown, pin1-pinn represent the input ports of the target functional unit, and the output circuit is equipped with output ports ( Figure 3 (Not shown in the text) is used to output data to subsequent circuits. Each input port corresponds to a timing path from the output circuit. Each timing path consists of multiple logic units connected in series. The logic unit adjacent to the input port belongs to the first-level gate circuit. According to the signal transmission direction, each logic unit connected to the first-level gate circuit is defined as the second-level gate circuit, and so on, until the output circuit is reached. Assume it can be divided into m levels of gate circuits, where m ≥ 1. Combined with... Figure 3 As shown, generally speaking, the higher the level, the fewer the number of logic units it includes, and the lower the level, the more logic units it includes. In practical applications, the number of gate-level circuits included in a functional unit can also be called the logic depth.
[0042] As will be seen in the following content, the target-level gate circuit is the reference benchmark for timing arc merging in the data characterization processing method provided in this embodiment. This method needs to merge the timing arcs between the input port of the target functional unit and the target-level gate circuit. In practical applications, the target-level gate circuit can be determined in multiple ways among the multi-level gate circuits included in the target timing path.
[0043] The inventors discovered that for functional units built based on multi-level logic units, the timing of different timing paths is similar. Furthermore, for any timing path at any input port, the difference in timing characteristics under different timing arcs decreases with the transmission of multi-level logic units. In other words, as the number of gate-level circuits (i.e., logic depth) increases, the difference in timing characteristics between different timing paths decreases. Based on this, as an optional implementation, starting from the last gate-level circuit in the multi-level gate-level circuit included in the target timing path, each level of gate-level circuit can be sequentially used as the target level gate-level circuit in the direction towards the starting point of the timing path. This can improve the merging efficiency of timing arcs. It is understood that the last gate-level circuit mentioned in this embodiment refers to the gate-level circuit adjacent to the end point of the timing path in the multi-level gate-level circuit included in the functional unit. Figure 3 As shown in the diagram, the m-th level gate circuit is first taken as the target level gate circuit, and subsequent operation steps are executed. If the m-th level gate circuit cannot perform timing arc merging (the specific judgment process will be elaborated in the following content), then the (m-1)-th level gate circuit is taken as the target level gate circuit along the direction towards the starting point of the timing path. Correspondingly, if the (m-1)-th level gate circuit still cannot perform timing arc merging, then the process continues to proceed in the direction towards the starting point of the timing path until timing arc merging is completed or all levels of gate circuits are traversed.
[0044] It is understandable that the closer a gate-level circuit is to the end of the timing path, the more timing arcs it corresponds to. Therefore, by progressing step by step from the last gate-level circuit of the timing path to the beginning of the timing path, it is possible to ensure that as many timing arcs as possible can be merged, thereby reducing the amount of data to be processed in subsequent simulation analysis and improving the processing efficiency of data featureization.
[0045] Of course, in some cases, such as when the function and structure of the functional unit are relatively simple, or when the computing power of the electronic device is sufficient, it is not necessary to strictly start trying to merge timing arcs from the gate-level circuit adjacent to the end of the timing path. Merging timing arcs at any level of gate-level circuit can also improve the efficiency of data featureization to a certain extent. Based on this, as another optional implementation, any level of the multi-level gate-level circuits included in the target timing path can be taken as the target-level gate-level circuit, and timing arc merging can be attempted starting from the target-level gate-level circuit. It is understandable that, since any level of gate-level circuit is taken as the target-level gate-level circuit, if it is determined by the method described later that timing arcs can be merged at the target-level gate-level circuit, it is also possible to continue trying in the direction closer to the end of the timing path, taking the next level of gate-level circuit of the current level as the target-level gate-level circuit. For example, if the current level gate-level circuit is the 5th level gate-level circuit, and it is determined that timing arcs can be merged at the 5th level gate-level circuit, it is also possible to further try to take the 6th, 7th, ... levels as target-level gate-level circuits. Conversely, if it is determined using the methods described later that it is difficult to merge timing arcs at the target level gate circuit, then it is necessary to continue along the direction close to the starting point of the timing arc and try to use the previous level gate circuit of the current level gate circuit as the target level gate circuit. For example, if it is determined that it is difficult to merge timing paths at the 5th level gate circuit, then it is possible to continue to try to use the 4th level gate circuit as the target level gate circuit.
[0046] S1103. Obtain the timing delay duration from the starting point of the target timing path to the target gate circuit.
[0047] After determining the target gate-level circuit, the timing delay duration from the starting point of the timing path to the target gate-level circuit is further obtained. Combined with... Figure 3 As shown, the timing path of input port pin n is used as the target timing path ( Figure 3 (shown as dashed lines in the image) In practical applications, the timing characteristics of the target timing path may be affected by the other n-1 input ports, and each input port may have two input values, "1" or "0". Based on this, when analyzing the timing characteristics of the target timing path, it is necessary to simulate for each input case of the other input ports to obtain the timing characteristic data of the target timing path under different input values of the other input ports.
[0048] Based on the above, when obtaining the timing delay duration from the starting point of the target timing path to the target gate circuit, it is necessary to traverse all input value combinations of other timing paths besides the target timing path, and for each input value combination, obtain the timing delay duration from the starting point of the target timing path to the target gate circuit.
[0049] by Figure 3The circuit architecture shown is invalid. The timing path of pin n (shown by the dashed line) is used as the target timing path, and the m-th level gate circuit is used as the target level gate circuit. The other n-1 input ports will correspond to 2... （n-1） For each combination of input values, and considering the case where other input ports use each combination of input values as input data, timing simulation analysis is performed on the target timing path to obtain the timing delay from the starting point of the timing path to the target gate circuit under different input value combinations. As mentioned earlier, Figure 3 The illustrated embodiment corresponds to 2. （n-1） Two combinations of input values are required. （n-1） The subsequent time-series simulation analysis yielded 2... （n-1） Each timing delay duration.
[0050] S1104. Merge the timing arcs of the target timing path before the target gate circuit according to the timing delay duration.
[0051] After obtaining all timing delays of the target timing path from its starting point to the target gate circuit, the timing arcs of the target timing path preceding the target gate circuit are merged based on these delays. However, merging timing arcs requires that, at the logic level corresponding to the target gate circuit, the input states of other timing paths have negligible impact on the timing characteristics of the target timing path. Only when this condition is met can the timing arcs of the target timing path preceding the target gate circuit be merged.
[0052] Specifically, firstly, the timing delay fluctuation duration is determined based on multiple timing delay durations corresponding to the target timing path. The fluctuation duration is then used to measure the overall fluctuation of all timing delay durations obtained in S1103. This application provides a method for determining the timing delay fluctuation duration: the maximum and minimum timing delay durations are determined among the multiple timing delay durations corresponding to the target timing path, and the difference between the maximum and minimum timing delay durations is taken as the timing delay fluctuation duration. Of course, other methods can also be used to determine the timing delay fluctuation duration, as long as the obtained timing delay fluctuation duration can measure the overall fluctuation of all timing delay durations. As long as this does not exceed the core concept of this application, it also falls within the scope of protection of this application.
[0053] Furthermore, if the obtained timing delay fluctuation duration is within the preset duration range, it is determined that the timing characteristics of the target timing path at the target level gate circuit are not affected by the input state of other input ports, and the timing arcs from the starting point of the timing path to the target level gate circuit can be merged into a single timing arc. Conversely, if the obtained timing delay fluctuation duration is not within the preset duration range, it is determined that the timing characteristics of the target timing path at the target level gate circuit are significantly affected by the input state of other input ports, and timing arc merging cannot be performed. In this case, it is necessary to return to execute S1101 and determine the target level gate circuit again among the multi-level gate circuits included in the target timing path until the timing arcs from the starting point of the timing path to the target level gate circuit are merged into a single timing arc. Of course, if timing arc merging cannot be performed after traversing all levels of gate circuits, the current execution flow can be exited.
[0054] As for the specific value of the aforementioned preset duration range, it can be determined in combination with the specific project requirements, the design parameters of the functional unit, and especially the requirements for timing characteristics. This application does not limit the specific value of the preset duration range.
[0055] As described above, each timing path of the target functional unit is traversed until the timing arcs of all timing paths are merged. This can achieve an exponential reduction in the number of timing arcs of the target functional unit, effectively improving the execution efficiency of simulation testing in subsequent processes.
[0056] S120. Simulation tests are performed on the target functional unit based on the merged timing arc to obtain the characteristic data of the target functional unit.
[0057] See Figure 4 As shown in the figure, this application provides a method for simulating and testing a target functional unit to obtain characteristic data, which mainly includes the following steps.
[0058] S1201. Obtain simulation excitation data and simulation process angle data.
[0059] In modern integrated circuit design, simulation tests are required before tape-out to obtain operating data of the integrated circuit under different process corners. This is to determine whether the integrated circuit meets the actual requirements and to provide a reference for subsequent design work. Based on this, the target functional unit, as part of the integrated circuit, also needs to undergo performance testing under different process corners. Therefore, it is necessary to obtain simulation process corner data.
[0060] It is understandable that the target functional unit needs to implement the preset function based on the input data in actual application. Therefore, when testing the performance of the target functional unit, it is necessary to simulate the data input situation in actual application. Thus, it is also necessary to obtain simulation stimulus data to support the target functional unit in implementing the preset function.
[0061] The specific composition of the simulation excitation data and simulation process corner data can be determined by the preset functions of the target functional unit, the input data, and the operating environment defined in the design file in actual application, and will not be described in detail here.
[0062] S1202. Generate multiple simulation files based on simulation excitation data and simulation process angle data.
[0063] In actual simulation testing, a large amount of simulation stimulus data and simulation process corner data are usually required. The number of simulation test scenarios obtained based on the combination of simulation stimulus data and simulation process corner data is even greater. In order to improve the efficiency of simulation testing, multiple simulation files can be generated based on simulation stimulus data and simulation process corner data. As for the specific generation process of simulation files, it can be implemented with reference to relevant technologies. This application does not limit it in this regard.
[0064] S1203. Perform simulation tests on the target functional unit after merging timing arcs according to each simulation file to obtain simulation test data.
[0065] After obtaining multiple simulation files, simulation tests can be performed on the target functional unit after merging timing arcs according to each simulation file, and the corresponding simulation test data can be obtained. It is understandable that, since the number of timing arcs in the target functional unit after merging timing arcs is reduced exponentially, the time required for the simulation test process can be greatly reduced, significantly improving the overall efficiency of the simulation test process. The specific process of performing simulation tests on the target functional unit for any given simulation file can be referred to relevant technologies and will not be detailed here.
[0066] S1204. Determine the characteristic data of the target functional unit based on the simulation test data.
[0067] In actual simulation testing, the obtained simulation test data may include various data types. The simulation test data related to the functional unit characterization process mainly includes: timing delay data, dynamic power consumption data and leakage power consumption data. In addition, leakage power consumption data refers to the leakage power consumption of each output terminal of the target functional unit.
[0068] It is understandable that the above timing arc merging process is based on the simulation test results of the target functional unit, rather than merging from the circuit logic. This will cause the merged timing arcs to form a logical inclusion relationship, and the timing arc conditions cannot be independent of each other. Therefore, in order to represent the merged timing arcs, it is necessary to make a necessary simplification representation of the circuit architecture of the target functional unit.
[0069] Combination Figure 3 As shown, each gate-level circuit in the target functional unit includes at least one input terminal. For example, the m-th gate-level circuit includes two input terminals, and the (m-1)-th gate-level circuit includes at least three input terminals (more input terminals are omitted in the figure). Based on this, any one of the at least one input terminal included in the target-level gate-level circuit in the target functional unit can be taken as the target input terminal, and all circuits connected to the target input terminal can be defined as the preceding stage circuit. Figure 5 As shown, the logic unit connected to the output terminal Z is the target-level gate circuit. The target-level gate circuit includes two input terminals, and the preceding circuit connected to each input terminal is the circuit within the dashed box.
[0070] Based on the above, the timing delay duration and dynamic power consumption of each timing path in the front-end circuit connected to the target input terminal of the target gate circuit are first obtained. Then, based on the timing delay duration and dynamic power consumption of each timing path in the front-end circuit, the timing characteristic data and dynamic power consumption characteristic data of the target functional unit are determined. Specifically, as an optional implementation, the timing path with the largest timing characteristic delay among the timing paths included in the front-end circuit can be taken as the critical timing path, and the timing delay duration of the critical timing path can be taken as the timing delay duration of the front-end circuit. Correspondingly, the dynamic power consumption of the critical timing path can be taken as the dynamic power consumption of the front-end circuit. After determining the timing delay duration and dynamic power consumption of all front-end circuits connected to the target gate circuit in this way, the timing characteristic data and dynamic power consumption characteristic data of the target functional unit are obtained.
[0071] by Figure 5 Taking the circuit architecture shown as an example, for the target timing path from A1 to Z (as shown by the dashed line in the figure), the relevant technologies record the timing arc of the target timing path as follows: when: "B1&A2&B2&A3&B3&A4&B4" Assuming that timing arcs can be combined in the last-stage gate circuit, this gate circuit includes two inputs, each of which includes a preceding stage circuit as shown in the dashed box. Treating each preceding stage circuit as a whole, we determine its critical timing paths. Assuming the critical timing path of one preceding stage circuit is A2 to Z, and the critical timing path of the other preceding stage circuit is A4 to Z, based on this, we take input A2 as the typical input port of its corresponding preceding stage circuit, and correspondingly, input A4 as the typical input port of its corresponding preceding stage circuit. The combined timing arc can be represented as: when: “A2&A4” Based on the above, the timing delay and dynamic power consumption of the timing path from A1 to Z when A2 and A4 are respectively set to logic value 1 (at this time, the logic states of other input pins are not considered), are used as... Figure 5 The timing characteristics and dynamic power consumption data of the functional unit pins A1 to Z are shown.
[0072] Furthermore, in related technologies, the leakage power consumption in the standard unit characteristic data refers to the leakage power consumption under the premise of including the complete timing arc. However, the timing arc merging process of this method may result in the loss of some timing arcs, that is, the omission of some timing arcs, which makes it impossible for the leakage power consumption of each output port corresponding to the target functional unit to be independent. Therefore, the data characteristic processing method provided in this embodiment uses the average value of the leakage power consumption of each output terminal of the target functional unit as the leakage power consumption characteristic data of the target functional unit.
[0073] It should be noted that, in practical applications, the aforementioned dynamic power consumption data and leakage power consumption data can be collectively referred to as power consumption characterization data.
[0074] Furthermore, as an optional implementation, in order to facilitate the direct calling of the target functional unit in the subsequent physical design process, a standard library file of the target functional unit can be generated based on the obtained timing characteristic data, dynamic power consumption characteristic data and leakage power consumption characteristic data. With this setting, when calling the target functional unit or performing simulation testing, the target functional unit can be called directly like calling a standard unit, thereby improving the efficiency of physical design and simulation testing.
[0075] In summary, the data feature processing method provided in this embodiment is used to perform data feature processing on a target functional unit. Any timing arc of the target functional unit includes at most one timing logic unit. After obtaining the target functional unit, a timing arc merging operation is performed on each timing path in the target functional unit. Based on the merged timing arc, the target functional unit is simulated and tested to obtain the feature data of the target functional unit. Since the timing arc of the target functional unit is merged before obtaining the feature data, the number of circuit state combinations that need to be simulated during the simulation test can be greatly reduced, thereby shortening the simulation test time, improving the efficiency of obtaining feature data, reducing the size of the feature data text, and correspondingly improving the overall design efficiency of the integrated circuit.
[0076] Furthermore, the obtained characteristic data is encapsulated into a standard library file, which can be called like a standard unit in subsequent physical design or simulation testing. This can significantly simplify the physical design and simulation testing process and is of great significance for improving design efficiency.
[0077] The data feature processing apparatus for functional units provided by this invention will be described below. This apparatus belongs to the same concept as the data feature processing method for functional units provided in the embodiments of this application. It can execute the data feature processing method for functional units provided in any embodiment of this application and possesses the corresponding functional modules and beneficial effects for executing the data feature processing method for functional units. Technical details not described in detail in this embodiment can be found in the data feature processing method for functional units provided in the embodiments of this application, and will not be repeated here.
[0078] See Figure 6 The feature data processing apparatus for functional units provided in this application embodiment includes: The acquisition unit 10 is used to acquire a target functional unit, which is used to implement a preset function of the integrated circuit, and any timing arc in the target functional unit includes at most one timing logic unit. The timing arc merging unit 20 is used to perform timing arc merging operations on each timing path in the target functional unit; The data processing unit 30 is used to perform simulation tests on the target functional unit based on the merged time arc to obtain the characteristic data of the target functional unit.
[0079] Furthermore, embodiments of this application also provide a feature-based data processing apparatus for another functional unit, see [link to relevant documentation]. Figure 7 As shown, in Figure 6 Based on the illustrated embodiment, the feature data processing apparatus provided in this embodiment further includes: The file generation unit 40 is used to generate a standard library file for the target functional unit based on the timing characteristic data, dynamic power consumption characteristic data and leakage power consumption characteristic data.
[0080] Below, for reference Figure 8 The electronic device provided in this embodiment of the invention may include: at least one processor 100, at least one communication interface 200, at least one memory 300, and at least one communication bus 400. In this embodiment of the invention, the number of processor 100, communication interface 200, memory 300, and communication bus 400 is at least one, and the processor 100, communication interface 200, and memory 300 communicate with each other through communication bus 400; obviously, Figure 8 The communication connections shown for the processor 100, communication interface 200, memory 300, and communication bus 400 are optional. Optionally, the communication interface 200 can be an interface of a communication module, such as the interface of a GSM module; the processor 100 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.
[0081] The memory 300 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.
[0082] Specifically, the processor 100 is used to execute the application program in the memory to implement the steps of the data feature processing method of the functional unit described above.
[0083] In some embodiments, this embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more instructions implementing the above steps are stored. When these one or more instructions are executed by one or more processors, the processors perform the data characterization processing method of the functional unit described above. For specific implementation details, please refer to the foregoing description; further elaboration is not provided here.
[0084] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the data characterization processing method of the functional units according to various embodiments of this application as described above.
[0085] Computer program products can be written in any combination of one or more programming languages to perform the operations of the embodiments of this application. The programming languages include object-oriented programming languages such as Java and C++, as well as conventional procedural programming languages such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.
[0086] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.
[0087] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.
[0088] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.
[0089] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.
[0090] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.
[0091] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.
Claims
1. A method for data feature processing of a functional unit, characterized in that, include: Obtain a target functional unit, which is used to implement a preset function of an integrated circuit, and any timing arc in the target functional unit includes at most one timing logic unit; Perform a timing arc merging operation on each timing path in the target functional unit; The target functional unit is simulated and tested based on the merged time arc to obtain the characteristic data of the target functional unit.
2. The method according to claim 1, characterized in that, Perform a timing arc merging operation on each timing path in the target functional unit, including: Each timing path in the target functional unit is sequentially taken as the target timing path; Determine the target-level gate circuit among the multi-level gate circuits included in the target timing path; Obtain the timing delay duration from the starting point of the target timing path to the target gate circuit; The timing arcs of the target timing path before the target gate circuit are merged according to the timing delay duration.
3. The method according to claim 2, characterized in that, Obtaining the timing delay duration from the starting point of the target timing path to the target gate circuit includes: Iterate through all combinations of input values for timing paths other than the target timing path; For each combination of input values, the timing delay duration from the starting point of the target timing path to the target gate circuit is obtained.
4. The method according to claim 3, characterized in that, Based on the timing delay duration, the timing arcs of the target timing path preceding the target-level gate circuit are merged, including: The timing delay fluctuation duration is determined based on the multiple timing delay durations corresponding to the target timing path; If the timing delay fluctuation duration is within a preset duration range, the timing arcs of the target timing path from the starting point of the timing path to the target gate circuit are merged into one timing arc. If the timing delay fluctuation duration is not within the preset duration range, the target level gate circuit is determined again in the multi-level gate circuits included in the target timing path, until the timing arcs from the starting point of the timing path to the target level gate circuit are merged into a single timing arc.
5. The method according to claim 4, characterized in that, The timing delay fluctuation duration is determined based on multiple timing delay durations corresponding to the target timing path, including: Determine the maximum and minimum timing delay durations from among the multiple timing delay durations corresponding to the target timing path; The difference between the maximum timing delay duration and the minimum timing delay duration is determined as the timing delay fluctuation duration.
6. The method according to claim 2, characterized in that, Determining the target-level gate circuit among the multi-level gate circuits included in the target timing path includes: Starting from the last gate circuit in the multi-level gate circuit included in the target timing path, each level of gate circuit is sequentially taken as the target level gate circuit in the direction towards the starting point of the timing path, wherein the last gate circuit is the gate circuit adjacent to the end point of the timing path in the multi-level gate circuit.
7. The method according to claim 2, characterized in that, Determining the target-level gate circuit among the multi-level gate circuits included in the target timing path includes: Take any one of the multi-level gate circuits included in the target timing path as the target-level gate circuit.
8. The method according to any one of claims 2 to 7, characterized in that, The simulation test of the target functional unit based on the merged time arcs yields the characteristic data of the target functional unit, including: Acquire simulation excitation data and simulation process angle data; Multiple simulation files are generated based on the simulation excitation data and the simulation process angle data; Simulation tests were performed on the target functional unit after merging timing arcs according to each of the aforementioned simulation files to obtain simulation test data. The characteristic data of the target functional unit are determined based on the simulation test data.
9. The method according to claim 8, characterized in that, The target-level gate circuit includes at least one input terminal, and the simulation test data includes timing delay data, dynamic power consumption data and leakage power consumption data, and the leakage power consumption data includes the leakage power consumption of each output terminal of the target functional unit. The characteristic data of the target functional unit are determined based on the simulation test data, including: The timing delay duration and dynamic power consumption of each timing path in the front-end circuit connected to the target input terminal are obtained, wherein the target input terminal is any one of the at least one input terminal; Based on the timing delay duration and dynamic power consumption of each timing path in the front-end circuit, the timing characteristic data and dynamic power consumption characteristic data of the target functional unit are determined. The average leakage power consumption of each of the output terminals is determined as the leakage power consumption characteristic data of the target functional unit.
10. The method according to claim 9, characterized in that, Also includes: Based on the timing characteristic data, dynamic power consumption characteristic data, and leakage power consumption characteristic data, a standard library file for the target functional unit is generated.
11. A data feature processing device for a functional unit, characterized in that, include: An acquisition unit is used to acquire a target functional unit, wherein the target functional unit is used to implement a preset function of the integrated circuit, and any timing arc in the target functional unit includes at most one timing logic unit. The timing arc merging unit is used to perform timing arc merging operations on each timing path in the target functional unit; The data processing unit is used to perform simulation tests on the target functional unit based on the merged time arc to obtain the characteristic data of the target functional unit.
12. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, characterized in that, When the processor executes the computer program, it implements the steps of the data characterization processing method for the functional unit as described in any one of claims 1 to 10.
13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the data characterization processing method for the functional unit as described in any one of claims 1 to 10.