Impulse neural network reasoning-oriented execution path control method and equipment

Abstract

The invention discloses a pulse neural network reasoning-oriented execution path control method and equipment. The method comprises the following steps of: generating and solidifying a group of execution path control data structures which can be directly read and executed by a processor in an offline stage; in an online reasoning stage, a processor reads the control data structure to generate a calculation unit enabling mask or an active index list according to low-cost statistical characteristics, which can be obtained in real time in a prefix time window, of an input sample; and according to this, scheduling execution is only performed on arithmetic instruction sequences and state updating paths corresponding to the shared subspace and the selected expert subspace, real skipping is performed on parameter block loading, arithmetic instruction transmitting, register or cache writing and state writing back corresponding to the non-enabled subspace, and a Top-k or full-activated rollback mechanism is triggered when the confidence coefficient is insufficient. According to the method, on the premise that the output precision is controllable, the number of multiply-add instruction sequences, the number of state write-back times and storage access and data handling overhead are reduced, and the resource utilization efficiency and controllability of reasoning deployment are improved.

Description

Technical Field

[0001] This invention relates to artificial intelligence and deep learning technologies in the field of computer technology, specifically to an execution path control method and device for spiking neural network inference. Background Technology

[0002] Spiking Neural Networks (SNNs) typically process input in discrete time steps, performing synaptic weighted summation, membrane potential accumulation, threshold comparison, and pulse output at each time step, accompanied by updates and write-backs of neuron states (e.g., membrane potential, reset state, refractory period markers, etc.). When performing SNN inference on a general-purpose processor (CPU), graphics processing unit (GPU), or other general-purpose accelerator, the above process manifests at the implementation level as follows: the processor repeatedly reads model parameters and intermediate activation data from memory in multiple time-step loops, executes a large number of arithmetic and comparison instructions, and writes the updated intermediate states back to memory or cache levels. The overhead of related arithmetic instruction issuance, state write-back, and memory access is usually difficult to eliminate automatically through existing hardware microarchitectures or conventional compiler optimizations.

[0003] In recent years, to improve the representational power and accuracy of SNNs in complex tasks such as image classification, existing techniques often expand model capacity by increasing network depth, widening the number of channels, or introducing attention mechanisms. However, as the model size and number of time steps increase, the number of synaptic events and impulse firings in the network also increases, leading to an increase in the number of state updates related to synaptic events, an increase in the frequency of register or cache writes, and an increase in the access to intermediate activations and parameters. For dense SNNs deployed on general-purpose processors or accelerators in the form of fixed operators or kernels, these expansions ultimately manifest as a significant increase in computational load, memory access load, and data transport overhead during the inference phase, weakening the deployment advantages in low-power or low-latency inference scenarios.

[0004] To improve model capacity while controlling the overhead of a single inference attempt, existing technologies have proposed various approaches to reduce inference costs, such as parameter pruning, quantization compression, and conditional computation. One representative approach is to introduce a structure with sub-network selection capabilities, allowing each input sample to be computed only through a subset of sub-networks or expert paths during inference. Taking the Mixture of Experts (MoE) structure as an example, a typical approach is to use gating or routing modules to select certain expert sub-networks for computation based on input features, thus theoretically decoupling the overall model capacity from the computational cost of a single inference attempt. Some studies have also attempted to apply similar ideas to SNNs, using gating mechanisms based on spurious activity or thresholds to select different spurious sub-network paths for execution at different time steps or for different samples.

[0005] However, from the perspective of computer execution path control, the above-mentioned sub-network selection schemes still have the following common problems when implemented on general-purpose processors or accelerators:

[0006] First, gating mechanisms often exist in the form of soft gating or probabilistic selection, lacking hard routing constraints that directly interface with the underlying execution engine. Even if a sparse activation pattern can be formed at the model representation level, in actual execution, it may still be necessary to assign operators or kernels to multiple candidate experts and prepare corresponding intermediate state buffers. This means that expert paths that are not expected to be selected will still generate arithmetic operations and state write-backs, resulting in a situation where the apparent sparseness does not significantly reduce the actual execution load, making it difficult to reduce the number of instructions and memory access overhead in a timely and stable manner.

[0007] Secondly, SNNs exhibit significant time-series and state accumulation characteristics, with neuron states such as membrane potential and adaptive thresholds continuously evolving across multiple time steps. When frequently switching between different expert paths or sub-network paths in the time dimension, the intermediate states corresponding to different paths require frequent reading, writing, and switching, which can easily lead to cache invalidation, increased data transfer, and additional context switching overhead. At the same time, excessively frequent path switching can undermine the assumption of continuous state evolution, affecting the network's numerical stability and inference accuracy in both channel and time dimensions, thereby weakening the stability advantage of conditional computation in practical deployments.

[0008] Third, many existing lightweight or conditional computation methods for SNNs (including some that introduce subnetwork selection mechanisms) typically rely on end-to-end training from scratch or large-scale retraining of the backbone network to directly constrain sparsity or gating behavior at the training loss level. On the one hand, these methods have high training costs, making it difficult to directly reuse existing high-performance pre-trained dense SNN models; on the other hand, end-to-end training often does not explicitly produce reusable intermediate products, such as structure mapping tables describing the functional subspace partitioning of the target layer, sample-level expert selection control labels for inference stage decisions, and routing control parameters that can be directly deployed into the inference engine. The lack of such control data structures means that it is difficult to naturally transform the gating behavior obtained from offline training into processor-readable and executable execution path control signals during the inference stage. This makes it difficult to audit and debug the reasons for structure formation, the basis for routing decisions, and the sources of computational savings, and makes it difficult to integrate them as a clear execution path control mechanism into a general inference framework.

[0009] In summary, existing solutions often focus on model training and gating strategy design, lacking a unified approach centered on execution path control. They fail to generate and solidify an execution path control data structure directly readable by the processor in the offline phase, while reusing pre-trained dense SNNs, and then transform this data structure into enable control signals that control the execution of arithmetic instructions, neuron state updates, and memory accesses during the inference phase. Therefore, there is an urgent need for an execution path control method for inference deployment of pre-trained dense SNNs. This method should be able to mine the functional subspace structure within the network through post-training, generate an execution path control data structure describing functional subspace partitioning and sample-level expert selection in the offline phase, and have the processor read this data structure during the inference phase to generate computation unit enable control signals. This prevents the execution of major arithmetic instructions (such as multiply-add or compare), neuron state update write-backs, and parameter block or intermediate activation data loading and memory accesses corresponding to unselected subspaces. This reduces the number of arithmetic instructions executed, state write-backs, and memory accesses by the processor while maintaining controllable output quality, thereby improving the inference execution efficiency and deployment controllability of SNNs on general computing platforms. Summary of the Invention

[0010] Purpose of the invention: To address the common technical problems in the engineering deployment of existing conditional computing or lightweight solutions, this invention provides an execution path control method and device for spiking neural network inference. Under the premise of controllable output accuracy, it reduces the number of multiply-accumulate instruction sequences, the number of state write-backs, storage access, and data transport overhead, thereby improving the resource utilization efficiency and controllability of inference deployment.

[0011] Technical solution: The execution path control method for spiking neural network inference described in this invention includes the following steps:

[0012] (1) Input data acquisition and preprocessing: Acquire the input data to be inferred and preprocess it, and encode the input data into a pulse sequence or event representation suitable for spiking neural network (SNN);

[0013] (2) Offline control data structure generation: Perform structure analysis on at least one target layer of the pre-trained dense SNN. Based on the target layer weight parameters and calibration dataset, divide the target layer parameters into shared subspace parameter segments and multiple expert subspace parameter segments. Construct a structure partitioning mapping table Partition, evaluate the output stability and resource consumption of different expert subspace enable configurations, and generate sample-level execution path control labels for each sample.

[0014] (3) Control data structure solidification and storage: Obtain the offline statistical feature vector B-view corresponding to the preset prefix time window, train the router based on the sample-level execution path control label and the feature vector B-view to obtain the routing control parameters used to predict the expert subspace activation result based on B-view; and solidify and store the structure partitioning mapping table Partition, the sample-level execution path control label and the routing control parameters in the memory in the form of data that can be directly read by the processor, so that the processor can read them during the online inference stage;

[0015] (4) Routing decision during the online inference phase: Obtain the low-cost statistical features of the target layer within the preset prefix time window and form an online statistical feature vector B-view. Read the routing control parameters from the memory and generate the expert subspace activation result based on the B-view and the routing control parameters.

[0016] (5) Enable control signal generation: Combine the expert subspace activation result with the structure partitioning mapping table Partition to generate enable control signals to indicate whether each computing unit in the target layer participates in this inference calculation;

[0017] (6) Actual execution skip: Based on the enable control signal, the computing unit in the disabled state skips the corresponding arithmetic instruction issuance, neuron state update and write-back, parameter block or intermediate activation data loading and storage access;

[0018] (7) Output of reasoning task results: Determine and output the reasoning task results based on the reasoning calculation results.

[0019] Furthermore, the input data in step (1) includes the input image to be classified, event stream data, or other sensor time-series data.

[0020] Further, the offline control data structure generation in step (2) includes parameter reorganization, structure mining, and teacher signal generation; the parameter reorganization is performed by the processor in the offline stage, and is used to reorganize the parameters of at least one target layer into shared parameter segments and multiple expert parameter segments without changing the inference semantics of the pre-trained dense SNN under the full expert-enabled configuration, and generate an index mapping relationship that can be referenced by the subsequent execution path control logic, so as to provide an addressable parameter layout and structure partitioning basis for the subsequent execution path control; the structure mining uses calibration data to statistically analyze the distribution behavior of the computing units inside the target layer to obtain the partitioning results of the shared subspace and multiple expert subspaces, and The signal is written into memory as a structural prior for subsequent teacher signal generation and routing control parameter solving. During the inference phase, it is used in conjunction with the routing output to convert it into specific computational unit enable control signals. Without changing the backbone network parameters, the teacher signal generation is based on the subspace partitioning described by Partition. The stability of the inference output and resource consumption of the same input sample under different expert subspace enable configurations are evaluated offline. Under a given resource budget, a reusable expert enable configuration is determined for each sample. The configuration is written into memory in the form of sample-level execution path control tags for subsequent routing control parameter solving and budget level selection during the deployment phase.

[0021] Furthermore, the structure partitioning mapping table Partition described in step (2) is in the form of an array, bitmap, or index list, recording the correspondence between channels or neuron groups and subspace identifiers.

[0022] Furthermore, the generation of the sample-level execution path control label in step (2) is based on a preset resource budget rule; the resource budget rule includes at least three cost trade-off strategies: saving, balancing, and conservatism.

[0023] Furthermore, the routing control parameters in step (3) include at least threshold parameters and linear weight parameters, and are stored in the memory in the form of an array, a threshold table, a linear weight parameter table, an index list, a bitmap, or a combination thereof.

[0024] Furthermore, in step (4), a rollback mechanism is set up during the process of generating the expert subspace activation result based on B-view and routing control parameters. The triggering conditions include the routing output confidence being lower than the threshold, the expert selection sorting being unstable, the routing output distribution being too flat, or the runtime budget statistics fluctuating abnormally. The rollback actions include increasing the Top-k value or enabling the full expert subspace.

[0025] Furthermore, the enable control signal in step (5) is a channel-level or expert-level enable mask, or an active index list; the computing units of the shared subspace and the selected expert subspace are in an enabled state, and the computing units of the unselected expert subspace are in an disabled state; the enable control signal can be directly read and parsed by the execution engine.

[0026] Furthermore, the actual execution skipping in step (6) is achieved in the following way:

[0027] ① On a general-purpose processor, through branch or loop control, based on the enable mask or active index list, only the enabled channels or experts are entered into the corresponding instruction sequence, so that the multiply-add, compare and write-back instructions of the disabled computing units are not issued;

[0028] ② On a graphics processor or other accelerator, operators or kernels are created and emitted only for the shared subspace and the selected expert subspace through operator or kernel-level scheduling, so that the parameter blocks corresponding to the unselected experts do not participate in this execution.

[0029] ③ By generating an active computing unit index list based on the enable mask, operations and status updates are performed only on the computing units indicated by the index list, effectively aggregating computations into a smaller set of work, reducing small-granularity task fragmentation and synchronization overhead.

[0030] An electronic device according to the present invention includes a memory, a processor, and an accelerator;

[0031] The memory is used to store computer programs that can run on the processor, including storing pre-trained dense SNN model parameters, image classification dataset samples for calibration and evaluation, as well as A-view and B-view statistical features, structure partitioning mapping (Partition), sample-level execution path control labels, and routing control parameters.

[0032] The processor is used to execute the steps of the execution path control method for spiking neural network inference as described above when running the computer program;

[0033] The accelerator is used to accelerate forward inference and offline evaluation of spiking neural networks.

[0034] Beneficial effects: Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] 1. Reduce the training and development costs of introducing execution path control mechanisms. In the offline stage, this invention generates a structure partitioning map, sample-level execution path control labels, and routing control parameters by analyzing the structure and evaluating the behavior of a pre-trained dense SNN. This allows for the acquisition of deployable execution path control data structures without performing end-to-end retraining of the backbone network from scratch, thereby significantly reducing the cost of adding execution path control capabilities to existing pre-trained models.

[0036] 2. Improve the auditability and controllability of execution paths; This invention explicitly generates and persistently stores control parameters such as Partition, execution path control tags, and deployment thresholds, forming a set of reusable and traceable intermediate products; With the help of these data structures, engineers can clearly analyze the target layer functional subspace structure, sample-level expert selection criteria, and sources of computational savings, which facilitates debugging, auditing, and version management in engineering practice, and supports configuring different execution path control strategies according to scenarios;

[0037] 3. Reduce resource overhead during inference and support budget configuration; During the inference phase, the processor generates a computation unit enable mask or active index list based on routing control parameters and partitions, ensuring that computations corresponding to unselected expert subspaces are not scheduled at the execution level. This includes not loading corresponding parameter blocks or intermediate buffers, not issuing corresponding multiply-add or compare main arithmetic instruction sequences, and avoiding write-back of neuron states and register or cache writes to unenabled subspaces, thereby reducing the number of instruction issuances, the number of state write-backs, and the overhead of memory access and data movement. In graphics processor or accelerator implementations, this can be manifested as unenabled experts not generating corresponding operators or kernel issuances and related memory accesses. By configuring parameters such as resource budget rules, Top-k strategies, confidence thresholds, and backoff rules, this invention can generate execution path control strategies with different budget levels to adapt to the resource constraint requirements of different devices and scenarios.

[0038] 4. Improve deployment stability and engineering availability of execution paths; In implementations with multi-level caching or requiring loading parameter blocks by expert, this invention reduces unnecessary frequent expert switching through structured partitioning and relatively stable expert subspace selection logic; Combined with a confidence-driven fallback mechanism, it can reduce the risk of additional parameter loading and cache failure caused by path jitter, thereby improving the robustness and deployment stability of the overall inference process and making the execution path control mechanism easier to integrate into a general inference framework. Attached Figure Description

[0039] Figure 1 This is a flowchart of an execution path control method for spiking neural network inference;

[0040] Figure 2 This is an interactive schematic diagram of the offline stage structure partitioning mapping and routing control parameter solving process provided by the present invention;

[0041] Figure 3 This is a logical flowchart of the online control and rollback mechanism for the execution path during the inference phase of this invention. Detailed Implementation

[0042] The present invention will now be described in further detail with reference to the accompanying drawings.

[0043] like Figure 1 As shown, this invention proposes an execution path control method for spiking neural network inference, the specific implementation process of which is as follows:

[0044] Step 1: Input Data Acquisition and Preprocessing. Acquire the input data to be inferred and preprocess it, encoding the input data into pulse sequences or event representations suitable for spiking neural networks (SNNs).

[0045] Input data includes the input image to be classified, event stream data, or other sensor time-series data. In this embodiment, image classification is taken as an example.

[0046] The original image undergoes resizing, normalization, color space conversion, and optional data augmentation operations, and the preprocessed image tensor is written to the input buffer. When using event coding or pulse coding, the preprocessed image tensor is converted into a pulse sequence or event sequence according to a preset coding rule and written to the pulse input buffer. In the offline phase, each sample in the calibration sample set undergoes the same preprocessing process, and the preprocessing results are used for subsequent structural analysis, path control label generation, and deployment effect evaluation. In the online inference phase, the same preprocessing is performed on the actual input data, and the results are provided to the input of the pre-trained dense SNN, ensuring consistency between offline analysis and online deployment on the input side.

[0047] Step 2: Offline control data structure generation, including parameter recycling, structure mining, and teacher signal generation, which are used together to generate the structure partitioning mapping table Partition and sample-level execution path control labels.

[0048] (2.1) Parameter reorganization: This step is performed by the processor in the offline stage. It is used to reorganize the parameters of at least one target layer into shared parameter segments and multiple expert parameter segments without changing the inference semantics of the pre-trained dense SNN under the full expert-enabled configuration, and generate an index mapping relationship that can be referenced by the subsequent execution path control logic, so as to provide an addressable parameter layout and structure partitioning basis for the subsequent execution path control.

[0049] like Figure 2 As shown, in the Upcycling step, the processor reads the model parameters of the pre-trained dense SNN, the set of target layers to be reorganized, and the preset configuration of the number of experts and the size of the shared subspace (e.g., the proportion or number of shared channels) from memory. The output of Upcycling includes the reorganized parameter set, which includes at least: a set of shared subspace parameters that are always enabled in the inference task, and multiple expert subspace parameter sets that can be selectively enabled according to the execution path control signal. The processor writes the above-mentioned shared parameter set and expert parameter set into independent and independently addressable parameter segments or index ranges in memory, for example, allocating a continuous parameter block or independent storage address range for each expert, to support subsequent on-demand scheduling, on-demand loading, or on-demand caching.

[0050] The processor constructs an initial mapping table describing the correspondence between independently controllable computational units (e.g., channels, neuron groups, or attention heads) in the target layer and shared subspaces or individual expert subspaces, mapping each computational unit to the identifier of the shared subspace or the k-th expert. This mapping table can be stored in memory as an integer array, bitmap, or indexed list, serving as the initial version for generating partitions in subsequent structure mining steps. Subsequent steps can then overwrite, replace, or update the partitions based on this initial version.

[0051] The segmented construction of the target layer can be applied to various linear mapping layers, including but not limited to convolutional layers, projection sublayers in multi-head attention, MLP sublayers, and other modules that can be abstracted into independently controllable sets of computational units in the output dimension. The processor performs structured reorganization on the set of computational units corresponding to the output dimension: based on a preset shared scale configuration, some units are selected from the output channel or other computational units and allocated to the shared subspace, while the remaining units are allocated to the routable subspace; the routable subspace is further divided into several expert subsets, and accordingly, the original target layer parameters are rearranged into a set of shared parameters (written into the shared parameter segment) and several sets of expert parameters (written into each expert parameter segment respectively). This reorganization does not require complex mathematical decomposition or parameter transformation; its key is to ensure that the shared parameter segments and each expert parameter segment can be independently addressed and scheduled in memory, so that during the inference phase, the operation of the corresponding parameter segment can be selectively executed according to the expert enable control signal.

[0052] To support conditional execution during the inference phase, an expert enable runtime control interface is provided after the Upcycling step. In full-activation mode, the processor can mark all experts as enabled, ensuring that the target layer output remains numerically equivalent to the pre-trained dense model under the same data type and numerical precision conditions, or is engineeringly approximately equivalent within a preset error range, thus inheriting the capabilities of the pre-trained model without loss. In conditional execution mode with execution path control enabled, the expert selection results output by the routing control logic in subsequent deployment steps are converted by the processor into expert enable control signals (e.g., expert-level enable masks or expert index lists). Based on these signals, the processor only performs corresponding arithmetic operations and state updates on the expert parameter segments marked as enabled. For expert parameter segments not marked as enabled, the corresponding instruction sequence or loop iteration is bypassed, or in accelerator scenarios, the corresponding operator or kernel is not scheduled, so that the corresponding parameter block does not participate in the current calculation, thereby reducing computational and storage access loads.

[0053] Optionally, to verify the equivalence of Upcycling under a fully expert-enabled configuration, the processor can perform a consistency check on the outputs of the recombined target model and the original dense model under a fully activated configuration, under the same execution platform, data type, and numerical precision conditions. For example, it can compare whether the maximum absolute error of the output prediction vector is lower than a preset threshold, or whether key performance indicators on the validation set remain within the target range. This check is used for quality assurance during engineering implementation, and this invention does not limit its application.

[0054] (2.2) Structure mining: After the parameter structure reorganization is completed, the processor performs structure mining (Discover) based on the statistical features of the complete time window in the offline stage to generate the structure partitioning mapping table Partition of the target layer.

[0055] By using calibration data to statistically analyze the firing behavior of computational units (such as channels or groups of neurons) within the target layer, the partitioning results of the shared subspace and multiple expert subspaces are obtained and written into memory as a structural prior for subsequent teacher signal generation and routing control parameter solving. During the inference phase, this prior is transformed into specific computational unit enable control signals in conjunction with the routing output.

[0056] The processor first selects several representative samples from the training or validation data to form the first dataset for structure mining, reads the target model after upcycling, and configures all expert subspaces to be fully enabled to ensure that the prediction behavior of the target model under this configuration is numerically equivalent to the original dense model or engineering approximately equivalent within a preset error range.

[0057] For each sample in the first dataset, the processor performs one forward inference under a fully expert-enabled configuration. During the inference process, it reads the intermediate pulse output of at least one target layer and buffers it by time step and computational unit. The activity of each computational unit is accumulated over the full time window to form statistical data describing the activity level and load pattern of that computational unit on the sample set. In this embodiment, these statistical features obtained based on the full time window are collectively referred to as A-view features.

[0058] In the specific implementation, the processor constructs and stores at least the following two types of A-view statistics for subsequent structure partitioning:

[0059] ① Sample-level statistics: For each sample, accumulate the number of pulse firings or equivalent intensity indices of that sample in each computing unit, and arrange them according to the computing unit dimension to form a sample-level feature vector;

[0060] ② Computational unit level statistics: The above sample-level results are reorganized by computational unit. For each computational unit, its distribution statistics on all samples are collected to obtain the feature vector describing the cross-sample activity pattern of the computational unit, and stacked into an A-view statistical matrix.

[0061] Optionally, the processor can also calculate one or more A-view features on the same intermediate pulse data, including time-dimensional histograms, membrane potential statistics, and cross-channel correlations, and perform normalization processing on the A-view statistical matrix (e.g., subtracting the mean by sample or channel, scaling by standard deviation, or norm normalization) to improve the stability and comparability of subsequent partitioning. A-view statistics rely on complete time windows and cross-sample information, and are only calculated and stored by the processor in the offline stage; they are not directly calculated and used in the online inference stage.

[0062] After obtaining the A-view statistical matrix, the processor performs unsupervised structural partitioning on the target layer output channels or other computing units to obtain the partitioning results of shared subspaces and multiple expert subspaces, and writes them into memory in the form of a partitioning table. Preferably, the processor first evaluates the overall activity intensity of each computing unit based on A-view statistics, such as calculating its average number of pulses or other intensity indicators on the first dataset, and sorts them accordingly; according to the preset shared subspace size configuration (e.g., shared channel ratio or number of shared channels), a subset of computing units with higher activity intensity are selected to form a shared subspace set, and the remaining computing units form a routable set. Optionally, overall importance can also be evaluated based on cross-sample variance, impact on output stability, task-related consistency measures, or other relevant indicators.

[0063] Subsequently, the processor performs clustering on the routable set, treating routable computational units as candidate sets of functional subspaces to be partitioned. Based on their A-view activity pattern characteristics, an unsupervised clustering algorithm is executed to divide the routable set into multiple sets of non-overlapping expert subspaces. The clustering algorithm can be K-means, spectral clustering, hierarchical clustering, or other algorithms that can divide computational units into several relatively stable, functionally similar subspaces based on A-view behavior; this invention does not limit the specific implementation. Through the above-described shared subspace selection and routable set clustering, the processor defines the structural partitioning results of shared subspaces and multiple expert subspaces on the target layer computational unit set.

[0064] The processor organizes the above structural partitioning results into a structural partitioning map table (Partition) and stores it in memory as a data structure. A Partition can be represented in at least one of the following forms: a one-dimensional integer array indexed by computational unit numbers and delimited by subspace identifiers, used to query the shared subspace or a specific expert subspace to which any computational unit belongs; a list of computational unit indices or a sparse mask indexed by expert subspace numbers, used to enumerate the set of computational units contained in each expert subspace; or a metadata structure containing the shared set and each expert set. In the case of multiple target layers, the processor can construct a corresponding structural partitioning map table for each target layer and store the Partitions of all target layers uniformly in the form of a set or dictionary.

[0065] Optionally, to improve the reliability and interpretability of the structural partitioning, the processor can perform stability and consistency analysis on the partitioning results. For example, it can run the clustering algorithm multiple times on the same A-view statistical data and compare the consistency of the partitioning results under different random initializations. Alternatively, it can compare the similarity between computational unit-level features constructed based on complete time window statistics and those constructed based on prefix time window statistics to evaluate the approximation capability of prefix statistics for complete behavior. The above analysis steps are used to adjust configuration parameters such as clustering granularity, sharing ratio, and prefix time window length, and do not affect the core execution path control logic of this invention.

[0066] The offline structure mining step based on A-view is essentially a data processing procedure executed by the processor, whose output is prior structural data such as partitions stored in memory. This step itself does not change the execution semantics of the model during inference. Instead, by providing reusable structure partitioning results, it enables subsequent steps to generate cost-aware teacher signals and routing control parameters in the offline stage, and to transform these parameters into specific execution path control signals in the inference stage, thereby reducing unnecessary computation and storage access.

[0067] (2.3) Teacher Signal Generation: After the target layer structure is partitioned, the processor performs the cost-aware teacher signal generation step offline. This step, without changing the backbone network parameters, utilizes the subspace partitioning described by the partition to offline evaluate the inference output stability and resource consumption of the same input sample under different expert subspace enablement configurations. Given a resource budget, a reusable expert enablement configuration is determined for each sample, and this configuration is written into memory as a sample-level execution path control label for subsequent routing control parameter solving and budget tier selection during the deployment phase.

[0068] The processor first generates expert enable mask templates for each expert based on the partition. For each target layer in the model after parameter reorganization, the processor reads the structural partitioning map partition of the target layer from memory and constructs a corresponding expert enable mask template for each expert. This marks the shared subspace computing units and the computing units within the expert subspace as enabled, while the remaining computing units are marked as disabled. The expert enable mask template can be stored in memory as a bit vector, an integer array, or a list of computing unit indices. Based on this template, during the offline evaluation phase and subsequent deployment phase, when a computing unit is marked as disabled, the processor can skip the corresponding arithmetic operations, neuron state updates and write-backs, and related memory accesses at the operator scheduling or execution level. Alternatively, in accelerator scenarios, it can not schedule its corresponding operator or kernel, preventing the corresponding parameter block from participating in the current computation. This reduces the computational and memory access load after execution path pruning, while ensuring that output stability meets deployment requirements.

[0069] Subsequently, the processor performs offline multi-configuration evaluation and execution cost statistics. The processor reads a second subset of data generated for the teacher configuration from memory. This subset can be selected from training or validation data, as long as it is representative of the task distribution. For each sample in the second subset, the processor applies different expert enable mask templates at the target layer, ensuring that the sample inferences only through the computational paths of the shared subspace and the corresponding expert subspace, and obtains output stability and resource consumption metrics for each enabled configuration. The output stability metric characterizes whether the inference output under the enabled configuration meets the preset deployment requirements, and can use classification correctness indicators, consistency metrics with the baseline output, validation set loss values, or other task-related computable indicators. The resource consumption metric characterizes the resource overhead under the enabled configuration, reflecting at least the computational and storage access load, such as the number of impulse events, the number of equivalent arithmetic operations, the number of state variable write-backs, the number of storage accesses, or inference latency. The processor organizes the output stability metrics and resource consumption metrics obtained from each sample under the enabled configuration of each expert into a two-dimensional table or equivalent record structure, and writes them into memory, which will be used as the basis for subsequent generation of sample-level execution path control labels and configuration resource budget rules.

[0070] After completing offline multi-configuration evaluation, the processor generates sample-level expert-enabled configurations based on preset cost trade-off rules. The system can pre-set several resource budget tiers, each corresponding to a trade-off strategy between output stability and resource consumption. For example, in a cost-saving mode, the system prioritizes enabling configurations with lower resource consumption and output stability that meet basic deployment requirements; in a balanced mode, it comprehensively compares output stability and resource consumption metrics among various enabling configurations, selecting the configuration that meets deployment requirements under given resource constraints and has lower resource consumption; in a conservative mode, it tends to select enabling configurations closer to the baseline output and limits resource consumption to an acceptable range. For each sample in the second data subset, the processor reads the measurement results of that sample under each expert-enabled configuration, compares different enabling configurations according to the cost trade-off rules corresponding to the current budget tier, determines one or more preferred expert-enabled results, and records the determined results in the form of sample-level execution path control labels. The execution path control label can be a single expert index or a set of experts within a predetermined upper limit (e.g., a Top-k expert set), used to represent the preferred subset of expert subspaces for the sample under that resource budget tier.

[0071] To support strategy selection during the deployment phase, the processor can generate an expert selection configuration table for a single resource budget tier, associating each sample index in the second data subset with its corresponding execution path control label. In scenarios requiring support for multiple resource budget tiers, the processor can generate multiple configuration tables for each tier, and write each configuration table, along with its corresponding Partition version identifier, budget tier identifier, and the identifier of the data subset used (e.g., data subset number or summary information), to non-volatile storage media. Optionally, the processor can also store the metric statistics summary obtained from offline evaluation for verification and debugging of the budget strategy during the deployment phase.

[0072] The Teacher step is an offline configuration generation process executed by the processor. Its output is sample-level execution path control labels and related control information stored in memory, and it does not directly participate in the forward computation of the online inference stage. Subsequent steps will solve the routing control parameters based on the statistical features of the online-available prefix time window, enabling the processor to generate expert activation results that are consistent with or approximately consistent with the offline labels during the inference stage. Furthermore, it will generate enable control signals, thereby allowing the arithmetic instruction issuance, neuron state write-back, and parameter block or intermediate activation data access corresponding to the disabled subspaces to be truly skipped at the execution level, reducing unnecessary arithmetic operations, state write-back, and memory access overhead.

[0073] Step 3: Obtain the offline statistical feature vector B-view corresponding to the preset prefix time window. Train the router based on the sample-level execution path control label and the feature vector B-view to obtain routing control parameters used to predict the expert subspace activation result based on B-view. Store the structure partitioning mapping table Partition, the sample-level execution path control label, and the routing control parameters in the memory in a data form that can be directly read by the processor, so that the processor can read them during the online inference stage.

[0074] After completing the partitioning mapping table (Partition) and generating sample-level execution path control labels, the processor performs routing control parameter generation and digitization (Distill) offline. Based on the offline-generated sample-level execution path control labels and the online-available low-cost statistical features (B-view), a set of lightweight routing control parameters is solved. This allows the processor to generate expert subspace enable results for each input sample during the inference phase, relying only on the B-view features within the prefix time window. Based on this, it generates expert enable masks and execution path control signals, thereby controlling the execution or skipping of arithmetic operations, state updates, and memory accesses corresponding to different subspaces in the target layer.

[0075] like Figure 3As shown, the processor first performs offline acquisition and preprocessing of B-view prefix features. For each target layer, under the condition of a pre-set prefix time window length, the processor performs forward inference on the subset of data used for Distill under a fully expert-enabled configuration, and performs accumulation or other low-cost statistics on the target layer output within the preset prefix time window to obtain channel-level prefix statistics (such as pulse counts, average activation frequency, or statistical values ​​after simple transformation within the prefix time window), which are then organized into sample-level B-view feature vectors in a preset order. B-view features can originate from a single target layer, or be the result of splicing or fusion of prefix statistics from multiple target layers. To ensure consistency during the deployment phase, the statistical method for acquiring B-view features offline is consistent with that in the online inference phase, both relying solely on pulse statistics information that can be obtained in real time within the prefix time window. Depending on implementation needs, the processor can also perform normalization, quantization, dimensionality reduction, or multi-layer feature fusion on the B-view features to reduce the input dimension of the routing control logic and improve numerical stability, and store the relevant feature transformation parameters and routing control parameters together in memory for feature preprocessing during the deployment phase.

[0076] Subsequently, the processor constructs lightweight routing control logic and defines its output format. The input to the routing controller is the B-view feature vector corresponding to each sample, and the output is the selection score, selection probability, or a directly given set of expert indices for that sample in each expert subspace, used to indicate the preferred set of expert subspaces to be enabled under the current input (e.g., Top-1 experts or Top-k expert set). The routing controller can be implemented using a feedforward neural network, a linear discriminant model, a tree model, or other shallow models, but its computational overhead should be significantly lower than that of the backbone SNN itself, and it should be able to generate the control signals required for subsequent time steps at the end of the prefix time window. During the routing control parameter solving stage, the processor freezes the backbone network and expert parameters, and only updates the routing controller parameters and their input feature transformation parameters to reduce offline processing costs and maintain the stability of the forward behavior of the pre-trained model.

[0077] Next, the processor solves for the routing control parameters based on the offline execution path control labels. The processor reads a subset of data from memory used for solving the routing control parameters; this subset may be the same as or partially overlap with the subset used in the Teacher step. For each sample in this subset, the processor has obtained the corresponding B-view feature vector and a sample-level execution path control label generated by the Teacher step, which indicates the preferred set of expert subspaces to be enabled for that sample given a resource budget tier. The processor combines the B-view features and the execution path control labels into input-target pairs and iteratively adjusts the routing controller parameters so that the expert selection result output by the routing controller for each sample is consistent with or approximately consistent with the corresponding execution path control label within a preset error range. Consistency can be evaluated using various computable discrepancy metrics, such as classification error rate, overlap between selection sets, ranking consistency index, or discrepancy index between output distributions. Optionally, to avoid long-term bias towards a few experts leading to the idleness of some expert subspaces, the processor can introduce expert usage distribution constraints during the routing control parameter solution process: the frequency of selection of each expert subspace on the statistical sample set is compared with the preset target usage distribution; when the usage frequency of some experts deviates significantly from the target range, the overall expert activation frequency is brought closer to the preset range by adjusting the weight update rules, introducing usage balance-related penalty terms, or reweighting the expert selection results of some samples.

[0078] The processor generates and persists routing control parameters through the following offline process: Performing one or more forward inference iterations on the samples under a fully expert-enabled configuration, collecting and storing B-view features; reading the sample-level execution path control labels generated in the Teacher step, constructing input-target pairs for parameter solving; iteratively updating the routing controller parameters while freezing the backbone network parameters until the target consistency index or error threshold is reached on the preset validation set; recording the final routing controller parameters and related input feature transformation parameters as the routing control parameter set, and writing them into memory or non-volatile storage media. The processor can simultaneously persist the following deployment-required information: the routing controller's structural description, parameters used for B-view feature normalization or quantization, and configuration parameters related to resource budget tiers (e.g., budget tier identifier, default Top-k value, confidence threshold, or backoff strategy parameters).

[0079] The Distill or routing control parameter generation step is an offline control parameter solving process executed by the processor. Its output is a set of routing control parameters and related input transformation parameters stored in memory, and it does not directly participate in the backbone forward computation in the online inference stage. In the online inference stage, the processor collects the B-view features of each target layer within the prefix time window and calculates the expert subspace enabling result of the current sample based on the routing control parameters. The processor combines Partition to generate expert enable masks and execution path control signals, and only performs arithmetic operations such as multiplication, addition, or comparison, neuron state updates, and write-back operations corresponding to the shared subspace and the selected expert subspace. This avoids loading and storing parameter blocks and intermediate activation data corresponding to the unselected expert subspaces, thereby directly reducing the computational load and storage access overhead during runtime, and providing a parameterizable execution path control basis for the Top-k strategy and rollback mechanism in the deployment stage.

[0080] Step 4: Routing decision during the online inference phase: Obtain low-cost statistical features of the target layer within a preset prefix time window and form an online statistical feature vector B-view. Then, generate the expert subspace activation result based on the B-view and routing control parameters.

[0081] In this embodiment, after obtaining the structure partitioning mapping table (Partition) and the routing control parameter set offline, the processor performs online execution path control and conditional computation deployment (Deploy) during the inference phase. The processor reads the reorganized model parameters, Partition, routing control parameter set, and deployment configuration parameters (including prefix time window length, Top-k activation rules, confidence threshold, resource budget constraints, and backoff strategies, etc.) from memory, and performs online inference for each input sample in discrete time steps.

[0082] Within the prefix time window after inference begins, while performing normal forward inference of the backbone SNN, the processor accumulates or performs other low-cost statistics on the impulse output of each target layer over time steps to obtain channel-level prefix statistics, which are then organized into sample-level B-view feature vectors in a preset order. The statistical method of B-view is consistent with that of the Distill stage, relying only on the impulse output that can be obtained in real time within the prefix time window. These outputs can originate from a single target layer or be obtained by concatenating or fusing prefix statistics from multiple target layers, without requiring additional repeated inference.

[0083] When the prefix time window ends or a preset trigger condition is met, the processor reads the B-view feature vector of the current sample from the online feature buffer, calls the lightweight routing control logic based on routing control parameters, performs a calculation on the feature vector, and outputs the selection score, selection probability, or directly given expert index set for each expert subspace. The processor converts this output into the expert activation set corresponding to the current sample according to the deployment configuration parameters, indicating the number of expert subspaces and their specific identifiers that need to participate in the calculation in subsequent time steps. For example, in a Top-1 configuration, the expert subspace with the highest score is selected; in a fixed Top-k configuration, several expert subspaces with high scores are selected; and in an adaptive Top-k configuration, the number of activated experts is dynamically determined based on the confidence index.

[0084] Step 5: Enable control signal generation: Combine the expert subspace activation result with the structure partitioning mapping table Partition to generate enable control signals to indicate whether each computing unit in the target layer participates in this inference calculation.

[0085] The processor generates compute unit enable control signals in conjunction with the Partition. Specifically, based on the shared subspace and the compute unit sets corresponding to each expert subspace recorded in the Partition, the processor maps the expert enable sets to channel-level or other granularity enable masks, or equivalent active index lists, ensuring that the compute units corresponding to the shared subspace are always enabled, the compute units corresponding to the selected expert subspace are enabled in this inference, and the compute units corresponding to the unselected expert subspaces are disabled. These enable flags can be written into registers, caches, or dedicated control buffers in the form of bit vectors, integer arrays, or index lists, and used as control inputs for the execution of target layer operators in subsequent time steps.

[0086] Step 6: Actual execution skip: Based on the enable control signal, the computing unit in the disabled state skips the corresponding arithmetic instruction issuance, neuron state update and write-back, parameter block or intermediate activation data loading and storage access.

[0087] In subsequent time steps after the prefix time window, the processor controls the execution path of the target layer according to the aforementioned enable control signal: for computing units in the enabled state, it performs synaptic accumulation, threshold comparison, impulse generation, and necessary neuron state updates and write-backs consistent with the original dense model; for computing units in the disabled state, it does not issue the corresponding multiply-accumulate instructions, comparison instructions, or other major arithmetic instruction sequences, does not perform the corresponding neuron state update and write-back operations, and avoids loading or writing back its corresponding parameter blocks and intermediate activation data in this inference, only performing the preset minimal state maintenance operations (such as fixed decay or remaining unchanged) when needed. In specific hardware implementations, true skipping can be manifested in at least one of the following ways: First, on a general-purpose processor, through branching or looping control, based on an enable mask or active index list, only the enabled channels or experts are entered into the corresponding instruction sequence, preventing multiply-accumulate, compare, and write-back instructions of disabled computation units from being issued; Second, on a graphics processor or other accelerator, through operator or kernel-level scheduling, only shared subspaces and selected expert subspaces are created and issued, preventing parameter blocks corresponding to unselected experts from participating in this execution; Third, by generating an active computation unit index list based on an enable mask, only the computation units indicated by the index list are operated on and their states updated, effectively aggregating computations into fewer work sets, thereby reducing small-granularity task fragmentation and synchronization overhead.

[0088] Regarding expert activation rules and stability protection, the processor interprets the routing output and determines the final number of experts activated based on deployment configuration parameters. Common configurations include: a Top-1 mode aimed at minimizing single-sample computation and memory access overhead; a fixed Top-k mode that improves stability while moderately increasing the budget; and an adaptive Top-k mode that dynamically increases or decreases redundant activation based on the routing output confidence level. To improve robustness under distribution offsets, abnormal inputs, or uncertain regions in routing control logic, the system can be configured with a runtime rollback mechanism. Triggering conditions can include routing output confidence falling below a threshold, significant instability in selection ranking, excessively flat output distribution, alarms from upper-layer anomaly detection modules, or abnormal fluctuations in runtime budget statistics. Corresponding rollback actions can include temporarily upgrading Top-1 to a higher Top-k mode, or temporarily activating all expert subspaces in extreme cases to make the current inference process nearly dense, ensuring output reliability. The processor can also calculate the average number of activated experts or the average deployment cost within a sliding time window. When the cost consistently exceeds the budget, the rollback strategy is tightened; when it consistently falls below the budget, the rollback strategy is appropriately relaxed, achieving a controllable trade-off between stability and resource consumption.

[0089] Optionally, the processor can also record runtime cost information during inference, such as the actual number of operators or kernels launched, the actual number of computing units or experts involved in the computation, the number of neuron state write-backs, parameter and intermediate activation access estimates, and single inference latency. Based on these statistics, the processor can reconfigure deployment configuration parameters during runtime according to device load or business objectives without retraining the backbone network. For example, it can adjust the prefix time window length, adjust the Top-k rules or confidence thresholds, select control parameter groups corresponding to different budget levels, or modify the fallback strategy level. Through the above-mentioned online execution path control and fallback mechanism, this invention prevents the main arithmetic paths and write-back paths of disabled subspaces from entering the actual execution process at the execution level, reducing invalid arithmetic operations and state write-backs. At the same time, it prevents parameter blocks and intermediate states corresponding to unselected expert subspaces from participating in this execution, thereby reducing storage access and data transfer overhead and improving the stability and deployment controllability of the overall inference process under preset resource budget constraints.

[0090] Step 7: Output the final result of the reasoning task after the reasoning process is completed.

[0091] After completing forward inference across all time steps and the aforementioned online execution path control, the processor reads the inference calculation results of the current sample from a preset output layer or readout layer, and generates task outputs usable by external modules according to the requirements of the target task. In general, the output layer can be a readout layer configured for the task dimension, and its internal state can include pulse counts, membrane potentials, accumulated currents, weighted sums, or other readout variables. At the end of inference, the processor performs task-related readout operations and post-processing operations on these variables, such as normalization, threshold comparison, maximum value index extraction, or other forms of decision logic, to obtain the final inference task result.

[0092] In discrete classification tasks such as image classification, the processor can organize the readout results from the output layer into a category score vector and determine the target category label based on this vector (e.g., selecting the category index with the highest score), and optionally output the complete category score or probability distribution. In other types of neural network inference tasks, the processor can map the readout results into regression prediction values, detection box parameters, keypoint coordinates, sequence labeling results, or other structured outputs adapted to the specific task. This embodiment does not limit the specific readout operator and post-processing method, as long as it can form a task-level output based on the readout variables from the output layer after the inference time step.

[0093] The processor can write the results of the above inference task to the result buffer in memory, or return them to the host system via the bus interface for display, recording, or use in subsequent decision-making logic by upper-layer applications. Whether the execution path control mechanism is enabled or not, the output interface of this step remains consistent. Execution path control only affects the set of subspaces involved in the computation during inference and their resource consumption; it does not change the task output format or invocation method under the premise of meeting deployment requirements.

[0094] This embodiment uses a large-scale image classification inference task as an example to illustrate a specific application process of the method of the present invention on a pre-trained spiking neural network. Those skilled in the art will understand that the method is also applicable to other neural network inference tasks, and the present invention is not limited to image classification scenarios. This embodiment is only used to illustrate the technical solution of the present invention and does not constitute a limitation on the scope of protection of the present invention.

[0095] The present invention also provides an electronic device, including at least one processor, at least one accelerator, and a memory. The processor is used to execute control logic, routing control, and some tensor operations; the accelerator is used to accelerate the forward inference and offline evaluation of the spiking neural network; the memory stores pre-trained dense SNN model parameters, image classification dataset samples for calibration and evaluation, and A-view and B-view statistical features, structural partitioning mappings, sample-level execution path control labels, and routing control parameters generated during the implementation of the present invention.

[0096] The target task can be any neural network inference task; this embodiment uses a large-scale image classification inference task as an example. The data can be a publicly available ImageNet-1K type image classification dataset, containing several training and validation samples, with the number of categories being a preset positive integer. Images are preprocessed to a fixed size by a processor or accelerator before being input into the network, and standard operations such as normalization are performed. The base model is a pre-trained dense spiking neural network stored in memory. In this embodiment, the overall structure adopts a Transformer-type spiking network, including several spiking residual blocks composed of multi-head attention and MLP. This is an optional implementation, and the invention is not limited to this structure. The total number of time steps is set to 4 in this embodiment. For ease of explanation, this embodiment selects a computationally expensive and structurally regular spiking MLP sublayer as the target layer; this layer has approximately 2560 output channels in dense mode.

[0097] In the parameter recycling step, the processor reads the original dense weights of the target layer from memory and reorganizes them into a shared subspace parameter set and several expert subspace parameter sets along the output channel dimension. In this embodiment, the number of experts is set to 8. Based on the overall channel distribution intensity obtained from offline statistics, the processor assigns a small portion of channels with consistently high activity levels to the shared set, while the remaining channels form a routable set, which is further divided into 8 expert subsets. The reorganized shared weights and each expert weight are written into an independent parameter segment in memory, and the index relationship between the computing unit and the subspace identifier is recorded to support independent addressing and scheduling by subspace. When inference is performed on the validation set under the full expert-enabled configuration, it can be observed that the model output under this configuration is basically consistent with the original dense pedestal model in terms of classification results and task-related evaluation metrics, indicating that Upcycling under the full activation configuration can be regarded as a functionally equivalent reorganization of the original model.

[0098] In the structure mining and partition generation (Discover) step, the processor selects a subset of training or validation samples, performs forward inference in full expert-enabled mode, and collects A-view statistical features over the entire time window at the target layer. For each channel, the processor statistically analyzes its pulse firing behavior within the entire time window on the sample set, performs normalization, and writes it to memory. Subsequently, the processor performs unsupervised clustering based on the channel-level A-view features, dividing the routable channels into 8 expert subspaces, resulting in several sets of functionally similar subspaces within the target layer. The clustering results are stored as a structure partitioning map, serving as a partition, used for subsequent generation of sample-level execution path control labels and online construction of expert-enabled masks.

[0099] In the sample-level execution path control label generation (Teacher) step, the processor evaluates different expert enablement configurations based on partitions in the offline phase. For each sample in the subset of data used for label generation, the processor performs forward inference with a shared subspace and a single expert subspace configuration, recording the corresponding output stability metrics (e.g., classification correctness flags, consistency metrics with baseline output, or validation set loss) and resource consumption metrics (e.g., equivalent arithmetic operations in the target layer, neuron state write-backs, or memory accesses), and writes the evaluation results to memory. Based on a preset resource budget strategy, under multiple levels such as biased output stability, balanced mode, and biased cost-saving, the processor selects one or more preferred expert enablement results for each sample and stores them in the form of sample-level execution path control labels. Offline evaluation shows that, with reasonable structural partitioning and enablement configurations, when only a single expert subspace is enabled, the model output remains stable within the preset deployment requirements, while the computational and memory access load related to the target layer is significantly reduced.

[0100] In the routing control parameter solving and consolidation (Distill) step, the processor trains lightweight routing control logic based on B-view features within the prefix time window. The processor reads the pulse output of the target layer from memory within the previous few time steps, accumulates channel-level prefix statistics for each sample, and constructs a sample-level B-view feature vector. The statistical method is consistent with the online acquisition during the deployment phase. In this embodiment, the routing control logic is implemented as a lightweight multilayer perceptron with an input dimension matching the number of channels in the target layer. Its output is the selection score or selection probability of eight expert subspaces. The processor combines the B-view feature vector with the execution path control labels generated in the aforementioned Teacher step to form input-target pairs. While freezing the backbone SNN model parameters, only the routing control parameters are updated, ensuring that the expert selection results output by the routing control logic for most samples maintain high consistency with the offline labels. After training, the routing control parameters and related feature transformation parameters at the time when the performance meets the preset requirements are written into memory as the deployment version.

[0101] In the online execution path control and rollback (Deploy) step, the processor reads the upcycled model parameters, partitions, routing control parameters, and deployment strategy configuration from memory, and inserts the routing control logic into the inference flow of the pre-trained SNN. The processor first configures the deployment strategy to full expert-enabled mode, verifying that the model classification results in this mode are basically consistent with the original dense pedestal model, confirming that the execution path control mechanism introduced in this invention does not significantly affect the inference output under the fully enabled configuration. Subsequently, the processor configures the deployment strategy to Top-1 hard routing mode: for each sample, only the expert subspace with the highest confidence output of the routing control logic is activated (plus the shared subspace), and the multiply-accumulate operations and intermediate state write-backs of the parameter blocks corresponding to the unenabled experts are skipped. In this mode, only one expert subspace is enabled per sample. Compared to the configuration of fully activating 8 experts, the number of expert-related computation paths in the target layer is reduced to about one-eighth of the original, and the corresponding number of multiply-accumulate operations, state write-backs, and storage access overhead are significantly reduced, while the model output on the validation set remains stable within the preset deployment requirements.

[0102] To further improve stability on uncertain inputs, this embodiment introduces a simple adaptive backoff mechanism. During the inference phase, the processor calculates a confidence index based on the expert selection probability distribution output by the routing control logic. When the confidence score falls below a preset threshold, the backoff mechanism is triggered, additionally activating a second optimal expert subspace. This expands the expert enable set for the current sample from a single expert to two experts, and regenerates the corresponding expert enable mask and execution path control signal. In the test configuration of this embodiment, it can be observed that after introducing this adaptive backoff mechanism, the model's output stability on difficult samples is improved, while the average number of activated experts per sample only increases from 1 to slightly more than 1, resulting in a small increase in resource overhead.

[0103] In summary, this embodiment demonstrates that, in image classification and reasoning tasks, by executing the closed-loop process proposed in this invention—parameter recombination, structure partitioning and partition generation, sample-level execution path control label generation, routing control parameter solving and solidification, and online execution path control and rollback—significantly reduces the number of multiply-accumulate instructions actually executed by the processor, the number of neuron state write-backs, and storage access overhead without retraining the backbone network. Furthermore, it achieves controllable output stability and cost trade-offs under configurable resource budget constraints, proving the engineering usability and deployment stability of the execution path control mechanism proposed in this invention on general-purpose computing platforms.

[0104] The above description is only a preferred embodiment of the present invention. For those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered to fall within the protection scope of the present invention.

Claims

1. An execution path control method for inference in spiking neural networks, characterized in that, Includes the following steps: (1) Input data acquisition and preprocessing: Acquire the input data to be inferred and preprocess it, and encode the input data into a pulse sequence or event representation suitable for spiking neural network (SNN); (2) Offline control data structure generation: Perform structure analysis on at least one target layer of the pre-trained dense SNN. Based on the target layer weight parameters and calibration dataset, divide the target layer parameters into shared subspace parameter segments and multiple expert subspace parameter segments. Construct a structure partitioning mapping table Partition, evaluate the output stability and resource consumption of different expert subspace enable configurations, and generate sample-level execution path control labels for each sample. (3) Control data structure solidification and storage: Obtain the offline statistical feature vector B-view corresponding to the preset prefix time window, train the router based on the sample-level execution path control label and the feature vector B-view to obtain the routing control parameters used to predict the expert subspace activation result based on B-view; and solidify and store the structure partitioning mapping table Partition, the sample-level execution path control label and the routing control parameters in the memory in the form of data that can be directly read by the processor, so that the processor can read them during the online inference stage; (4) Routing decision during the online inference phase: Obtain the low-cost statistical features of the target layer within the preset prefix time window and form an online statistical feature vector B-view. Read the routing control parameters from the memory and generate the expert subspace activation result based on the B-view and the routing control parameters. (5) Enable control signal generation: Combine the expert subspace activation result with the structure partitioning mapping table Partition to generate enable control signals to indicate whether each computing unit in the target layer participates in this inference calculation; (6) Actual execution skip: Based on the enable control signal, the computing unit in the disabled state skips the corresponding arithmetic instruction issuance, neuron state update and write-back, parameter block or intermediate activation data loading and storage access; (7) Output of reasoning task results: Determine and output the reasoning task results based on the reasoning calculation results.

2. The execution path control method for spiking neural network inference according to claim 1, characterized in that, The input data in step (1) includes the input image to be classified, event stream data, or other sensor time series data.

3. The execution path control method for spiking neural network inference according to claim 1, characterized in that, Step (2) of the offline control data structure generation includes parameter reorganization, structure mining, and teacher signal generation. The parameter reorganization is performed by the processor in the offline stage. It is used to reorganize the parameters of at least one target layer into shared parameter segments and multiple expert parameter segments without changing the inference semantics of the pre-trained dense SNN under the full expert-enabled configuration. It also generates an index mapping relationship that can be referenced by the subsequent execution path control logic, providing an addressable parameter layout and structure partitioning basis for the subsequent execution path control. The structure mining uses calibration data to statistically analyze the distribution behavior of the computing units inside the target layer, obtains the partitioning results of the shared subspace and multiple expert subspaces, and writes them into the memory as the structural prior for subsequent teacher signal generation and routing control parameter solving. In the inference stage, it is converted into specific computing unit enable control signals in conjunction with the routing output. The teacher signal generation is based on the Partition without changing the backbone network parameters. The described subspace partitioning performs offline evaluation of the inference output stability and resource consumption of the same input sample under different expert subspace enabling configurations. Under a given resource budget, a reusable expert enabling configuration is determined for each sample, and the configuration is written into the memory in the form of a sample-level execution path control tag for subsequent routing control parameter solving and budget level selection in the deployment phase.

4. The execution path control method for spiking neural network inference according to claim 1, characterized in that, The structure partitioning mapping table Partition described in step (2) uses an array, bitmap, or index list to record the correspondence between channels or neuron groups and subspace identifiers.

5. The execution path control method for spiking neural network inference according to claim 1, characterized in that, The generation of the sample-level execution path control label in step (2) is based on a preset resource budget rule; the resource budget rule includes at least three cost trade-off strategies: saving, balancing, and conservatism.

6. The execution path control method for spiking neural network inference according to claim 1, characterized in that, The routing control parameters in step (3) include at least threshold parameters and linear weight parameters, and are stored in the memory in the form of an array, threshold table, linear weight parameter table, index list, bitmap or a combination thereof.

7. The execution path control method for spiking neural network inference according to claim 1, characterized in that, In step (4), a rollback mechanism is set up during the process of generating the expert subspace activation result based on B-view and routing control parameters. The triggering conditions include the routing output confidence being lower than the threshold, the expert selection sorting being unstable, the routing output distribution being too flat, or the runtime budget statistics fluctuating abnormally. The rollback actions include increasing the Top-k value or enabling the full expert subspace.

8. The execution path control method for spiking neural network inference according to claim 1, characterized in that, The enable control signal in step (5) is a channel-level or expert-level enable mask, or an active index list; the computing units of the shared subspace and the selected expert subspace are in an enabled state, and the computing units of the unselected expert subspace are in an disabled state. The enable control signal can be directly read and parsed by the execution engine.

9. The execution path control method for spiking neural network inference according to claim 1, characterized in that, The actual execution skipping step (6) is achieved in the following way: ① On a general-purpose processor, through branch or loop control, based on the enable mask or active index list, only the enabled channels or experts are entered into the corresponding instruction sequence, so that the multiply-add, compare and write-back instructions of the disabled computing units are not issued; ② On a graphics processor or other accelerator, operators or kernels are created and emitted only for the shared subspace and the selected expert subspace through operator or kernel-level scheduling, so that the parameter blocks corresponding to the unselected experts do not participate in this execution. ③ By generating an active computing unit index list based on the enable mask, operations and status updates are performed only on the computing units indicated by the index list, effectively aggregating computations into a smaller set of work, reducing small-granularity task fragmentation and synchronization overhead.

10. An electronic device, characterized in that, The electronic device includes: a memory, a processor, and an accelerator; The memory is used to store computer programs that can run on the processor, including storing pre-trained dense SNN model parameters, image classification dataset samples for calibration and evaluation, as well as A-view and B-view statistical features, structure partitioning mapping (Partition), sample-level execution path control labels, and routing control parameters. The processor is configured to, while running the computer program, execute the steps of the execution path control method for spiking neural network inference as described in any one of claims 1 to 9; The accelerator is used to accelerate forward inference and offline evaluation of spiking neural networks.

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