A low noise current sampling and rejection system for capacity grading testing

Abstract

The application discloses a low-noise current sampling and suppression system for capacity grading test, relates to the field of battery test, and comprises a main current sampling shunt, a main current sampling connecting copper bar, blind measurement wiring and an analog front-end compensation circuit; the main current sampling shunt is connected in series in a main circuit; one end of the main current sampling connecting copper bar is connected with the main current sampling shunt; the blind measurement wiring is arranged in parallel with the main current sampling connecting copper bar on the surface of a same test tray, and both ends of the blind measurement wiring are connected with the input end of the analog front-end compensation circuit; the analog front-end compensation circuit collects voltage signals from both ends of the blind measurement wiring, generates an inverted compensation signal through inversion processing, then superimposes the inverted compensation signal with the collected main sampling voltage signal to output a direct-current compensation voltage signal. The application solves the problem that the serious cumulative error of capacity calculation is caused by the direct-current drift noise of thermoelectric potential generated due to the space temperature gradient in the battery test.

Description

Technical Field

[0001] This invention relates to the field of battery testing, and more specifically, to a low-noise current sampling and suppression system for capacity grading testing. Background Technology

[0002] In battery manufacturing and production processes, formation and capacity testing are crucial steps that determine battery performance and quality. To accurately assess and classify battery capacity, testing equipment needs to perform high-precision current sampling over a charging and discharging process that can last for several hours, and then integrate the current data over time. As battery production lines develop towards higher density and higher power, the number of channels integrated within the test tray has increased dramatically, making electromagnetic interference and heat distribution in the testing environment extremely complex.

[0003] Currently, there has been considerable exploration within the industry regarding the optimization of batching and capacity testing systems and current sampling. For example, Chinese patent CN119959607A, "Current Sampling Circuit and Current Sampling Method Based on Gallium Nitride Power Transistor," discloses a temperature-compensated current sampling scheme aimed at reducing the impact of component heating on current detection accuracy. However, these existing technologies still have insurmountable blind spots when facing the current high-density batching and capacity testing environment. First, during long-term charging and discharging, a significant temperature gradient inevitably forms on the surface of the entire test tray. When this non-uniform temperature field acts on the current sampling shunt and its connecting copper busbar, it generates slowly drifting thermoelectric potential DC noise based on the Seebeck effect. Conventional temperature compensation techniques often only focus on the absolute temperature of the chip or resistor itself, completely ignoring this extremely low-frequency DC drift caused by spatial temperature differences. This results in the thermoelectric potential being mistakenly superimposed on the actual sampling current, causing severe batching capacity errors after long-term integration.

[0004] Secondly, because the switching power supply frequencies of hundreds or thousands of adjacent channels are extremely close but not globally synchronized, spatial magnetic field coupling will generate extremely low-frequency beat frequency interference in the sampling circuit. This interference frequency is extremely low, and if it is filtered out using a conventional low-pass filter, it will severely slow down the dynamic response speed of current sampling, making it impossible to accurately capture the current changes at the moment of operating condition switching.

[0005] Finally, the micro-vibrations caused by the equipment's cooling fan or the thermal expansion and contraction of the contacts can lead to minute relative slippage between the formation probe and the battery tabs. This slippage can cause instantaneous step-like noise, and traditional moving average filtering algorithms not only fail to completely eliminate such instantaneous anomalies, but also smooth them out and distribute them to subsequent normal sampling points, turning instantaneous errors into persistent errors and severely contaminating the measurement results. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a low-noise current sampling and suppression system for capacity grading testing, so as to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A low-noise current sampling and suppression system for capacity grading testing includes a main current sampling shunt, a main current sampling connection copper busbar, blind test traces, and an analog front-end compensation circuit.

[0009] The main current sampling shunt is connected in series in the main circuit used for capacity grading test;

[0010] The main current sampling connection copper busbar is connected to one end of the main current sampling shunt;

[0011] The blind test trace and the main current sampling connection copper busbar are arranged parallel to each other on the same test tray surface, and both ends of the blind test trace are connected to the input terminal of the analog front-end compensation circuit.

[0012] The analog front-end compensation circuit acquires the blind test line voltage signal from both ends of the blind test line;

[0013] The analog front-end compensation circuit inverts the blind test line voltage signal to generate an inverted compensation signal.

[0014] The analog front-end compensation circuit acquires the main sampling voltage signal at both ends of the main current sampling shunt.

[0015] The analog front-end compensation circuit superimposes the inverted compensation signal and the main sampled voltage signal to output a DC compensation voltage signal.

[0016] Preferably, the geometry and material composition of the blind test trace are consistent with the geometry and material composition of the main current sampling connection copper busbar;

[0017] The blind test traces and the main current sampling connection copper busbar are adjacent in physical location but do not make electrical contact.

[0018] Preferably, the analog front-end compensation circuit includes an inverting amplifier and an analog adder;

[0019] Both ends of the blind test trace are connected to the input terminal of the inverting amplifier;

[0020] The inverting amplifier outputs the inverting compensation signal;

[0021] The output terminal of the inverting amplifier is connected to the first input terminal of the analog adder;

[0022] The two ends of the main current sampling shunt are connected to the second input terminal of the analog adder;

[0023] The DC compensation voltage signal is output from the output terminal of the analog adder.

[0024] Preferably, the analog front-end compensation circuit includes a digital processing microcontroller and a programmable inverting amplifier;

[0025] The digital processing microcontroller has a thermoelectric potential compensation mapping machine learning model deployed inside, and the thermoelectric potential compensation mapping machine learning model is a multilayer perceptron network.

[0026] The digital processing microcontroller acquires the digital quantity of the blind test trace voltage signal and inputs it into the thermoelectric potential compensation mapping machine learning model, and the thermoelectric potential compensation mapping machine learning model outputs the compensation coefficient.

[0027] The digital processing microcontroller sends the compensation coefficient to the control terminal of the programmable inverting amplifier;

[0028] The programmable inverting amplifier performs gain adjustment and inversion processing on the blind test line voltage signal according to the compensation coefficient to generate the inverting compensation signal;

[0029] The thermoelectric potential compensation mapping machine learning model is trained using a training set containing historical blind test line voltage signal samples and corresponding real thermoelectric potential drift voltage labels via backpropagation algorithm.

[0030] Preferably, the system further includes an AC component extraction circuit, a phase-locked loop circuit, and an analog-to-digital converter;

[0031] The input terminal of the AC component extraction circuit is connected to both ends of the blind test trace;

[0032] The AC component extraction circuit filters out the DC component in the blind test trace voltage signal and outputs an AC interference voltage signal.

[0033] The input terminal of the phase-locked loop circuit is connected to the output terminal of the AC component extraction circuit;

[0034] The phase-locked loop circuit tracks the phase of the AC interference voltage signal and outputs a zero-crossing trigger signal when the value of the AC interference voltage signal is zero.

[0035] The signal input terminal of the analog-to-digital converter receives the DC compensation voltage signal;

[0036] The trigger input terminal of the analog-to-digital converter receives the zero-crossing trigger signal;

[0037] The analog-to-digital converter samples the DC compensation voltage signal and outputs a digital current signal when it receives the zero-crossing trigger signal.

[0038] Preferably, the AC component extraction circuit includes a DC blocking capacitor and an active bandpass filter;

[0039] The blind test trace voltage signal passes through the DC blocking capacitor and enters the input terminal of the active bandpass filter;

[0040] The active bandpass filter outputs the AC interference voltage signal.

[0041] Preferably, the phase-locked loop circuit includes a trigger adjustment microprocessor;

[0042] The trigger adjustment microprocessor is internally deployed with a sampling time prediction reinforcement learning model.

[0043] The trigger adjustment microprocessor inputs the time series of the AC interference voltage signal into the sampling time prediction reinforcement learning model, and the sampling time prediction reinforcement learning model outputs the trigger time offset.

[0044] The trigger adjustment microprocessor adds the time point of the zero-crossing trigger signal to the trigger time offset to obtain the corrected trigger signal;

[0045] The analog-to-digital converter samples the DC compensation voltage signal and outputs a digital current signal when it receives the correction trigger signal.

[0046] Preferably, the system further includes a formation probe, a probe voltage acquisition circuit, and a digital signal processor;

[0047] The formation probe is connected in series with the main circuit and makes contact with the tab of the test battery;

[0048] The probe voltage acquisition circuit acquires the probe voltage drop signal across the two ends of the formation probe;

[0049] The digital signal processor receives the digital current signal output by the analog-to-digital converter and the probe voltage drop signal;

[0050] The digital signal processor is internally equipped with a machine learning model for recognizing mechanical displacement noise.

[0051] The digital signal processor concatenates the digital current signal and the probe voltage drop signal into two-dimensional time series data and inputs it into the mechanical displacement noise recognition machine learning model. The mechanical displacement noise recognition machine learning model outputs the mechanical displacement noise Boolean value at each sampling time point.

[0052] The digital signal processor discards the corresponding digital current signal at the time point when the mechanical displacement noise Boolean value is true, and extracts the digital current signal corresponding to the time point before the time point when the mechanical displacement noise Boolean value is true and the time point when the mechanical displacement noise Boolean value is false, and performs linear extrapolation filling.

[0053] Preferably, the network architecture of the machine learning model for mechanical displacement noise recognition is a temporal convolutional network, which includes one-dimensional convolutional layers and residual connection structures.

[0054] The machine learning model for mechanical displacement noise recognition extracts the local temporal jump features and inter-channel joint change features of the two-dimensional time series data, and the classifier at the end outputs the Boolean value of the mechanical displacement noise.

[0055] Preferably, the machine learning model for identifying mechanical displacement noise undergoes supervised learning training before deployment;

[0056] The training dataset for training the machine learning model for mechanical displacement noise recognition includes sample two-dimensional time series data collected by running the test equipment and labels of the mechanical slip occurrence time manually annotated.

[0057] The training process uses the cross-entropy loss function to update the weight parameters of the one-dimensional convolutional layer.

[0058] The advantage of this invention over the prior art is that it addresses the complex interference problems in existing high-density fractional capacity testing by using multi-dimensional physical and data-based collaborative suppression methods, which significantly improves the purity of current sampling and the accuracy of capacity integration.

[0059] This invention cleverly solves the problem of DC drift in thermoelectric potential caused by temperature gradients by adding parallel blind test traces next to the main current sampling circuit. Since the blind test traces are identical in material and geometry to the main current sampling connection copper busbar and have no electrical connection to the main circuit, they are completely exposed to the same local temperature gradient field, thus enabling the pure extraction of thermoelectric potential noise caused by ambient temperature differences. The analog front-end compensation circuit inverts this pure noise signal and superimposes it with the main sampling voltage, directly canceling low-frequency DC errors at the lowest physical simulation level. This fundamentally avoids the capacity accumulation error problem caused by the inability of conventional filtering to handle low-frequency temperature drift.

[0060] Building upon this core architecture, this invention further reuses the physical characteristics of blind test traces to address spatial magnetic field coupling interference. An AC component extraction circuit separates the AC interference signals induced by the blind test traces from adjacent channels, and a phase-locked loop circuit with a reinforcement learning model is used for phase tracking. The system can accurately predict the zero-crossing moments of the interference signals. The analog-to-digital converter only triggers sampling at the zero-crossing moment when spatial magnetic field interference is at its lowest. This sampling mechanism, which avoids interference peaks, obtains clean data without the need for any low-pass filters, ensuring extremely high dynamic response speed for current sampling.

[0061] Furthermore, to address the step noise caused by microscopic slippage at the probe contact surface, this invention incorporates the objective law that the electrochemical reaction of a battery is a continuous and gradual process, utilizing a time-convolutional network model to simultaneously analyze the probe voltage drop and sampling current sequence. When instantaneous mechanical displacement noise that does not conform to electrochemical characteristics is identified, the system actively discards the outlier and uses normal time-series data for linear extrapolation to fill the gap. This mechanism completely eliminates instantaneous spikes caused by mechanical oscillations, effectively preventing the error tailing phenomenon caused by traditional moving average algorithms, and ensuring high data reliability throughout the entire tiered testing cycle. Attached Figure Description

[0062] Figure 1 This is a top view of the physical layout of the main circuit and blind test traces of the present invention on the surface of the test tray;

[0063] Figure 2 This is a schematic diagram of the analog front-end compensation circuit based on an inverting amplifier and an analog adder in this invention;

[0064] Figure 3 This is a diagram of the intelligent front-end compensation circuit of the present invention, which has a thermoelectric potential compensation mapping model.

[0065] Figure 4 This is a schematic diagram of the digital signal processing system of the present invention, which includes probe signal acquisition and data cleaning. Detailed Implementation

[0066] The present invention will be further described below with reference to the accompanying drawings and embodiments. The present invention addresses battery capacity grading testing scenarios. In this scenario, the testing system typically needs to perform long-term charge-discharge cycles on a large number of test batteries and calculate the capacity based on the integral of the current over time. Since capacity calculation inherently accumulates sampling errors over time, even microvolt-level additional drift can translate into visible capacity deviations after prolonged testing. Therefore, the present invention does not merely improve the accuracy of a single device, but rather constructs a low-noise current sampling and suppression system that combines front-end compensation, synchronous sampling, and back-end cleaning, addressing the real-world parasitic thermoelectric potentials, AC coupling interference, and probe contact disturbances near the main circuit.

[0067] In one embodiment, a main current sampling shunt is connected in series in the main circuit used for capacity grading testing. This main circuit may include a test power supply, control switch, test battery, formation probe, and return conductor. The main current sampling shunt can be made of manganese-copper shunt or other low-temperature-coefficient resistive materials, and its resistance value can be selected from 50μΩ to 500μΩ depending on the test current range. When the test object is a single-cell power battery or energy storage cell, the main current is typically in the range of 0.5A to 30A. At this time, the main sampling voltage signal formed across the main current sampling shunt is generally in the millivolt range. Millivolt signals are inherently small and easily affected by thermoelectric potential, conductor coupling voltage, and tooling contact fluctuations; therefore, targeted processing is required at the front end.

[0068] like Figure 1 As shown, the main current sampling connection copper busbar is connected to one end of the main current sampling shunt, used to introduce or extract the test current from the main circuit into or out of the main current sampling shunt. The blind test trace is arranged parallel to the main current sampling connection copper busbar on the same test tray surface, and the blind test trace is not electrically connected to the main circuit. The blind test trace referred to here is an auxiliary conductor that does not carry the main circuit operating current but is intentionally placed in a physical environment close to the main current sampling connection copper busbar. It is called "blind test" because it does not directly measure the main current, but is used to sense the additional parasitic voltage caused by the same or similar thermal, electromagnetic, and spatial coupling environments as the main current sampling connection copper busbar.

[0069] To ensure that the blind test traces more accurately reflect the parasitic effects near the main current sampling connection copper busbar, in one embodiment, the geometry and material composition of the blind test traces are consistent with those of the main current sampling connection copper busbar, and the two are spatially adjacent without electrical contact. Consistent geometry here preferably means that the length, width, thickness, bending method, and lead-out direction are consistent. For example, the main current sampling connection copper busbar can be 50mm to 300mm long, 5mm to 20mm wide, and 0.5mm to 3mm thick, and the blind test traces use the same dimensions. Consistent material composition is preferably achieved using the same copper material or copper alloy and the same surface plating to reduce the additional contact thermoelectric potential between different metal contacts. The edge spacing between the two can be 1mm to 10mm. Within this range, the blind test traces can share approximately the same thermal gradient and electromagnetic coupling conditions with the main current sampling connection copper busbar, while avoiding electrical contact through an insulating layer or insulating support.

[0070] In actual operation, the main sampling voltage signal at both ends of the main current sampling shunt includes not only the voltage component reflecting the actual current, but may also be superimposed with additional voltages caused by tray temperature difference, device heating, airflow, and coupling of adjacent circuits. Since the blind test trace does not carry the main current, its signal does not contain the resistance voltage drop directly corresponding to the main current, but mainly manifests as parasitic voltages related to the environment. Therefore, there is a certain correlation between the main sampling voltage signal and the blind test trace voltage signal. This invention utilizes this correlation to invert the blind test trace voltage signal in the analog front-end compensation circuit, and then superimposes it with the main sampling voltage signal to obtain a DC compensation voltage signal. This can be understood as first using an auxiliary conductor that is "same as, very close to, but not energized" as the main current sampling busbar to separately sense the additional influences that are not part of the actual current information, and then trying to cancel out these influences before entering the analog-to-digital conversion.

[0071] In one embodiment, the analog front-end compensation circuit can be implemented using a purely analog method. For example... Figure 2 As shown, the analog front-end compensation circuit includes an inverting amplifier and an analog adder. The two ends of the blind test trace are connected to the input of the inverting amplifier, which outputs an inverted compensation signal. The output of the inverting amplifier is connected to the first input of the analog adder. The two ends of the main current sampling shunt are connected to the second input of the analog adder, and the output of the analog adder outputs a DC compensation voltage signal.

[0072] The inverting amplifier can be constructed using a low-offset, low-drift operational amplifier to form a differential inverting stage. Since the blind test trace voltage signal is generally in the microvolt to millivolt range, a chopper-type or zero-drift amplifier with an input offset voltage not exceeding 10μV and an input drift not exceeding 50nV / ℃ is preferred. The gain of the inverting amplifier can be set by a precision resistor network, with a common range of -0.5 to -2.0. When the initial structure is relatively symmetrical and the blind test trace and the main current sampling connection copper busbar are at the same height, the gain can be preferentially set between -0.8 and -1.2 to ensure that the main parasitic component of the blind test trace voltage signal and the corresponding parasitic component in the main sampling voltage signal have similar amplitudes and opposite phases. The analog adder can be implemented using a differential summing structure, and its output satisfies the linear superposition relationship between the main sampling voltage signal and the inverting compensation signal. This is significant because the compensation action occurs before the analog-to-digital conversion, reducing the total noise swing at the input of the subsequent analog-to-digital converter and improving the effective bit utilization.

[0073] To further adapt to situations where the parasitic thermoelectric potential amplitude is not constant under different test trays, different heat dissipation conditions, and different operating conditions, in another embodiment, the analog front-end compensation circuit can adopt an implementation with intelligent adjustment capabilities. For example... Figure 3As shown, the analog front-end compensation circuit includes a digital processing microcontroller and a programmable inverting amplifier. The digital processing microcontroller internally deploys a thermoelectric potential compensation mapping machine learning model, which is a multilayer perceptron network. The digital processing microcontroller acquires the digital quantity of the blind-test trace voltage signal and inputs it to the thermoelectric potential compensation mapping machine learning model. The model outputs compensation coefficients, which are then sent by the microcontroller to the control terminal of the programmable inverting amplifier. The amplifier adjusts the gain and inverts the signal based on the compensation coefficients to generate an inverted compensation signal.

[0074] The compensation coefficient here essentially represents the mapping ratio between the blind-test trace voltage signal and the parasitic thermoelectric potential component in the main sampled voltage signal under the current operating conditions. It is not fixed to a single constant because the representation of the true parasitic drift by the blind-test trace will change under different time periods, ambient temperatures, and channel heat distributions on the test tray. The digital processing microcontroller can be a 32-bit microcontroller, equipped with a 16-bit to 24-bit analog-to-digital sampling module, sampling the blind-test trace voltage signal at a sampling frequency of 100Hz to 10kHz. The input to the thermoelectric potential compensation mapping machine learning model can be either the digital quantity of the blind-test trace voltage signal at a certain moment, or a short-time vector composed of the current sampling point and several previous sampling points. To balance computational load and expressive power, in one embodiment, the input dimension can be set to 4 to 32 dimensions, corresponding to the current value, several historical values, and simple time-related statistics, respectively. The network can include 2 to 4 hidden layers, with each layer containing 16, 32, 64, or 128 neurons. The hidden layer activation function can be ReLU, and the output layer uses a linear activation function, outputting a scalar compensation coefficient. This compensation coefficient is typically limited to between 0.7 and 1.3, but can be extended to 0.5 to 1.5 if the testing environment varies significantly. The programmable inverting amplifier can be constructed using a digital potentiometer in conjunction with an operational amplifier, or it can be implemented using a programmable gain amplifier, allowing for real-time adjustment of the inverting gain based on the compensation coefficient issued by the digital processing microcontroller.

[0075] The training process of the thermoelectric potential compensation mapping machine learning model also needs to be matched with the actual device structure. Since the goal of this model is to output more accurate compensation coefficients, the labels in the training set should be as close as possible to the "true thermoelectric potential drift voltage" or the optimal compensation ratio derived from it. In one embodiment, multiple known low-current or zero-current periods can be set during the prototype testing phase. During these periods, the pure current voltage drop on the main current sampling shunt is theoretically known or close to 0. At this time, the main residual in the main sampled voltage signal is thermoelectric potential drift and other slowly varying parasitic quantities. Combined with high-precision reference instruments or four-wire calibration results, historical blind test line voltage signal samples and corresponding true thermoelectric potential drift voltage labels can be constructed. During training, mean square error can be used as the loss function, and the network parameters are updated through the backpropagation algorithm. The learning rate can be set to 0.0001 to 0.01, the batch size can be set to 32 to 256, and the number of training rounds can be set to 50 to 300. After training, the model parameters are embedded in the digital processing microcontroller, and only forward inference is performed during field operation.

[0076] After completing the parasitic compensation at the DC level, this invention also considers that AC interference can cause the same instantaneous real current to exhibit different measured values ​​at different sampling phases. In one embodiment, the system further includes an AC component extraction circuit, a phase-locked loop circuit, and an analog-to-digital converter. The input terminal of the AC component extraction circuit is connected to both ends of the blind test trace, and is used to filter out the DC component in the voltage signal of the blind test trace and output the AC interference voltage signal. Here, the AC component is still preferentially extracted from the blind test trace because the blind test trace does not contain the main current signal body, making it more suitable as an AC interference observation channel.

[0077] In a further embodiment, the AC component extraction circuit includes a DC blocking capacitor and an active bandpass filter. The blind test trace voltage signal passes through the DC blocking capacitor and enters the input terminal of the active bandpass filter, which outputs an AC interference voltage signal. The DC blocking capacitor is used to cut off slow-changing DC drift, and its capacitance can be selected from 0.1μF to 10μF based on the source impedance of the preceding stage and the target lower limit frequency. The passband of the active bandpass filter can be set according to the main interference frequency band at the site. When the test site is mainly affected by the power frequency and its adjacent frequencies, the passband center can be set near 50Hz or 60Hz, the lower cutoff frequency can be set to 40Hz to 45Hz, and the upper cutoff frequency can be set to 65Hz to 120Hz. When there are also strong power switching harmonics at the site, the passband can be appropriately widened to 40Hz to 500Hz, but it should not be too wide to avoid introducing too much irrelevant frequency noise. The AC interference voltage signal obtained through this circuit can more stably characterize the AC coupling phase of the current station.

[0078] The input of the phase-locked loop (PLL) circuit is connected to the output of the AC component extraction circuit. The PLL circuit tracks the phase of the AC interference voltage signal and outputs a zero-crossing trigger signal when the AC interference voltage signal reaches zero. The analog-to-digital converter (ADC) receives a DC compensation voltage signal at its signal input and a zero-crossing trigger signal at its trigger input. It samples the DC compensation voltage signal and outputs a digital current signal at the moment the zero-crossing trigger signal is received. This design utilizes the fact that for approximately sinusoidal or quasi-periodic AC interference, its instantaneous amplitude is smallest near the zero-crossing point, thus minimizing its superposition effect on the main signal. Therefore, arranging the sampling of the main current signal as close as possible to the zero-crossing moment of the AC interference can further reduce AC coupling errors. The ADC can be a high-resolution 18-bit to 24-bit ADC with a sampling rate set from 100Hz to 20kHz. If an externally triggered ADC is used, the sampling pulse can be directly generated by the PLL circuit; if an internally timed ADC is used, the microcontroller can write the zero-crossing trigger signal into the trigger timing register.

[0079] Considering that the phase estimation of the phase-locked loop circuit itself, the filter group delay, and the sample-and-hold time of the analog-to-digital converter may all cause a slight deviation between the ideal zero-crossing moment and the optimal sampling moment, in another embodiment, the phase-locked loop circuit may also include a trigger adjustment microprocessor. The trigger adjustment microprocessor internally deploys a sampling moment prediction reinforcement learning model. The trigger adjustment microprocessor inputs the time series of the AC interference voltage signal into the sampling moment prediction reinforcement learning model, which outputs a trigger moment offset. The time point of the zero-crossing trigger signal is then added to the trigger moment offset to obtain a corrected trigger signal. The analog-to-digital converter samples the DC compensation voltage signal and outputs a digital current signal at the moment it receives the corrected trigger signal.

[0080] The trigger time offset here can be understood as a time correction value made after fine-tuning relative to the ideal zero-crossing time. Since the optimal sampling point in a real system may not be strictly equal to the mathematically defined zero-crossing point, using a reinforcement learning model to gradually approach the sampling time with the "minimum residual AC error" during operation is more adaptable to the differences in real devices than a fixed delay. In one embodiment, the sampling time prediction reinforcement learning model can use a discrete action reinforcement learning network. Its state can be composed of the time series of AC interference voltage signals within the most recent 1 to 3 AC cycles, the previous trigger offset, and the statistics of the residuals from the most recent sampling. Its action can be defined as a set of discrete time offset candidate values, such as several offsets with step sizes of 10μs, 20μs, or 50μs within the range of -500μs to 500μs. Its reward value can be constructed based on the size of the residual AC swing in the DC compensation voltage signal after correction sampling; the smaller the swing, the higher the reward. If the offset change is too large, a slight penalty can be applied to avoid drastic jumps in the trigger time. The model structure can employ a 2- to 3-layer fully connected network, with each layer containing 32 to 128 neurons, and a discount factor set to 0.90 to 0.99. Training can be performed either offline pre-training using historical data or short-term online fine-tuning during the initial stages of equipment operation. After training, the trigger adjustment microprocessor can output a trigger timing offset more suited to the current workstation.

[0081] After obtaining the digital current signal, this invention further considers another practical problem in capacity grading testing: mechanical slippage, bouncing, or micro-vibration may occur when the formation probe contacts the test battery tab. These problems do not necessarily indicate a sudden change in the actual current, but they can cause short-term changes in the local contact resistance of the probe, leaving abnormal traces in both the probe voltage drop signal and the current sampling results. Directly using these abnormal points as actual current data in capacity integration will result in a deviation in the capacity results.

[0082] like Figure 4 As shown, in one embodiment, the system further includes a formation probe, a probe voltage acquisition circuit, and a digital signal processor. The formation probe is connected in series with the main circuit and contacts the tab of the test battery. The probe voltage acquisition circuit acquires the probe voltage drop signal across the formation probe. The digital signal processor receives the digital current signal output from the analog-to-digital converter and the probe voltage drop signal, and internally deploys a mechanical displacement noise recognition machine learning model. The digital signal processor concatenates the digital current signal and the probe voltage drop signal into two-dimensional time series data and inputs it into the mechanical displacement noise recognition machine learning model. The model outputs a mechanical displacement noise Boolean value for each sampling time point. When the mechanical displacement noise Boolean value is true, it indicates that the data at that time point is contaminated by probe mechanical displacement noise; when the mechanical displacement noise Boolean value is false, it indicates that the time point can be used as a normal capacity calculation sample.

[0083] The reason for using digital current signals and probe voltage drop signals in combination is that genuine electrochemical current changes and spurious changes caused by mechanical slippage are sometimes difficult to distinguish in a single channel. However, if both are observed on the same time axis, mechanical displacement often manifests as synchronous jumps, spikes, or recoveries in the probe voltage drop and current measurement values. Utilizing this combined change characteristic is more reliable than judging anomalies solely from the current curve itself.

[0084] In a further embodiment, the network architecture of the machine learning model for mechanical displacement noise recognition is a temporal convolutional network, which includes a one-dimensional convolutional layer and a residual connection structure. This model is used to extract local temporal jump features and inter-channel joint change features from two-dimensional time series data, and the classifier at the end outputs a Boolean value for mechanical displacement noise. Here, the two-dimensional time series data can have two dimensions: the first dimension being a digital current signal and the second dimension being a probe voltage drop signal. The length of the time window fed into the model each time can be set to 16 to 256 sampling points, preferably 32 to 128 sampling points, to balance local anomaly recognition capability and real-time computation. The kernel length of the one-dimensional convolutional layer can be set to 3, 5, or 7, and the number of convolutional channels can be set to 16, 32, 64, or 128. To allow the model to simultaneously see short-term mutations and longer-term dependencies, dilated convolutions can be set, with dilation rates of 1, 2, 4, 8, etc. The residual connection structure helps alleviate the training difficulties of deep networks, allowing shallow mutation information to be more smoothly transmitted to the subsequent classifier.

[0085] The machine learning model for mechanical displacement noise recognition underwent supervised learning training before deployment. The training dataset includes two-dimensional time-series data collected from test equipment and manually labeled time stamps indicating mechanical slippage. Manual labeling can be combined with high-speed video, equipment logs, and probe pressure drop abrupt changes to ensure label reliability. During training, the cross-entropy loss function is used to update the weight parameters of the one-dimensional convolutional layers. The optimizer can employ Adam or stochastic gradient descent algorithms, with an initial learning rate of 0.0001 to 0.005, a batch size of 16 to 128, and 30 to 200 training epochs. To avoid class imbalance caused by a significantly larger number of normal samples compared to abnormal samples, oversampling of abnormal samples in the training set or applying class weights to the cross-entropy loss can be performed.

[0086] After model deployment, the digital signal processor (DSP) outputs a Boolean value for mechanical displacement noise at each sampling time point and discards the corresponding digital current signal at the time point where the Boolean value of mechanical displacement noise is true. This "discarding" is not simply deleting and not processing further, but rather preventing outliers from directly entering the capacity integration process. To maintain the continuity of the time series, the DSP further extracts the digital current signals corresponding to the time points where the Boolean value of mechanical displacement noise is false, prior to the time point where it is true, and performs linear extrapolation to fill in the missing current values ​​during the period of the outlier. In one embodiment, 3 to 20 consecutive normal sampling points before the anomaly can be taken, and a linear relationship can be obtained by fitting using the least squares method. This linear relationship is then extrapolated to fill in the missing current values ​​during the period of the anomaly. If the duration of the anomaly is very short, the slope can be directly calculated using only the two most recent normal sampling points before the anomaly for linear extrapolation. Using preceding normal points for extrapolation, instead of immediately backfilling with mixed points after the anomaly, aims to avoid bringing unstable information from the recovery phase back into the anomaly segment, thus making the filling result closer to the true current evolution trend before the anomaly.

[0087] Based on the above structure, this invention can operate in the following manner during a complete capacity grading test. After the test begins, the main current flows through the main current sampling shunt. The main current sampling connection copper busbar performs the main circuit current conduction function. The blind test trace senses parasitic thermoelectric potential and AC coupling at a position adjacent to the main current sampling connection copper busbar. The analog front-end compensation circuit first uses the blind test trace voltage signal to generate an inverse compensation signal, which is then superimposed with the main sampling voltage signal to obtain a DC compensation voltage signal. Subsequently, the AC component extraction circuit extracts the AC interference voltage signal from the blind test trace voltage signal, and the phase-locked loop circuit tracks its phase and generates a zero-crossing trigger signal. If the device is equipped with a trigger adjustment microprocessor, the zero-crossing sampling time is further fine-tuned by the sampling time prediction reinforcement learning model to obtain a corrected trigger signal. The analog-to-digital converter samples the DC compensation voltage signal at the corresponding trigger time and outputs a digital current signal. Afterwards, the digital signal processor combines the probe voltage drop signal to identify mechanical displacement noise, discards contaminated sampling points, and performs linear extrapolation to fill in the noise. The digital current signal processed by this link can then be used for subsequent capacity integration and grading determination.

[0088] It should be noted that some parameters in this invention can be adjusted according to the test object and equipment level. A smaller resistance value in the main current sampling shunt results in lower power consumption, but also a smaller amplitude of the main sampling voltage signal. Closer spacing between the blind test traces and the main current sampling connection copper busbar improves environmental consistency, but insulation safety margin must also be ensured simultaneously. The closer the gain of the inverting amplifier is to the true parasitic component mapping ratio, the more significant the compensation effect. If the trigger correction value for phase-locked loop sampling is set too high, it is easy to deviate from the minimum AC disturbance point; if it is set too low, it is difficult to compensate for hardware delay. Therefore, these parameters can be tuned through short-term calibration and statistical analysis of operating data in different devices, but the basic technical concept remains unchanged.

[0089] Those skilled in the art will understand that, without departing from the overall concept of this invention, the digital processing microcontroller, trigger adjustment microprocessor, and digital signal processor can be implemented on the same processing platform or by multiple processing units respectively; the inverting amplifier, analog adder, AC component extraction circuit, and phase-locked loop circuit can also be implemented using discrete components or integrated into the same analog front-end board. These adjustments do not affect the core technical approach of this invention: sensing parasitic quantities through blind testing of traces, reducing front-end drift through inversion compensation, reducing AC sampling errors through phase synchronization, and identifying and cleaning mechanical displacement noise through joint probe identification.

Claims

1. A low-noise current sampling and suppression system for capacity grading testing, characterized in that, This includes the main current sampling shunt, the main current sampling connection copper busbar, blind test traces, and the analog front-end compensation circuit. The main current sampling shunt is connected in series in the main circuit used for capacity grading test; The main current sampling connection copper busbar is connected to one end of the main current sampling shunt; The blind test trace and the main current sampling connection copper busbar are arranged parallel to each other on the same test tray surface, and both ends of the blind test trace are connected to the input terminal of the analog front-end compensation circuit. The analog front-end compensation circuit acquires the blind test line voltage signal from both ends of the blind test line; The analog front-end compensation circuit inverts the blind test line voltage signal to generate an inverted compensation signal. The analog front-end compensation circuit acquires the main sampling voltage signal at both ends of the main current sampling shunt. The analog front-end compensation circuit superimposes the inverted compensation signal with the main sampled voltage signal to output a DC compensation voltage signal. The analog front-end compensation circuit includes a digital processing microcontroller and a programmable inverting amplifier. The digital processing microcontroller has a thermoelectric potential compensation mapping machine learning model deployed inside, and the thermoelectric potential compensation mapping machine learning model is a multilayer perceptron network. The digital processing microcontroller acquires the digital quantity of the blind test trace voltage signal and inputs it into the thermoelectric potential compensation mapping machine learning model, and the thermoelectric potential compensation mapping machine learning model outputs the compensation coefficient. The digital processing microcontroller sends the compensation coefficient to the control terminal of the programmable inverting amplifier; The programmable inverting amplifier performs gain adjustment and inversion processing on the blind test line voltage signal according to the compensation coefficient to generate the inverting compensation signal; The thermoelectric potential compensation mapping machine learning model is trained using a training set containing historical blind test line voltage signal samples and corresponding real thermoelectric potential drift voltage labels via backpropagation algorithm.

2. The low-noise current sampling and suppression system for capacity grading testing according to claim 1, characterized in that: The geometry and material composition of the blind test trace are consistent with the geometry and material composition of the main current sampling connection copper busbar; The blind test traces and the main current sampling connection copper busbar are adjacent in physical location but do not make electrical contact.

3. The low-noise current sampling and suppression system for capacity grading testing according to claim 1, characterized in that, The system also includes an AC component extraction circuit, a phase-locked loop circuit, and an analog-to-digital converter; The input terminal of the AC component extraction circuit is connected to both ends of the blind test trace; The AC component extraction circuit filters out the DC component in the blind test trace voltage signal and outputs an AC interference voltage signal. The input terminal of the phase-locked loop circuit is connected to the output terminal of the AC component extraction circuit; The phase-locked loop circuit tracks the phase of the AC interference voltage signal and outputs a zero-crossing trigger signal when the value of the AC interference voltage signal is zero. The signal input terminal of the analog-to-digital converter receives the DC compensation voltage signal; The trigger input terminal of the analog-to-digital converter receives the zero-crossing trigger signal; The analog-to-digital converter samples the DC compensation voltage signal and outputs a digital current signal when it receives the zero-crossing trigger signal.

4. A low-noise current sampling and suppression system for capacity grading testing according to claim 3, characterized in that, The AC component extraction circuit includes a DC blocking capacitor and an active bandpass filter; The blind test trace voltage signal passes through the DC blocking capacitor and enters the input terminal of the active bandpass filter; The active bandpass filter outputs the AC interference voltage signal.

5. A low-noise current sampling and suppression system for capacity grading testing according to claim 3, characterized in that, The phase-locked loop circuit includes a trigger adjustment microprocessor; The trigger adjustment microprocessor is internally deployed with a sampling time prediction reinforcement learning model. The trigger adjustment microprocessor inputs the time series of the AC interference voltage signal into the sampling time prediction reinforcement learning model, and the sampling time prediction reinforcement learning model outputs the trigger time offset. The trigger adjustment microprocessor adds the time point of the zero-crossing trigger signal to the trigger time offset to obtain the corrected trigger signal; The analog-to-digital converter samples the DC compensation voltage signal and outputs a digital current signal when it receives the correction trigger signal.

6. A low-noise current sampling and suppression system for capacity grading testing according to claim 3, characterized in that, The system also includes a formation probe, a probe voltage acquisition circuit, and a digital signal processor; The formation probe is connected in series with the main circuit and makes contact with the tab of the test battery; The probe voltage acquisition circuit acquires the probe voltage drop signal across the two ends of the formation probe; The digital signal processor receives the digital current signal output by the analog-to-digital converter and the probe voltage drop signal; The digital signal processor is internally equipped with a machine learning model for recognizing mechanical displacement noise. The digital signal processor concatenates the digital current signal and the probe voltage drop signal into two-dimensional time series data and inputs it into the mechanical displacement noise recognition machine learning model. The mechanical displacement noise recognition machine learning model outputs the mechanical displacement noise Boolean value at each sampling time point. The digital signal processor discards the corresponding digital current signal at the time point when the mechanical displacement noise Boolean value is true, and extracts the digital current signal corresponding to the time point before the time point when the mechanical displacement noise Boolean value is true and the time point when the mechanical displacement noise Boolean value is false, and performs linear extrapolation filling.

7. A low-noise current sampling and suppression system for capacity grading testing according to claim 6, characterized in that: The network architecture of the machine learning model for mechanical displacement noise recognition is a temporal convolutional network, which includes a one-dimensional convolutional layer and a residual connection structure. The machine learning model for mechanical displacement noise recognition extracts the local temporal jump features and inter-channel joint change features of the two-dimensional time series data, and the classifier at the end outputs the Boolean value of the mechanical displacement noise.

8. A low-noise current sampling and suppression system for capacity grading testing according to claim 7, characterized in that: The machine learning model for mechanical displacement noise recognition was trained using supervised learning before deployment. The training dataset for training the machine learning model for mechanical displacement noise recognition includes sample two-dimensional time series data collected by running the test equipment and labels of the mechanical slip occurrence time manually annotated. The training process uses the cross-entropy loss function to update the weight parameters of the one-dimensional convolutional layer.

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