Optical chip and optical module

Abstract

The invention provides an optical chip and an optical module, the optical chip comprises a first optical modulator and a second optical modulator, the first optical modulator comprises a first modulation electrode area and a first modulation waveguide, the first modulation electrode area is located at the lower edge of the optical chip, and the first modulation waveguide is located above the first modulation electrode area. The second optical modulator comprises a second modulation electrode area and a second modulation waveguide, the second modulation electrode area is located on the upper edge of the optical chip, and the second modulation waveguide is located below the second modulation electrode area. The second modulation waveguide is located on the right side of the first modulation waveguide, and the second modulation waveguide and the first modulation waveguide are overlapped in the vertical direction of the optical chip. A first modulation electrode area is located at the lower edge of the optical chip, a first modulation waveguide is located above the first modulation electrode area, a second modulation electrode area is located at the upper edge of the optical chip, a second modulation waveguide is located below the second modulation electrode area, and the second modulation waveguide and the first modulation waveguide are overlapped in the vertical direction of the optical chip. The size of the optical chip in the left-right direction is reduced.

Description

[0001] This application claims priority to Chinese patent application No. 202511884282.0, filed on December 12, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of optical communication technology, and in particular to an optical chip and an optical module. Background Technology

[0003] With the development of new business and application models such as cloud computing, mobile internet, and video, advancements in optical communication technology have become increasingly important. In optical communication technology, the optical module, as one of the key components in optical communication equipment, enables photoelectric signal conversion; and in the development of optical communication technology, the data transmission rate of optical modules is required to continuously improve. Summary of the Invention

[0004] In some embodiments, an optical chip and an optical module are provided to provide an optical chip design.

[0005] In some embodiments, an optical chip is provided, comprising: The optical port is located at the right edge of the optical chip; The demodulation region is located on the left edge of the optical chip and is optically connected to the optical port end, so that the demodulation region receives the light to be demodulated and demodulates the light to be demodulated; A modulation region is located between the optical port and the demodulation region, and is optically connected to the optical port so that the modulation region receives the light to be modulated, modulates the light to be modulated to generate an optical signal, and outputs the optical signal. The modulation region includes: The first optical modulator includes: The first modulation electrode region is located at the lower edge of the optical chip; The first modulation waveguide is located above the first modulation electrode region; The second optical modulator includes: The second modulation electrode region is located at the upper edge of the optical chip; The second modulation waveguide is located below the second modulation electrode region and to the right of the first modulation waveguide; the second modulation waveguide overlaps with the first modulation waveguide in the vertical direction of the optical chip. Light enters from the upper and lower edges of the optical port end, and light exits from the center of the optical port end.

[0006] One of the above technical solutions has the following advantages or beneficial effects: This application discloses an optical chip, including an optical port, a demodulation region, and a modulation region. The optical port is located at the right edge of the optical chip, the demodulation region is located at the left edge of the optical chip, and the modulation region is located between the optical port and the demodulation region, that is, the demodulation region is located to the left of the modulation region, and the optical port is located to the right of the modulation region. The demodulation region is optically connected to the optical port so that the demodulation region receives the light to be demodulated and demodulates the light to be demodulated. The modulation region is connected to the optical port so that the modulation region receives the light to be modulated, modulates the light to be modulated to generate an optical signal, and outputs the optical signal. The modulation region includes a first optical modulator and a second optical modulator. The first optical modulator includes a first modulation electrode region and a first modulation waveguide. The first modulation electrode region is located at the lower edge of the optical chip, and the first modulation waveguide is located above the first modulation electrode region. The input end of the first modulation waveguide is close to the first modulation electrode region, and the output end of the first modulation waveguide is far away from the first modulation electrode region. Therefore, the input end of the first modulation waveguide is located at the lower edge of the optical chip, and the output end of the first modulation waveguide is located in the middle of the optical chip. The second optical modulator includes a second modulation electrode region and a second modulation waveguide. The second modulation electrode region is located at the upper edge of the optical chip, and the second modulation waveguide is located below the second modulation electrode region. The input end of the second modulation waveguide is close to the second modulation electrode region, and the output end of the second modulation waveguide is far from the second modulation electrode region. Therefore, the input end of the second modulation waveguide is located at the upper edge of the optical chip, and the output end of the second modulation waveguide is located in the middle of the optical chip. The first modulation electrode region is located at the lower edge of the optical chip, and the first modulation waveguide is located above the first modulation electrode region. The second modulation electrode region is located at the upper edge of the optical chip, and the second modulation waveguide is located below the second modulation electrode region. The second modulation waveguide is located to the right of the first modulation waveguide. The second modulation waveguide and the first modulation waveguide overlap vertically in the optical chip, reducing the horizontal dimension of the optical chip and thus improving its integration density. The optical output port array is located in the middle of the optical port end to shorten the transmission path between the first and second modulation waveguides and the output optical port array, reducing transmission loss. The demodulation region is located to the left of the modulation region, and the optical port is located to the right of the modulation region. Light enters from the upper and / or lower edges of the optical port, allowing the light to be demodulated to be efficiently coupled into the optical chip from one side of the upper and / or lower edge. This helps to shorten the transmission path of the optical signal inside the chip and reduce transmission loss. The remaining area of ​​the optical port allows the light to be modulated to enter, realizing bidirectional transmission and processing of the optical signal. In this disclosure, the first modulation electrode region is located at the lower edge of the optical chip, the first modulation waveguide is located above the first modulation electrode region, the second modulation electrode region is located at the upper edge of the optical chip, and the second modulation waveguide is located below the second modulation electrode region. The second modulation waveguide overlaps with the first modulation waveguide in the vertical direction of the optical chip, reducing the horizontal dimension of the optical chip.

[0007] In some embodiments, an optical chip is provided, wherein the optical port includes: An input optical port array, located at the upper or lower edge of the optical port end, is connected to the demodulation region to receive the light to be demodulated and transmit the light to be demodulated into the demodulation region; A light source input optical port array and the input optical port array are located at opposite edges of the optical port end and connected to the input ends of the first modulation waveguide and the second modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input ends of the first modulation waveguide and the second modulation waveguide; An output optical port array is located between the input optical port array and the light source input optical port array, and is connected to the output ends of the first modulation waveguide and the second modulation waveguide to receive the optical signal and output the optical signal.

[0008] One of the above technical solutions has the following advantages or beneficial effects: The optical port includes an input optical port array, a light source input optical port array, and an output optical port array. The input optical port array is connected to the demodulation region to receive the light to be demodulated and transmit it to the demodulation region, enabling the demodulation region to demodulate the light to be demodulated. The light source input optical port array is connected to the input ends of the first and second modulation waveguides to receive the light to be modulated and transmit the modulated light to the input ends of the first and second modulation waveguides, enabling the first and second modulation waveguides to modulate the light to be modulated and generate an optical signal. The output optical port array is connected to the output ends of the first and second modulation waveguides to receive the optical signal output from the output ends of the first and second modulation waveguides and output the optical signal. The input optical port array is located at the upper or lower edge of the optical port, allowing the light to be demodulated to be efficiently coupled into the optical chip from the upper or lower edge, which helps to shorten the transmission path of the optical signal inside the chip and reduce transmission loss. The light source input optical port array and the input optical port array are located at opposite edges of the optical port end, which can avoid the optical path crossing of the light to be modulated and the light to be demodulated inside the optical chip. The output optical port array is located between the input optical port array and the light source input optical port array to shorten the transmission path between the first modulation waveguide, the second modulation waveguide and the output optical port array, and reduce transmission loss.

[0009] In some embodiments, an optical chip is provided, wherein the optical port includes: An input optical port array, located at the upper or lower edge of the optical port end, is connected to the demodulation region to receive the light to be demodulated and transmit the light to be demodulated into the demodulation region; The light source input optical port array includes: The first light source input port is arranged adjacent to the input port array and connected to the input end of the second modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input end of the second modulation waveguide; The second light source input port and the input port array are located at opposite edges of the port end and connected to the input end of the first modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input end of the first modulation waveguide. An output optical port array is located between the first light source input optical port and the second light source input optical port, and is connected to the output ends of the first modulation waveguide and the second modulation waveguide to receive the optical signal and output the optical signal.

[0010] One of the above technical solutions has the following advantages or beneficial effects: The optical port includes an input optical port array, a light source input optical port array, and an output optical port array. The input optical port array is connected to the demodulation region to receive the light to be demodulated and transmit it to the demodulation region, enabling the demodulation region to demodulate the light to be demodulated. The output optical port array is connected to the output ends of the first and second modulation waveguides to receive the optical signals output from the output ends of the first and second modulation waveguides and output the optical signals. The input optical port array is located at the upper or lower edge of the optical port, allowing the light to be demodulated to be efficiently coupled into the optical chip from the upper or lower edge, which helps to shorten the transmission path of the optical signal inside the chip and reduce transmission loss. The light source input optical port array includes a first light source input optical port and a second light source input optical port. The first light source input optical port is connected to the input end of the second modulation waveguide to receive the light to be modulated and transmit the modulated light to the input end of the second modulation waveguide, enabling the second modulation waveguide to modulate the light to be modulated and generate an optical signal. The second light source input port is connected to the input end of the first modulation waveguide to receive the light to be modulated and transmit the modulated light to the input end of the first modulation waveguide, so that the first modulation waveguide modulates the light to be modulated to generate an optical signal. The first light source input port and the input port array are arranged adjacent to each other, the second light source input port and the input port array are located on opposite edges of the port ends, and the output port array is located between the first light source input port and the second light source input port. This can shorten the transmission path between the first light source input port and the input end of the second modulation waveguide and reduce transmission loss.

[0011] In some embodiments, an optical chip is provided, wherein the optical port includes: An input optical port array, located at the upper or lower edge of the optical port end, is connected to the demodulation region to receive the light to be demodulated and transmit the light to be demodulated into the demodulation region; The light source input optical port array includes: The first light source input port is connected to the input end of the second modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input end of the second modulation waveguide; The second light source input port and the input port array are located at opposite edges of the port end and connected to the input end of the first modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input end of the first modulation waveguide. The output optical port array includes: The first output optical port is located between the input optical port array and the first light source input optical port, and is connected to the output end of the first modulation waveguide to receive the optical signal and output the optical signal. The second output optical port is located between the first light source input optical port and the second light source input optical port, and is connected to the output end of the second modulation waveguide to receive the optical signal and output the optical signal.

[0012] One of the above technical solutions has the following advantages or beneficial effects: The optical port end includes an input optical port array, a light source input optical port array, and an output optical port array. The input optical port array is connected to the demodulation region to receive the light to be demodulated and transmit it to the demodulation region, enabling the demodulation region to demodulate the light to be demodulated. The input optical port array is located at the upper or lower edge of the optical port end, allowing the light to be demodulated to be efficiently coupled into the optical chip from the upper or lower edge, which helps to shorten the transmission path of the optical signal inside the chip and reduce transmission loss. The light source input optical port array includes a first light source input optical port and a second light source input optical port. The first light source input optical port is connected to the input end of a second modulation waveguide to receive the light to be modulated and transmit the modulated light to the input end of the second modulation waveguide, enabling the second modulation waveguide to modulate the light to be modulated and generate an optical signal. The second light source input optical port is connected to the input end of the first modulation waveguide to receive the light to be modulated and transmit the modulated light to the input end of the first modulation waveguide, enabling the first modulation waveguide to modulate the light to be modulated and generate an optical signal. The output optical port array includes a first output optical port and a second output optical port. The first output optical port is connected to the output end of the first modulation waveguide to receive the optical signal output from the output end of the first modulation waveguide and output the optical signal. The second output optical port is connected to the output end of the second modulation waveguide to receive the optical signal output from the output end of the second modulation waveguide and output the optical signal. The first output optical port is located between the input optical port array and the first light source input optical port, and the second output optical port is located between the first light source input optical port and the second light source input optical port. This not only shortens the transmission path between the input end of the second modulation waveguide and the first light source input optical port, but also shortens the transmission path between the output end of the first modulation waveguide and the first output optical port, thus reducing transmission loss.

[0013] In some embodiments, an optical chip is provided, wherein a first modulation waveguide extends upward and its end extends beyond the central axis of the optical chip; and a second modulation waveguide extends downward and its end extends beyond the central axis of the optical chip.

[0014] One of the above technical solutions has the following advantages or beneficial effects: the first modulation waveguide extends upward and its end exceeds the central axis of the optical chip, and the second modulation waveguide extends downward and its end exceeds the central axis of the optical chip, so that the first modulation waveguide and the second modulation waveguide overlap in the vertical direction of the optical chip.

[0015] In some embodiments, an optical chip is provided in which the width of the optical chip occupied by the first optical modulator and the second optical modulator is greater than half the width of the optical chip and less than the width of the optical chip.

[0016] One of the above technical solutions has the following advantages or beneficial effects: the width of the optical chip occupied by the first optical modulator and the second optical modulator is greater than half of the width of the optical chip and smaller than the width of the optical chip, so that the first optical modulator and the second optical modulator overlap in the vertical direction of the optical chip.

[0017] In some embodiments, an optical chip is provided in which the length of the first modulation waveguide and the length of the second modulation waveguide are both greater than half the width of the optical chip and less than the width of the optical chip.

[0018] One of the above technical solutions has the following advantages or beneficial effects: the length of the first modulation waveguide and the length of the second modulation waveguide are both greater than half the width of the optical chip and less than the width of the optical chip, so that the width of the optical chip occupied by the first optical modulator and the second optical modulator is both greater than half the width of the optical chip and less than the width of the optical chip.

[0019] In some embodiments, an optical module is provided, comprising: Optical chip; The first driving chip is located below the optical chip; The second driving chip is located on top of the optical chip; The optical chip includes: The optical port is located at the right edge of the optical chip; The demodulation region is located on the left edge of the optical chip and is optically connected to the optical port end, so that the demodulation region receives the light to be demodulated and demodulates the light to be demodulated; A modulation region is located between the optical port and the demodulation region, and is optically connected to the optical port so that the modulation region receives the light to be modulated, modulates the light to be modulated to generate an optical signal, and outputs the optical signal. The modulation region includes: The first optical modulator includes: The first modulation electrode region is located at the lower edge of the optical chip and is electrically connected to the first driving chip; The first modulation waveguide is located above the first modulation electrode region; The second optical modulator includes: The second modulation electrode region is located at the upper edge of the optical chip and is electrically connected to the second driving chip; The second modulation waveguide is located below the second modulation electrode region and to the right of the first modulation waveguide; the second modulation waveguide overlaps with the first modulation waveguide in the vertical direction of the optical chip. Light enters from the upper and lower edges of the optical port end, and light exits from the center of the optical port end.

[0020] One of the above technical solutions has the following advantages or beneficial effects: The optical module includes an optical chip, a first driver chip, and a second driver chip. The first driver chip is located on the lower side of the optical chip, and the second driver chip is located on the upper side of the optical chip. The optical chip includes an optical port, a demodulation region, and a modulation region. The optical port is located on the right edge of the optical chip, the demodulation region is located on the left edge of the optical chip, and the modulation region is located between the optical port and the demodulation region, that is, the demodulation region is located to the left of the modulation region, and the optical port is located to the right of the modulation region. The demodulation region is optically connected to the optical port so that the demodulation region receives the light to be demodulated and demodulates the light to be demodulated. The modulation region is connected to the optical port so that the modulation region receives the light to be modulated, modulates the light to be modulated to generate an optical signal, and outputs the optical signal. The modulation region includes a first optical modulator and a second optical modulator. The first optical modulator includes a first modulation electrode region and a first modulation waveguide. The first modulation electrode region is located on the lower edge of the optical chip and is electrically connected to the first driver chip, and the first modulation waveguide is located above the first modulation electrode region. The first modulation waveguide has its input end close to the first modulation electrode region and its output end far from the first modulation electrode region. Therefore, the input end of the first modulation waveguide is located at the lower edge of the optical chip, and its output end is located in the middle of the optical chip. The second optical modulator includes a second modulation electrode region and a second modulation waveguide. The second modulation electrode region is located at the upper edge of the optical chip and is electrically connected to the second driver chip. The second modulation waveguide is located below the second modulation electrode region. The second modulation waveguide has its input end close to the second modulation electrode region and its output end far from the second modulation electrode region. Therefore, the input end of the second modulation waveguide is located at the upper edge of the optical chip, and its output end is located in the middle of the optical chip. The first modulation electrode region is located at the lower edge of the optical chip, and the first modulation waveguide is located above the first modulation electrode region. The second modulation electrode region is located at the upper edge of the optical chip, and the second modulation waveguide is located below the second modulation electrode region. The second modulation waveguide is located to the right of the first modulation waveguide. The second modulation waveguide and the first modulation waveguide overlap vertically in the optical chip, reducing the horizontal dimension of the optical chip and thus improving its integration density. The optical port outputs light from the center, meaning the output optical port array is located in the middle of the optical port to shorten the transmission path between the first and second modulation waveguides and the output optical port array, reducing transmission loss. The demodulation region is located to the left of the modulation region, and the optical port is located to the right of the modulation region. Light enters from the upper and / or lower edges of the optical port, allowing the light to be demodulated to be efficiently coupled into the optical chip from one side of the upper and / or lower edge. This helps to shorten the transmission path of the optical signal inside the chip and reduce transmission loss. The remaining area of ​​the optical port receives the light to be modulated, enabling bidirectional transmission and processing of the optical signal.

[0021] In some embodiments, an optical chip is provided, wherein the optical port includes: An input optical port array, located at the upper or lower edge of the optical port end, is connected to the demodulation region to receive the light to be demodulated and transmit the light to be demodulated into the demodulation region; A light source input optical port array and the input optical port array are located at opposite edges of the optical port end and connected to the input ends of the first modulation waveguide and the second modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input ends of the first modulation waveguide and the second modulation waveguide; An output optical port array is located between the input optical port array and the light source input optical port array, and is connected to the output ends of the first modulation waveguide and the second modulation waveguide to receive the optical signal and output the optical signal.

[0022] One of the above technical solutions has the following advantages or beneficial effects: The optical port includes an input optical port array, a light source input optical port array, and an output optical port array. The input optical port array is connected to the demodulation region to receive the light to be demodulated and transmit it to the demodulation region, enabling the demodulation region to demodulate the light to be demodulated. The light source input optical port array is connected to the input ends of the first and second modulation waveguides to receive the light to be modulated and transmit the modulated light to the input ends of the first and second modulation waveguides, enabling the first and second modulation waveguides to modulate the light to be modulated and generate an optical signal. The output optical port array is connected to the output ends of the first and second modulation waveguides to receive the optical signal output from the output ends of the first and second modulation waveguides and output the optical signal. The input optical port array is located at the upper or lower edge of the optical port, allowing the light to be demodulated to be efficiently coupled into the optical chip from the upper or lower edge, which helps to shorten the transmission path of the optical signal inside the chip and reduce transmission loss. The light source input optical port array and the input optical port array are located at opposite edges of the optical port end. This not only shortens the transmission path of the light to be modulated entering one of the first and second modulation waveguides, reducing transmission loss, but also prevents the optical paths of the light to be modulated and the light to be demodulated from crossing inside the optical chip. The output optical port array is located between the input optical port array and the light source input optical port array to shorten the transmission path between the first and second modulation waveguides and the output optical port array, reducing transmission loss.

[0023] In some embodiments, an optical chip is provided, wherein the demodulation region includes: First optical demodulator, surface formation: First cathode section; First anode section; Third cathode section; The second optical demodulator is disposed adjacent to the first optical demodulator, and its surface is formed as follows: Second cathode section; Second anode section; The fourth cathode portion; the distance between the second anode portion and the first anode portion is less than 8.4 times the diameter of the first anode portion; the second cathode portion and the fourth cathode portion are located at the upper and lower ends of one side of the second anode portion, the first cathode portion and the third cathode portion are located at the upper and lower ends of one side of the first anode portion, the second anode portion and the first anode portion are located in the first column of the optical chip, and the fourth cathode portion, the second cathode portion, the third cathode portion and the first cathode portion are located in the second column of the optical chip; The left side of the optical chip is also provided with: The first transimpedance amplifier chip, corresponding to the first optical demodulator, has the following surface formation: The first negative electrode connection part is electrically connected to the first cathode part; The first positive electrode connection portion is electrically connected to the first anode portion; The third negative electrode connection part is electrically connected to the third cathode part; The second transimpedance amplifier chip, corresponding to the second optical demodulator, has the following surface formation: The second negative electrode connection part is electrically connected to the second cathode part; The second positive electrode connection part is electrically connected to the second anode part; The fourth negative electrode connection part is electrically connected to the fourth cathode part; The distance between the second positive electrode connection and the first positive electrode connection is 0.8 to 1.2 times the distance between the first anode part and the second anode part.

[0024] One of the above technical solutions has the following advantages or beneficial effects: The demodulation region includes a first optical demodulator and a second optical demodulator, which are arranged adjacent to each other. The surface of the first optical demodulator forms a first cathode, a first anode, and a third cathode, while the surface of the second optical demodulator forms a second cathode, a second anode, and a fourth cathode. The distance between the second anode and the first anode is less than 8.4 times the diameter of the first anode. Since the first, first, third, second, second, and fourth cathodes cannot be located in the same column of the optical chip, they need to be placed in different columns. The second and fourth cathodes are located at the upper and lower ends of one side of the second anode, and the first and third cathodes are located at the upper and lower ends of one side of the first anode, so that the first, first, and third cathodes and the second, second, and fourth cathodes form a triangle. This effectively reduces the electrode spacing between adjacent optical demodulators, thereby integrating more optical demodulator channels within a limited chip area, further improving the integration density and board utilization of the optical chip. The second anode and the first anode are located in the first column of the optical chip, while the fourth cathode, the second cathode, the third cathode, and the first cathode are located in the second column. This arrangement of the anodes and cathodes in columns avoids the electrodes of adjacent optical demodulators intersecting in the column direction, reducing interference between electrodes and ensuring the accuracy and stability of the demodulated signal. A first transimpedance amplifier chip and a second transimpedance amplifier chip are also located on the left side of the optical chip. The first transimpedance amplifier chip is correspondingly positioned to the first optical demodulator, and the second transimpedance amplifier chip is correspondingly positioned to the second optical demodulator. The surface of the first transimpedance amplifier chip has a first negative electrode connection portion, a first positive electrode connection portion, and a third negative electrode connection portion. The first negative electrode connection portion is electrically connected to the first cathode, the first positive electrode connection portion is electrically connected to the first anode, and the third negative electrode connection portion is electrically connected to the third cathode, thus electrically connecting the first transimpedance amplifier chip to the first optical demodulator. The surface of the second transimpedance amplifier chip forms a second negative electrode connection portion, a second positive electrode connection portion, and a fourth negative electrode connection portion. The second negative electrode connection portion is electrically connected to the second cathode portion, the second positive electrode connection portion is electrically connected to the second anode portion, and the fourth negative electrode connection portion is electrically connected to the fourth cathode portion, so that the second transimpedance amplifier chip is electrically connected to the second optical demodulator. The spacing between the second positive electrode connection portion and the first positive electrode connection portion is 0.8 to 1.2 times the spacing between the first anode portion and the second anode portion, to ensure that the traces connecting the first anode portion and the first positive electrode connection portion, as well as the traces connecting the second anode portion and the second positive electrode connection portion on the circuit board, have similar lengths and similar paths, thereby reducing signal delay and loss inconsistencies caused by trace differences. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] Figure 1 This is a schematic diagram of an optical module connected to a host computer according to some embodiments; Figure 2a This is a partial structure of a host computer and an optical module according to some embodiments. Figure 1 ; Figure 2b Partial breakdown of an optical module according to some embodiments Figure 1 ; Figure 2c A partial exploded view of an optical module provided according to some embodiments is shown in Figure 2. Figure 3 This is a schematic diagram of an optical module structure according to some embodiments; Figure 4 An exploded view of an optical module according to some embodiments; Figure 5a For the local optical path of a first type of optical module according to some embodiments Figure 1 ; Figure 5b A partial optical path diagram of a first type of optical module according to some embodiments is shown in Figure 2. Figure 5c For the local optical path of a first type of optical module provided according to some embodiments Figure 3 ; Figure 5d For the local optical path of a first type of optical module provided according to some embodiments Figure 4 ; Figure 6 A partial optical path diagram of a second type of optical module provided according to some embodiments; Figure 7a This is a schematic diagram of a partial connection between a first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments. Figure 1 ; Figure 7b A second schematic diagram showing a partial connection between a first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments; Figure 7c This is a partial connection diagram of a second type of first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments; Figure 7d This is a partial connection diagram of a third type of first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments; Figure 7e This is a partial connection diagram of a fourth type of first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments; Figure 8a This is a partial schematic diagram of a third type of optical module provided according to some embodiments; Figure 8b This is a partial schematic diagram of a fourth optical module provided according to some embodiments; Figure 9a This is a partial schematic diagram of a fifth optical module provided according to some embodiments; Figure 9b This is a partial schematic diagram of a sixth optical module provided according to some embodiments; Figure 10 This is a schematic diagram of the internal electrical connections of a first optical demodulator according to some embodiments; Figure 11a This is a partial connection diagram of the fifth type of first optical demodulator array and first transimpedance amplifier chip array according to some embodiments. Figure 1 ; Figure 11b This is a partial connection diagram of the fifth type of first optical demodulator array and first transimpedance amplifier chip array provided according to some embodiments; Figure 11c This is a partial connection diagram of the sixth type of first optical demodulator array and first transimpedance amplifier chip array according to some embodiments. Figure 1 ; Figure 11d This is a partial connection diagram of the sixth type of first optical demodulator array and first transimpedance amplifier chip array according to some embodiments; Figure 11e This is a partial connection diagram of a seventh type of first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments; Figure 11f This is a partial connection diagram of the eighth type of first optical demodulator array and first transimpedance amplifier chip array according to some embodiments; Figure 12 This is a schematic diagram showing the electrical connection between a first optical demodulator and a first transimpedance amplifier chip according to some embodiments; Figure 13 This is a schematic diagram showing the electrical connection of a first optical demodulator and a first transimpedance amplifier chip to a circuit board according to some embodiments; Figure 14This is a schematic diagram showing the electrical connection between another first optical demodulator and a first transimpedance amplifier chip according to some embodiments. Detailed Implementation

[0027] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0028] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0029] In optical communication technology, information is loaded onto light to generate optical signals, which are then used to transmit information between information processing devices. Connections are established between these devices via optical transmission equipment. Optical power loss is minimal during transmission through optical transmission equipment, allowing for long-distance transmission with minimal power loss. Light boasts extremely high transmission speeds. The cost of optical transmission equipment, such as fiber optic cables, is lower than that of electrical transmission equipment like copper wires. Using optical signals to transmit information offers advantages such as long-distance transmission, high speed, and low cost.

[0030] Information processing equipment typically includes switches, servers, optical network units (ONUs), optical distribution networks (ODNs), optical line terminals (OLTs), gateways, routers, mobile phones, computers, tablets, televisions, etc.; optical transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can recognize and process electrical signals, while optical transmission equipment can transmit optical signals. Therefore, optical modules are needed between the optical transmission equipment and the information processing equipment to perform the conversion between optical and electrical signals.

[0031] In some embodiments, the optical signal input and / or optical signal output of the optical module are connected to an optical fiber, and the electrical signal input and / or electrical signal output of the optical module are connected to a switch; a first optical signal from the optical fiber is transmitted to the optical module, the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the switch; a second electrical signal from the switch is transmitted to the optical module, the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber.

[0032] Information processing equipment connected to optical modules is also known as the host computer for optical modules. In access network transmission scenarios, the host computer for optical modules is usually an ONU, ODN, or OLT; in data center transmission scenarios, the host computer for optical modules is usually a Switch or Server.

[0033] Figure 1 This is a schematic diagram illustrating the structure of an optical module connected to a host computer according to some embodiments. Figure 1 As shown, the host computer 100 includes a circuit board 102, on which a processing chip 110 is mounted; multiple optical modules 200 are placed around the processing chip 110. The optical modules 200 are directly placed on the host computer's circuit board 102, surrounding the processing chip 110. This design not only shortens the distance of electrical signal transmission but also increases the area for optical module deployment, enabling high-density, high-quality signal transmission. This combination of optical modules and the host computer is known in the industry as NPO (Near packaged optics) or CPO (Co-packaged optics).

[0034] In some embodiments, the optical module 200 extends outwards along the periphery of the processing chip 110. Its extension direction is the length direction of the optical module 200. Therefore, the width of the optical module 200 determines the arrangement density of the optical modules 200 that can be placed around the processing chip 110. The higher the arrangement density of the optical modules 200 around the processing chip 110, the more optical modules can be deployed per unit area, and the higher the overall data transmission bandwidth. To meet the requirements of high-density arrangement, the width of the optical module needs to be minimized, which places higher demands on the integration and layout design of the internal components of the optical module.

[0035] Multiple optical modules are directly deployed on the circuit board of the host computer, establishing electrical signal communication between the optical modules and the host computer; optical fiber 101 is connected to the optical modules, establishing optical signal communication between the optical fiber and the optical modules. One end of optical fiber 101 is connected to the optical module, and the other end of optical fiber 101 ( Figure 1 (not shown in the image) connects to another optical module ( Figure 1 (Not shown in the image), another optical module is connected to its corresponding host computer ( Figure 1 (Not shown in the image).

[0036] In some embodiments, the optical fiber 101 and the optical module 200 are detachably connected; in other embodiments, the optical fiber 101 and the optical module 200 are non-detachably connected.

[0037] In some embodiments, the host computer 100 is configured to provide data electrical signals to the optical module 200, or receive data electrical signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0038] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0039] Figure 2a This is a partial structure of a host computer and an optical module according to some embodiments. Figure 1 . Figure 2b Partial breakdown of an optical module according to some embodiments Figure 1 . Figure 2c This is a partially exploded view of an optical module according to some embodiments, as shown in Figure 2. Figure 2a , Figure 2b and Figure 2c Only the structure of the host computer 100 related to the optical module 200 is shown.

[0040] In some embodiments, the optical module includes a housing 201, a circuit board 300, and an electrical connection socket 103. The housing and the electrical connection socket 103 are combined to form a cavity, and the circuit board 300 is placed in the cavity between the housing 201 and the electrical connection socket 103. The electrical connection between the circuit board 300 of the optical module and the host computer circuit board 102 is achieved through the electrical connection socket 103.

[0041] In some embodiments, the optical module includes a housing 201 and a circuit board 300. An electrical connection socket 103 is located on the circuit board 102 of the host computer, and the electrical connection between the circuit board 300 of the optical module and the circuit board 102 of the host computer is realized through the electrical connection socket 103.

[0042] When optical module manufacturers provide optical module products, whether the optical module includes the electrical connection socket 103 or not is a matter of commercial choice and there is no technical difference; the electrical connection socket 103 is used to establish the electrical connection between the optical module circuit board 300 and the host computer circuit board 102.

[0043] In some embodiments, the host computer 100 includes an electrical connection socket 103 disposed on the surface of the PCB circuit board 102, while the optical module 200 does not include the electrical connection socket 103. The optical module 200 is directly inserted into the electrical connection socket 103, and the optical module 200 is fixed by the electrical connection socket 103, thereby fixing the optical module 200 to the host computer 100.

[0044] In some embodiments, the host computer 100 does not include the electrical connection socket 103, and the optical module 200 includes the electrical connection socket 103. The electrical connection socket 103 is fixed to the surface of the PCB circuit board 102 so that the optical module 200 is fixed to the host computer 100.

[0045] In some embodiments, an electrical connector 134 is provided inside the electrical connection socket 103. One end of the electrical connector 134 is electrically connected to the circuit board 300 of the optical module, and the other end of the electrical connector 134 is electrically connected to the circuit board 102 of the host computer, thereby establishing an electrical signal connection between the optical module 200 and the host computer 100.

[0046] In some embodiments, the optical interface of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0047] Figure 3 This is a schematic diagram of an optical module structure according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4As shown, in some embodiments, the optical module 200 may include a housing 201 and a circuit board 300. The housing 201 covers the circuit board 300, and an opening is formed on the side of the housing for connecting an optical fiber.

[0048] In some embodiments, the housing 201 is made of a metallic material, which facilitates electromagnetic shielding and heat dissipation.

[0049] The assembly method of combining the housing 201 and the circuit board 300 facilitates the installation of optical chips and other devices between the circuit board 300 and the housing 201. The housing 201 and the circuit board can encapsulate and protect the optical chips and other devices.

[0050] In some embodiments, the circuit board 300 includes circuit traces, electronic components, and chips. The electronic components and chips are connected according to the circuit design through the circuit traces to realize functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include silicon photonics chips, microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery (CDR) chips, power management chips, and digital signal processing (DSP) chips.

[0051] In some embodiments, the circuit board includes a rigid circuit board, which, due to its relatively rigid material, can also serve a load-bearing function, such as being able to stably support the aforementioned electronic components and chips.

[0052] In some embodiments, the circuit board further includes a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board to increase the area for the placement of electrical components.

[0053] In some embodiments, the optical module 200 includes a fiber optic ferrule array 800, which includes at least one fiber optic ferrule. In some embodiments, the fiber optic ferrule array 800 is capable of transmitting optical signals emitted by the optical module 200; in some embodiments, the fiber optic ferrule array 800 is capable of receiving external optical signals; in some embodiments, the fiber optic ferrule array 800 is capable of receiving external light that does not carry signals.

[0054] In some embodiments, the optical module 200 may include a fiber optic connector array 600. A fiber optic ferrule array 800 may be inserted into one end of the fiber optic connector array 600 to connect the fiber optic ferrule array 800 to the fiber optic connector array 600. An external fiber optic ferrule array may be inserted into the other end of the fiber optic connector array 600 to connect the external fiber optic ferrule array to the fiber optic connector array 600, thereby connecting the fiber optic ferrule array 800 to the external fiber optic ferrule array via the fiber optic connector array 600.

[0055] The fiber optic connector array 600 may include at least one fiber optic connector. The number of fiber optic connectors may be the same as the number of fiber optic ferrules, so that each fiber optic connector can be connected to its corresponding fiber optic ferrule to achieve stable transmission of optical signals. The arrangement of the fiber optic connector array 600 allows the optical module 200 to be easily connected to external fiber optic devices, improving the flexibility and applicability of the optical module.

[0056] In some embodiments, the optical module 200 may include an optical fiber ribbon 710. One end of the optical fiber ribbon 710 may be connected to the optical fiber ferrule array 800. The optical fiber ribbon 710 may include multiple optical fibers.

[0057] In some embodiments, the optical module 200 may include an optical chip 900, which may be disposed on the upper surface of the circuit board 300 and electrically connected to the upper surface of the circuit board 300. In some embodiments, the circuit board 300 may provide data signals from a host computer to the optical chip 900, and the optical chip 900 may modulate light emitted by an external light source that does not carry data signals into an optical signal; in some embodiments, the optical chip 900 may receive external optical signals, demodulate the optical signals into electrical signals, and output the demodulated electrical signals to the host computer through the circuit board 300.

[0058] In some embodiments, the optical chip 900 can modulate 8 optical signals without data signals into 32 optical signals, or demodulate the received 32 optical signals into 32 electrical signals.

[0059] In some embodiments, the optical chip 900 can modulate four optical signals without data signals into 16 optical signals, or demodulate the received 16 optical signals into 16 electrical signals.

[0060] In some embodiments, the optical module 200 may include one optical chip 900; in some embodiments, the optical module 200 may include two optical chips 900.

[0061] In some embodiments, a wire bonding process is used to place the back side of the optical chip 900 facing the circuit board 300 and the front side of the optical chip 900 facing away from the circuit board 300. The pads on the front side of the optical chip 900 are wire bonded to the pads on the upper surface of the circuit board 300 so that the optical chip 900 is electrically connected to the circuit board 300.

[0062] In some embodiments, a flip chip process is used, with the front side of the optical chip 900 facing the circuit board 300 and the back side of the optical chip 900 facing away from the circuit board 300. The pads on the front side of the optical chip 900 are electrically connected to the solder balls, and the solder balls are soldered to the pads on the upper surface of the circuit board 300, so that the optical chip 900 is electrically connected to the circuit board 300.

[0063] In some embodiments, the optical module 200 may include an optical fiber connector 700. One end of the optical fiber connector 700 may be optically coupled to an optical chip 900, enabling light transmission between the optical chip 900 and the optical fiber connector 700. The other end of the optical fiber connector 700 may be connected to an optical fiber ribbon 710, allowing light transmission between the optical fiber ferrule array 800 and the optical fiber connector 700 via the optical fiber ribbon 710. In some embodiments, the optical module 200 may include one optical chip and one optical fiber connector 700, with one optical chip 900 coupled to one optical fiber connector 700. In some embodiments, the optical module 200 may include two optical chips and two optical fiber connectors 700, with one optical chip 900 coupled to one optical fiber connector 700. In some embodiments, the optical module 200 may include one optical chip and two optical fiber connectors 700, with one optical chip 900 coupled to two optical fiber connectors 700 respectively.

[0064] In some embodiments, the fiber optic ferrule array 800 may include a second fiber optic ferrule 820. The second fiber optic ferrule 820 may be connected to a second external fiber optic cable so that the second fiber optic ferrule 820 can transmit optical signals to the outside of the optical module 200.

[0065] In some embodiments, the fiber optic ferrule array 800 may include a second fiber optic ferrule 820 and a first fiber optic ferrule 810. The first fiber optic ferrule 810 may be connected to an external light source via a first external optical fiber, so that the first fiber optic ferrule 810 can receive light emitted by the external light source that does not carry data signals.

[0066] In some embodiments, the fiber optic ferrule array 800 includes a third fiber optic ferrule 830, or includes a second fiber optic ferrule 820 and a third fiber optic ferrule 830; or includes a second fiber optic ferrule 820, a first fiber optic ferrule 810 and a third fiber optic ferrule 830; the third fiber optic ferrule 830 can be connected to a third external fiber optic cable so that the third fiber optic ferrule 830 can receive external optical signals.

[0067] In some embodiments, the fiber optic ribbon 710 may include a first fiber optic ribbon 711, one end of which may be connected to a fiber optic connector 700, and the other end of which may be connected to a first fiber optic ferrule 810, so that a fiber optic connector 700 is connected to the first fiber optic ferrule 810, and an optical chip 900 coupled to a fiber optic connector 700 can receive light emitted by an external light source that does not carry data signals.

[0068] In some embodiments, the fiber optic strip 710 may include a first fiber optic strip 711 and a second fiber optic strip 712. One end of the first fiber optic strip 711 and one end of the second fiber optic strip 712 are respectively connected to the first fiber optic ferrule 810. The other end of the first fiber optic strip 711 is connected to one optical chip, and the other end of the second fiber optic strip 712 is connected to another optical chip. This allows light from the first fiber optic ferrule 810 that does not carry a data signal to be transmitted to two different optical chips.

[0069] In some embodiments, the fiber optic ribbon 710 may include a third fiber optic ribbon 713, or may include a first fiber optic ribbon 711 and a third fiber optic ribbon 713. One end of the third fiber optic ribbon 713 may be connected to the fiber optic connector 700, and the other end of the third fiber optic ribbon 713 may be connected to the second fiber optic ferrule 820, so that the fiber optic connector 700 is connected to the second fiber optic ferrule 820, and the optical signal emitted by the optical chip 900 can be emitted through the second fiber optic ferrule 820.

[0070] In some embodiments, the fiber optic strip 710 may include a first fiber optic strip 711, a second fiber optic strip 712, a third fiber optic strip 713, and a fifth fiber optic strip 715; the first fiber optic strip 711 transmits light without carrying a data signal to the optical chip, and the optical signal output by the optical chip is transmitted to the third fiber optic strip 713; the second fiber optic strip 712 transmits light without carrying a data signal to another optical chip, and the optical signal output by the other optical chip is transmitted to the fifth fiber optic strip 715.

[0071] In some embodiments, the fiber optic ribbon 710 may include a fourth fiber optic ribbon 714, one end of which may be connected to the fiber optic connector 700 and the other end of which may be connected to the third fiber optic ferrule 830, so that the fiber optic connector 700 is connected to the third fiber optic ferrule 830, and the optical chip 900 can receive external optical signals.

[0072] In some embodiments, the optical emitting component may include an optical chip 900. The optical chip 900 is used to modulate and demodulate optical signals. The optical chip 900 modulates received electrical signals into optical signals and demodulates received optical signals into electrical signals.

[0073] In some embodiments, the optical chip 900 can be a monolithically integrated optical chip. For example, the optical chip 900 can be a monolithically integrated silicon optical chip. Silicon material is easily etched, allowing for the integration of functional devices within the silicon optical chip, resulting in good integration. The optical chip 900 can also be a monolithically integrated thin-film lithium niobate chip. Thin-film lithium niobate exhibits a linear electro-optic effect; an applied electric field causes a linear change in its refractive index in the corresponding direction, allowing the light wave propagating in the medium to have adjustable intensity, phase, and other information. Therefore, thin-film lithium niobate can be selected as the material for the optical modulator, thereby achieving higher modulation rates, etc.

[0074] In some embodiments, the optical chip 900 can be a hybrid integrated optical chip. Exemplarily, the optical chip 900 can be a III-V group / Si hybrid integrated optical chip. In the III-V group / Si hybrid integrated optical chip, the growth material system of the optical modulator is a III-V group semiconductor material. III-V group semiconductors are direct bandgap semiconductors with a strong quantum well-confined Stark effect. By controlling the change of the applied electric field, a change in charge carriers is caused, thereby causing a change in refractive index and realizing optical signal modulation. The growth material system of the beam splitter, beam combiner, mixer, photodetector, etc., is a Si-based material. Exemplarily, the optical chip 900 can be a thin-film lithium niobate / Si hybrid integrated optical chip. Compared to the III-V group / Si hybrid integrated optical chip, the optical modulator in the thin-film lithium niobate / Si hybrid integrated optical chip is a thin-film lithium niobate-based optical modulator.

[0075] Figure 5a For the local optical path of a first type of optical module according to some embodiments Figure 1 . Figure 5b This is a partial optical path diagram of a first type of optical module according to some embodiments, as shown in Figure 2. Figure 5a and Figure 5b As shown, in some embodiments, the circuit board 300 is located within the enclosure of the optical module. The enclosure has an optical interface and an electrical interface. The optical interface connects to an external optical fiber, and the electrical interface is electrically connected to a host computer. For example, the optical interface is located at the right end of the enclosure, and the electrical interface is located at the left end of the enclosure.

[0076] In some embodiments, the optical chip 900 is used for modulating and demodulating optical signals. The optical chip 900 may include an optical port 910. The optical port 910 is optically coupled to the outside of the optical chip 900. The optical port 910 is located on the right edge of the optical chip 900, and the various input and output optical ports included in the optical port 910 are disposed along the right edge of the optical chip 900. The optical port 910 and the optical interface are located on the same side, which facilitates optical coupling between the optical port 910 and the optical interface.

[0077] In some embodiments, the optical chip 900 may include a demodulation region 970. The demodulation region 970 receives light to be demodulated coupled into the optical chip along the optical port 910 and demodulates the light to generate an electrical signal. The demodulation region 970 is located at the edge of the optical chip 900 opposite to the optical port 910. For example, the optical port 910 is located at the right edge of the optical chip, and the demodulation region 970 is located at the left edge of the optical chip. The fact that the demodulation region 970 is entirely located along the left edge of the optical chip 900 facilitates the external transmission of the demodulated electrical signal generated by the demodulation region 970.

[0078] In some embodiments, the optical chip 900 may include a modulation region 920. The modulation region 920 receives a light source to be modulated coupled to the interior of the optical chip along the optical port 910, and modulates the light source according to an electrical signal. The resulting optical signal is output to the outside of the optical chip 900 along the optical port 910. Since the modulation region 920 is located between the optical port 910 and the demodulation region 970, it is close to both the optical and electrical interfaces. This facilitates the modulation region 920 receiving the light source to be modulated sequentially coupled along the optical interface and the optical port 910, and also facilitates its receiving of electrical signals transmitted from the electrical interface for modulating the light source according to the electrical signals. The resulting optical signal is output sequentially along the optical port 910 and the optical interface along the optical chip 900. Simultaneously, this facilitates electrical connection between the modulation region 920 and peripheral chips of the optical chip.

[0079] In some embodiments, the optical signal input at the optical port 910 is coupled to the demodulation region 970 above or below the modulation region 920 to demodulate the optical signal and generate an electrical signal. For example, the optical signal input along the input optical port array 913 is coupled to the demodulation region 970 above the modulation region 920.

[0080] In some embodiments, the optical port 910 may include a light source input optical port array 911. One end of the light source input optical port array 911 faces the light source that provides the light to be modulated to the optical chip 900, and the other end faces the interior of the optical chip 900 and is connected to the modulation region 920, so as to introduce the light to be modulated into the modulation region 920 for modulation.

[0081] In some embodiments, the optical port 910 may include an output optical port array 912. The output optical port array 912 includes output optical ports for multiple optical signals. One end of the output optical port array 912 faces the interior of the optical chip 900 and is connected to the modulation region 920 to receive the optical signals modulated by the optical chip 900. The other end of the output optical port array 912 faces the exterior of the optical chip 900 to output the modulated multiple optical signals to the exterior of the optical chip 900.

[0082] In some embodiments, the optical port 910 may include an input optical port array 913. The input optical port array 913 includes input optical ports for multiple optical signals. One end of the input optical port array 913 faces the outside of the optical chip 900, and the other end faces the inside of the optical chip 900 and is connected to the demodulation region 970, so as to introduce external optical signals into the demodulation region 970 for demodulation.

[0083] In some embodiments, the optical module 200 may include a first driver chip 310 and a second driver chip 320. The first driver chip 310 and the second driver chip 320 may be located on different sides of the optical chip 900, such that the first driver chip 310 and the second driver chip 320 are arranged opposite to each other. For example, the first driver chip 310 is located on the lower side of the optical chip 900, and the second driver chip 320 is located on the upper side of the optical chip 900, as shown below. Figure 5a and Figure 5b As shown.

[0084] In some embodiments, the first driver chip 310 and the second driver chip 320 may be located on the same side of the optical chip 900. For example, the first driver chip 310 and the second driver chip 320 are located on the upper side of the optical chip 900.

[0085] In some embodiments, the modulation region 920 includes a multi-channel optical modulator. Among adjacent optical modulators in the modulation region 920, one optical modulator is electrically connected to the first driver chip 310 to modulate according to the drive signal output by the first driver chip 310; the other optical modulator is electrically connected to the second driver chip 320 to modulate according to the drive signal output by the second driver chip 320.

[0086] In some embodiments, the modulation region 920 may include a first optical modulator array 920a. The first optical modulator array 920a includes a first optical modulator 921. The first optical modulator 921 may be electrically connected to the first driver chip 310. The optical modulators in the same row as the first optical modulator 921 constitute the first optical modulator array 920a.

[0087] In some embodiments, the modulation region 920 may include a second optical modulator array 920b. The second optical modulator array 920b includes a second optical modulator 924. The second optical modulator 924 may be electrically connected to the second driver chip 320. The optical modulators in the same row as the second optical modulator 924 constitute the second optical modulator array 920b. The second optical modulator 924 may be located to one side of the first optical modulator 921, so that the second optical modulator 924 and the first optical modulator 921 can be arranged adjacent to each other. For example, the second optical modulator 924 is located to the right of the first optical modulator 921.

[0088] In some embodiments, the first optical modulator 921 includes a first modulation waveguide 922. The first modulation waveguide 922 is arranged vertically. The surface of the first optical modulator 921 includes a first modulation electrode region 923. The first modulation electrode region 923 is arranged laterally. The first modulation electrode region 923 is connected to the first modulation waveguide 922. The first modulation electrode region 923 is located at one edge of the optical chip 900 so that the first modulation electrode region 923 is electrically connected to the first driver chip 310.

[0089] In some embodiments, the second optical modulator 924 includes a second modulation waveguide 925. The second modulation waveguide 925 is arranged vertically. The surface of the second optical modulator 924 includes a second modulation electrode region 926. The second modulation electrode region 926 is arranged laterally. The second modulation electrode region 926 is connected to the second modulation waveguide 925. The second modulation electrode region 926 is located at one edge of the optical chip 900 so that the second modulation electrode region 926 is electrically connected to the second driver chip 320.

[0090] like Figure 5a and Figure 5b As shown, in some embodiments, the first modulation electrode region 923 and the second modulation electrode region 926 are located at opposite edges of the optical chip 900. For example, the first modulation electrode region 923 is located at the lower edge of the optical chip 900, and the second modulation electrode region 926 is located at the upper edge of the optical chip.

[0091] The first modulation electrode region 923 and the second modulation electrode region 926 are located at opposite edges of the optical chip 900, and the extension directions of the first modulation waveguide 922 and the second modulation waveguide 925 are opposite. For example, the first modulation electrode region 923 is located at the lower edge of the optical chip 900, the second modulation electrode region 926 is located at the upper edge of the optical chip, the first modulation waveguide 922 extends upward, and the second modulation waveguide 925 extends downward.

[0092] In some embodiments, the first modulation waveguide 922 extends upward and its end extends beyond the central axis of the optical chip 900; the second modulation waveguide 925 extends downward and its end extends beyond the central axis of the optical chip 900, so that the first modulation waveguide 922 and the second modulation waveguide 925 overlap in the vertical direction of the optical chip 900.

[0093] In some embodiments, the width of the optical chip 900 occupied by the first optical modulator 921 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900, and the width of the optical chip 900 occupied by the second optical modulator 924 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900, such that the first optical modulator 921 and the second optical modulator 924 overlap in the vertical direction of the optical chip 900.

[0094] In some embodiments, the length of the first modulation waveguide 922 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900, so that the width of the optical chip 900 occupied by the first optical modulator 921 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900.

[0095] In some embodiments, the length of the second modulation waveguide 925 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900, so that the width of the optical chip 900 occupied by the second optical modulator 924 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900.

[0096] In some embodiments, the first modulation electrode region 923 and the second modulation electrode region 926 are located at the same edge of the optical chip 900. For example, both the first modulation electrode region 923 and the second modulation electrode region 926 are disposed along the upper edge of the optical chip 900.

[0097] The first modulation electrode region 923 and the second modulation electrode region 926 are located on the same edge of the optical chip 900, and the extension direction of the first modulation waveguide 922 is the same as that of the second modulation waveguide 925. For example, the first modulation electrode region 923 and the second modulation electrode region 926 are located on the upper edge of the optical chip 900, and the first modulation waveguide 922 and the second modulation waveguide 925 extend downward.

[0098] In some embodiments, both the first modulation waveguide 922 and the second modulation waveguide 925 extend downwards, with their ends extending beyond the central axis of the optical chip 900, so that the first modulation waveguide 922 and the second modulation waveguide 925 overlap in the vertical direction of the optical chip 900.

[0099] In some embodiments, the width of the optical chip 900 occupied by the first optical modulator 921 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900, and the width of the optical chip 900 occupied by the second optical modulator 924 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900, such that the first optical modulator 921 and the second optical modulator 924 overlap in the vertical direction of the optical chip 900.

[0100] In some embodiments, the length of the first modulation waveguide 922 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900, so that the width of the optical chip 900 occupied by the first optical modulator 921 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900.

[0101] In some embodiments, the length of the second modulation waveguide 925 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900, so that the width of the optical chip 900 occupied by the second optical modulator 924 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900.

[0102] In some embodiments, the surfaces of the first modulation electrode region 923 and the second modulation electrode region 926 are soldered downwards to the surface of the circuit board 300, thereby upside down mounting the active surface of the optical chip 900 onto the surface of the circuit board 300 to achieve electrical connection between the two, while avoiding the parasitic effects introduced by gold wire bonding. Solder joints are used for conductive interconnection and can be solder balls or solder pillars. Solder balls are spheres composed of solder, and solder pillars include copper pillars with a layer of solder covering the top of the copper pillar.

[0103] In some embodiments, the first modulation electrode region 923 sequentially includes a first ground portion, a first differential solder joint portion, a second differential solder joint portion, and a second ground portion. One end of the first differential solder joint portion is electrically connected to the first output terminal of the first driver chip 310, and the other end is electrically connected to the first optical modulator 921, so as to transmit the positive differential drive signal output from the first output terminal to the first optical modulator 921. One end of the second differential solder joint portion is electrically connected to the second output terminal of the first driver chip 310, and the other end is electrically connected to the first optical modulator 921, so as to transmit the negative differential drive signal output from the second output terminal to the first optical modulator 921.

[0104] In some embodiments, a positive differential drive signal and a negative differential drive signal are respectively loaded onto the two modulation arms of the first optical modulator 921. Under the drive of the positive differential drive signal and the negative differential drive signal, the first optical modulator 921 modulates the light to be modulated.

[0105] In some embodiments, a first transimpedance amplifier chip array 330 is provided on one side of the optical chip 900, and a second transimpedance amplifier chip array 340 and a third transimpedance amplifier chip array 350 are respectively provided on the two sides adjacent to this side. The second transimpedance amplifier chip array 340 and the third transimpedance amplifier chip array 350 are arranged opposite to each other. For example, the first transimpedance amplifier chip array 330 is provided on the left side of the optical chip 900, the second transimpedance amplifier chip array 340 is provided on the upper side adjacent to the first transimpedance amplifier chip array 330, and the third transimpedance amplifier chip array 350 is provided on the lower side adjacent to the first transimpedance amplifier chip array 330.

[0106] In some embodiments, the demodulation region 970 may include a first optical demodulator array 930. The first optical demodulator array 930 is disposed adjacent to the first transimpedance amplifier chip array 330, allowing them to be electrically connected via traces on the surface of the circuit board 300, transmitting the demodulated electrical signal to the first transimpedance amplifier chip array 330 for amplification. The first optical demodulator array 930 is disposed along one edge of the optical chip 900. The first optical demodulator array 930 is located opposite the optical port 910. The first optical demodulator array 930 includes multiple optical demodulators, which can be photodetectors, performing photoelectric conversion to achieve optical signal demodulation. Exemplarily, the optical port 910 is disposed along the right edge of the optical chip 900, and the first optical demodulator array 930 is disposed along the left edge of the optical chip 900.

[0107] In some embodiments, the demodulation region 970 may include a second optical demodulator array 940. The second optical demodulator array 940 is disposed adjacent to the second transimpedance amplifier chip array 340, allowing them to be electrically connected via traces on the surface of the circuit board 300, transmitting the demodulated electrical signal to the second transimpedance amplifier chip array 340 for amplification. The second optical demodulator array 940 is located on an adjacent edge side of the first optical demodulator array 930. The second optical demodulator array 940 includes multiple optical demodulators, which can be photodetectors, performing photoelectric conversion to achieve optical signal demodulation. For example, if the second optical demodulator array 940 is disposed along the upper edge of the optical chip 900, then the second optical demodulator array 940 is disposed adjacent to the first optical demodulator array 930.

[0108] In some embodiments, the demodulation region 970 may include a third optical demodulator array 950. The third optical demodulator array 950 is disposed adjacent to the third transimpedance amplifier chip array 350, allowing them to be electrically connected via traces on the surface of the circuit board 300, transmitting the demodulated electrical signal to the third transimpedance amplifier chip array 350 for amplification. The third optical demodulator array 950 is located on another adjacent edge side of the first optical demodulator array 930. The third optical demodulator array 950 includes multiple optical demodulators, which can be photodetectors, performing photoelectric conversion to achieve optical signal demodulation. The third optical demodulator array 950 is disposed opposite to the second optical demodulator array 940. For example, if the third optical demodulator array 950 is disposed along the lower edge of the optical chip 900, then the third optical demodulator array 950 is disposed adjacent to the first optical demodulator array 930, and the third optical demodulator array 950 is disposed opposite to the second optical demodulator array 940.

[0109] The first optical demodulator array 930 is arranged adjacent to the first transimpedance amplifier chip array 330, the second optical demodulator array 940 is arranged adjacent to the second transimpedance amplifier chip array 340, and the third optical demodulator array 950 is arranged adjacent to the third transimpedance amplifier chip array 350. This arrangement ensures that the electrical connection distance between each optical demodulator in the first optical demodulator array 930, the second optical demodulator array 940, and the third optical demodulator array 950 and the corresponding transimpedance amplifier chip is short and consistent, thereby ensuring consistent optical performance of each channel.

[0110] Taking the demodulation of 16-channel optical signals by optical chip 900 as an example, the first transimpedance amplifier chip array 330 integrates 8 transimpedance amplifier chips, the second transimpedance amplifier chip array 340 integrates 4 transimpedance amplifier chips, and the third transimpedance amplifier chip array 350 integrates 4 transimpedance amplifier chips. Correspondingly, the first optical demodulator array 930 includes 8 optical demodulators, the second optical demodulator array 940 includes 4 optical demodulators, and the third optical demodulator array 950 includes 4 optical demodulators.

[0111] In some embodiments, each of the optical demodulators in the first optical demodulator array 930, the second optical demodulator array 940, and the third optical demodulator array 950 has its own demodulation electrode region on its surface. The surface with the demodulation electrode region is soldered downwards to the surface of the circuit board 300, and the active surface of the optical chip 900 is upside down mounted on the surface of the circuit board 300 to achieve electrical connection between the two, while avoiding the parasitic effects introduced by gold wire bonding.

[0112] In some embodiments, the demodulation electrode regions on the surfaces of the first optical demodulator array 930, the second optical demodulator array 940, and the third optical demodulator array 950 may be arranged in the same manner.

[0113] Taking a first optical demodulator array 930, comprising a first optical demodulator 931 and a second optical demodulator 932, with the first optical demodulator 931 having a third demodulation electrode region on its surface and the second optical demodulator 932 having a fourth demodulation electrode region on its surface, as an example, the first optical demodulator array 930 is described. The third demodulation electrode region may include a first cathode portion and a first anode portion, and the fourth demodulation electrode region may include a second cathode portion and a second anode portion. The first cathode portion and the first anode portion are electrically connected to the PN junction region of the first optical demodulator 931, respectively, so that the electrical signal converted from the optical signal is output to the circuit board 300 through the first cathode portion and the first anode portion. The second cathode portion and the second anode portion are also electrically connected to the PN junction region of the second optical demodulator 932, respectively, so that the converted electrical signal is output.

[0114] Taking a first transimpedance amplifier chip array 330, which includes a first transimpedance amplifier chip and a second transimpedance amplifier chip, as an example, the first transimpedance amplifier chip array 330 is described below. The first transimpedance amplifier chip may include a first negative terminal connection portion and a first positive terminal connection portion, wherein the first negative terminal connection portion is electrically connected to a first cathode portion, and the first positive terminal connection portion is electrically connected to a first anode portion. The second transimpedance amplifier chip may include a second negative terminal connection portion and a second positive terminal connection portion, wherein the second negative terminal connection portion is electrically connected to a second cathode portion, and the second positive terminal connection portion is electrically connected to a second anode portion.

[0115] In some embodiments, the spacing between the second positive electrode connection portion and the first positive electrode connection portion is 0.8 to 1.2 times the spacing between the first anode portion and the second anode portion, to ensure that the traces connecting the first anode portion and the first positive electrode connection portion on the circuit board 300, as well as the traces connecting the second anode portion and the second positive electrode connection portion, have similar lengths and paths, thereby reducing signal delay and loss inconsistencies caused by trace differences, and further ensuring the uniformity of the performance of each channel during multi-channel optical signal demodulation.

[0116] In some embodiments, the spacing between the second positive electrode connection portion and the first positive electrode connection portion is equal to the spacing between the first anode portion and the second anode portion, so that the spacing between the first anode portion and the second anode portion and the spacing between the second positive electrode connection portion and the first positive electrode connection portion are perfectly matched. This can maximize the consistency of the connection traces, effectively avoid trace length differences and path deviations caused by spacing mismatch, and further improve the uniformity and stability of the performance of each channel during multi-channel optical signal demodulation.

[0117] In some embodiments, the second optical demodulator array 940 may include a third optical demodulator 941 and a fourth optical demodulator 942. The third optical demodulator 941 includes a fifth demodulation electrode region, which includes a fifth cathode portion and a third anode portion. The fourth optical demodulator 942 includes a sixth demodulation electrode region, which includes a sixth cathode portion and a fourth anode portion.

[0118] In some embodiments, the fifth cathode portion and the third anode portion are arranged at the upper edge of the optical chip, and the sixth cathode portion and the fourth anode portion are arranged at the upper edge of the optical chip, such that the optical demodulator electrodes of the second optical demodulator array are arranged in an orderly manner along the upper edge of the optical chip.

[0119] In some embodiments, the fifth cathode portion, the third anode portion, the sixth cathode portion, and the fourth anode portion are arranged in the same way as the first cathode portion, the first anode portion, the second cathode portion, and the second anode portion, so as to ensure the uniformity of the electrode area layout in different optical demodulator arrays, facilitate the design and matching of corresponding traces on the circuit board 300, and reduce wiring complexity.

[0120] In some embodiments, the spacing between the first anode portion and the second anode portion is equal to the spacing between the third anode portion and the fourth anode portion. By setting the spacing between different anode portions to a uniform standard, the layout can be regularized and modularized during the layout design stage of the optical chip.

[0121] In some embodiments, the third optical demodulator array 950 includes a fifth optical demodulator 951 and a sixth optical demodulator 952. The fifth optical demodulator 951 includes a seventh demodulation electrode region, which includes a seventh cathode portion and a fifth anode portion. The sixth optical demodulator 952 includes an eighth demodulation electrode region, which includes an eighth cathode portion and a sixth anode portion.

[0122] In some embodiments, the seventh cathode portion and the fifth anode portion are arranged at the lower edge of the optical chip, and the eighth cathode portion and the sixth anode portion are arranged at the lower edge of the optical chip, such that the optical demodulator electrodes of the third optical demodulator array are arranged in an orderly manner along the lower edge of the optical chip.

[0123] In some embodiments, the arrangement of the seventh cathode portion, the fifth anode portion, the eighth cathode portion, and the sixth anode portion is the same as the arrangement of the first cathode portion, the first anode portion, the second cathode portion, and the second anode portion, so as to ensure the uniformity of the electrode area layout in different optical demodulator arrays, facilitate the design and matching of corresponding traces on the circuit board 300, and reduce wiring complexity.

[0124] In some embodiments, the spacing between the first anode portion and the second anode portion is equal to the spacing between the fifth anode portion and the sixth anode portion. By setting the spacing between different anode portions to a uniform standard, the layout can be standardized and modularized during the layout design stage of the optical chip.

[0125] Figure 5c For the local optical path of a first type of optical module provided according to some embodiments Figure 3 . Figure 5d For the local optical path of a first type of optical module provided according to some embodiments Figure 4 .like Figure 5a , Figure 5b , Figure 5c and Figure 5d As shown, the first modulation electrode region 923 is located at the lower edge of the optical chip 900, the first modulation waveguide 922 is located above the first modulation electrode region 923, the second modulation electrode region 926 is located at the upper edge of the optical chip 900, and the second modulation waveguide 925 is located below the second modulation electrode region 926.

[0126] The input end of the modulation waveguide is close to the modulation electrode region, and the output end of the modulation waveguide is far away from the modulation electrode region. Therefore, the input end of the first modulation waveguide 922 is located at the lower edge of the optical chip 900, the input end of the second modulation waveguide 925 is located at the upper edge of the optical chip 900, and the output ends of the first modulation waveguide 922 and the second modulation waveguide 925 are both located in the middle of the optical chip 900.

[0127] like Figure 5a , Figure 5b , Figure 5c and Figure 5d As shown, the first modulation electrode region 923 is located at the lower edge of the optical chip 900, the second modulation electrode region 926 is located at the upper edge of the optical chip 900, the first modulation waveguide 922 extends upward and its end exceeds the central axis of the optical chip 900, and the second modulation waveguide 925 extends downward and its end exceeds the central axis of the optical chip 900, so that the second modulation waveguide 925 and the first modulation waveguide 922 overlap in the vertical direction of the optical chip 900.

[0128] like Figure 5a , Figure 5b , Figure 5c and Figure 5d As shown, the width of the first optical modulator 921 and the second optical modulator 924 on the optical chip 900 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900, so that the second modulation waveguide 925 overlaps with the first modulation waveguide 922 in the vertical direction of the optical chip 900.

[0129] like Figure 5a , Figure 5b , Figure 5c and Figure 5d As shown, the length of the first modulation waveguide 922 and the length of the second modulation waveguide 925 are both greater than half the width of the optical chip 900 and less than the width of the optical chip 900, so that the width of the optical chip 900 occupied by the first optical modulator 921 and the second optical modulator 924 is both greater than half the width of the optical chip 900 and less than the width of the optical chip 900.

[0130] like Figure 5a , Figure 5b , Figure 5c and Figure 5d As shown, the second modulation waveguide 925 is located on one side of the first modulation waveguide 922, and the second modulation waveguide 925 and the first modulation waveguide 922 overlap in the vertical direction of the optical chip 900. For example, the second modulation waveguide 925 is located to the right of the first modulation waveguide 922.

[0131] The first modulation electrode region 923 is located at the lower edge of the optical chip 900, the first modulation waveguide 922 is located above the first modulation electrode region 923, the second modulation electrode region 926 is located at the upper edge of the optical chip 900, the second modulation waveguide 925 is located below the second modulation electrode region 926, and the second modulation waveguide 925 is located to the right of the first modulation waveguide 922. The second modulation waveguide 925 and the first modulation waveguide 922 overlap in the vertical direction of the optical chip 900, reducing the horizontal dimension of the optical chip and thus improving the integration density of the optical chip.

[0132] Without considering the demodulation region 970, the first modulation electrode region 923 and the second modulation electrode region 926 are located at different edges of the optical chip 900, that is, the first modulation electrode region 923 and the second modulation electrode region 926 are arranged opposite to each other, which can reduce the length of the optical chip 900 and thus reduce the length of the optical module 200.

[0133] like Figure 5a , Figure 5b , Figure 5c and Figure 5d As shown, the first driver chip 310 is located on the lower side of the optical chip 900, and the second driver chip 320 is located on the upper side of the optical chip 900.

[0134] The output terminals of the first modulation waveguide 922 and the second modulation waveguide 925 are both located in the middle of the optical chip 900. In some embodiments, the output optical port array 912 is located in the middle of the optical port end 910, that is, the optical signal is emitted from the middle of the optical port end 910, so as to reduce the transmission path between the output terminal of the optical modulator and the output optical port array 912 and reduce transmission loss.

[0135] The output optical port array 912 is connected to the output terminals of the first optical modulator array 920a and the second optical modulator array 920b, so that the output optical port array 912 can receive the optical signals output from the output terminals of the first optical modulator array 920a and the second optical modulator array 920b. For example, the output optical port array 912 may include a first output optical port 9121 and a second output optical port 9122, with the first output optical port 9121 connected to the output terminal of the first optical modulator 921 and the second output optical port 9122 connected to the output terminal of the second optical modulator 924.

[0136] The demodulation region 970 is located to the left of the modulation region 920, and the optical port 910 is located to the right of the modulation region 920, as shown below. Figure 5b , Figure 5c and Figure 5dAs shown, in some embodiments, the input optical port array 913 is located at the upper or lower edge of the optical port end 910, that is, the optical signal to be demodulated enters from the upper or lower edge of the optical port end 910. This allows the externally input optical signal (i.e., the optical signal to be demodulated) to be efficiently coupled into the optical chip from the upper or lower edge side, which helps to shorten the transmission path of the optical signal inside the chip and reduce transmission loss. For example, the input optical port array 913 is located at the upper edge of the optical port end 910.

[0137] In some embodiments, the input optical port array 913 may be located at the upper and lower edges of the optical port end 910, that is, the upper and lower edges of the optical port end 910 receive demodulated light.

[0138] The upper and / or lower edges of the optical port 910 can receive the light to be demodulated, and the middle of the optical port 910 can emit an optical signal. In some embodiments, the remaining area of ​​the optical port 910 can receive the light to be modulated, thereby realizing bidirectional transmission and processing of the optical signal.

[0139] The light source input optical port array 911 is connected to the input terminals of the first optical modulator array 920a and the second optical modulator array 920b, so that the input terminals of the first optical modulator array 920a and the second optical modulator array 920b can receive the modulated light output from the light source input optical port array 911. For example, the light source input optical port array 911 includes a first light source input optical port 9111 and a second light source input optical port 9112. The first light source input optical port 9111 is connected to the input terminal of the second modulation waveguide 925, and the second light source input optical port 9112 is connected to the input terminal of the first modulation waveguide 922.

[0140] like Figure 5b As shown, in some embodiments, the light source input optical port array 911 and the input optical port array 913 can be located at opposite edges of the optical chip 900 to avoid optical path crossing between the light to be modulated and the light to be demodulated inside the optical chip, further reducing the possibility of optical path crosstalk. For example, the input optical port array 913 is located at the upper edge of the optical port end 910, the light source input optical port array 911 is located at the lower edge of the optical port end 910, and the output optical port array 912 is located between the input optical port array 913 and the light source input optical port array 911.

[0141] like Figure 5cAs shown, in some embodiments, the light source input optical port array 911 may include a first light source input optical port array 911a and a second light source input optical port array 911b. The first light source input optical port array 911a is arranged adjacent to the input optical port array 913, and the second light source input optical port array 911b and the input optical port array 913 are located at opposite edges of the optical chip 900. The output optical port array 912 is located between the first light source input optical port array 911a and the second light source input optical port array 911b, which can reduce the transmission path between the first light source input optical port array 911a and the input end of the second modulation waveguide 925. For example, the first light source input optical port array 911a may include a first light source input optical port 9111, and the second light source input optical port array 911b may include a second light source input optical port 9112.

[0142] like Figure 5d As shown, in some embodiments, the output optical port array 912 may include a first output optical port array 912a and a second output optical port array 912b. The first output optical port array 912a may be located between the input optical port array 913 and the first light source input optical port array 911a, and the second output optical port array 912b may be located between the first light source input optical port array 911a and the second light source input optical port array 911b. This not only shortens the transmission path between the input end of the second modulation waveguide 925 and the first light source input optical port array 911a, but also shortens the transmission path between the output end of the first modulation waveguide 922 and the first output optical port array 912a, reducing transmission loss. For example, the first output optical port array 912a may include a first output optical port 9121, and the second output optical port array 912b may include a second output optical port 9122.

[0143] Taking the optical chip 900 as an example of a 16-channel optical chip, the light source input optical port array 911 includes four light source input optical ports, one of which outputs four channels of light to be modulated, which are respectively fed into four optical modulators for signal modulation. Figure 5b As shown, the light source input optical port array 911 includes a first light source input optical port 9111. A first path of modulated light output from the first light source input optical port 9111 enters along the lower end of a first optical modulator 921. The modulated first optical signal exits along the upper end of the first optical modulator 921 and then propagates along the internal waveguide of the optical chip 900 until it reaches the first output optical port 9121 in the output optical port array 912. A second path of modulated light output from the first light source input optical port 9111 enters along the upper end of a second optical modulator 924. The modulated second optical signal exits along the lower end of the second optical modulator 924 and then propagates along the internal waveguide of the optical chip 900 until it reaches the second output optical port 9122 in the output optical port array 912.

[0144] Figure 6This is a partial optical path diagram of a second type of optical module provided according to some embodiments. For example... Figure 6 As shown, the first modulation electrode region 923 and the second modulation electrode region 926 are both located at the upper edge of the optical chip 900, the first modulation waveguide 922 is located below the first modulation electrode region 923, and the second modulation waveguide 925 is located below the second modulation electrode region 926.

[0145] With the input end of the modulation waveguide close to the modulation electrode region and the output end of the modulation waveguide far from the modulation electrode region, the input ends of the first modulation waveguide 922 and the second modulation waveguide 925 are both located at the upper edge of the optical chip 900, and the output ends of the first modulation waveguide 922 and the second modulation waveguide 925 are both located in the middle of the optical chip 900. This allows the light to be modulated to enter the first modulation waveguide 922 and the second modulation waveguide 925 through the upper edge of the optical chip 900, and the optical signal generated by the modulation of the first modulation waveguide 922 and the second modulation waveguide 925 is output from the middle of the optical chip 900.

[0146] like Figure 6 As shown, the first modulation electrode region 923 and the second modulation electrode region 926 are both located at the upper edge of the optical chip 900. The first modulation waveguide 922 and the second modulation waveguide 925 both extend downward, and their ends exceed the central axis of the optical chip 900, so that the second modulation waveguide 925 and the first modulation waveguide 922 overlap in the vertical direction of the optical chip 900.

[0147] like Figure 6 As shown, the width of the first optical modulator 921 and the second optical modulator 924 on the optical chip 900 is greater than half the width of the optical chip 900 and less than the width of the optical chip 900, so that the second modulation waveguide 925 overlaps with the first modulation waveguide 922 in the vertical direction of the optical chip 900.

[0148] like Figure 6 As shown, the length of the first modulation waveguide 922 and the length of the second modulation waveguide 925 are both greater than half the width of the optical chip 900 and less than the width of the optical chip 900, so that the width of the optical chip 900 occupied by the first optical modulator 921 and the second optical modulator 924 is both greater than half the width of the optical chip 900 and less than the width of the optical chip 900.

[0149] like Figure 6 As shown, the second modulation waveguide 925 is located on one side of the first modulation waveguide 922, and the second modulation waveguide 925 and the first modulation waveguide 922 overlap in the vertical direction of the optical chip 900. For example, the second modulation waveguide 925 is located to the left of the first modulation waveguide 922.

[0150] The first modulation electrode region 923 and the second modulation electrode region 926 are both located on the upper edge of the optical chip 900. The first modulation waveguide 922 is located below the first modulation electrode region 923, and the second modulation waveguide 925 is located below the second modulation electrode region 926. The second modulation waveguide 925 is located on one side of the first modulation waveguide 922. The second modulation waveguide 925 and the first modulation waveguide 922 overlap in the vertical direction of the optical chip 900, so that the second modulation waveguide 925 and the first modulation waveguide 922 are arranged side by side along the horizontal direction of the optical chip 900, which can effectively shorten the width of the modulation region 920 in the vertical direction of the optical chip 900.

[0151] Without considering the demodulation region 970, the first modulation electrode region 923 and the second modulation electrode region 926 are located on the same edge (upper edge or lower edge) of the optical chip 900, which can reduce the width of the optical chip 900 and thus reduce the width of the optical module 200.

[0152] like Figure 6 As shown, the first driver chip 310 and the second driver chip 320 are located on the upper side of the optical chip 900.

[0153] The input terminals of the first modulation waveguide 922 and the second modulation waveguide 925 are both located at the upper edge of the optical chip 900. In some embodiments, the light source input optical port array 911 is located at the upper edge of the optical chip 900, that is, the light source input optical port array 911 and the first modulation electrode region 923 are located at the same edge of the optical chip 900. This can reduce the transmission path between the light source input optical port array 911 and the input terminals of the first optical modulator array 920a and the second optical modulator array 920b, thereby reducing transmission loss. Similarly, the light source input optical port array 911 and the first modulation electrode region 923 are located at the lower edge of the optical chip.

[0154] The demodulation region 970 is located to the left of the modulation region 920, and the optical port 910 is located to the right of the modulation region 920. In some embodiments, the input optical port array 913 is located at the lower edge of the optical port 910, that is, the input optical port array 913 and the first modulation electrode region 923 are located at opposite edges of the optical chip 900. The lower edge of the optical port 910 receives the light to be demodulated, so that the light to be demodulated output from the input optical port array 913 can be transmitted to the demodulation region 970 along the opposite edge of the first modulation electrode region 923, avoiding spatial interference between the transmission path of the light to be demodulated and the modulation region 920, thereby reducing signal interference caused by the potential influence of the electrode region on the optical path. Similarly, the input optical port array 913 is located at the upper edge of the optical chip 900, and the first modulation electrode region 923 is located at the lower edge of the optical chip 900.

[0155] The output terminals of the first modulation waveguide 922 and the second modulation waveguide 925 are both located in the middle of the optical chip 900. In some embodiments, the output optical port array 912 is located between the light source input optical port array 911 and the input optical port array 913, which can reduce the transmission path between the output optical port array 912 and the output terminals of the first optical modulator array 920a and the second optical modulator array 920b, thereby reducing transmission loss.

[0156] Figure 7a This is a schematic diagram of a partial connection between a first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments. Figure 1 . Figure 7b This is a schematic diagram showing a partial connection between a first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments. Figure 7a and Figure 7b As shown, in some embodiments, the first optical demodulator array 930 may be a first optical demodulator array 930a. The first optical demodulator array 930a may include a first optical demodulator 931a and a second optical demodulator 932a. The surface of the first optical demodulator 931a includes a third demodulation electrode region 933a, and the surface of the second optical demodulator 932a includes a fourth demodulation electrode region 934a. The third demodulation electrode region 933a may include a first cathode portion 9331, a first anode portion 9332, and a third cathode portion 9333. The first cathode portion 9331 and the third cathode portion 9333 are located on the upper and lower sides of the first anode portion 9332. The fourth demodulation electrode region 934a may include a second cathode portion 9341, a second anode portion 9342, and a fourth cathode portion 9343. The second cathode portion 9341 and the fourth cathode portion 9343 are located on the upper and lower sides of the second anode portion 9342.

[0157] The diameters of the first cathode portion 9331, the first anode portion 9332, the third cathode portion 9333, the second cathode portion 9341, the second anode portion 9342, and the fourth cathode portion 9343 are all equal. The gaps between the first cathode portion 9331 and the first anode portion 9332, between the first anode portion 9332 and the third cathode portion 9333, between the third cathode portion 9333 and the second cathode portion 9341, between the second cathode portion 9341 and the second anode portion 9342, and between the second anode portion 9342 and the fourth cathode portion 9343 are also equal. Considering product performance, extensive experiments and tests have revealed the proportional boundary between the gap and the diameter of the first anode portion 9332; that is, the gap is 0.8-1.8 times the diameter of the first anode portion 9332. The gap is 0.8-1.8 times the diameter of the first anode 9332, which can reserve a suitable operating space for subsequent bonding processes and avoid short circuits or signal crosstalk problems during bonding due to the gap being too small.

[0158] If the first cathode portion 9331, the first anode portion 9332, the third cathode portion 9333, the second cathode portion 9341, the second anode portion 9342, and the fourth cathode portion 9343 can be located in different rows but the same column of the optical chip 900, and the third cathode portion 9333 and the second cathode portion 9341 are provided between the first anode portion 9332 and the second anode portion 9342, and the gap is 0.8-1.8 times the diameter of the first anode portion 9332, then when the distance between the first anode portion 9332 and the second anode portion 9342 is greater than or equal to 8.4 times the diameter of the first anode portion 9332, that is, when the distance between the first anode portion 9332 and the second anode portion 9342 is large, the first cathode portion 9331, the first anode portion 9332, the third cathode portion 9333, the second cathode portion 9341, the second anode portion 9342, and the fourth cathode portion 9343 can be located in different rows but the same column of the optical chip 900.

[0159] When the distance between the first anode portion 9332 and the second anode portion 9342 is less than 8.4 times the diameter of the first anode portion 9332, the first cathode portion 9331, the first anode portion 9332 and the third cathode portion 9333 cannot be located in different rows and the same column of the optical chip 900, and the second cathode portion 9341, the second anode portion 9342 and the fourth cathode portion 9343 cannot be located in different rows and the same column of the optical chip 900. It is necessary to place the first cathode portion 9331 and the third cathode portion 9333 in different rows and different columns of the optical chip 900 from the first anode portion 9332, and the second cathode portion 9341 and the fourth cathode portion 9343 in different rows and different columns of the optical chip 900 from the second anode portion 9342. Preferably, when the distance between the first anode portion 9332 and the second anode portion 9342 is less than 5.4 times the diameter of the first anode portion 9332, the first cathode portion 9331 and the third cathode portion 9333 are located in different rows and columns of the optical chip 900 from the first anode portion 9332, and the second cathode portion 9341 and the fourth cathode portion 9343 are located in different rows and columns of the optical chip 900 from the second anode portion 9342.

[0160] The distance between two adjacent anode portions is the distance between the centers of the two adjacent anode portions. For example, the distance between the first anode portion 9332 and the second anode portion 9342 is the distance between the center of the first anode portion 9332 and the center of the second anode portion 9342.

[0161] like Figure 7a and Figure 7bAs shown, the first cathode portion 9331 and the third cathode portion 9333 are located in different rows and the same column of the first anode portion 9332 in the first optical demodulator 931a, respectively. The second cathode portion 9341 and the fourth cathode portion 9343 are located in different rows and the same column of the second anode portion 9342 in the second optical demodulator 932a, respectively, so that the first cathode portion 9331, the first anode portion 9332, the third cathode portion 9333, the second cathode portion 9341, the second anode portion 9342 and the fourth cathode portion 9343 are located in different rows and the same column of the optical chip 900.

[0162] The first cathode portion 9331, the first anode portion 9332, the third cathode portion 9333, the second cathode portion 9341, the second anode portion 9342, and the fourth cathode portion 9343 are located in different rows but the same column of the optical chip 900. In some embodiments, the spacing between the first anode portion 9332 and the second anode portion 9342 can conform to a first spacing, that is, the anode portion spacing between the first optical demodulator 931a and the second optical demodulator 932a in the first optical demodulator array 930a conforms to the first spacing.

[0163] In some embodiments, the first transimpedance amplifier chip array 330 may be a first transimpedance amplifier chip array 330a. The first transimpedance amplifier chip array 330a may include a first transimpedance amplifier chip 331 and a second transimpedance amplifier chip 332. The first transimpedance amplifier chip 331 may be disposed adjacent to and electrically connected to the first optical demodulator 931a, and the second transimpedance amplifier chip 332 may be disposed adjacent to and electrically connected to the second optical demodulator 932a.

[0164] In some embodiments, the first transimpedance amplifier chip array 330 may be a first transimpedance amplifier chip array 330b. The first transimpedance amplifier chip array 330b may include a first transimpedance amplifier chip 331a and a second transimpedance amplifier chip 332a. The first transimpedance amplifier chip 331a may be disposed adjacent to and electrically connected to the first optical demodulator 931a, and the second transimpedance amplifier chip 332a may be disposed adjacent to and electrically connected to the second optical demodulator 932a.

[0165] In some embodiments, the first surfaces of both the first transimpedance amplifier chip 331 and the first transimpedance amplifier chip 331a may include a first negative electrode connection portion 3311, a first positive electrode connection portion 3312, and a third negative electrode connection portion 3313. The first negative electrode connection portion 3311 can be connected to the first cathode portion 9331 via traces on the surface of the circuit board 300, the first positive electrode connection portion 3312 can be connected to the first anode portion 9332 via traces on the surface of the circuit board 300, and the third negative electrode connection portion 3313 can be connected to the third cathode portion 9333 via traces on the surface of the circuit board 300, so that the first transimpedance amplifier chip 331 or the first transimpedance amplifier chip 331a is electrically connected to the first optical demodulator 931a. The first surfaces of both the second transimpedance amplifier chip 332 and the second transimpedance amplifier chip 332a may include a second negative electrode connection portion 3321, a second positive electrode connection portion 3322, and a fourth negative electrode connection portion 3323. The second negative electrode connection portion 3321 can be connected to the second cathode portion 9341 via traces on the surface of the circuit board 300. The second positive electrode connection portion 3322 can be connected to the second anode portion 9342 via traces on the surface of the circuit board 300. The fourth negative electrode connection portion 3323 can be connected to the fourth cathode portion 9343 via traces on the surface of the circuit board 300, so that the second transimpedance amplifier chip 332 or the second transimpedance amplifier chip 332a is electrically connected to the second optical demodulator 932a. The first negative electrode connection portion 3311 and the third negative electrode connection portion 3313 are located on the upper and lower sides of the first positive electrode connection portion 3312, and the second negative electrode connection portion 3321 and the fourth negative electrode connection portion 3323 are located on the upper and lower sides of the second positive electrode connection portion 3322.

[0166] The diameters of the first negative electrode connection 3311, the first positive electrode connection 3312, the third negative electrode connection 3313, the second negative electrode connection 3321, the second positive electrode connection 3322, and the fourth negative electrode connection 3323 are all equal. The gaps between the first negative electrode connection 3311 and the first positive electrode connection 3312, between the first positive electrode connection 3312 and the third negative electrode connection 3313, between the third negative electrode connection 3313 and the second negative electrode connection 3321, between the second negative electrode connection 3321 and the second positive electrode connection 3322, and between the second positive electrode connection 3322 and the fourth negative electrode connection 3323 are all equal. Considering product performance, extensive experiments and tests have revealed the proportional boundary between the gap and the diameter of the first anode portion 3332, i.e., this gap is 0.8-1.8 times the diameter of the first positive electrode connection 3312. The gap is 0.8-1.8 times the diameter of the first positive electrode connection 3312, which can reserve a suitable operating space for subsequent bonding processes and avoid short circuits or signal crosstalk problems during the bonding process due to the gap being too small.

[0167] If the first negative electrode connection 3311, the first positive electrode connection 3312, the third negative electrode connection 3313, the second negative electrode connection 3321, the second positive electrode connection 3322, and the fourth negative electrode connection 3323 can be located in different rows but the same column of the first transimpedance amplifier chip array 330, and the third negative electrode connection 3313 and the second negative electrode connection 3321 are provided between the first positive electrode connection 3312 and the second positive electrode connection 3322, and the gap is 0.8-1.8 times the diameter of the first positive electrode connection 3312, then when the first negative electrode connection 3311, the second positive electrode connection 3322, and the third negative electrode connection 3313 and the second negative electrode connection 3321 are provided, the gap is 0.8-1.8 times the diameter of the first positive electrode connection 3312, then when the first negative electrode connection 3311, the second positive electrode connection 3312, the third negative electrode connection 3313, the second positive electrode connection 3322, and the fourth negative electrode connection 3323 are located in different rows but the same column of the first transimpedance amplifier chip array 330, the third negative electrode connection 3313 and the second negative electrode connection 3321 are provided, and the gap is 0.8-1.8 times the diameter of the first positive electrode connection 3312, the fourth negative electrode connection 3323 is located between the first positive electrode connection 3312 and the second positive electrode connection 332 ... When the distance between the first positive electrode connection 3312 and the second positive electrode connection 3322 is greater than or equal to 8.4 times the diameter of the first positive electrode connection 3312, that is, when the distance between the first positive electrode connection 3312 and the second positive electrode connection 3322 is large, the first negative electrode connection 3311, the first positive electrode connection 3312, the third negative electrode connection 3313, the second negative electrode connection 3321, the second positive electrode connection 3322 and the fourth negative electrode connection 3323 can be located in different rows and the same column of the first transimpedance amplifier chip array 330.

[0168] The distance between two adjacent positive electrode connections is the distance between the centers of the two adjacent positive electrode connections. For example, the distance between the first positive electrode connection 3312 and the second positive electrode connection 3322 refers to the distance between the center of the first positive electrode connection 3312 and the center of the second positive electrode connection 3322.

[0169] When the distance between the first positive electrode connection 3312 and the second positive electrode connection 3322 is less than 8.4 times the diameter of the first positive electrode connection 3312, the first negative electrode connection 3311, the first positive electrode connection 3312, and the third negative electrode connection 3313 cannot be located in different rows and the same column of the first transimpedance amplifier chip array 330, and the second negative electrode connection 3321, the second positive electrode connection 3322, and the fourth negative electrode connection 3323 cannot be located in different rows and the same column of the first transimpedance amplifier chip array 330. Therefore, the first negative electrode connection 3311 and the third negative electrode connection 3313 need to be located in different rows and different columns of the first transimpedance amplifier chip array 330 from the first positive electrode connection 3312, and the second negative electrode connection 3321 and the fourth negative electrode connection 3323 need to be located in different rows and different columns of the first transimpedance amplifier chip array 330 from the second positive electrode connection 3322, respectively. Figure 7a and Figure 7bAs shown. Preferably, when the distance between the first positive electrode connection portion 3312 and the second positive electrode connection portion 3322 is less than 5.4 times the diameter of the first positive electrode connection portion 3312, the first negative electrode connection portion 3311 and the third negative electrode connection portion 3313 are located in different rows and columns of the first transimpedance amplifier chip array 330, respectively, and the second negative electrode connection portion 3321 and the fourth negative electrode connection portion 3323 are located in different rows and columns of the first transimpedance amplifier chip array 330, respectively, and the second positive electrode connection portion 3322 is located in different rows and columns of the first transimpedance amplifier chip array 330, respectively.

[0170] In some embodiments, the first negative electrode connection portion 3311 and the third negative electrode connection portion 3313 are respectively disposed at the upper and lower ends of one side of the first positive electrode connection portion 3312, so that the first negative electrode connection portion 3311, the first positive electrode connection portion 3312, and the third negative electrode connection portion 3313 form a triangle. The second negative electrode connection portion 3321 and the fourth negative electrode connection portion 3323 are respectively disposed at the upper and lower ends of one side of the second positive electrode connection portion 3322, so that the second negative electrode connection portion 3321, the second positive electrode connection portion 3322, and the fourth negative electrode connection portion 3323 form a triangle. The formation of a triangle by the first negative electrode connection portion 3311, the first positive electrode connection portion 3312, and the third negative electrode connection portion 3313, and the formation of a triangle by the second negative electrode connection portion 3321, the second positive electrode connection portion 3322, and the fourth negative electrode connection portion 3323, can effectively reduce the electrode spacing between adjacent transimpedance amplifier chips, thereby integrating more transimpedance amplifier chip channels within a limited chip area.

[0171] In some embodiments, the first negative electrode connection portion 3311, the first positive electrode connection portion 3312, and the third negative electrode connection portion 3313 are respectively arranged in different rows. The first negative electrode connection portion 3311 and the first positive electrode connection portion 3312 are staggered, and the third negative electrode connection portion 3313 and the first positive electrode connection portion 3312 are staggered. This shortens the distance between the first positive electrode connection portion 3312 and the second positive electrode connection portion 3322, while ensuring a safe distance between the first negative electrode connection portion 3311 and the first positive electrode connection portion 3312, and also ensuring a safe distance between the third negative electrode connection portion 3313 and the first positive electrode connection portion 3312.

[0172] In some embodiments, the first positive electrode connection portion 3312 and the second positive electrode connection portion 3322 are sequentially disposed in the first column of the first transimpedance amplifier chip array 330, and the first column of the first transimpedance amplifier chip array 330 is disposed adjacent to each other along the edge of the first transimpedance amplifier chip array 330. The first positive electrode connection portion 3312 and the second positive electrode connection portion 3322 may be on the same axis.

[0173] In some embodiments, the first negative electrode connection portion 3311, the third negative electrode connection portion 3313, the second negative electrode connection portion 3321 and the fourth negative electrode connection portion 3323 are sequentially arranged and located in the second column of the first transimpedance amplifier chip array 330. The second column of the first transimpedance amplifier chip array 330 is located on one side of the first column of the first transimpedance amplifier chip array 330, which can effectively avoid spatial crosstalk interference of positive and negative electrode traces and reduce the risk of signal crosstalk.

[0174] like Figure 7a As shown, in some embodiments, the first column of the first transimpedance amplifier chip array 330 is closer to the first optical chip 900 than the second column of the first transimpedance amplifier chip array 330. That is, the first positive electrode connection portion 3312 and the second positive electrode connection portion 3322 are closer to the right edge of the first transimpedance amplifier chip array 330 than the first negative electrode connection portion 3311, the third negative electrode connection portion 3313, the second negative electrode connection portion 3321 and the fourth negative electrode connection portion 3323.

[0175] like Figure 7b As shown, in some embodiments, the first column of the first transimpedance amplifier chip array 330 is further away from the first optical chip 900 relative to the second column of the first transimpedance amplifier chip array 330, that is, the first positive electrode connection portion 3312 and the second positive electrode connection portion 3322 are further away from the edge of the first transimpedance amplifier chip array 330 relative to the first negative electrode connection portion 3311, the third negative electrode connection portion 3313, the second negative electrode connection portion 3321 and the fourth negative electrode connection portion 3323.

[0176] The first cathode portion 9331, the first anode portion 9332, the third cathode portion 9333, the second cathode portion 9341, the second anode portion 9342, and the fourth cathode portion 9343 are arranged sequentially along the left edge of the optical chip 900. The first positive electrode connection portion 3312 and the second positive electrode connection portion 3322 are closer to the edge of the first transimpedance amplifier chip array 330 than the first negative electrode connection portion 3311, the third negative electrode connection portion 3313, the second negative electrode connection portion 3321, and the fourth negative electrode connection portion 3323. This can reduce the vertical distance between the first positive electrode connection portion 3312 and the first anode portion 9332, and the vertical distance between the second positive electrode portion 3332 and the second anode portion 9342. In turn, reducing the RF traces between the first transimpedance amplifier chip array 330 and the first optical demodulator array 930 can reduce parasitic parameters, thereby suppressing resonance peaks, improving phase consistency, and enhancing signal integrity.

[0177] In some embodiments, the vertical distance between the center of the first negative electrode connection 3311 and the center of the first positive electrode connection 3312 is less than the sum of the radius of the first negative electrode connection 3311 and the radius of the first positive electrode connection 3312. This shortens the vertical distance between the row where the first negative electrode connection 3311 is located and the row where the first positive electrode connection 3312 is located, thereby shortening the distance between the first positive electrode connection 3312 and the second positive electrode connection 3322, thereby reducing the length of the first transimpedance amplifier chip array 330a and the first transimpedance amplifier chip array 330b.

[0178] In some embodiments, the first negative electrode connection portion 3311 and the third negative electrode connection portion 3313 may be symmetrically distributed at the upper and lower ends of one side of the first positive electrode connection portion 3312. The distances from the first positive electrode connection portion 3312 to the first negative electrode connection portion 3311 and the third negative electrode connection portion 3313 may be equal to ensure the continuity and uniformity of the characteristic impedance in the transmission path, effectively suppressing signal reflection and ensuring signal integrity. Similarly, the second negative electrode connection portion 3321 and the fourth negative electrode connection portion 3323 are symmetrically distributed at the upper and lower ends of one side of the second positive electrode connection portion 3322.

[0179] In some embodiments, the distance from the first positive electrode connection 3312 to the first optical demodulator array 930a is equal to the distance from the second positive electrode connection 3322 to the first optical demodulator array 930a, thereby maintaining the consistency of the trace distance between each channel and the first optical demodulator array 930a, and thus ensuring the consistency of the performance of each channel.

[0180] Figure 7c This is a partial connection diagram of a second type of first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments. Figure 7d This is a partial connection diagram of a third type of first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments. Figure 7c and Figure 7d As shown, in some embodiments, the first optical demodulator array 930 may be a first optical demodulator array 930b. The first optical demodulator array 930b may include a first optical demodulator 931b and a second optical demodulator 932b. The surface of the first optical demodulator 931b includes a third demodulation electrode region 933b, and the surface of the second optical demodulator 932b includes a fourth demodulation electrode region 934b. The third demodulation electrode region 933b may include a first cathode portion 9331, a first anode portion 9332, and a third cathode portion 9333. The fourth demodulation electrode region 934b may include a second cathode portion 9341, a second anode portion 9342, and a fourth cathode portion 9343.

[0181] In some embodiments, the first optical demodulator array 930 may be a first optical demodulator array 930c, which is disposed adjacent to and electrically connected to the first transimpedance amplifier chip array 330c via surface traces on a circuit board. The first optical demodulator array 930c may include a first optical demodulator 931c and a second optical demodulator 932c. The surface of the first optical demodulator 931c includes a third demodulation electrode region 933c, and the surface of the second optical demodulator 932c includes a fourth demodulation electrode region 934c. The third demodulation electrode region 933c may include a first cathode portion 9331, a first anode portion 9332, and a third cathode portion 9333. The fourth demodulation electrode region 934c may include a second cathode portion 9341, a second anode portion 9342, and a fourth cathode portion 9343.

[0182] like Figure 7c and Figure 7d As shown, the distance between the first anode portion 9332 and the second anode portion 9342 is less than 8.4 times the diameter of the first anode portion 9332. The first cathode portion 9331 and the third cathode portion 9333 are located in different rows and columns of the optical chip 900 from the first anode portion 9332, and the second cathode portion 9341 and the fourth cathode portion 9343 are located in different rows and columns of the optical chip 900 from the second anode portion 9342, respectively. Preferably, the distance between the first anode portion 9332 and the second anode portion 9342 is less than 5.4 times the diameter of the first anode portion 9332, and the first cathode portion 9331 and the third cathode portion 9333 are located in different rows and columns of the optical chip 900 from the first anode portion 9332, respectively. The second cathode portion 9341 and the fourth cathode portion 9343 are located in different rows and columns of the optical chip 900 from the second anode portion 9342, respectively.

[0183] In some embodiments, the first cathode portion 9331 and the third cathode portion 9333 are located at the upper and lower ends of one side of the first anode portion 9332, so that the first cathode portion 9331, the first anode portion 9332, and the third cathode portion 9333 form a triangle. The second cathode portion 9341 and the fourth cathode portion 9343 are located at the upper and lower ends of one side of the second anode portion 9342, so that the second cathode portion 9341, the second anode portion 9342, and the fourth cathode portion 9343 form a triangle. The formation of the first cathode portion 9331, the first anode portion 9332, and the third cathode portion 9333, and the formation of the second cathode portion 9341, the second anode portion 9342, and the fourth cathode portion 9343 in a triangle can effectively reduce the electrode spacing between adjacent optical demodulators, thereby integrating more optical demodulator channels within a limited chip area, further improving the integration density and board utilization of the optical chip.

[0184] In some embodiments, the first cathode portion 9331, the first anode portion 9332, and the third cathode portion 9333 are respectively arranged in different rows. The first cathode portion 9331 and the first anode portion 9332 are staggered, and the first anode portion 9332 and the third cathode portion 9333 are staggered. This shortens the distance between the first anode portion 9332 and the second anode portion 9342, while ensuring a safe distance between the first cathode portion 9331 and the first anode portion 9332, and also ensuring a safe distance between the first anode portion 9332 and the third cathode portion 9333.

[0185] In some embodiments, the first anode portion 9332 and the second anode portion 9342 are sequentially disposed in the first column of the optical chip 900, and the first column of the optical chip 900 is disposed adjacent to each other along the left edge of the optical chip 900. The first anode portion 9332 and the second anode portion 9342 may be on the same axis.

[0186] In some embodiments, the first cathode portion 9331, the third cathode portion 9333, the second cathode portion 9341, and the fourth cathode portion 9343 are sequentially arranged and located in the second column of the optical chip 900. The second column of the optical chip 900 is located on one side of the first column of the optical chip 900, so that the anode portion and the cathode portion are arranged in columns to avoid the electrodes of adjacent optical demodulators from intersecting each other in the column direction, reduce interference between electrodes, and ensure the accuracy and stability of the demodulated signal.

[0187] like Figure 7c As shown, in some embodiments, the first column of the optical chip 900 is closer to the left edge of the optical chip 900 than the second column of the optical chip 900, that is, the first anode portion 9332 and the second anode portion 9342 are closer to the left edge of the optical chip 900 than the first cathode portion 9331, the third cathode portion 9333, the second cathode portion 9341 and the fourth cathode portion 9343.

[0188] like Figure 7d As shown, in some embodiments, the first column of the optical chip 900 is further away from the left edge of the optical chip 900 relative to the second column of the optical chip 900, that is, the first anode portion 9332 and the second anode portion 9342 are further away from the left edge of the optical chip 900 relative to the first cathode portion 9331, the third cathode portion 9333, the second cathode portion 9341 and the fourth cathode portion 9343.

[0189] In some embodiments, if the vertical distance between the center of the first cathode portion 9331 and the center of the first anode portion 9332 is less than the sum of the radius of the first cathode portion 9331 and the radius of the first anode portion 9332, then the vertical distance between the row containing the first cathode portion 9331 and the row containing the first anode portion 9332 is shortened, thereby shortening the distance between the first anode portion 9332 and the second anode portion 9342, so that the distance between the first anode portion 9332 and the second anode portion 9342 is the second distance.

[0190] In some embodiments, the first cathode portion 9331 and the third cathode portion 9333 may be symmetrically distributed at the upper and lower ends of one side of the first anode portion 9332. The distances from the first anode portion 9332 to the first cathode portion 9331 and the third cathode portion 9333 may be equal, thereby ensuring the continuity and uniformity of the characteristic impedance in the transmission path, effectively suppressing signal reflection, and ensuring signal integrity. Similarly, the second cathode portion 9341 and the fourth cathode portion 9343 may be symmetrically distributed at the upper and lower ends of one side of the second anode portion 9342.

[0191] In some embodiments, the distance from the first anode portion 9332 to the first transimpedance amplifier chip array 330c is equal to the distance from the second anode portion 9342 to the first transimpedance amplifier chip array 330c, thereby maintaining the consistency of the trace distance between each channel and the first transimpedance amplifier chip array 330c, and thus ensuring the consistency of the performance of each channel.

[0192] like Figure 7c and Figure 7d As shown, in some embodiments, the first transimpedance amplifier chip array 330 may be a first transimpedance amplifier chip array 330c. The first transimpedance amplifier chip array 330c is disposed adjacent to the first optical demodulator array 930b, and the two are electrically connected through surface traces on a circuit board. The first transimpedance amplifier chip array 330c may include a first transimpedance amplifier chip 331b and a second transimpedance amplifier chip 332b. The first transimpedance amplifier chip 331b may include a first negative terminal connection portion 3311, a first positive terminal connection portion 3312, and a third negative terminal connection portion 3313. The second transimpedance amplifier chip 332b may include a second negative terminal connection portion 3321, a second positive terminal connection portion 3322, and a fourth negative terminal connection portion 3323. The first negative terminal connection portion 3311 and the third negative terminal connection portion 3313 are located on the upper and lower sides of the first positive terminal connection portion 3312, and the second negative terminal connection portion 3321 and the fourth negative terminal connection portion 3323 are located on the upper and lower sides of the second positive terminal connection portion 3322.

[0193] like Figure 7c and Figure 7d As shown, the first negative electrode connection 3311, the first positive electrode connection 3312, the third negative electrode connection 3313, the second negative electrode connection 3321, the second positive electrode connection 3322 and the fourth negative electrode connection 3323 can be located in different rows and the same column of the first transimpedance amplifier chip array 330.

[0194] The first negative electrode connection portion 3311, the first positive electrode connection portion 3312, the third negative electrode connection portion 3313, the second negative electrode connection portion 3321, the second positive electrode connection portion 3322, and the fourth negative electrode connection portion 3323 are arranged sequentially along the right edge of the first transimpedance amplifier chip array 330c. The first anode portion 9332 and the second anode portion 9342 are closer to the left edge of the optical chip 900 than the first cathode portion 9331, the third cathode portion 9333, the second cathode portion 9341, and the fourth cathode portion 9343. This can reduce the vertical distance between the first positive electrode connection portion 3312 and the first anode portion 9332, and the vertical distance between the second positive electrode portion 3332 and the second anode portion 9342. In turn, reducing the RF traces between the first transimpedance amplifier chip array 330 and the first optical demodulator array 930 can reduce parasitic parameters, thereby suppressing resonance peaks, improving phase consistency, and enhancing signal integrity.

[0195] Figure 7e This is a partial connection diagram of a fourth type of first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments. Figure 7e As shown, in some embodiments, the first optical demodulator array 930 may be a first optical demodulator array 930d, which may include a first optical demodulator 931d and a second optical demodulator 932d. The surface of the first optical demodulator 931d includes a third demodulation electrode region 933d, and the surface of the second optical demodulator 932d includes a fourth demodulation electrode region 934d. The third demodulation electrode region 933d may include a first cathode portion 9334 and a first anode portion 9332, and the fourth demodulation electrode region 934d may include a second cathode portion 9344 and a second anode portion 9342.

[0196] In some embodiments, the first cathode portion 9334 and the first anode portion 9332 are located in different rows but the same column of the first optical demodulator 931d, and the second cathode portion 9344 and the second anode portion 9342 are located in different rows but the same column of the second optical demodulator 932d, so that the first cathode portion 9334, the first anode portion 9332, the second cathode portion 9344 and the second anode portion 9342 are located in different rows but the same column of the optical chip 900.

[0197] The second cathode portion 9344 is located between the first anode portion 9332 and the second anode portion 9842. In some embodiments, the spacing between the first anode portion 9332 and the second anode portion 9842 can conform to a second spacing, that is, the anode portion spacing between the first optical demodulator 931d and the second optical demodulator 932d in the first optical demodulator array 930d conforms to the second spacing. This conformity of the second spacing between the anode portions of the first optical demodulator 931d and the second optical demodulator 932d in the first optical demodulator array 930d reduces the length of the first optical demodulator array 930d.

[0198] like Figure 7e As shown, in some embodiments, the first transimpedance amplifier chip array 330 may be a first transimpedance amplifier chip array 330d. The first transimpedance amplifier chip array 330d may include a first transimpedance amplifier chip 331c and a second transimpedance amplifier chip 332c. The first transimpedance amplifier chip 331c may include a first negative electrode connection portion 3314 and a first positive electrode connection portion 3312, and the second transimpedance amplifier chip 332c may include a second negative electrode connection portion 3324 and a second positive electrode connection portion 3322. The first negative electrode connection portion 3314 and the first cathode portion 9334 may be connected via surface traces on the circuit board 300, and the first positive electrode connection portion 3312 and the first anode portion 9332 may be connected via surface traces on the circuit board 300, so that the third demodulation electrode region 933d is electrically connected to the first transimpedance amplifier chip 331c. The second negative electrode connection portion 3324 and the second cathode portion 9344 can be connected by traces on the surface of the circuit board 300, and the second positive electrode connection portion 3322 and the second anode portion 9842 can be connected by traces on the surface of the circuit board 300, so that the fourth demodulation electrode region 934d is electrically connected to the second transimpedance amplifier chip 332c.

[0199] In some embodiments, the first negative electrode connection portion 3314 and the first positive electrode connection portion 3312 are located in different rows but the same column of the first transimpedance amplifier chip 331c, and the second negative electrode connection portion 3324 and the second positive electrode connection portion 3322 are located in different rows but the same column of the second transimpedance amplifier chip 332c, so that the first negative electrode connection portion 3314, the first positive electrode connection portion 3312, the second negative electrode connection portion 3324 and the second positive electrode connection portion 3322 are located in different rows but the same column of the first transimpedance amplifier chip array 330d.

[0200] The first cathode portion 9334, the first anode portion 9332, the second cathode portion 9344, and the second anode portion 9342 are located in different rows but the same column of the optical chip 900. The first negative electrode connection portion 3314, the first positive electrode connection portion 3312, the second negative electrode connection portion 3324, and the second positive electrode connection portion 3322 are located in different rows but the same column of the first transimpedance amplifier chip array 330d. This ensures that the trace lengths from the cathode and anode portions of the same optical demodulator to the corresponding connection portions of the transimpedance amplifier chip are consistent, reducing the signal delay inconsistency caused by differences in trace lengths, thereby improving the synchronization and stability of signal transmission.

[0201] The first optical demodulator array is disposed at one edge of the optical chip 900. The second and third optical demodulator arrays are both disposed adjacent to the first optical demodulator array and are disposed opposite to each other. This can disperse the optical demodulators along the left-right and up-down directions, reduce the width of the optical chip 900 occupied by the optical demodulators, and thus reduce the width of the optical chip 900.

[0202] Figure 8a This is a partial schematic diagram of a third type of optical module provided according to some embodiments. Figure 8b This is a partial schematic diagram of a fourth optical module according to some embodiments. Figure 8a and Figure 8b As shown, in some embodiments, a first optical demodulator array is provided on one edge of the optical chip 900, and a fourth optical demodulator array 980 is provided on the other edge of the optical chip 900. The fourth optical demodulator array 980 includes a plurality of optical demodulators. For example, the fourth optical demodulator array 980 includes eight optical demodulators. Taking the first optical demodulator array 930d as an example, this optical module is described.

[0203] In some embodiments, the structures of the first optical demodulator array 930d and the fourth optical demodulator array 980 may be different.

[0204] In some embodiments, the first optical demodulator array 930d and the fourth optical demodulator array 980 may have the same structure to realize the modular design of the optical chip demodulation region, which facilitates production and performance debugging.

[0205] In some embodiments, one edge of the optical chip 900 is disposed adjacent to another edge of the optical chip 900, such that the first optical demodulator array 930d and the fourth optical demodulator array 980 are disposed adjacent to each other. For example, the left edge of the optical chip 900 has the first optical demodulator array 930d, and the upper edge (or lower edge) of the optical chip 900 has the fourth optical demodulator array 980, as shown below. Figure 8a and Figure 8b As shown.

[0206] In some embodiments, one edge of the optical chip 900 is disposed opposite to another edge of the optical chip 900, such that the first optical demodulator array 930d is disposed opposite to the fourth optical demodulator array 980. For example, the lower edge of the optical chip 900 is provided with the first optical demodulator array 930d, and the upper edge of the optical chip 900 is provided with the fourth optical demodulator array 980.

[0207] In some embodiments, a first transimpedance amplifier chip array 330d is provided on one side of the optical chip 900, and a fourth transimpedance amplifier chip array 370 is provided on the other side of the optical chip 900 adjacent to or opposite to the first transimpedance amplifier chip array 330d, so that the first optical demodulator array 930d is correspondingly arranged with the first transimpedance amplifier chip array 330d, and the fourth optical demodulator array 980 is correspondingly arranged with the fourth transimpedance amplifier chip array 370. For example, the first transimpedance amplifier chip array 330d is provided on the left side of the optical chip 900, and the fourth transimpedance amplifier chip array 370 is provided on the upper side adjacent to the first transimpedance amplifier chip array 330d.

[0208] The first transimpedance amplifier chip array 330d is disposed adjacent to and electrically connected to the first optical demodulator array 930d, so that the first transimpedance amplifier chip array 330d can receive the electrical signal emitted by the first optical demodulator array 930d. The fourth transimpedance amplifier chip array 370 is disposed adjacent to and electrically connected to the fourth optical demodulator array 980, so that the fourth transimpedance amplifier chip array 370 can receive the electrical signal emitted by the fourth optical demodulator array 980.

[0209] In some embodiments, the structures of the first transimpedance amplifier chip array 330d and the fourth transimpedance amplifier chip array 370 may be different.

[0210] In some embodiments, the first transimpedance amplifier chip array 330d and the fourth transimpedance amplifier chip array 370 may have the same structure to achieve standardized design and reduce the complexity of production and assembly.

[0211] Ignoring the optical modulation region 920, the optical chip 900 has a first optical demodulator array 930d on one edge and a fourth optical demodulator array 980 on the other edge, which can reduce the width of the optical chip 900.

[0212] Figure 9a This is a partial schematic diagram of a fifth optical module provided according to some embodiments. Figure 9b This is a partial schematic diagram of a sixth optical module according to some embodiments. Figure 9a and Figure 9b As shown, in some embodiments, a first transimpedance amplifier chip array 360 is provided on one side of the optical chip 900, which integrates multiple transimpedance amplifier chips. For example, the first transimpedance amplifier chip array 360 integrates 16 transimpedance amplifier chips.

[0213] In some embodiments, the demodulation region 970 may include a first optical demodulator array 960, which is disposed along the left edge of the optical chip 900. This facilitates the transmission of the electrical signal demodulated by the first optical demodulator array 960 outward along the left edge, and also facilitates the electrical connection between the first optical demodulator array 960 and the peripheral electrical chip disposed on the left side of the optical chip 900.

[0214] In some embodiments, the first optical demodulator array 960 and the first transimpedance amplifier chip array 360 are arranged adjacent to each other, which can shorten the trace distance between the first optical demodulator array 960 and the first transimpedance amplifier chip array 360.

[0215] In some embodiments, the first optical demodulator array 960 includes a plurality of optical demodulators, each electrically connected to the first transimpedance amplifier chip array 360. Each optical demodulator is sequentially arranged along the edge of the optical chip 900 to ensure consistent distance from each demodulator to the transimpedance amplifier chip. Each optical demodulator has a demodulation electrode region on its active surface. The surface with the demodulation electrode region is soldered to the surface of the circuit board 300, i.e., the active surface of the optical chip 900 is soldered downwards to the surface of the circuit board 300, thus inverting the optical chip 900 onto the surface of the circuit board 300 to avoid parasitic effects introduced by gold wire bonding. For example, the first optical demodulator array 960 includes 16 optical demodulators.

[0216] In some embodiments, the first optical demodulator array 960 may include a first optical demodulator 961 and a second optical demodulator 962, which are disposed adjacent to each other along the edge of the optical chip 900. The surface of the first optical demodulator 961 is provided with a first demodulation electrode region 963, and the surface of the second optical demodulator 962 is provided with a second demodulation electrode region 964. The first demodulation electrode region 963 and the second demodulation electrode region 964 are disposed adjacent to each other along the edge of the optical chip 900.

[0217] Taking a first optical demodulator array 960, comprising a first optical demodulator 961 and a second optical demodulator 962, with the first optical demodulator 961 having a first demodulation electrode region on its surface and the second optical demodulator 962 having a second demodulation electrode region on its surface, the first optical demodulator array 960 is described as an example. The first demodulation electrode region may include a first cathode portion and a first anode portion, and the second demodulation electrode region may include a second cathode portion, a second anode portion, and a fourth cathode portion. The first cathode portion and the first anode portion are electrically connected to the PN junction region of the first optical demodulator 961, respectively, so that the electrical signal converted from the optical signal is output to the circuit board 300 through the first cathode portion and the first anode portion. The second cathode portion and the second anode portion are also electrically connected to the PN junction region of the second optical demodulator 962, respectively, so that the converted electrical signal is output.

[0218] Taking a first transimpedance amplifier chip array 360, which includes a first transimpedance amplifier chip and a second transimpedance amplifier chip, as an example, the first transimpedance amplifier chip array 360 is described below. The first transimpedance amplifier chip may include a first negative terminal connection portion and a first positive terminal connection portion. The first negative terminal connection portion is electrically connected to a first cathode portion, and the first positive terminal connection portion is electrically connected to a first anode portion. The second transimpedance amplifier chip may include a second negative terminal connection portion and a second positive terminal connection portion. The second negative terminal connection portion is electrically connected to a second cathode portion, and the second positive terminal connection portion is electrically connected to a second anode portion.

[0219] In some embodiments, the spacing between the second positive electrode connection portion and the first positive electrode connection portion is 0.8 to 1.2 times the spacing between the first anode portion and the second anode portion, to ensure that the traces connecting the first anode portion and the first positive electrode connection portion on the circuit board 300, as well as the traces connecting the second anode portion and the second positive electrode connection portion, have similar lengths and paths, thereby reducing signal delay and loss inconsistencies caused by trace differences, and further ensuring the uniformity of the performance of each channel during multi-channel optical signal demodulation.

[0220] In some embodiments, the spacing between the second positive electrode connection portion and the first positive electrode connection portion is equal to the spacing between the first anode portion and the second anode portion, so that the spacing between the first anode portion and the second anode portion and the spacing between the second positive electrode connection portion and the first positive electrode connection portion are perfectly matched. This can maximize the consistency of the connection traces, effectively avoid trace length differences and path deviations caused by spacing mismatch, and further improve the uniformity and stability of the performance of each channel during multi-channel optical signal demodulation.

[0221] Figure 10 This is a schematic diagram of the internal electrical connections of a first optical demodulator according to some embodiments. Figure 10 As shown, in some embodiments, the first demodulation electrode region 963 may include a first cathode portion 9631, a first anode portion 9632, and a third cathode portion 9633.

[0222] In some embodiments, the first demodulation electrode region 963 may include a PN junction region 9635. The PN junction region 9635 is located at the center of the region enclosed by the first cathode portion 9631, the first anode portion 9632, and the third cathode portion 9633. The first anode portion 9632 is electrically connected to the P-region of the PN junction region 9635. The first cathode portion 9631 and the third cathode portion 9633 are respectively electrically connected to the N-region of the PN junction region 9635.

[0223] In some embodiments, the waveguide width between the PN junction region 9635 and the first anode portion 9632 gradually changes to achieve impedance continuity. The waveguide width between the PN junction region 9635 and the first cathode portion 9631 gradually changes to achieve impedance continuity. The waveguide width between the PN junction region 9635 and the third cathode portion 9633 gradually changes to achieve impedance continuity.

[0224] Figure 11a This is a partial connection diagram of the fifth type of first optical demodulator array and first transimpedance amplifier chip array according to some embodiments. Figure 1 . Figure 11b This is a partial connection diagram of the fifth type of first optical demodulator array and first transimpedance amplifier chip array provided according to some embodiments. (See diagram 2.) Figure 11a and Figure 11bAs shown, in some embodiments, the first optical demodulator array 960 may be a first optical demodulator array 960a. The first optical demodulator array 960a may include a first optical demodulator 961a and a second optical demodulator 962a. The surface of the first optical demodulator 961a is provided with a first demodulation electrode region 963a, and the surface of the second optical demodulator 962a is provided with a second demodulation electrode region 964a. The first demodulation electrode region 963a may include a first cathode portion 9631, a first anode portion 9632 and a third cathode portion 9633, and the second demodulation electrode region 964a may include a second cathode portion 9641, a second anode portion 9642 and a fourth cathode portion 9643.

[0225] In some embodiments, the first cathode portion 9631 and the third cathode portion 9633 are connected to a common ground to provide shielding protection for the signal of the first anode portion 9632. The second cathode portion 9641 and the fourth cathode portion 9643 are connected to a common ground to provide shielding protection for the signal of the second anode portion 9642.

[0226] like Figure 11a and Figure 11b As shown, the distance between the first anode portion 9632 and the second anode portion 9642 is less than 8.4 times the diameter of the first anode portion 9632. The first cathode portion 9631 and the third cathode portion 9633 are located in different rows and columns of the optical chip 900 from the first anode portion 9632, respectively. The second cathode portion 9641 and the fourth cathode portion 9643 are located in different rows and columns of the optical chip 900 from the second anode portion 9642, respectively. Preferably, the distance between the first anode portion 9632 and the second anode portion 9642 is less than 5.4 times the diameter of the first anode portion 9632. The first cathode portion 9631 and the third cathode portion 9633 are located in different rows and columns of the optical chip 900 from the first anode portion 9632, respectively. The second cathode portion 9641 and the fourth cathode portion 9643 are located in different rows and columns of the optical chip 900 from the second anode portion 9642, respectively.

[0227] In some embodiments, the first cathode portion 9631 and the third cathode portion 9633 are respectively disposed at the upper and lower ends of one side of the first anode portion 9632, and the first cathode portion 9631, the first anode portion 9632, and the third cathode portion 9633 form a triangular shape. The second cathode portion 9641 and the fourth cathode portion 9643 are respectively disposed at the upper and lower ends of one side of the second anode portion 9642, and the second cathode portion 9641, the second anode portion 9642, and the fourth cathode portion 9643 form a triangular shape. The formation of a triangle by the first cathode portion 9631, the first anode portion 9632, and the third cathode portion 9633, and the formation of a triangle by the second cathode portion 9641, the second anode portion 9642, and the fourth cathode portion 9643, can effectively reduce the electrode spacing between adjacent optical demodulators, thereby integrating more optical demodulator channels within a limited chip area, further improving the integration density and board utilization of the optical chip.

[0228] In some embodiments, the distance between the first anode portion 9632 and the second anode portion 9642 is a second distance. The second distance value is less than the first distance value. For example, the second distance value can be 250 μm, and the first distance value can be 500 μm.

[0229] In some embodiments, the first cathode portion 9631, the first anode portion 9632, and the third cathode portion 9633 are respectively arranged in different rows, and the second cathode portion 9641, the second anode portion 9642, and the fourth cathode portion 9643 are respectively arranged in different rows. The first cathode portion 9631 and the third cathode portion 9633 are respectively staggered from the first anode portion 9632, and the second cathode portion 9641 and the fourth cathode portion 9643 are respectively staggered from the second anode portion 9642. In this way, while shortening the distance between the first anode portion 9632 and the second anode portion 9642, a safe distance between the first cathode portion 9631 and the third cathode portion 9633 and the first anode portion 9632 can also be guaranteed, as well as a safe distance between the second cathode portion 9641 and the fourth cathode portion 9643 and the second anode portion 9642.

[0230] In some embodiments, the first anode portion 9632 and the second anode portion 9642 are sequentially disposed in the first column of the optical chip 900, and the first anode portion 9632 and the second anode portion 9642 may be on the same axis.

[0231] In some embodiments, the first cathode portion 9631, the third cathode portion 9633, the second cathode portion 9641, and the fourth cathode portion 9643 are sequentially arranged and located in the second column of the optical chip 900. The second column of the optical chip 900 is located on one side of the first column of the optical chip 900, so that the anode portion and the cathode portion are arranged in parallel, avoiding the electrodes of adjacent optical demodulators from intersecting each other in the column direction, reducing interference between electrodes, and ensuring the accuracy and stability of the demodulated signal.

[0232] In some embodiments, the first column of the optical chip 900 is closer to the left edge of the optical chip 900 relative to the second column of the optical chip 900. That is, the first anode portion 9632 and the second anode portion 9642 are closer to the left edge of the optical chip 900 relative to the first cathode portion 9631, the third cathode portion 9633, the second cathode portion 9641 and the fourth cathode portion 9643.

[0233] In some embodiments, if the vertical distance between the center of the first cathode portion 9631 and the center of the first anode portion 9632 is less than the sum of the radius of the first cathode portion 9631 and the radius of the first anode portion 9632, then the vertical distance between the row where the first cathode portion 9631 is located and the row where the first anode portion 9632 is located is shortened, thereby shortening the distance between the first anode portion 9632 and the second anode portion 9642, and thus reducing the length of the first optical demodulator array 960.

[0234] In some embodiments, the first cathode portion 9631 and the third cathode portion 9633 may be symmetrically distributed at the upper and lower ends of one side of the first anode portion 9632. The distances from the first anode portion 9632 to the first cathode portion 9631 and the third cathode portion 9633 may be equal, thereby ensuring the continuity and uniformity of the characteristic impedance in the transmission path, effectively suppressing signal reflection, and ensuring signal integrity. Similarly, the second cathode portion 9641 and the fourth cathode portion 9643 may be symmetrically distributed at the upper and lower ends of one side of the second anode portion 9642.

[0235] In some embodiments, the distance from the first anode portion 9632 to the first transimpedance amplifier chip array 360 is equal to the distance from the second anode portion 9642 to the first transimpedance amplifier chip array 360, thereby maintaining the consistency of the trace distance between each channel and the first transimpedance amplifier chip array 360, and thus ensuring the consistency of the performance of each channel.

[0236] like Figure 11a and Figure 11b As shown, in some embodiments, the first transimpedance amplifier chip array 360 may be a first transimpedance amplifier chip array 360a. The first transimpedance amplifier chip array 360a may include a first transimpedance amplifier chip 361 and a second transimpedance amplifier chip 362. The first transimpedance amplifier chip 361 may be disposed adjacent to and electrically connected to the first optical demodulator 961a, and the second transimpedance amplifier chip 362 may be disposed adjacent to and electrically connected to the second optical demodulator 962a.

[0237] In some embodiments, the first transimpedance amplifier chip array 360 may be a first transimpedance amplifier chip array 360b. The first transimpedance amplifier chip array 360b may include a first transimpedance amplifier chip 361a and a second transimpedance amplifier chip 362a. The first transimpedance amplifier chip 361a may be disposed adjacent to and electrically connected to the first optical demodulator 961a, and the second transimpedance amplifier chip 362a may be disposed adjacent to and electrically connected to the second optical demodulator 962a.

[0238] In some embodiments, the first surfaces of both the first transimpedance amplifier chip 361a and the first transimpedance amplifier chip 361 include a first negative electrode connection portion 3611, a first positive electrode connection portion 3612, and a third negative electrode connection portion 3613. The first negative electrode connection portion 3611 can be connected to the first cathode portion 9631 via traces on the surface of the circuit board 300, the first positive electrode connection portion 3612 can be connected to the first anode portion 9632 via traces on the surface of the circuit board 300, and the third negative electrode connection portion 3613 can be connected to the first cathode portion 9631 via traces on the surface of the circuit board 300, so that the first transimpedance amplifier chip 361a or the first transimpedance amplifier chip 361 is electrically connected to the first optical demodulator 961a. The first surfaces of both the second transimpedance amplifier chip 362a and the second transimpedance amplifier chip 362 include a second negative electrode connection portion 3621, a second positive electrode connection portion 3622, and a fourth negative electrode connection portion 3623. The second negative electrode connection portion 3621 can be connected to the second cathode portion 9641 via traces on the surface of the circuit board 300. The second positive electrode connection portion 3622 can be connected to the second anode portion 9642 via traces on the surface of the circuit board 300. The fourth negative electrode connection portion 3623 can be connected to the fourth cathode portion 9643 via traces on the surface of the circuit board 300, so that the second transimpedance amplifier chip 362a or the second transimpedance amplifier chip 362 is electrically connected to the second optical demodulator 932a.

[0239] like Figure 11a and Figure 11b As shown, the distance between the first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 is less than 8.4 times the diameter of the first positive electrode connection portion 3612. The first negative electrode connection portion 3611 and the third negative electrode connection portion 3613 are located in different rows and columns of the first transimpedance amplifier chip array 360, respectively, and the second negative electrode connection portion 3621 and the fourth negative electrode connection portion 3623 are located in different rows and columns of the first transimpedance amplifier chip array 360, respectively, and the second positive electrode connection portion 3622 is located in different rows and columns of the first transimpedance amplifier chip array 360. Preferably, the distance between the first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 is less than 5.4 times the diameter of the first positive electrode connection portion 3612. The first negative electrode connection portion 3611 and the third negative electrode connection portion 3613 are located in different rows and columns of the first transimpedance amplifier chip array 360, respectively, and the second negative electrode connection portion 3621 and the fourth negative electrode connection portion 3623 are located in different rows and columns of the first transimpedance amplifier chip array 360, respectively, and the second positive electrode connection portion 3622 is located in different rows and columns of the first transimpedance amplifier chip array 360.

[0240] In some embodiments, the first negative electrode connection portion 3611 and the third negative electrode connection portion 3613 are respectively disposed at the upper and lower ends of one side of the first positive electrode connection portion 3612, so that the first negative electrode connection portion 3611, the first positive electrode connection portion 3612, and the third negative electrode connection portion 3613 form a triangle. The second negative electrode connection portion 3621 and the fourth negative electrode connection portion 3623 are respectively disposed at the upper and lower ends of one side of the second positive electrode connection portion 3622, so that the second negative electrode connection portion 3621, the second positive electrode connection portion 3622, and the fourth negative electrode connection portion 3623 form a triangle. The formation of a triangle by the first negative electrode connection portion 3611, the first positive electrode connection portion 3612, and the third negative electrode connection portion 3613, and the formation of a triangle by the second negative electrode connection portion 3621, the second positive electrode connection portion 3622, and the fourth negative electrode connection portion 3623, can effectively reduce the electrode spacing between adjacent transimpedance amplifier chips, thereby integrating more transimpedance amplifier chip channels within a limited chip area.

[0241] like Figure 11a As shown, in some embodiments, the first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 are sequentially disposed in the first column of the first transimpedance amplifier chip array 360a, and the first negative electrode connection portion 3611, the third negative electrode connection portion 3613, the second negative electrode connection portion 3621 and the fourth negative electrode connection portion 3623 are sequentially disposed in the second column of the first transimpedance amplifier chip array 360a. The first column is closer to the optical chip 900 than the second column, that is, the first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 are closer to the right edge of the first transimpedance amplifier chip array 360a than the first negative electrode connection portion 3611, the third negative electrode connection portion 3613, the second negative electrode connection portion 3621 and the fourth negative electrode connection portion 3623.

[0242] like Figure 11b As shown, in some embodiments, the first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 are sequentially disposed in the first column of the first transimpedance amplifier chip array 360b, and the first negative electrode connection portion 3611, the third negative electrode connection portion 3613, the second negative electrode connection portion 3621 and the fourth negative electrode connection portion 3623 are sequentially disposed in the second column of the first transimpedance amplifier chip array 360b. The first column is further away from the optical chip 900 than the second column, that is, the first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 are further away from the right edge of the first transimpedance amplifier chip array 360b than the first negative electrode connection portion 3611, the third negative electrode connection portion 3613, the second negative electrode connection portion 3621 and the fourth negative electrode connection portion 3623.

[0243] Since the first anode portion 9632 and the second anode portion 9642 are closer to the left edge of the optical chip 900 than the first cathode portion 9631, the third cathode portion 9633, the second cathode portion 9641, and the fourth cathode portion 9643, and the first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 are closer to the right edge of the first transimpedance amplifier chip array 360a than the first negative electrode connection portion 3611, the third negative electrode connection portion 3613, the second negative electrode connection portion 3621, and the fourth negative electrode connection portion 3623, the vertical distance between the first positive electrode connection portion 3612 and the first anode portion 9632, and the vertical distance between the second positive electrode portion 3632 and the second anode portion 9642, can be reduced. This reduces the parasitic parameters of the RF traces between the first transimpedance amplifier chip array 360 and the first optical demodulator array 960a, thereby suppressing resonance peaks, improving phase consistency, and enhancing signal integrity.

[0244] Figure 11c This is a partial connection diagram of the sixth type of first optical demodulator array and first transimpedance amplifier chip array according to some embodiments. Figure 1 . Figure 11d This is a partial connection diagram of the sixth type of first optical demodulator array and first transimpedance amplifier chip array provided according to some embodiments. (See diagram 2.) Figure 11c and Figure 11d As shown, in some embodiments, the first optical demodulator array 960 may be a first optical demodulator array 960b. The first optical demodulator array 960b may include a first optical demodulator 961b and a second optical demodulator 962b. The surface of the first optical demodulator 961b is provided with a first demodulation electrode region 963b, and the surface of the second optical demodulator 962b is provided with a second demodulation electrode region 964b. The first demodulation electrode region 963b may include a first cathode portion 9631, a first anode portion 9632, and a third cathode portion 9633. The second demodulation electrode region 964b may include a second cathode portion 9641, a second anode portion 9642, and a fourth cathode portion 9643. The first anode portion 9632 and the second anode portion 9642 are arranged adjacent to each other along the edge in a first column. The first cathode portion 9631, the third cathode portion 9633, the second cathode portion 9641, and the fourth cathode portion 9643 are arranged sequentially and located in a second column. The second column is further away from the interior of the optical chip 900 than the first column. That is, the first anode portion 9632 and the second anode portion 9642 are further away from the left edge of the optical chip 900 relative to the first cathode portion 9631, the third cathode portion 9633, the second cathode portion 9641 and the fourth cathode portion 9643.

[0245] The first positive electrode connection portion 3612 is closer to the right edge of the first transimpedance amplifier chip array 360a, and the first anode portion 9632 is further away from the left edge of the optical chip 900. The trace lengths connecting the first positive electrode connection portion 3612 and the first anode portion 9632, the trace lengths connecting the first negative electrode connection portion 3611 and the first cathode portion 9631, or the trace lengths connecting the third negative electrode connection portion 3613 and the third cathode portion 9633 can be equal. Similarly, the traces connecting the cathode portion of the first optical demodulator array 960c and the negative electrode portion of the first transimpedance amplifier chip array 360a, and the traces connecting the anode portion of the first optical demodulator array 960c and the positive electrode portion of the first transimpedance amplifier chip array 360a can be equal.

[0246] In some embodiments, the distance between the first anode portion 9632 and the second anode portion 9642 is a second distance.

[0247] Figure 11e This is a partial connection diagram of a seventh type of first optical demodulator array and a first transimpedance amplifier chip array according to some embodiments. Figure 11e As shown, in some embodiments, the first optical demodulator array 960 may be a first optical demodulator array 960c. The first optical demodulator array 960c may include a first optical demodulator 961c and a second optical demodulator 962c. The surface of the first optical demodulator 961c includes a first demodulation electrode region 963c, and the surface of the second optical demodulator 962c includes a second demodulation electrode region 964c. The first demodulation electrode region 963c may include a first cathode portion 9634 and a first anode portion 9632. The first cathode portion 9634 and the first negative electrode connection portion 3614 may be connected via traces on the surface of the circuit board 300, and the first anode portion 9632 and the first positive electrode connection portion 3612 may be connected via traces on the surface of the circuit board 300, so that the first demodulation electrode region 963c is electrically connected to the first transimpedance amplifier chip 361b. The second demodulation electrode region 964c may include a second cathode portion 9644 and a second anode portion 9642. The second cathode portion 9644 and the sixth negative electrode connection portion 9931 can be connected by traces on the surface of the circuit board 300. The second anode portion 9642 and the second positive electrode connection portion 9932 can be connected by traces on the surface of the circuit board 300, so that the second demodulation electrode region 964c is electrically connected to the second transimpedance amplifier chip 362b.

[0248] In some embodiments, the first cathode portion 9634 and the first anode portion 9632 are located in different rows but the same column of the first optical demodulator 961c, and the second cathode portion 9644 and the second anode portion 9642 are located in different rows but the same column of the second optical demodulator 962c, so that the first cathode portion 9634, the first anode portion 9632, the second cathode portion 9644 and the second anode portion 9642 are located in the same column of the optical chip 900.

[0249] In some embodiments, the spacing between the first anode portion 9632 and the second anode portion 9642 can conform to a second spacing, that is, the spacing between the anode portions of the first optical demodulator 961c and the second optical demodulator 962c in the first optical demodulator array 960c conforms to the second spacing. This conformity of the second spacing between the anode portions of the first optical demodulator 961c and the second optical demodulator 962c in the first optical demodulator array 960c reduces the length of the first optical demodulator array 960c.

[0250] In some embodiments, the first transimpedance amplifier chip array 360 may be a first transimpedance amplifier chip array 360c. The first transimpedance amplifier chip array 360c is disposed adjacent to and electrically connected to the first optical demodulator array 960c. The first transimpedance amplifier chip array 360c may include a first transimpedance amplifier chip 361b and a second transimpedance amplifier chip 362b. The first transimpedance amplifier chip 361b may include a first negative terminal connection portion 3614 and a first positive terminal connection portion 3612. The second transimpedance amplifier chip 362b may include a second negative terminal connection portion 3624 and a second positive terminal connection portion 3622. The first negative terminal connection portion 3614 and the first positive terminal connection portion 3612 are located in different rows but the same column of the first transimpedance amplifier chip 361b. The second negative terminal connection portion 3624 and the second positive terminal connection portion 3622 are located in different rows but the same column of the second transimpedance amplifier chip 362b, so that the first negative terminal connection portion 3614, the first positive terminal connection portion 3612, the second negative terminal connection portion 3624 and the second positive terminal connection portion 3622 are sequentially arranged along different rows but the same column of the first transimpedance amplifier chip array 360c.

[0251] The first cathode portion 9634, the first anode portion 9632, the second cathode portion 9644, and the second anode portion 9642 are located in different rows but the same column of the optical chip 900. The first negative electrode connection portion 3614, the first positive electrode connection portion 3612, the second negative electrode connection portion 3624, and the second positive electrode connection portion 3622 are located in different rows but the same column of the first transimpedance amplifier chip array 360c. This ensures that the trace lengths from the cathode and anode portions of the same optical demodulator to the corresponding connection portions of the transimpedance amplifier chip are consistent, reducing the signal delay inconsistency caused by differences in trace lengths, thereby improving the synchronization and stability of signal transmission.

[0252] Figure 11f This is a partial connection diagram of the eighth type of first optical demodulator array and first transimpedance amplifier chip array according to some embodiments. Figure 11fAs shown, in some embodiments, the first optical demodulator array 960 may be a first optical demodulator array 960d, which may include a first optical demodulator 961d and a second optical demodulator 962d. The surface of the first optical demodulator 961d includes a first demodulation electrode region 963d, and the surface of the second optical demodulator 962d includes a second demodulation electrode region 964d. The first demodulation electrode region 963d may include a first cathode portion 9634 and a first anode portion 9632, and the second demodulation electrode region 964d may include a second cathode portion 9644 and a second anode portion 9642.

[0253] like Figure 11f As shown, in some embodiments, the distance between the first anode portion 9632 and the second anode portion 9642 is less than 5.6 times the diameter of the first anode portion 9632. The first cathode portion 9634 and the first anode portion 9632 are located in different rows and columns of the optical chip 900, and the second cathode portion 9644 and the second anode portion 9642 are also located in different rows and columns of the optical chip 900. This arrangement effectively reduces the electrode spacing between adjacent optical demodulators, thereby integrating more optical demodulator channels within a limited chip area, further improving the integration density and board utilization of the optical chip. Preferably, the distance between the first anode portion 9632 and the second anode portion 9642 is less than 3.6 times the diameter of the first anode portion 9632, the first cathode portion 9634 and the first anode portion 9632 are located in different rows and columns of the optical chip 900, and the second cathode portion 9644 and the second anode portion 9642 are located in different rows and columns of the optical chip 900.

[0254] In some embodiments, the distance between the first anode portion 9632 and the second anode portion 9642 is smaller than the second distance.

[0255] In some embodiments, the first anode portion 9632 and the second anode portion 9642 are sequentially disposed in the first column of the optical chip 900, and the first anode portion 9632 and the second anode portion 9642 may be on the same axis.

[0256] In some embodiments, the first cathode portion 9634 and the second cathode portion 9644 are sequentially disposed and located in the second column of the optical chip 900. The second column of the optical chip 900 is located on one side of the first column of the optical chip 900, so that the anode portion and the cathode portion are disposed in parallel, avoiding the electrodes of adjacent optical demodulators from intersecting each other in the column direction, reducing interference between electrodes, and ensuring the accuracy and stability of the demodulated signal.

[0257] like Figure 11fAs shown, in some embodiments, the first column of the optical chip 900 is closer to the left edge of the optical chip 900 relative to the second column of the optical chip 900. That is, the first anode portion 9632 and the second anode portion 9642 are closer to the left edge of the optical chip 900 relative to the first cathode portion 9634 and the second cathode portion 9644.

[0258] In some embodiments, the first column of the optical chip 900 is further away from the left edge of the optical chip 900 relative to the second column of the optical chip 900. That is, the first anode portion 9632 and the second anode portion 9642 are further away from the left edge of the optical chip 900 relative to the first cathode portion 9634 and the second cathode portion 9644.

[0259] In some embodiments, if the vertical distance between the center of the first cathode portion 9634 and the center of the first anode portion 9632 is less than the sum of the radius of the first cathode portion 9634 and the radius of the first anode portion 9632, then the vertical distance between the row where the first cathode portion 9634 is located and the row where the first anode portion 9632 is located is shortened, thereby shortening the distance between the first anode portion 9632 and the second anode portion 9642, and thus reducing the length of the first optical demodulator array 960.

[0260] In some embodiments, the distance from the first anode portion 9632 to the first transimpedance amplifier chip array 360 is equal to the distance from the second anode portion 9642 to the first transimpedance amplifier chip array 360, thereby maintaining the consistency of the trace distance between each channel and the first transimpedance amplifier chip array 360, and thus ensuring the consistency of the performance of each channel.

[0261] like Figure 11f As shown, in some embodiments, the first transimpedance amplifier chip array 360 may be a first transimpedance amplifier chip array 360d. The first transimpedance amplifier chip array 360d is disposed adjacent to and electrically connected to the first optical demodulator array 960d. The first transimpedance amplifier chip array 360d may include a first transimpedance amplifier chip 361c and a second transimpedance amplifier chip 362c. The first transimpedance amplifier chip 361c may include a first negative terminal connection portion 3614 and a first positive terminal connection portion 3612, and the second transimpedance amplifier chip 362c may include a second negative terminal connection portion 3624 and a second positive terminal connection portion 3622.

[0262] like Figure 11fAs shown, when the distance between the first positive electrode connection 3612 and the second positive electrode connection 3622 is less than 5.6 times the diameter of the first positive electrode connection 3612, the first negative electrode connection 3614 and the first positive electrode connection 3612 are located in different rows and columns of the first transimpedance amplifier chip array 360c, and the second negative electrode connection 3624 and the second positive electrode connection 3622 are located in different rows and columns of the first transimpedance amplifier chip array 360c. Preferably, when the distance between the first positive electrode connection 3612 and the second positive electrode connection 3622 is less than 3.6 times the diameter of the first positive electrode connection 3612, the first negative electrode connection 3614 and the first positive electrode connection 3612 are located in different rows and columns of the first transimpedance amplifier chip array 360c, and the second negative electrode connection 3624 and the second positive electrode connection 3622 are located in different rows and columns of the first transimpedance amplifier chip array 360c.

[0263] In some embodiments, the first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 are sequentially disposed in the first column of the first transimpedance amplifier chip array 360c, and the first column of the first transimpedance amplifier chip array 360c is disposed adjacent to each other along the edge of the first transimpedance amplifier chip array 360c. The first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 may be on the same axis.

[0264] In some embodiments, the first negative electrode connection portion 3614 and the second negative electrode connection portion 3624 are sequentially arranged and located in the second column of the first transimpedance amplifier chip array 360c. The second column of the first transimpedance amplifier chip array 360c is located on one side of the first column of the first transimpedance amplifier chip array 360c, which can effectively avoid spatial cross-interference of positive and negative electrode traces and reduce the risk of signal crosstalk.

[0265] like Figure 11f As shown, in some embodiments, the first column of the first transimpedance amplifier chip array 360c is closer to the first optical chip 900 than the second column of the first transimpedance amplifier chip array 360c, that is, the first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 are closer to the right edge of the first transimpedance amplifier chip array 360c than the first negative electrode connection portion 3614 and the second negative electrode connection portion 3624.

[0266] In some embodiments, the first column of the first transimpedance amplifier chip array 360c is further away from the first optical chip 900 than the second column of the first transimpedance amplifier chip array 360c, that is, the first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 are further away from the right edge of the first transimpedance amplifier chip array 360c than the first negative electrode connection portion 3614 and the second negative electrode connection portion 3624.

[0267] The first anode portion 9632 and the second anode portion 9642 are closer to the left edge of the optical chip 900 than the first cathode portion 9634 and the second cathode portion 9644, respectively. The first positive electrode connection portion 3612 and the second positive electrode connection portion 3622 are closer to the right edge of the first transimpedance amplifier chip array 360c than the first negative electrode connection portion 3614 and the second negative electrode connection portion 3624. This can reduce the vertical distance between the first positive electrode connection portion 3612 and the first anode portion 9632, and the vertical distance between the second positive electrode portion 3632 and the second anode portion 9642. In turn, reducing the RF traces between the first transimpedance amplifier chip array 360c and the first optical demodulator array 960c can reduce parasitic parameters, thereby suppressing resonance peaks, improving phase consistency, and enhancing signal integrity.

[0268] An optical chip 900 has a first optical demodulator array 960 on one edge. The spacing between two adjacent anode portions of the first optical demodulator array 960 is a second spacing or even smaller, which can reduce the length of the first optical demodulator array 960. Without considering the optical modulation region 920, reducing the length of the first optical demodulator array 960 can reduce the width of the optical chip 900. Considering the optical modulation region 920, reducing the length of the first optical demodulator array 960 can reduce the size of the optical chip 900 occupied by the first optical demodulator array 960, reserving more space for other functional areas and contributing to the miniaturization design of the optical chip.

[0269] Figures 7a-7e , Figures 11a-11f The dashed lines shown are not gold lines, but represent the correspondence between the positive and negative terminals of the first transimpedance amplifier chip array and the cathode and anode terminals of the first optical demodulator array.

[0270] In some embodiments, the spacing between two adjacent optical modulators in the first optical modulator array 920a is 500 μm, the spacing between two adjacent optical modulators in the second optical modulator array 920b is 500 μm, and each optical modulator of the first optical modulator array 920a and each optical modulator of the second optical modulator array 920b are arranged adjacently along the left-right direction of the optical chip 900. The size occupied by the first optical modulator array 920a and the second optical modulator array 920b in the left-right direction of the optical chip 900 is 4 mm. The 500 μm spacing between two adjacent optical modulators refers to the 500 μm spacing between the center points of the modulation electrodes of two adjacent optical modulators and the 500 μm spacing between the center points of the modulation waveguides of two adjacent optical modulators.

[0271] In some embodiments, the first optical modulator array 920a has a dimension of 3.5 mm along the vertical direction of the optical chip 900, the second optical modulator array 920b has a dimension of 3.5 mm along the vertical direction of the optical chip 900, the first optical modulator array 920a and the second optical modulator array 920b overlap along the vertical direction of the optical chip 900, and the dimension occupied by the first optical modulator array 920a and the second optical modulator array 920b in the vertical direction of the optical chip 900 is 4 mm.

[0272] The distance between the first optical modulator array 920a and the lower edge of the optical chip 900 is 250μm. The vertical dimension of the optical chip 900 occupied by the first optical modulator array 920a and the second optical modulator array 920b is 4mm. The distance between the second optical modulator array 920b and the upper edge of the optical chip 900 is 250μm. The distance between the left edge of the optical chip 900 and the first optical modulator array 920a is 4mm. The horizontal dimension of the optical chip 900 occupied by the first optical modulator array 920a and the second optical modulator array 920b is 4mm. The distance between the second optical modulator array 920b and the right edge of the optical chip 900 is 3mm. Therefore, the first optical modulator array 920a and the second optical modulator array 920b overlap along the vertical direction of the optical chip 900, and the width of the optical chip with each optical modulator arranged adjacent to each other along the horizontal direction of the optical chip 900 is 4.5mm and the length is 11mm.

[0273] In some embodiments, the spacing between two adjacent optical modulators of the first optical modulator array 920a is 375 μm, the spacing between two adjacent optical modulators of the second optical modulator array 920b is 375 μm, each optical modulator of the first optical modulator array 920a and each optical modulator of the second optical modulator array 920b are arranged sequentially, the spacing between the first optical modulator array 920a and the second optical modulator array 920b is 1 mm, and the size of the first optical modulator array 920a and the second optical modulator array 920b in the left and right directions of the optical chip 900 is 7 mm.

[0274] In some embodiments, the first optical modulator array 920a has a dimension of 3.5 mm along the vertical direction of the optical chip 900, and the second optical modulator array 920b has a dimension of 3.5 mm along the vertical direction of the optical chip 900. The first optical modulator array 920a and the second optical modulator array 920b almost completely overlap along the vertical direction of the optical chip 900, and the dimension occupied by the first optical modulator array 920a and the second optical modulator array 920b in the vertical direction of the optical chip 900 is 3.5 mm.

[0275] The distance between the first optical modulator array 920a and the lower edge of the optical chip 900 is 600 μm. The vertical dimension of the optical chip 900 occupied by the first optical modulator array 920a and the second optical modulator array 920b is 3.5 mm. The distance between the second optical modulator array 920b and the upper edge of the optical chip 900 is 300 μm. The distance between the left edge of the optical chip 900 and the first optical modulator array 920a is 3.5 mm. The horizontal dimension of the optical chip 900 occupied by the first optical modulator array 920a and the second optical modulator array 920b is 7 mm. The distance between the second optical modulator array 920b and the right edge of the optical chip 900 is 2.5 mm. Therefore, the first optical modulator array 920a and the second optical modulator array 920b completely overlap along the vertical direction of the optical chip 900, and the width of the optical chip arranged sequentially along the horizontal direction of the optical chip 900 is 4.4 mm and the length is 13 mm.

[0276] Figure 12 This is a schematic diagram of the electrical connection between a first optical demodulator and a first transimpedance amplifier chip according to some embodiments. Figure 13 This is a schematic diagram showing the electrical connection of a first optical demodulator and a first transimpedance amplifier chip to a circuit board according to some embodiments. Figure 14 This is a schematic diagram illustrating the electrical connection between another first optical demodulator and a first transimpedance amplifier chip according to some embodiments. Figure 12 , Figure 13 and Figure 14 As shown, in some embodiments, the first optical demodulator 931b is electrically connected to the first transimpedance amplifier chip 331b.

[0277] In some embodiments, the first optical demodulator 961a is electrically connected to the first transimpedance amplifier chip 361.

[0278] In some embodiments, the first surfaces of the first transimpedance amplifier chip 331b and the first transimpedance amplifier chip 361 are both active surfaces, which are soldered to the surface of the circuit board 300. The first transimpedance amplifier chip 331b and the first transimpedance amplifier chip 361 are flip-soldered onto the surface of the circuit board 300. The first surface of the optical chip 900 is also an active surface, and its first surface is soldered to the surface of the circuit board 300. The optical chip 900 is flip-soldered onto the surface of the circuit board 300.

[0279] In some embodiments, the circuit board 300 includes a top layer 301. The top layer 301 is located on the upper surface of the circuit board 300. The surface of the top layer 301 is provided with a first trace 3011, a second trace 3012, and a third trace 3013 arranged in parallel. The first trace 3011 is electrically connected to the first negative terminal connection portion 3311 and the first cathode portion 9331. The second trace 3012 is electrically connected to the first positive terminal connection portion 3312 and the first anode portion 9332. The third trace 3013 is electrically connected to the third negative terminal connection portion 3313 and the third cathode portion 9333, thereby realizing the electrical connection between the first optical demodulator 931b and the first transimpedance amplifier chip 331b.

[0280] In some embodiments, the top layer 301 surface is provided with a first trace 3011a, a second trace 3012a, and a third trace 3013a arranged in parallel. The first trace 3011a is electrically connected to the first negative electrode connection portion 3611 and the first cathode portion 9631. The second trace 3012a is electrically connected to the first positive electrode connection portion 3612 and the first anode portion 9632. The third trace 3013a is electrically connected to the third negative electrode connection portion 3613 and the third cathode portion 9633, thereby realizing the electrical connection between the first optical demodulator 961a and the first transimpedance amplifier chip 361.

[0281] In some embodiments, the reverse bias voltage source can be output by a first transimpedance amplifier chip, which provides a reverse bias voltage to a first optical demodulator along a first trace, a second trace, and a third trace. Specifically, the first and third traces apply the same voltage to the first optical demodulator, and the voltage difference between the first and third traces and the second trace forms the reverse bias voltage. Under the action of the reverse bias voltage, the first optical demodulator generates a photocurrent signal. The generated photocurrent signal is transmitted to the first transimpedance amplifier chip along the second trace 3012.

[0282] In some embodiments, a first cutout region 3014 is formed in the top layer 301, and the first optical demodulator is located within the first cutout region 3014. The copper around the first, second, and third traces is removed, reducing the electric field coupling area between the traces and the surrounding conductive areas, thereby reducing parasitic capacitance. Simultaneously, the influence of surrounding copper on the loops of the first, second, and third traces is reduced, decreasing the current loop area and lowering parasitic inductance.

[0283] In some embodiments, the circuit board 300 includes a first inner layer 302, which is located below the top layer 301. The projection areas of the first, second, and third traces on the first inner layer 302 do not have metal regions, thus forming a second cutout area. In this case, the first, second, and third traces use a lower layer as a reference ground plane, reducing grounding capacitance and improving signal integrity.

[0284] In some embodiments, a first dielectric layer is provided between the top layer 301 and the first inner layer 302. The first dielectric layer retains a complete layered structure and is not stripped of copper foil, so the surface of the top layer 301 can be supported by the first dielectric layer.

[0285] In some embodiments, the circuit board 300 includes a second inner layer 303. The second inner layer 303 is located below the first inner layer 302. The projection areas of the first trace, the second trace, and the third trace on the second inner layer 303 do not have metal regions to form a third cutout area. In this case, the first trace, the second trace, and the third trace use a lower layer as a reference ground plane, thereby reducing ground capacitance and improving signal integrity.

[0286] In some embodiments, the surface of the top layer 301 has a first reference ground plane 3015. In some embodiments, the circuit board 300 includes a bottom layer 304 located on the lower surface of the circuit board. The surface of the bottom layer 304 has a second reference ground plane.

[0287] In some embodiments, the first surface of the first transimpedance amplifier chip 331b includes a first ground connection portion 3315 and a second ground connection portion 3316. The first ground connection portion 3315 is electrically connected to a first reference ground plane 3015, and the second ground connection portion 3316 is electrically connected to the first reference ground plane. The second reference ground plane and the first reference ground plane 3015 are electrically connected through vias, thereby enabling the first ground connection portion 3315 and the second ground connection portion 3316 to be grounded via the second reference ground plane of the bottom layer 304.

[0288] In some embodiments, the projection areas of the first trace, the second trace, and the third trace on the inner layers between the top layer 301 and the bottom layer 304 do not form metal regions, thereby reducing the parasitic capacitance between each trace and the copper layer and improving signal transmission integrity.

[0289] Figure 12 The same scheme applies to the first negative electrode connection part 3311, the first positive electrode connection part 3312 and the third negative electrode connection part 3313 being arranged in a triangle, and the first cathode part 9331, the first anode part 9332 and the third cathode part 9333 being arranged in a straight line, that is, in the same column.

[0290] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An optical chip, characterized in that, include: The optical port is located at the right edge of the optical chip; The demodulation region is located on the left edge of the optical chip and is optically connected to the optical port end, so that the demodulation region receives the light to be demodulated and demodulates the light to be demodulated; A modulation region is located between the optical port and the demodulation region, and is optically connected to the optical port so that the modulation region receives the light to be modulated, modulates the light to be modulated to generate an optical signal, and outputs the optical signal. The modulation region includes: The first optical modulator includes: The first modulation electrode region is located at the lower edge of the optical chip; The first modulation waveguide is located above the first modulation electrode region; The second optical modulator includes: The second modulation electrode region is located at the upper edge of the optical chip; The second modulation waveguide is located below the second modulation electrode region and to the right of the first modulation waveguide; the second modulation waveguide overlaps with the first modulation waveguide in the vertical direction of the optical chip. Light enters from the upper and lower edges of the optical port end, and light exits from the center of the optical port end.

2. The optical chip according to claim 1, characterized in that, The optical port includes: An input optical port array, located at the upper or lower edge of the optical port end, is connected to the demodulation region to receive the light to be demodulated and transmit the light to be demodulated into the demodulation region; A light source input optical port array and the input optical port array are located at opposite edges of the optical port end and connected to the input ends of the first modulation waveguide and the second modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input ends of the first modulation waveguide and the second modulation waveguide; An output optical port array is located between the input optical port array and the light source input optical port array, and is connected to the output ends of the first modulation waveguide and the second modulation waveguide to receive the optical signal and output the optical signal.

3. The optical chip according to claim 1, characterized in that, The optical port includes: An input optical port array, located at the upper or lower edge of the optical port end, is connected to the demodulation region to receive the light to be demodulated and transmit the light to be demodulated into the demodulation region; The light source input optical port array includes: The first light source input port is arranged adjacent to the input port array and connected to the input end of the second modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input end of the second modulation waveguide; The second light source input port and the input port array are located at opposite edges of the port end and connected to the input end of the first modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input end of the first modulation waveguide. An output optical port array is located between the first light source input optical port and the second light source input optical port, and is connected to the output ends of the first modulation waveguide and the second modulation waveguide to receive the optical signal and output the optical signal.

4. The optical chip according to claim 1, characterized in that, The optical port includes: An input optical port array, located at the upper or lower edge of the optical port end, is connected to the demodulation region to receive the light to be demodulated and transmit the light to be demodulated into the demodulation region; The light source input optical port array includes: The first light source input port is connected to the input end of the second modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input end of the second modulation waveguide; The second light source input port and the input port array are located at opposite edges of the port end and connected to the input end of the first modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input end of the first modulation waveguide. The output optical port array includes: The first output optical port is located between the input optical port array and the first light source input optical port, and is connected to the output end of the first modulation waveguide to receive the optical signal and output the optical signal. The second output optical port is located between the first light source input optical port and the second light source input optical port, and is connected to the output end of the second modulation waveguide to receive the optical signal and output the optical signal.

5. The optical chip according to claim 1, characterized in that, The first modulation waveguide extends upward, with its end extending beyond the central axis of the optical chip; the second modulation waveguide extends downward, with its end extending beyond the central axis of the optical chip.

6. The optical chip according to claim 1, characterized in that, The width of the optical chip occupied by the first optical modulator and the second optical modulator is greater than half the width of the optical chip, but less than the width of the optical chip.

7. The optical chip according to claim 6, characterized in that, The length of both the first modulation waveguide and the second modulation waveguide is greater than half the width of the optical chip and less than the width of the optical chip.

8. An optical module, characterized in that, include: Optical chip; The first driving chip is located below the optical chip; The second driving chip is located on top of the optical chip; The optical chip includes: The optical port is located at the right edge of the optical chip; The demodulation region is located on the left edge of the optical chip and is optically connected to the optical port end, so that the demodulation region receives the light to be demodulated and demodulates the light to be demodulated; A modulation region is located between the optical port and the demodulation region, and is optically connected to the optical port so that the modulation region receives the light to be modulated, modulates the light to be modulated to generate an optical signal, and outputs the optical signal. The modulation region includes: The first optical modulator includes: The first modulation electrode region is located at the lower edge of the optical chip and is electrically connected to the first driving chip; The first modulation waveguide is located above the first modulation electrode region; The second optical modulator includes: The second modulation electrode region is located at the upper edge of the optical chip and is electrically connected to the second driving chip; The second modulation waveguide is located below the second modulation electrode region and to the right of the first modulation waveguide; the second modulation waveguide overlaps with the first modulation waveguide in the vertical direction of the optical chip. Light enters from the upper and lower edges of the optical port end, and light exits from the center of the optical port end.

9. The optical module according to claim 8, characterized in that, The optical port includes: An input optical port array, located at the upper or lower edge of the optical port end, is connected to the demodulation region to receive the light to be demodulated and transmit the light to be demodulated into the demodulation region; A light source input optical port array and the input optical port array are located at opposite edges of the optical port end and connected to the input ends of the first modulation waveguide and the second modulation waveguide to receive the light to be modulated and transmit the light to be modulated to the input ends of the first modulation waveguide and the second modulation waveguide; An output optical port array is located between the input optical port array and the light source input optical port array, and is connected to the output ends of the first modulation waveguide and the second modulation waveguide to receive the optical signal and output the optical signal.

10. The optical module according to claim 8, characterized in that, The demodulation region includes: First optical demodulator, surface formation: First cathode section; First anode section; Third cathode section; The second optical demodulator is disposed adjacent to the first optical demodulator, and its surface is formed as follows: Second cathode section; Second anode section; The fourth cathode portion; the distance between the second anode portion and the first anode portion is less than 8.4 times the diameter of the first anode portion; the second cathode portion and the fourth cathode portion are located at the upper and lower ends of one side of the second anode portion, the first cathode portion and the third cathode portion are located at the upper and lower ends of one side of the first anode portion, the second anode portion and the first anode portion are located in the first column of the optical chip, and the fourth cathode portion, the second cathode portion, the third cathode portion and the first cathode portion are located in the second column of the optical chip; The left side of the optical chip is also provided with: The first transimpedance amplifier chip, corresponding to the first optical demodulator, has the following surface formation: The first negative electrode connection part is electrically connected to the first cathode part; The first positive electrode connection portion is electrically connected to the first anode portion; The third negative electrode connection part is electrically connected to the third cathode part; The second transimpedance amplifier chip, corresponding to the second optical demodulator, has the following surface formation: The second negative electrode connection part is electrically connected to the second cathode part; The second positive electrode connection portion is electrically connected to the second anode portion; The fourth negative electrode connection part is electrically connected to the fourth cathode part; The distance between the second positive electrode connection and the first positive electrode connection is 0.8 to 1.2 times the distance between the first anode part and the second anode part.

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