Fusion instruction monitoring system and method and electronic equipment

Abstract

The invention provides a fusion instruction monitoring system and method and electronic equipment, and is suitable for the technical field of CPU monitoring. The fusion instruction monitoring system comprises an assembly line monitoring circuit which is used for capturing instruction information of a target instruction in the process that the CPU processes the target instruction and outputting the instruction information of the target instruction after the execution of the target instruction is finished; the target instruction comprises a fusion instruction and at least two original instructions corresponding to the fusion instruction; and the event printing device is used for printing instruction information of the target instruction based on the instruction type corresponding to the target instruction output by the assembly line monitoring circuit. According to the embodiment of the invention, the instruction information of the target instruction is printed, so that a circuit designer can check whether an exception exists in the execution process of the fusion instruction, and monitoring of the fusion instruction is realized.

Description

Technical Field

[0001] This application relates to the field of CPU monitoring technology, and in particular to a monitoring system, method and electronic device for fused instructions. Background Technology

[0002] To improve performance, the decoding module within the CPU (Central Processing Unit) provides instruction fusion. The fused instruction becomes a new instruction that incorporates two or more operations from the original instruction. What would have required the execution time of two or more instructions can be combined into a single instruction execution time, thereby increasing the CPU's instructions per cycle (IPC).

[0003] However, CPU core circuit designers cannot monitor fusion instructions and cannot check for anomalies during fusion instruction execution. Summary of the Invention

[0004] In view of this, embodiments of this application provide a monitoring system, method, and electronic device for fusion instructions to solve the problem in the prior art that it is impossible to check whether there are abnormalities during the execution of fusion instructions.

[0005] A first aspect of this application provides a monitoring system for fused instructions, comprising: The pipeline monitoring circuit is used to capture the instruction information of the target instruction during the process of the central processing unit (CPU) processing the target instruction, and to output the instruction information of the target instruction after the execution of the target instruction is completed; the target instruction includes a fused instruction and at least two original instructions corresponding to the fused instruction; An event printing device is used to print the instruction information of a target instruction based on the instruction type corresponding to the target instruction output by the pipeline monitoring circuit.

[0006] In one possible implementation, the pipeline monitoring circuit includes a buffer module, an update logic module, a retirement monitor, a rearranged virtual queue, and an output queue; The buffer module is connected to the rearrangement virtual queue. The buffer module is used to fetch instruction information from the CPU's decoding module and write the instruction information into the rearrangement virtual queue. The update logic module is connected to the rearrangement virtual queue. The update logic module is used to monitor the CPU's execution module, capture the instruction execution information generated by the execution module during the execution phase of the target instruction, and update the instruction information of the target instruction based on the instruction execution information. The retirement monitor is connected to the rearrangement virtual queue. When the retirement monitor detects the signal that the execution of the target instruction has ended, it deletes the instruction information of the target instruction that has ended execution from the rearrangement virtual queue based on the number information of the target instruction. The rearranged virtual queue is connected to the output queue. The rearranged virtual queue is used to output the instruction information of the target instruction that has finished execution to the output queue. The output queue is used to output the instruction information of the target instruction that has been executed to the event printing device.

[0007] In one possible implementation, the buffer module includes a pre-decoding buffer, a pre-renaming buffer, a post-renaming buffer, and a sending buffer; The pre-decoding buffer is used to capture the instruction information of the target instruction before the decoding module decodes it and output it to the reordered virtual queue; The pre-renaming buffer is used to capture the instruction information of the target instruction generated by the decoding module during the decoding stage before renaming it and output it to the reordering virtual queue. The renamed buffer is used to capture the renamed instruction information of the target instruction generated by the decoding module during the decoding stage and output it to the rearranged virtual queue. The send buffer is used to capture the instruction information of the target instruction generated by the decoding module during the distribution phase and distribute it to the execution module, and output it to the reordered virtual queue.

[0008] In one possible implementation, the pre-decoding buffer includes a first fusion buffer module and a second fusion buffer module, and the fusion instruction includes a first fusion instruction and a second fusion instruction. The first fusion buffer module is used to capture the instruction information of the first fusion instruction before the decoding module decodes; the first fusion instruction is the instruction obtained by fusing two sequentially consecutive original instructions. The second fusion buffer module is used to capture the instruction information of the second fusion instruction before the decoding module decodes it; the second fusion instruction is the instruction obtained by fusing multiple fusionable original instruction sequences in the same instruction fetch block region.

[0009] In one possible implementation, the instruction information of the first fused instruction includes the instruction type, the fused instruction address, and the binary code instruction information; The instruction information for the second fusion instruction includes the instruction type.

[0010] In one possible implementation, the event printing device includes a fused event module; The fusion event module is used to print the instruction information of the fusion command and to identify the instruction information of the fusion command.

[0011] In one possible implementation, the fusion event module is used to identify the instruction type of the first fusion instruction, and to identify the fusion instruction address and binary code instruction information of the first fusion instruction if the fusion instruction is a first fusion instruction; and to identify the instruction type of the second fusion instruction if the fusion instruction is a second fusion instruction.

[0012] A second aspect of this application provides a method for monitoring fusion instructions, comprising: During the CPU's processing of the target instruction, the pipeline monitoring circuit captures the instruction information of the target instruction. After the target instruction is executed, the instruction information of the target instruction is output to the event printing device. The target instruction includes a fused instruction and at least two original instructions corresponding to the fused instruction. The event printing device prints the instruction information of the target instruction based on the instruction type corresponding to the target instruction.

[0013] In one possible implementation, the event printing device prints the instruction information of the target instruction based on the instruction type corresponding to the target instruction, including: The event printing device prints the instruction information of the fusion command through the fusion event module and identifies the instruction information of the fusion command.

[0014] A third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the functions of a monitoring system for fusion instructions as described in the first aspect or the steps of a monitoring method for fusion instructions as described in the second aspect.

[0015] Compared with the prior art, the embodiments of this application have at least the following technical effects: The first aspect of this application provides a fusion instruction monitoring system including a pipeline monitoring circuit and an event printing device. The pipeline monitoring circuit is used to capture the instruction information of the target instruction during the CPU's processing of the target instruction, and output the instruction information of the target instruction after the execution of the target instruction is completed. Since the target instruction includes a fusion instruction and at least two original instructions corresponding to the fusion instruction, this application embodiment can monitor the fusion instruction through the instruction information of the fusion instruction and the instruction information of the original instructions. At the same time, the event printing device is used to print the instruction information of the target instruction based on the instruction type corresponding to the target instruction output by the pipeline monitoring circuit, so that the circuit designer of the CPU core can view the printed instruction information of the target instruction, and then check whether there are any abnormalities during the execution of the fusion instruction, thereby realizing the monitoring of the fusion instruction.

[0016] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the framework of a monitoring system for fused instructions provided in an embodiment of this application; Figure 2 This is a schematic diagram of the framework of another monitoring system for fused instructions provided in an embodiment of this application; Figure 3 This is a schematic diagram of the framework of another monitoring system for fused instructions provided in the embodiments of this application; Figure 4 This is a schematic diagram of the internal data format of an output queue provided in an embodiment of this application; Figure 5 This is a flowchart of a monitoring method for fusion instructions provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0019] Figure label: 10-Pipeline monitoring circuit, 11-Buffer module, 12-Update logic module, 13-Rearrange virtual queue, 14-Output queue, 15-Retirement monitor, 111-Decoding pre-buffer, 1111-First fusion buffer module, 1112-Second fusion buffer module, 112-Rename pre-buffer, 113-Rename post-buffer, 114-Transmit buffer; 20 - Event printing device, 21 - Retirement event module, 211 - Fusion event module. Detailed Implementation

[0020] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0021] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0022] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0023] In the description of this application, unless otherwise stated, the " / " used in this specification and appended claims indicates that the related objects are in an "or" relationship. For example, A / B can mean A or B. The "and / or" in this application merely describes the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c. Here, a, b, and c can be single or multiple.

[0024] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0025] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0027] First, the relevant technologies involved in this application will be introduced: 1. Instruction Fusion Technology In processor design, instruction fusion is a key hardware performance optimization technique. Its core idea is to merge two or more consecutive instructions that meet specific conditions into a single "fused instruction" at an early stage of execution (such as the fetch or decode stage). This technique aims to effectively improve the efficiency of the processor's mid-levels (such as the decoding unit) and back-ends (such as the execution unit), reduce resource consumption, and ultimately improve overall instruction throughput and energy efficiency.

[0028] By implementing instruction fusion technology, processors can process more effective instructions per unit of time. This improvement mainly stems from more efficient utilization of processor pipeline resources, reducing overhead in the instruction processing process.

[0029] 2. Hardware Performance Counter (PMC) Monitoring Implementation principle: Pipeline events (branch prediction errors, cache misses, instruction retirements, etc.) are captured through the processor's built-in fixed / configurable performance counters (such as Intel's 4 fixed + 4 configurable PMCs). The top-down methodology constructs a hierarchical decision tree (L1-L4) based on PMC data to locate performance bottlenecks (such as front-end blocking, back-end resource conflicts). The PMC (PCI Mezzanine Card) interface is an extension module based on the PCI (Peripheral Component Interconnect) bus, designed to provide efficient data transfer and system expansion capabilities.

[0030] Application scenario: By polling PMC data and combining multiplexing technology, the limitation on the number of PMC interfaces is solved, supporting performance analysis on the Linux platform.

[0031] 3. Instruction-level tracing technology Dynamic range compression: By filtering the program counter (PC) range, only instruction trace data within a specific address range is stored, reducing on-chip memory usage.

[0032] Multi-stage pipeline probes: Hardware probes are inserted in the Fetch, Decode, EX, MEM, and WB stages to capture intermediate values ​​such as operands and ALU (arithmetic and logic unit) outputs, which are used to verify the transaction-level transformation of the platform (such as UVMMonitor).

[0033] Further research revealed three shortcomings in the existing monitor architecture during the CPU development phase: 1. Insufficient monitoring granularity Existing technologies mainly rely on two types of monitoring solutions: System-level monitoring: CPU register status is collected through the BMC controller, but only macroscopic indicators (such as temperature and load) can be obtained. It cannot capture intermediate values ​​of instructions at each stage of the pipeline (such as operands, ALU outputs, and address calculation results).

[0034] Instruction tracing technology: Based on program counter (PC) range compressed tracing data, it only records the instruction address stream and lacks the ability to reconstruct the intermediate state of the instruction execution process, especially for fused instructions.

[0035] 2. Data storage and processing bottlenecks Full instruction tracing leads to a surge in storage overhead, and existing compression methods (such as PC value range filtering) may lose critical context (such as branch jump target chains, fusion instructions, etc.), affecting the accuracy of fault diagnosis.

[0036] The monitor in the verification phase (such as the UVM platform) requires an additional transformation layer to map hardware signals into transaction-level data, which results in poor real-time performance and increased verification complexity.

[0037] 3. Insufficient monitoring of instruction fusion Transparency and Hardware Dependency of Instruction Fusion: Instruction fusion is an optimization operation automatically executed by the processor at the hardware level (such as during the instruction fetch or decode phase). For the upper-level operating system and applications, this process is typically "transparent," meaning it cannot be directly observed. Traditional performance monitoring tools (such as profiling tools based on performance counters) often struggle to directly track and count the "fused instructions" event itself. They focus more on monitoring macroscopic metrics such as cache hit rate, branch prediction error rate, and IPC (instructions per cycle), rather than the dynamic combination and changes of instructions deep within the pipeline.

[0038] The complexity of monitoring mechanism design: Achieving precise monitoring of instruction fusion at the hardware level requires embedding dedicated Performance Monitoring Unit (PMU) events in the processor's critical paths (such as decoders and renaming / scheduling units). This involves complex circuit design and consumes valuable chip area and power budget. Processor manufacturers typically prioritize improving the performance and energy efficiency of mainstream applications during design and optimization, rather than providing comprehensive observation points for in-depth microarchitecture debugging. This makes dedicated hardware events for tracking instruction fusion very scarce or functionally limited.

[0039] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0040] See Figure 1 As shown, this application provides a schematic diagram of the framework of a monitoring system for fused instructions. Figure 1 As shown, the monitoring system for fusion instructions in this application embodiment includes: a pipeline monitoring circuit 10 and an event printing device 20.

[0041] The pipeline monitoring circuit 10 is used to capture the instruction information of the target instruction during the process of the central processing unit (CPU) processing the target instruction, and to output the instruction information of the target instruction after the execution of the target instruction is completed; the target instruction includes a fused instruction and at least two original instructions corresponding to the fused instruction; The event printing device 20 is used to print the instruction information of the target instruction based on the instruction type corresponding to the target instruction output by the pipeline monitoring circuit 10.

[0042] The production line monitoring circuit 10 and the event printing device 20 can transmit data via a communication connection or an electrical connection.

[0043] Optionally, the target instruction may also include ordinary instructions, i.e., non-fused instructions. Fusion instructions are instructions obtained by fusing at least two original instructions. Both ordinary instructions and fused instructions are instructions that the central processing unit (CPU) needs to execute during operation.

[0044] Optionally, the instruction type includes the fusion type of the fusion instruction.

[0045] In practical applications, a CPU is mainly divided into five pipelines: instruction fetch, decode, issue, execute, and write-back. Instruction fetch corresponds to the PRU-BPU (branch prediction module) and the IFU (instruction fetch module). The decode module is mainly responsible for decoding and issuing. The various execution modules in between—FXU (floating-point execution module), IXU (integer execution module), VXU (vector execution module), and LSU (load-memory module)—are responsible for execution and write-back. The GPC / ROB (General Purpose Controller / Retirement Buffer) manages the instruction exit order under out-of-order execution.

[0046] Optionally, the pipeline monitoring circuit 10 is used to monitor the operating status of the CPU core circuit and capture the instruction information generated by the CPU core circuit at different stages of the instruction pipeline, which includes the fetch stage, decode stage, issue stage, execution stage, and retirement stage.

[0047] Among them, the CPU core circuit is a circuit involved in the tape-out process. The event printing device 20 proposed in this application can help developers understand the CPU's operating status in real time.

[0048] To improve performance, the decoding module provides instruction fusion functionality. The fused instruction becomes a new instruction that includes two or more operations from the original instruction. The execution time that originally required two or more instructions can be combined into one instruction execution time, thereby increasing the CPU's Instructions Per Cycle (IPC). However, for CPU core circuit designers, two key functions are essential: (1) information about the original instructions before instruction fusion is needed to determine whether the subsequent execution logic is correct; and (2) identifying instruction fusion-related instructions to determine whether the instruction fusion logic is correct. Therefore, designing a monitor to monitor instruction fusion is a very necessary task.

[0049] The fusion instruction monitoring system provided in this application includes a pipeline monitoring circuit 10 and an event printing device 20. The pipeline monitoring circuit 10 is used to capture the instruction information of the target instruction during the process of the central processing unit (CPU) processing the target instruction, and to output the instruction information of the target instruction after the execution of the target instruction is completed. Since the target instruction includes a fusion instruction and at least two original instructions corresponding to the fusion instruction, this application embodiment can monitor the execution process of the fusion instruction through the instruction information of the fusion instruction and the instruction information of the original instructions.

[0050] Meanwhile, the event printing device 20 is used to print the instruction information of the target instruction based on the instruction type corresponding to the target instruction output by the pipeline monitoring circuit 10, so that the circuit designer of the CPU core can view the printed instruction information of the target instruction and then check whether there are any abnormalities in the execution of the fused instruction, thereby realizing the monitoring of the fused instruction.

[0051] This application embodiment mainly provides a function to monitor the instruction fusion process independently of the CPU core main circuit under a full-element CPU monitor architecture. It saves all information of the CPU before instruction fusion during the development process and isolates it from the tape-out circuit during the tape-out stage, ensuring that the auxiliary circuits in the development process do not interfere with the final product.

[0052] See Figure 2 As shown in the diagram, this application provides a framework schematic of another monitoring system for fused instructions. Figure 2 As shown, the pipeline monitoring circuit 10 includes a buffer module 11, an update logic module 12, a retirement monitor 15, a rearranged virtual queue 13, and an output queue 14.

[0053] The buffer module 11 is connected to the rearranged virtual queue 13. The buffer module 11 is used to retrieve instruction information from the CPU's decoding module and write the instruction information into the rearranged virtual queue 13.

[0054] The update logic module 12 is connected to the rearranged virtual queue 13. The update logic module 12 is used to monitor the CPU's execution module, capture the instruction execution information generated by the execution module during the target instruction execution stage, and update the instruction information of the target instruction based on the instruction execution information.

[0055] The retirement monitor 15 is connected to the rearranged virtual queue 13. When the retirement monitor 15 captures the signal that the execution of the target instruction has ended, it deletes the instruction information of the target instruction that has ended execution from the rearranged virtual queue 13 based on the number information of the target instruction.

[0056] The rearranged virtual queue 13 is connected to the output queue 14. The rearranged virtual queue 13 is used to output the instruction information of the target instruction that has finished execution to the output queue 14.

[0057] Output queue 14 is used to output the instruction information of the target instruction that has been executed to the event printing device 20.

[0058] Optionally, non-intrusive connections are made between the buffer module 11 and the decoding module, between the update logic module 12 and the execution module in the CPU core circuit, and between the retirement monitor 15 and the general controller or retirement buffer in the CPU core circuit, which helps to separate the monitoring circuit and the actual fabricated circuit.

[0059] Optionally, the instruction execution information includes the final value of the registers, such as the final value of the integer register, the final value of the floating-point register, the final value of the vector register, etc.

[0060] Each target instruction has a corresponding number, namely ROBID, which corresponds to the order information written into the rearranged virtual queue 13.

[0061] Correspondingly, based on the target instruction number information, the instruction information of the target instructions that have finished executing in the Virtual Queue of ROB is deleted, including: based on the target instruction number information, the instruction information of all target instructions that are located before the target instruction number information is deleted.

[0062] Correspondingly, the instruction information of all deleted target instructions will be written to output queue 14 (Output Queue).

[0063] During the execution phase, the modules are executed out of order. The retirement monitor 15 captures the execution completion signal based on the signal characteristics of each module. After capture, it updates the information in the rearrangement virtual queue 13. During the instruction retirement phase, the retirement monitor 15 deletes the relevant instruction information from the rearrangement virtual queue 13.

[0064] See Figure 3 As shown in the diagram, this application provides a framework schematic of another monitoring system for fused instructions. Figure 3 As shown, the buffer module 11 includes a pre-decoding buffer 111, a pre-renaming buffer 112, a post-renaming buffer 113, and a sending buffer 114.

[0065] The pre-decoding buffer 111 is used to capture the instruction information of the target instruction before the decoding module decodes it and output it to the reordered virtual queue 13.

[0066] The pre-renaming buffer 112 is used to capture the instruction information of the target instruction generated by the decoding module during the decoding stage before renaming and output it to the reordering virtual queue 13.

[0067] The renamed buffer 113 is used to capture the renamed instruction information of the target instruction generated by the decoding module during the decoding stage and output it to the reordered virtual queue 13.

[0068] The send buffer 114 is used to capture the instruction information of the target instruction generated by the decoding module during the distribution phase and distribute it to the execution module, and output it to the reordered virtual queue 13.

[0069] Specifically, the pre-dec buffer 111 is used to store instruction information before decoding, mainly including the original information of the fusion instructions and related PC addresses, and specifically captures basic fusion instructions and advanced fusion instructions.

[0070] The pre-renaming buffer 112 is used to store the decoded instruction information before renaming, mainly including the logical register number information and instruction type (e.g., arithmetic instruction) information.

[0071] Post-Ren Buffer 113 is used to store the renamed physical register number information.

[0072] The dispatch buffer 114 is used to store the relevant order and ROBID information of the dispatch, and writes it into the rearranged virtual queue 13 in the order of dispatch.

[0073] In some embodiments, the pre-decoding buffer 111 includes a first fusion buffer module 1111 and a second fusion buffer module 1112, and the fusion instruction includes a first fusion instruction and a second fusion instruction; The first fusion buffer module 1111 is used to capture the instruction information of the first fusion instruction before the decoding module decodes; the first fusion instruction is the instruction obtained by fusing two sequentially consecutive original instructions. The second fusion buffer module 1112 is used to capture the instruction information of the second fusion instruction before the decoding module decodes; the second fusion instruction is the instruction obtained by fusing multiple fusionable original instruction sequences in the same instruction fetching block region.

[0074] This application embodiment can specifically capture basic fusion instructions and advanced fusion instructions.

[0075] Optionally, the first fusion instruction can adopt an adjacent instruction fusion mode. This mode corresponds to the basic fusion instruction, and the relevant operations are completed during the decoding stage. This mode focuses on the fusion of two sequentially consecutive instructions. After the processor core's instruction fetch unit obtains two machine instructions that are immediately adjacent in the program flow, the fusion detection unit will analyze in real time whether they meet the preset fusion conditions.

[0076] Fusion conditions: The core criteria for determining fusion include the operation type of the instructions and register dependencies. A typical condition is that the first instruction is an arithmetic or logical operation instruction (such as addition, subtraction, or comparison), and the second instruction depends on the result of that operation (such as conditional branching or masking operations). Furthermore, the destination registers of the two instructions usually need to be the same, or there should be a direct read-write dependency, to ensure semantic consistency after fusion.

[0077] Hardware Logic and Advantages: Once the conditions are met, the hardware will fuse two instructions into a single fused instruction before the decoding stage. This new instruction is treated as a single unit in subsequent pipeline stages (such as register renaming, issue, and execution). Its advantages lie in directly reducing the number of instructions that need to be scheduled and executed in the pipeline, lowering hardware overhead, and reducing pipeline stalls by resolving data dependencies, thereby improving overall efficiency.

[0078] Optionally, the second fused instruction can adopt the fetch block region fusion mode, which corresponds to the high-level fused instruction, and the related operations are not completed in the decoding stage. This mode is optimized at a higher granularity. Its basic unit is not a fixed number of instructions, but a contiguous address space that the processor fetches from the instruction cache at one time, i.e., a fetch block region (for example, a common implementation is to fetch 16-byte aligned instruction data for each fetch operation).

[0079] Merging conditions and scope: The merging logic analyzes all instructions within the entire instruction fetch block region and identifies multiple merging instruction sequences. These sequences may not be strictly adjacent, but as long as they are located within the same instruction fetch block region and conform to a specific pattern (e.g., consecutive memory operation instructions or simple arithmetic instructions that can be parallelized), they may be merged.

[0080] Hardware Logic and Advantages: Implementing this mode typically requires more complex detection circuitry capable of rapidly scanning the entire instruction block during the fetch or pre-decode phase. Its core advantage lies in maximizing the effective work accomplished in a single instruction fetch. By "packaging" multiple potential operations within an instruction block, it significantly improves instruction-level parallelism and code density, particularly beneficial for data-parallel intensive tasks, such as enhancing performance in vector operations or specific algorithm kernels.

[0081] In some embodiments, the instruction information of the first fusion instruction includes the instruction type, the fusion instruction address, and the binary code instruction information; The instruction information for the second fusion instruction includes the instruction type.

[0082] Optionally, the instruction type of the fusion instruction can be a fusion type, such as basic fusion or advanced fusion.

[0083] See Figure 4 As shown in the figure, this application embodiment provides a schematic diagram of the internal data format of an output queue 14. Table 1 below provides an explanation of the names of the internal data format of the output queue 14.

[0084] Table 1:

[0085] like Figure 4 As shown, 0, 1, and 2 can be used as numbering information.

[0086] Based on the above technical solution, this application embodiment provides a process for fusing instruction capture and the entire lifecycle of captured information. The signal capture and usage process includes steps A1, A2, A3, A4, and A5. Steps A1, A2, A3, and A4 are all executed by the pre-decoding buffer 111.

[0087] A1. Extract the main characteristics of fusion commands and distinguish whether the command type is basic fusion or advanced fusion; A2. Capture target instructions (e.g., the original instructions before fusion), such as PC_Addr and PC_Data; A3. Update the relevant monitoring line information. If it is a basic fusion command, update Fusion Type, Fusion PCAddr, and Fusion PC Data; if it is an advanced fusion command, update Fusion Type. Recording all PC addresses and original commands for advanced fusion commands may consume some resources; simply record the command type.

[0088] A4. Update other information in the monitoring row, such as PC Addr / PC Data, etc. A5. Pass the monitoring line forward and update other instruction information in the process.

[0089] Among them, the key monitoring information and operations are B1 and B2.

[0090] B1, the monitoring information line, is finally written into the rearranged virtual queue 13 after being updated through different processes in the decoding stage.

[0091] B2. The instruction is written to the output queue after execution.

[0092] See also Figure 3 As shown, the event printing device 20 includes a fusion event module 211. The fusion event module 211 is used to print the instruction information of the fusion command and to identify the instruction information of the fusion command.

[0093] Specifically, the event printing device 20 includes a retirement event module 21, which includes a fusion event module 211.

[0094] The Retire Event module 21 prints the result and all information of the instruction after it has been fully executed.

[0095] In some embodiments, the fusion event module 211 is used to identify the instruction type of the first fusion instruction and the fusion instruction address and binary code instruction information of the first fusion instruction if the fusion instruction is a first fusion instruction; and to identify the instruction type of the second fusion instruction if the fusion instruction is a second fusion instruction.

[0096] Specifically, the Fusion Event module 211 prints the result and all information of the instruction after it has been fully executed, and identifies the instruction type (FusionType). The instruction type is displayed as Basic. The binary code and PC address of the instruction type marked as Basic are provided by the binary code instruction information Fusion PC Addr and the fusion instruction address Fusion PCD Data.

[0097] The embodiments of this application can save relevant information on instruction fusion at each stage of the CPU pipeline, and also record the time point of each action, which facilitates chip development to quickly locate problem points and eliminate error functions, and is beneficial for error investigation and debugging of fused instructions.

[0098] See Figure 5 As shown, this application provides a flowchart of a method for monitoring fusion instructions. Figure 5 As shown, the monitoring method for fusion instructions in this application embodiment includes steps S501 to S502.

[0099] S501. During the process of the central processing unit (CPU) processing the target instruction, the pipeline monitoring circuit 10 captures the instruction information of the target instruction. After the target instruction is executed, the instruction information of the target instruction is output to the event printing device 20. The target instruction includes a fused instruction and at least two original instructions corresponding to the fused instruction.

[0100] S502, The event printing device 20 prints the instruction information of the target instruction based on the instruction type corresponding to the target instruction.

[0101] In some embodiments, the event printing device 20 prints instruction information of the target instruction based on the instruction type corresponding to the target instruction, including: The event printing device 20 prints the instruction information of the fusion command through the fusion event module 211 and identifies the instruction information of the fusion command.

[0102] The implementation principle of the fusion instruction monitoring method in this application embodiment is the same as that of the fusion instruction monitoring system in this application embodiment. For details of the fusion instruction monitoring method in this application embodiment, please refer to the detailed description of the fusion instruction monitoring system in the above application embodiment.

[0103] This application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the functions of the fusion instruction monitoring system of this application or the steps of the fusion instruction monitoring method of this application.

[0104] See Figure 6 As shown, this application provides a schematic diagram of the structure of an electronic device 60. Figure 6 As shown, the electronic device 60 of this application embodiment includes: a memory 62, a processor 61, and a computer program 63 stored in the memory 62 and executable on the processor 61. When the processor 61 executes the computer program, it implements the functions of the fusion instruction monitoring system of this application embodiment or the steps of the fusion instruction monitoring method of this application embodiment.

[0105] Electronic device 60 can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. Electronic device 60 may include, but is not limited to, a processor 61 and a memory 62. Those skilled in the art will understand that electronic device 60 may also include more or fewer components, or combinations of certain components, or different components, such as input / output devices, network access devices, etc.

[0106] The processor 61 can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0107] In some embodiments, memory 62 may be an internal storage unit, such as a hard disk or RAM. Memory 62 may be a removable / non-removable, volatile / non-volatile computer system storage medium; for example, memory 62 may be a non-volatile memory used for reading and writing non-volatile magnetic media. In other embodiments, memory 62 may be an external storage device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD) card, flash card, etc., provided on electronic device 60. Memory 62 is used to store operating systems, applications, bootloaders, data, and other programs, such as program code for computer programs. Memory 62 may also be used to temporarily store data that has been output or will be output.

[0108] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0109] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0110] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0111] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc. The storage medium can also include combinations of the above types of memory.

[0112] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0113] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0114] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0115] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A monitoring system with integrated commands, characterized in that, include: A pipeline monitoring circuit is used to capture the instruction information of the target instruction during the process of the central processing unit (CPU) processing the target instruction, and to output the instruction information of the target instruction after the execution of the target instruction is completed; the target instruction includes a fused instruction and at least two original instructions corresponding to the fused instruction; An event printing device is used to print the instruction information of the target instruction based on the instruction type corresponding to the target instruction output by the pipeline monitoring circuit.

2. The monitoring system for fused commands according to claim 1, characterized in that, The pipeline monitoring circuit includes a buffer module, an update logic module, a retirement monitor, a rearranged virtual queue, and an output queue; The buffer module is connected to the rearranged virtual queue. The buffer module is used to retrieve the instruction information from the CPU's decoding module and write the instruction information into the rearranged virtual queue. The update logic module is connected to the rearranged virtual queue. The update logic module is used to monitor the execution module of the CPU, capture the instruction execution information generated by the execution module during the target instruction execution stage, and update the instruction information of the target instruction based on the instruction execution information. The retirement monitor is connected to the rearranged virtual queue. When the retirement monitor detects the signal that the target instruction has finished executing, it deletes the instruction information of the target instruction that has finished executing from the rearranged virtual queue based on the number information of the target instruction. The rearranged virtual queue is connected to the output queue, and the rearranged virtual queue is used to output the instruction information of the target instruction that has finished execution to the output queue; The output queue is used to output the instruction information of the target instruction that has been executed to the event printing device.

3. The monitoring system for fused commands according to claim 2, characterized in that, The buffer module includes a pre-decoding buffer, a pre-renaming buffer, a post-renaming buffer, and a sending buffer. The pre-decoding buffer is used to capture the instruction information of the target instruction before the decoding module decodes it and output it to the rearranged virtual queue; The pre-renaming buffer is used to capture the instruction information of the target instruction generated by the decoding module during the decoding stage before renaming after decoding and output it to the rearranged virtual queue; The renamed buffer is used to capture the renamed instruction information of the target instruction generated by the decoding module during the decoding stage and output it to the rearranged virtual queue; The sending buffer is used to capture the instruction information of the target instruction generated by the decoding module during the distribution phase and distribute it to the execution module, and output it to the rearranged virtual queue.

4. The monitoring system for fused commands according to claim 3, characterized in that, The pre-decoding buffer includes a first fusion buffer module and a second fusion buffer module, and the fusion instruction includes a first fusion instruction and a second fusion instruction; The first fusion buffer module is used to capture the instruction information of the first fusion instruction before the decoding module decodes; the first fusion instruction is the instruction obtained by fusing two sequentially consecutive original instructions. The second fusion buffer module is used to capture the instruction information of the second fusion instruction before the decoding module decodes; the second fusion instruction is an instruction obtained by fusing multiple fusionable original instruction sequences in the same instruction fetching block region.

5. The monitoring system for fusion commands according to claim 4, characterized in that, The instruction information of the first fusion instruction includes the instruction type, the fusion instruction address, and the binary code instruction information; The instruction information of the second fusion instruction includes the instruction type.

6. The monitoring system for fusion commands according to any one of claims 1-5, characterized in that, The event printing device includes a fused event module; The fusion event module is used to print the instruction information of the fusion command and to identify the instruction information of the fusion command.

7. The monitoring system for fusion commands according to claim 6, characterized in that, The fusion event module is used to identify the instruction type of the first fusion instruction, and to identify the fusion instruction address and binary code instruction information of the first fusion instruction if the fusion instruction is a first fusion instruction; and to identify the instruction type of the second fusion instruction if the fusion instruction is a second fusion instruction.

8. A method for monitoring fused commands, characterized in that, include: During the CPU's processing of the target instruction, the pipeline monitoring circuit captures the instruction information of the target instruction. After the target instruction is executed, the instruction information of the target instruction is output to the event printing device. The target instruction includes a fused instruction and at least two original instructions corresponding to the fused instruction. The event printing device prints the instruction information of the target instruction based on the instruction type corresponding to the target instruction.

9. The monitoring method for fusion commands according to claim 8, characterized in that, The step of printing instruction information of the target instruction based on the instruction type corresponding to the target instruction through the event printing device includes: The event printing device prints the instruction information of the fusion command through the fusion event module and identifies the instruction information of the fusion command.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the functions of the monitoring system for fusion instructions as described in any one of claims 1 to 7, or the steps of the monitoring method for fusion instructions as described in any one of claims 8 to 9.

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