Printer USB (Universal Serial Bus) insertion detection method and equipment based on dual delay mechanism

Abstract

The invention relates to the field of pulse circuit and input and output interface control, in particular to a printer USB (Universal Serial Bus) insertion detection method and equipment based on a dual delay mechanism. The method comprises the following steps: performing term registration and dual delay window arrangement by acquiring signals such as a USB insertion trigger level, and constructing a configurable sequential relationship; executing charging and discharging sequence starting and delay endurance processing, and generating an ordered expiration mark sequence; sampling for the first time and sampling for the second time based on the sequence, and constructing a judgment result through consistency comparison; and finally, completing power supply latching, enumeration configuration and state filing according to a judgment result. According to the invention, the anti-interference capability and reliability of insertion detection are effectively improved, and structured management and full-link auditing in the detection process are realized.

Description

Technical Field

[0001] This invention relates to the field of pulse circuits and input / output interface control, and in particular to a printer USB insertion detection method and device based on a dual delay mechanism. Background Technology

[0002] In the field of pulse circuits and input / output interface control, existing solutions for printer USB insertion detection typically involve sampling and determining the USB insertion trigger level and the main power enable signal. These solutions combine the USB interface hardware unit list to load detection points and enumerate session configurations. However, these solutions suffer from limitations such as inconsistent terminology, a lack of unified orchestration for delay links, and a lack of sequence archiving for expiration markers. Existing methods often rely on single-shot recording or lack a coordinated mechanism for debounced delays and expiration trigger binding. In printer USB insertion detection, this can lead to inconsistencies in the triggering relationships between the initial and subsequent sampling records, and a lack of traceable correlation in constructing the insertion determination result structure, making it difficult to achieve stable USB insertion detection. For the joint processing of USB insertion trigger level, main power enable signal, and USB interface hardware unit list, existing technologies generally lack a consistent data field association between the dual delay window configuration structure, delay expiration sequence structure, and insertion judgment result structure. Furthermore, there is a lack of a consistent closed loop between the generation of power latch control field, enumeration session configuration generation, and status archiving processing. This makes it difficult to form a consistent process of acquisition and registration, archiving and alignment, judgment and control, and recording and archiving in printer USB insertion detection. Consequently, it is difficult to establish a continuous correspondence between the startup status record structure and the preceding inputs and intermediate products, thus constraining the consistency of judgment and the traceability of status archiving in the production assembly and debugging process. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a printer USB insertion detection method based on a dual delay mechanism, comprising: Obtain the USB insertion trigger level, main power enable signal, and USB interface hardware unit list; register terminology dictionary entries, delay circuit parameter groups, and perform dual delay window arrangement processing to generate a dual delay window configuration structure. Obtain the dual delay window configuration structure, perform charge / discharge sequence startup, delayed endurance and expiration mark sequence archiving processing, and generate the delayed expiration sequence structure; Based on the delayed expiration sequence structure, the operations of generating the first sampling record, binding the de-shaking delayed expiration trigger, and generating the re-sampling record are performed to construct the insertion judgment result structure. Based on the insertion judgment result structure, the power latch control field is generated, the session configuration is enumerated and the status is archived, and the startup status record structure is generated.

[0004] Furthermore, the process of registering the delay circuit parameter set also includes: The delay circuit parameter group registration process includes component list entries to form a resistor and capacitor component parameter group. The first threshold group of the threshold discrimination unit is read from the parameter group to register the power-on delay parameters, and the second threshold group is read to register the debouncing delay parameters. The power-on delay parameters include a power-on delay threshold identifier, a power-on delay window start event defined as the write time of the main power enable signal trigger edge, a power-on delay window termination event defined as the write time of the first expiration mark output by the delay unit, and a power-on delay rollback condition. The debouncing delay parameters include a debouncing delay threshold identifier, a debouncing delay window start event defined as the completion time of the first sampling record generation action, a debouncing delay window termination event defined as the write time of the second expiration mark output by the delay unit, a debouncing delay trigger dependency defined as the power-on delay expiration mark having been generated and the session not rolled back, and a debouncing delay rollback condition defined as the number of jitter toggles exceeding a threshold. Subsequently, the power-on delay parameters and the debouncing delay parameters are merged.

[0005] Furthermore, the process of dual-delay window orchestration also includes: The dual delay window orchestration process includes constructing the timing relationship of the dual delay windows using delay circuit parameter groups, generating window identifiers, window start and end event sets, threshold group reference sets, expiration mark write address sets, expiration mark circular buffers in running memory, window state fields, rollback condition field groups, and jitter monitoring rule references for the power-on delay window and debouncing delay window, and registering window trigger dependencies and mutual exclusion rules for the debouncing delay window.

[0006] Furthermore, the process of initiating the charge / discharge sequence also includes: The charge / discharge sequence startup process includes: after detecting the main power enable signal trigger edge write, placing the delay unit into the charging working channel, and turning on the main power rail and turning off the discharge unit release channel through the power supply path linkage link; making the threshold discrimination unit discriminate according to the first threshold group through the threshold discrimination linkage link and outputting the first expiration mark when the threshold is met; and continuously reading the rollback condition field group through the abnormal rollback linkage link and triggering rollback when the condition is met.

[0007] Furthermore, the process of extending battery life also includes: The delayed battery life processing includes extracting the de-jitter delay start marker and performing trigger dependency verification. After the verification passes, the threshold discrimination unit is switched to the second threshold group by writing the threshold group selection control field, or the charging path is switched to the second charging path by writing the path switching control field, or the loop is switched to the de-jitter delay loop by writing the loop switching control field, so that the delay unit continues to charge and evolves towards the second threshold group. When the threshold discrimination unit determines that the condition is met.

[0008] Furthermore, the process of generating the initial sampling record also includes: The initial sampling record generation process includes performing a detection point set loading process. This process involves loading three types of detection points—power line detection point signals, positive data line detection point signals, and negative data line detection point signals—by performing port binding, polarity binding, and de-glitch configuration. Subsequently, the detection point sampling unit performs continuous sampling according to the sampling window parameters. The microcontroller unit reads the sampling results and binds them to a noise marker field.

[0009] Furthermore, the process of triggering the binding upon the expiration of the de-shaking delay also includes: The de-jitter delay expiration trigger binding process includes reading the de-jitter delay expiration flag entry in the delay expiration sequence structure, establishing a trigger subscription relationship, and extracting the resampling trigger conditions. The resampling trigger conditions include the consistency condition of the detection point set, the stability condition of the first sampling, and the session state condition.

[0010] Furthermore, the process of resampling and generating records also includes: The resampling record generation process includes writing the resampling trigger condition into the condition latch field of the sampling control register, the detection point sampling unit continuously samples the three detection points again according to the sampling window parameters, and the microcontroller reads the sampling results and generates a record containing a summary of the trigger subscription field and the condition latch field.

[0011] Furthermore, the process of generating the power latch control field also includes: The power latch control field generation process includes generating a latch control template, which includes a latch enable bit, a latch holding condition set including a session identifier consistency condition, a power supply feedback valid condition and a judgment evidence closure condition, and a latch release condition set including an exception code triggered release, a power supply feedback failure release, a trigger source drop release and a timeout release. The microcontroller sets the latch enable bit according to the judgment status field branch matching result and issues a latch request command or a shutdown preparation command.

[0012] Furthermore, a printer USB insertion detection device based on a dual delay mechanism, applied to any of the methods described above, includes: The insertion detection session configuration module is used to obtain the USB insertion trigger level, the main power enable signal, the USB interface hardware unit list, and perform terminology dictionary entry set registration processing to obtain the insertion detection session configuration structure. The dual delay window configuration module is used to extract the parameter group of resistor and capacitor components from the insertion detection session configuration structure and register the power-on delay parameter and the debounce delay parameter to generate the delay circuit parameter group; The delayed expiration sequence generation module is used to obtain the dual delay window configuration structure and perform charge / discharge sequence start-up processing to obtain the power-on delayed expiration mark and generate the delayed expiration sequence structure; The insertion determination module is used to load the detection point set into the delayed expiration sequence structure to obtain the first sampling record and generate the insertion determination result structure. The power latch control module is used to insert the judgment result structure to generate the power latch control field. The enumeration session configuration module is used to extract the enumeration trigger flag from the power latch control field and generate the enumeration session configuration structure. The startup state recording module is used to perform state archiving processing on the enumerated session configuration structure and generate a startup state recording structure.

[0013] The key innovations of this invention include: (1) A dual delay window configuration structure that can be directly called by subsequent processing is formed by using a through link of terminology dictionary entry set registration, delay circuit parameter group registration and dual delay window arrangement processing around the USB insertion trigger level, main power enable signal and USB interface hardware unit list.

[0014] (2) Based on the dual delay window configuration structure, the charging and discharging sequence start-up, delayed endurance and expiration mark sequence archiving are organized into a continuous expiration mark generation and archiving process, and the delayed expiration sequence structure with sequence succession relationship is output.

[0015] (3) Based on the delayed expiration sequence structure, the first sampling record generation, the de-jittering delayed expiration trigger binding and the re-sampling record generation operation are combined into a consistent sampling link and the insertion judgment result structure is constructed. The insertion judgment result structure is then passed to the power latch control field generation, the enumeration session configuration generation and the status archiving process to generate the startup status record structure.

[0016] The following are its main beneficial effects: (1) In view of the inconsistency in link connection caused by the scattered scope of terminology dictionary entries and the lack of unified organization of dual delay windows in the existing scheme, the dual delay window configuration structure solidifies the registration relationship of USB insertion trigger level, main power enable signal, USB interface hardware unit list and delay circuit parameter group within the same data object, so that the subsequent charging and discharging sequence start-up and delay endurance obtain a consistent input reference scope, reducing the configuration reference deviation caused by the difference in scope.

[0017] (2) In view of the lack of sequence archiving of expiration marks in the existing scheme, the triggering basis is difficult to be connected. The delayed expiration sequence structure incorporates the expiration marks generated by the start of the charging and discharging sequence and the delayed battery life into the same sequence object and maintains the sequential association through the expiration mark sequence archiving process. This makes the generation of the first sampling record and the binding of the de-jittering delayed expiration trigger have a verifiable triggering basis source, reducing the break in the triggering relationship caused by the dispersion of expiration marks.

[0018] (3) In view of the inconsistency in the triggering relationship between the generation of the first sampling record and the generation of the second sampling record in the existing scheme, and the lack of connection between the control output and the state retention in the insertion judgment result structure, the de-jittering delay expiration trigger binding establishes a unified triggering link between the generation of the first sampling record and the generation of the second sampling record on the delay expiration sequence structure, and provides consistent judgment input from the insertion judgment result structure to the generation of the power latch control field and the generation of the enumeration session configuration. At the same time, the startup state record structure is formed through state archiving, so that the field reference relationship between the insertion judgment result structure, the power latch control field, and the enumeration session configuration structure remains consistent, reducing the lack of association between judgment, control, and record. Attached Figure Description

[0019] Figure 1 A flowchart illustrating a printer USB insertion detection method based on a dual delay mechanism, provided in an embodiment of this application; Figure 2 This is a structural block diagram of a printer USB insertion detection device based on a dual delay mechanism, provided in an embodiment of this application. Detailed Implementation

[0020] Example 1: Refer to Figure 1 This is a flowchart illustrating a printer USB insertion detection method based on a dual delay mechanism provided in an embodiment of the present invention. The process may include at least steps S100-S400: S100: Obtain the USB insertion trigger level, main power enable signal, and USB interface hardware unit list; register terminology dictionary entries, delay circuit parameter groups, and perform dual delay window arrangement processing to generate a dual delay window configuration structure. S200: Obtain the dual delay window configuration structure, perform charge / discharge sequence startup, delayed endurance and expiration mark sequence archiving processing, and generate the delayed expiration sequence structure; S300: Based on the delayed expiration sequence structure, perform the first sampling record generation, de-jitter delayed expiration trigger binding and re-sampling record generation operations to construct the insertion judgment result structure; S400: Based on the insertion judgment result structure, generate power latch control fields, enumerate session configuration generation and status archiving, and generate startup status record structure.

[0021] Step S100 includes at least steps S110-S130: S110: Obtain the USB insertion trigger level, main power enable signal, and USB interface hardware unit list; perform terminology dictionary entry set registration processing; and obtain the insertion detection session configuration structure. Specifically, this embodiment addresses the overall control link of a printer with Universal Serial Bus (USB) insertion and power-on capability. When insertion occurs, the power and data contacts of the USB interface first make mechanical contact, followed by a USB insertion trigger level generated by the power line detection point on the interface side. This USB insertion trigger level refers to the trigger level formed by the interface-side detection point when the plug contacts and a stable power supply is observed. This trigger level is collected by the detection point sampling unit in the USB interface hardware unit list and converted into the trigger source of the main power enable signal by the switch control unit. The main power enable signal refers to the enable pin level or equivalent control channel level of the power management chip, used to drive the power switch control path into a power-on preparation state. In engineering deployment, the main power enable signal is connected to the printer's standby power rail. The control logic unit powered by the standby power rail continuously monitors the USB insertion trigger level. Upon meeting the trigger conditions, it automatically raises the main power enable signal and writes an event record when the trigger edge arrives.

[0022] In one engineering embodiment, the printer is in a standby power-off state, and the standby power rail only supplies power to the control logic unit and a small number of monitoring circuits. After the user connects one end of the USB cable to the host port and the other end to the printer's USB interface, the power line detection point on the interface side changes the level and generates a USB insertion trigger level. When the USB insertion trigger level meets the trigger condition, the control logic unit pulls up the main power enable signal, the power management chip starts to establish the main power rail, and the delay unit enters the charging and discharging working state. In this scenario, the protection unit in the USB interface hardware unit list first clamps the electrostatic discharge at the moment of insertion, the discharge unit preprocesses the initial residual voltage of the delay unit, and then the microcontroller unit (MCU) enters and executes the terminology dictionary entry set registration processing of this step, forming an insertion detection session configuration structure and writing it into the session queue for automatic continuation and calling in subsequent steps.

[0023] Furthermore, the USB interface hardware unit list is generated during the hardware design phase and includes at least a delay unit, a detection point sampling unit, a switch control unit, a protection unit, and a discharge unit. The delay unit includes a resistor-capacitor (RC) charging / discharging circuit, a threshold discrimination unit, and an expiration marker output channel. The detection point sampling unit includes a power line detection point input channel, a data line positive terminal detection point input channel, a data line negative terminal detection point input channel, and their current-limiting voltage divider network. The switch control unit includes a transistor switching stage, a field-effect transistor switching stage, or an equivalent power switching device and its gate drive network. The protection unit includes electrostatic discharge protection devices, surge suppression devices, and overvoltage clamping devices. The discharge unit includes a discharge diode and a resistor discharge channel, used to release the residual charge of the delay unit to the reference ground in the event of power failure or accidental triggering of a rollback. This list is read by the MCU on the software side and loaded as a hardware mapping table. The hardware mapping table records the connection port identifier, detection point number, sampling polarity, default pull-up / pull-down configuration, exception code mapping, and log writing strategy for each hardware unit.

[0024] During the terminology dictionary entry set registration process, the MCU reads the terminology dictionary entry set version record from non-volatile memory during the startup boot phase. The terminology dictionary entry set is a structured data collection used for unified naming and unified reference, containing at least term names, term definitions, term alias disabling rules, field name mappings, and version number fields. Specifically, the registration process first registers "USB insertion trigger level," "main power enable signal," "USB interface hardware unit list," and "insertion detection session configuration structure" as basic terms, and writes their definitions into the terminology dictionary entry set. Then, parent-child relationships are established for terms such as delay unit, detection point sampling unit, switch control unit, protection unit, and discharge unit within the USB interface hardware unit list, and reference constraints are registered. Furthermore, terms such as "resistor-capacitor component parameter group," "power-on delay parameter," "debouncing delay parameter," "delay circuit parameter group," and "dual delay window configuration structure," which will be used in subsequent steps, are pre-registered as referable terms. This pre-registration includes field naming, data type constraints, and generation source pointers. After the terminology dictionary entry set registration process is completed, the MCU will perform a consistency check between the registration results of this round and the terminology dictionary entry set version record. The check dimensions include term duplication, term missing, alias conflict and reference closure. After the check passes, the new version record will be written to the storage and an auditable registration log will be generated. The registration log records the trigger time, old version number, new version number, change entry summary and rollback flag.

[0025] Based on the aforementioned terminology dictionary entry set registration process, the MCU binds three types of inputs—USB insertion trigger level, main power enable signal, and USB interface hardware unit list—to the same session context, generating an insertion detection session configuration structure as the output field name for this step. The insertion detection session configuration structure includes at least a session identifier, a trigger source field, a hardware mapping table reference, a detection point set reference, a power supply path identifier, a delay unit reference, an exception handling strategy, and a logging strategy. The session identifier is automatically generated by the MCU when it detects the rising edge of the USB insertion trigger level. The trigger source field records the source port of the trigger level and the sampling timestamp. The hardware mapping table reference points to the hardware mapping table obtained from the USB interface hardware unit list. The exception handling strategy includes trigger jitter detection, power backoff detection, and residual voltage discharge detection. The logging strategy includes key field persistence and sampling field rotation. This insertion detection session configuration structure is written to the running memory and simultaneously written to the session queue in non-volatile memory. It is then called as the "insertion detection session configuration structure" input in S120, and its session identifier is used as the associated primary key in the cross-step log archiving of subsequent S200, S300, and S400 steps.

[0026] S120. Extract the resistor and capacitor component parameter group from the insertion detection session configuration structure, register the power-on delay parameter and the debounce delay parameter, and generate the delay circuit parameter group. Specifically, after loading the insertion detection session configuration structure, the MCU locates the component list entry of the delay unit from the hardware mapping table, reads the nominal parameters, tolerance levels, temperature coefficients, mounting point mappings, and detection port connection relationships of the resistors and capacitors related to the delay unit, and forms a resistor-capacitor component parameter group. This parameter group is a structured set of fields describing the charging and discharging behavior of the delay unit, and includes at least the nominal resistance value of the delay resistor, the tolerance of the delay resistor, the nominal capacitance of the delay capacitor, the tolerance of the delay capacitor, the initial discharge path parameters, the input polarity of the threshold discrimination unit, the threshold grouping of the threshold discrimination unit, and the expiration mark output port. In engineering implementation, the nominal resistance value of the delay resistor is often in the tens of thousands of ohms range, the nominal capacitance of the delay capacitor is often in the tens of microfarads range, the initial discharge path parameters are provided by the bleeder unit, and the threshold grouping of the threshold discrimination unit is given by a voltage divider network or a reference source; these parameters are obtained through hardware mapping table references without introducing additional measurement actions.

[0027] When registering power-on delay parameters, the MCU reads the first threshold group from the parameter group of resistor and capacitor components. The first threshold group corresponds to the threshold discrimination condition for power-on delay expiration. The power-on delay parameter registration includes power-on delay threshold identifier, power-on delay threshold source, power-on delay window start event, power-on delay window end event, and power-on delay rollback condition. The power-on delay window start event is defined as the time when the main power enable signal trigger edge is written. The power-on delay window end event is defined as the time when the first expiration mark is written to the delay unit output. The power-on delay rollback condition is defined as the time when the USB insertion trigger level drops and reaches the rollback discrimination threshold during the window period. To support automated operation, the MCU registers trigger conditions and timeout handling conditions simultaneously when registering power-on delay parameters. Trigger conditions are obtained from the trigger source field of the inserted detection session configuration structure, and timeout handling conditions are given by the exception handling strategy. The exception handling strategy points to two paths: power-on rollback judgment and residual voltage discharge judgment. When the rollback condition is met, the MCU outputs a release command to the discharge unit, records the rollback event, and closes the session queue enqueue action.

[0028] During the dejitter delay parameter registration, the MCU reads the second threshold group from the resistor and capacitor component parameter group. This second threshold group corresponds to the threshold discrimination condition for dejitter delay expiration. The dejitter delay parameter registration includes the dejitter delay threshold identifier, the dejitter delay threshold source, the dejitter delay window start event, the dejitter delay window end event, the dejitter delay trigger dependency, and the dejitter delay rollback condition. The dejitter delay window start event is defined as the moment the first sampling record generation action is completed. The dejitter delay trigger dependency is defined as the power-on delay expiration flag being generated and the session not rolling back. The dejitter delay window end event is defined as the moment the second expiration flag is written to the delay unit output. The dejitter delay rollback condition is defined as the USB insertion trigger level toggling multiple times during the dejitter delay window, with the number of toggles exceeding the jitter threshold in the session configuration structure. The jitter threshold is written to the insertion detection session configuration structure as one of the minimum parameter sets. Preferably, the configuration includes threshold templates for different connector structures, but the template selection action is included in the subsequent strategy version record update process and is not discussed in this step.

[0029] After completing the registration of power-on delay parameters and debouncing delay parameters, the MCU merges the two registration results into the same delay circuit parameter group as the output field name for this step. The delay circuit parameter group includes at least a reference to the resistor / capacitor component parameter group, a power-on delay parameter field group, a debouncing delay parameter field group, a threshold group reference, a rollback condition field group, and a log field group. The threshold group reference points to the first and second threshold groups of the threshold discrimination unit. The log field group records the trigger source and version number of each registration action. The delay circuit parameter group is written to the running memory and persisted to the session queue entry. It is then called as the "delay circuit parameter group" input in S130. Simultaneously, its power-on delay parameter field group and debouncing delay parameter field group are referenced in the subsequent expiration flag generation processes in S210 and S220, forming a cross-step parameter consistency association. In terms of version management, the MCU binds the delay circuit parameter group to the session identifier of the insertion detection session configuration structure and writes the parameter group version number. If subsequent steps trigger a rollback and require retry, the system calls the delay circuit parameter group corresponding to the previous stable version number, thereby supporting audit traceability and playback reproduction.

[0030] S130. Perform dual delay window arrangement processing on the delay circuit parameter group to generate a dual delay window configuration structure; Specifically, after receiving the delay circuit parameter group, the MCU reads the power-on delay parameter field group and the debouncing delay parameter field group, and combines them with the threshold group reference given by the resistor and capacitor component parameter group reference to construct the timing relationship of the dual delay window. The dual delay window orchestration process refers to the unified orchestration and solidification of the start and end events, trigger dependencies, mutual exclusion relationships, backoff conditions, and expiration mark write positions of the power-on delay window and the debouncing delay window. The orchestration result is carried by the dual delay window configuration structure. In engineering implementation, the MCU generates a window identifier for each window during the orchestration stage, and the window identifier forms a composite key with the session identifier; and generates an expiration mark write address for each window. The write address is located in the expiration mark circular buffer in the running memory. The circular buffer is maintained by the session queue management module and has two modes: overwrite write and audit mirror write. The audit mirror write mode is enabled in the debug version and disabled in the mass production version. The two are controlled by the policy version record switch field.

[0031] In the power-on delay window orchestration sub-link, the MCU registers the write time of the main power enable signal trigger edge as the window start timestamp, and the write time of the expiration mark corresponding to the first threshold group of the delay unit as the window end timestamp, while also registering the window monitoring point set. The window monitoring point set includes at least a USB insertion trigger level sampling channel, a main power enable signal feedback channel, and a delay unit expiration mark feedback channel; wherein the main power enable signal feedback channel is used to record whether the enable action is accepted by the power management chip, and the delay unit expiration mark feedback channel is used to record the expiration mark output by the threshold discrimination unit. If a USB insertion trigger level drop occurs during the window period and the fallback condition field group is met, the MCU writes the fallback status into the window status field and triggers the discharge unit release action. The release action drives the residual charge release path of the delay unit through the discharge unit control port. After the release is completed, the window status field is written into the session queue entry for subsequent steps to read and determine whether to enter the S200 expiration mark generation link.

[0032] In the dejitter delay window orchestration sub-link, the MCU registers the completion time of the first sampling record generation action as the window start timestamp, and registers the time when the expiration flag corresponding to the second threshold group of the delay unit is written as the window end timestamp. Simultaneously, it registers window trigger dependencies and mutual exclusion rules. The window trigger dependencies at least include that the power-on delay expiration flag has been written and the window status field is in a non-rollback state. The mutual exclusion rules at least include that two dejitter delay window instances cannot be started concurrently under the same session identifier to prevent repeated queuing of windows due to contact jitter. To support automation in engineering scenarios, this embodiment registers jitter monitoring rules within the dejitter delay window. The jitter monitoring rules reference the jitter threshold of the dejitter delay parameter field group and bind the USB insertion trigger level sampling channel. When the number of toggles reaches the threshold, the window status field writes a rollback flag and triggers the release action of the discharge unit, while simultaneously writing a jitter event log to the session queue. The jitter monitoring rules are one of the minimum sets required for core improvements. The jitter threshold and the rollback write position are fixed in the dual delay window configuration structure. The temperature compensation threshold and aging compensation threshold are optional extended functions. If enabled, the compensation switch field is enabled in the policy version record and written to the compensation coefficient table. The compensation coefficient table is generated by the subsequent calibration process.

[0033] After completing the orchestration of both the power-on delay window and the de-jitter delay window, the MCU generates a dual-delay window configuration structure as the output field name for this step. The dual-delay window configuration structure includes at least a session identifier, a window identifier set, a window start / end event set, a threshold group reference set, an expiration flag write address set, a window state field, a rollback condition field group, a jitter monitoring rule reference, and an audit record pointer. The audit record pointer points to the registration log and parameter group version number, and is used in subsequent steps S200 and S210 to call the dual-delay window configuration structure as input to perform charge / discharge sequence startup processing and generate a power-on delay expiration flag. Simultaneously, in S220, the de-jitter delay window orchestration result is referenced to generate a de-jitter delay expiration flag. Furthermore, the session identifier of the dual-delay window configuration structure serves as an association key during the two sampling record generation processes in S300 and as an audit index during the startup state record structure archiving process in S400, thus ensuring data link consistency across main steps.

[0034] In summary, the technical effects of this step are as follows: the dual delay window orchestration process transforms the registration of power-on delay parameters and debouncing delay parameters into executable window start and end events and writes the expiration mark into constraints, so that the output mark of the delay unit and the triggering order of the sampling action remain stable. The linkage between the jitter monitoring rules and the rollback condition field group reduces the repeated window queuing caused by contact bounce. The binding of the audit record pointer with the parameter group version number supports playback reproduction.

[0035] Step S200 includes at least steps S210-S230: S210. Obtain the dual delay window configuration structure, perform charge / discharge sequence start processing, and obtain the power-on delay expiration mark; Specifically, this step is automatically triggered after the dual delay window configuration structure is generated and enters the running state. The dual delay window configuration structure is derived from the output product of the dual delay window arrangement processing of the delay circuit parameter group in the previous step. It is loaded into the session queue entry corresponding to the insertion detection session configuration structure on the running side and bound to the session identifier. The charge / discharge sequence start processing is completed by the delay unit and the switch control unit in the USB interface hardware unit list. During the boot phase, the microcontroller reads the session queue entry to obtain the window start / end event set, threshold group reference set, expiration mark write address set, and backoff condition field group. Then, it registers the trigger edge of the main power enable signal as the start event of the charge / discharge sequence and places the delay unit into the charging working channel. The charge-discharge sequence is a charge state sequence that continuously evolves during the power supply establishment period of the internal resistor-capacitor charge-discharge circuit of the delay unit. It is defined by the parameter group of the resistor and capacitor components, which determines the initial residual voltage release path, charging path impedance, reference ground loop channel and input polarity of the threshold discrimination unit. During the charge-discharge process, the threshold discrimination unit performs threshold discrimination on the capacitor terminal voltage or equivalent sampling node voltage and outputs the corresponding expiration mark.

[0036] In the engineering embodiment, when the printer is in standby mode, the standby power rail supplies power to the control logic unit via the detection point sampling unit. After the USB insertion trigger level is activated, the switch control unit pulls up the main power enable signal, and the power management chip begins to establish the main power rail. During the establishment of the main power rail, there are rising edge jitter, ripple creep, and load access transients. The dual delay window configuration structure is used during this stage to define the power-on delay window start event, the expiration mark write address, and the abnormal rollback condition. After detecting the main power enable signal trigger edge write, the microcontroller writes the charging start state of the delay unit to the session queue entry and simultaneously starts the write pointer of the expiration mark circular buffer. The expiration mark circular buffer is an internal data structure of the session queue management module, which includes the write address, write sequence number, mirror write switch, and audit record pointer. The threshold discrimination unit of the delay unit obtains the first threshold group through the threshold group reference set. The first threshold group corresponds to the power-on delay expiration discrimination threshold. When the threshold discrimination is satisfied, the threshold discrimination unit outputs the first expiration flag in the expiration flag output channel. The switch control unit synchronously sends the flag to the interrupt input or polling input of the microcontroller. After receiving the flag, the microcontroller completes the writing action of the expiration flag writing address set to the address specified by the microcontroller and associates the writing timestamp with the session identifier for hardening.

[0037] Furthermore, the charge / discharge sequence initiation process includes three key processing links: a power supply path linkage link, a threshold discrimination linkage link, and an anomaly fallback linkage link. In the power supply path linkage link, the switch control unit turns on the main power rail after the main power enable signal is valid, simultaneously establishes a connection between the power supply terminal of the delay unit and the main power rail, and puts the release channel of the discharge unit in a closed state to prevent the charging charge from being bypassed by the discharge channel; if the anomaly handling strategy of the inserted detection session configuration structure determines that there is residual voltage that has not been released, the discharge unit is first triggered to perform pre-release, and then the charging working channel is switched after the pre-release is completed. In the threshold discrimination linkage link, the threshold discrimination unit reads the threshold identifier corresponding to the first threshold group and loads the hysteresis configuration. The hysteresis configuration is used for jitter suppression near the threshold, and it exists as an optional extended field in the threshold group reference set of the delay circuit parameter group; when the hysteresis configuration is not loaded, the threshold discrimination unit outputs the expiration mark according to the default single threshold rule. In the abnormal rollback linkage, the microcontroller continuously reads the rollback condition field group, which includes at least the USB insertion trigger level drop judgment, the main power enable signal cancellation judgment, and the jitter event count judgment. When any judgment is true, the microcontroller writes the session queue entry status field to the rollback flag and sends a shutdown command to the switch control unit. The switch control unit shuts down the main power rail and triggers the discharge unit to release the residual charge. Then, it stops the advance of the expiration flag ring buffer write pointer and records the rollback log.

[0038] The power-on delay expiration flag, as the output field name of this step, is generated by the threshold discrimination linkage link. Its fields include at least the session identifier, window identifier, threshold identifier, expiration flag write address, expiration write timestamp, and status verification field. The status verification field is used to characterize whether the session queue entry is in a non-rollback state and whether the main power rail is in a conducting state when the expiration flag is generated, and records the corresponding verification code. After generation, the power-on delay expiration flag is written to the expiration flag circular buffer and is automatically called as the input of the "power-on delay expiration flag" in the subsequent step S220. At the same time, this flag is associated with the audit record pointer of the dual delay window configuration structure, providing a traceable basis for the subsequent steps of extracting the de-jitter delay start flag and the sequential archiving of delay continuation processing. In terms of cross-main step connection, the power-on delay expiration flag participates in the trigger condition binding during the generation of the two sampling records in the subsequent S300, and participates in the establishment of the status link audit index during the archiving of the startup status record structure in the subsequent S400, so that the session identifier of the inserted detection session configuration structure runs through the entire operation link.

[0039] S220. Extract the de-jitter delay start flag from the power-on delay expiration flag, perform delay continuation processing, and generate the de-jitter delay expiration flag. Specifically, this step is triggered after the power-on delay expiration flag is written to the expiration flag circular buffer and the status verification field is written. The microcontroller reads the session identifier and window identifier of the power-on delay expiration flag, retrieves the dual delay window configuration structure under the same session identifier, obtains the trigger dependency and mutual exclusion rules of the debouncing delay window, and performs debouncing delay start flag extraction processing accordingly. The debouncing delay start flag refers to the recordable representation of the start event of the debouncing delay window in the running state, which includes at least the session identifier, debouncing window identifier, start event timestamp, trigger dependency verification code, and event source field. The event source field is used to characterize whether the start event originates from the sampling link preparation stage after the power-on delay expiration flag is triggered or from the completion time of the first sampling record generation action. The two have different event type identifiers in the window start and end event set of the dual delay window configuration structure. In this embodiment, the debouncing delay window start event definition in the window start and end event set is used as the main path, while alternative paths are reserved for use in structural change scenarios.

[0040] In one embodiment, the de-jitter delay start flag is taken from the expiration write timestamp of the power-on delay expiration flag, and this timestamp is registered as the start timestamp of the de-jitter delay window. Subsequently, through delay continuation processing, the delay unit is kept in the charging working channel, allowing the resistor-capacitor charging and discharging circuit to continue evolving from near the first threshold group to the second threshold group. This method is suitable for delay units using a single-capacitor two-threshold discrimination structure, where both the first and second threshold groups discriminate the same sampling node voltage. On the hardware side, the delay continuation processing is manifested as no switching of the charging path, the discharge channel remaining closed, and the threshold discrimination unit switching to the second threshold group. The threshold discrimination unit switching action is completed by the microcontroller issuing a threshold group selection control field. The threshold group selection control field belongs to the threshold group reference set field in the delay circuit parameter group. After the microcontroller writes this field, the threshold discrimination unit performs threshold discrimination according to the second threshold group and outputs the de-jitter delay expiration flag when the threshold is met.

[0041] In another embodiment, the de-jitter delay start flag is taken from the completion time of the first sampling record generation action. This completion time is written into the session queue entry by the session queue management module of the insertion detection session configuration structure and simultaneously written into the event appendage area of ​​the expiration flag circular buffer. This method is suitable for delay units using a two-segment charging path structure. The first charging path uses a larger impedance during the power-on delay phase, and the second charging path uses a smaller impedance or a controlled impedance during the de-jitter delay phase. In this method, the delay continuation processing includes path switching control. The microcontroller unit drives the charging path switching device to switch to the second charging path through the switch control unit, while maintaining the second threshold group loading state of the threshold discrimination unit. Both the path switching control field and the threshold group selection control field are written into the session queue entry as the execution credential for delay continuation processing and are associated with the audit record pointer.

[0042] In another embodiment, the delay unit adopts a dual-capacitor or dual-loop structure. The power-on delay and the de-jitter delay are generated by different resistor-capacitor charging and discharging loops. The delay and battery life processing includes loop switching from the power-on delay loop to the de-jitter delay loop. The loop switching is completed by the switch control unit driving the loop selection device. After extracting the de-jitter delay start flag, the microcontroller writes the loop switching control field and reads the loop switching feedback channel. The loop switching feedback channel belongs to the detection point sampling unit extended input channel of the USB interface hardware unit list. When the feedback channel reaches the loop switching condition, the microcontroller loads the second threshold group and starts the de-jitter delay window counting logic. The counting logic is the software-side timestamp difference recording logic, which is an optional extended function used for debugging and recording, and is not used as the core minimum set parameter. The core minimum set parameter is still the threshold group reference set, the expiration flag write address set, and the same backoff condition field group.

[0043] During the delayed battery life process, the microcontroller continuously performs trigger dependency checks. These checks include at least the following: the power-on delay expiration flag's status field is valid; the session queue entry status field is not rollback; and the main power rail conduction feedback channel is valid. If any check fails, the delayed battery life process enters a rollback path, consistent with the S210 abnormal rollback linkage, including main power rail shutdown, discharge unit release, and log persistence. If the check passes, the threshold discrimination unit performs threshold discrimination on the second threshold group during the delayed battery life process. When the discrimination is satisfied, it outputs the second expiration flag, which in this embodiment is defined as the debouncing delay expiration flag. After receiving the debouncing delay expiration flag, the microcontroller writes the debouncing delay expiration flag to the specified address in the expiration flag write address set, and writes the expiration write timestamp, threshold identifier, and window identifier of the debouncing delay expiration flag field, along with the trigger dependency check code.

[0044] The de-jitter delay expiration flag is used as the output field name for this step. The field includes at least the session identifier, de-jitter window identifier, second threshold identifier, expiration write timestamp, and delay continuation execution fingerprint and state verification field. The delay continuation execution fingerprint is used to characterize the implementation method type used in this delay continuation processing, the threshold grouping selection control field value, and the path switching control field value, for establishing an auditable link during subsequent sequence archiving. After generation, the de-jitter delay expiration flag is written to the expiration flag circular buffer and automatically invoked as the input for the "de-jitter delay expiration flag" in subsequent step S230. Simultaneously, the session identifier of the de-jitter delay expiration flag is referenced in the resampling record generation action trigger binding in subsequent S300, and a mapping relationship is established with the session identifier of the enumerated session configuration structure in the state archiving of subsequent S400, thereby maintaining the continuous operation and audit consistency of the dual delay mechanism link.

[0045] S230. Perform sequence archiving on the de-jittering delay expiration markers to generate a delay expiration sequence structure; Specifically, this step is triggered after the debouncing delay expiration flag is written to the expiration flag circular buffer and the delay continuation execution fingerprint is written. The microcontroller reads the session identifier of the debouncing delay expiration flag and retrieves the power-on delay expiration flag under the same session identifier, thereby forming an expiration flag pair bound to the session identifier. The sequence archiving process is completed collaboratively by the session queue management module and the audit record module. The session queue management module is responsible for writing the expiration flags into the delay expiration sequence structure in window identifier order, and the audit record module is responsible for writing the associated fields into the archiving area pointed to by the audit record pointer and generating an archiving verification code. The delay expiration sequence structure is a data structure that carries an ordered set of events in the running state of the dual delay mechanism. It includes at least a session identifier, a power-on delay expiration flag entry, a debouncing delay expiration flag entry, an entry order field, an archiving timestamp, an archiving verification code, and a rollback associated field. The rollback associated field is used to indicate whether a rollback path is triggered before archiving and records the corresponding rollback log index. If a rollback path is triggered, the delay expiration sequence structure is still written into the single entry status field and recorded as a rollback state for subsequent steps to perform branch processing during loading.

[0046] In the sequence archiving processing chain, the first step is to perform entry integrity verification, which includes session identifier consistency verification, window identifier matching verification, threshold identifier matching verification, and expiration write address consistency verification. If the verification fails, the audit log module writes an exception code and sets the session queue entry status field to archive failure, subsequently triggering the rollback action of the exception handling strategy. Next, the sequence field is generated. Sequence field generation determines the order of power-on delay expiration marker entries based on the window start and end event set of the dual-delay window configuration structure, placing them before the debouncing delay expiration marker entries. Simultaneously, the entry interval timestamp difference record field is written. This field is an optional extended field used for debugging and tracing; the core minimum set remains the entry sequence field and two expiration marker entries. Finally, the archive write is performed. Archive write writes the delayed expiration sequence structure into the sequence archiving area of ​​the session queue entry and writes the archive timestamp and archive checksum into the audit area pointed to by the audit log pointer. The archive checksum is generated by the audit log module according to fixed verification rules, which are bound to the terminology dictionary entry set version record. The version record field is written into the delayed expiration sequence structure, forming a version-auditable archiving chain.

[0047] In the engineering embodiment, after the printer is triggered by USB insertion, it undergoes power-on delay expiration mark generation and debouncing delay expiration mark generation. Sequence archiving is automatically executed after the main power rail is established and stabilized into the running state. The delay expiration sequence structure is written to the running memory and synchronously written to the session queue mirror area of ​​the non-volatile memory. The mirror area writing is determined by the control switch field of the audit record module, and the switch field comes from the log policy of the insertion detection session configuration structure. The mirror area writing is an optional extended function. In the mass production configuration, it can be turned off and the archive checksum and key fields can be retained. The key fields include at least the session identifier, two expiration mark entries and the archive timestamp. After the delay expiration sequence structure is generated, it is used as the output field name of this step and is called by the "delay expiration sequence structure" input in the subsequent step S310. It is used to bind the trigger condition of the detection point set loading and the generation of the first sampling record. At the same time, the archive checksum and version record field in the delay expiration sequence structure are referenced in the startup status record structure archiving in the subsequent step S400, forming an audit closed loop across the main steps.

[0048] In summary, the technical effects of this step are as follows: Sequence archiving establishes an ordered archive based on the session identifier for the power-on delay expiration marker and the debouncing delay expiration marker, and solidifies the archive verification code, so that subsequent sampling trigger binding has a stable event input boundary. The combination of mirroring the archive area and writing the same version record field ensures that the running link has a consistent traceability basis in retry and replay scenarios.

[0049] Step S300 includes at least steps S310-S330: S310. Based on the delayed expiration sequence structure, perform detection point set loading processing to obtain the first sampling record; Specifically, this step is automatically triggered by the session queue management module corresponding to the insertion detection session configuration structure after the delayed expiration sequence structure is generated in the previous step. The delayed expiration sequence structure is the output product after the sequence archiving of the power-on delayed expiration mark and the debouncing delayed expiration mark. It contains a session identifier, an entry order field, an archiving timestamp, and an archiving verification code. After the microcontroller reads the delayed expiration sequence structure from the session queue entry, it first performs archiving verification and simultaneously reads the hardware mapping table reference in the insertion detection session configuration structure. Then, it locates the power-on delayed expiration mark entry according to the entry order field and uses the entry status as the starting condition for the first sampling action. When the entry status is non-backoff and the window identifier matches, the microcontroller enters the detection point set loading processing link.

[0050] The loading and processing of the detection point set is completed collaboratively by the microcontroller unit and the detection point sampling unit in the USB interface hardware unit list. Specifically, the microcontroller unit reads the detection point set definition based on the hardware mapping table. The detection point set is defined as a structured set of three types of detection points: power line detection point signals, data line positive terminal detection point signals, and data line negative terminal detection point signals. The power line detection point signals come from the detection point sampling channel of the interface power supply path, while the data line positive terminal detection point signals and data line negative terminal detection point signals come from two sampling channels of the interface data path. All three are connected to the input port of the detection point sampling unit through a current limiting and voltage dividing network. The loading process includes three consecutive steps: port binding, polarity binding, and de-glitch configuration loading. The port binding step maps the three types of detection points to the sampling channel number and writes this mapping into the detection point set reference field of the session queue entry. The polarity binding step writes a high-level active or low-level active flag for each detection point based on the hardware mapping table reference, preventing misreading due to inversion under the same decision logic for different circuit models. The de-glitch configuration loading step reads the sampling method identifier and sampling window parameters from the inserted detection session configuration structure and writes these parameters into the sampling control register of the detection point sampling unit. The sampling window parameters, as one of the minimum parameter sets required for the core improvement of this invention, include sampling start delay, single sampling hold time, and consecutive sampling count. The sampling start delay is bound to the expiration timestamp of the power-on delay expiration flag entry, used to avoid transient disturbances during the power supply rail and main control initialization phase. The temperature compensation sampling window and aging compensation sampling window are optional extended functions, participating in the writing of the sampling control register only when the strategy version record switch field is enabled.

[0051] After completing the loading of the detection point set, the microcontroller performs the initial sampling action and generates the initial sampling record. On the hardware side, the initial sampling action is performed by the detection point sampling unit. This unit continuously samples the three detection points according to the sampling window parameters and normalizes each sampling result to a valid or invalid state based on its polarity. Simultaneously, it writes the number of flips during the sampling process into the noise flag field. On the software side, the microcontroller reads the sampling output buffer of the detection point sampling unit, binds the valid or invalid state of the three detection points to the noise flag field with a session identifier, and writes it to the session queue entry, forming the initial sampling record as the output field name for this step. The initial sampling record includes at least the session identifier, sampling timestamp, detection point set reference, three-channel detection point status field, sampling method identifier, noise flag field, and power supply feedback field. The power supply feedback field comes from the switch control unit feedback channel in the USB interface hardware unit list and is used to record the main power enable signal feedback and the main power rail conduction feedback. In terms of anomaly handling, if the noise marker field reaches the jitter event count threshold during sampling, the microcontroller writes the anomaly code to the initial sampling record and simultaneously writes it to the log area pointed to by the audit record pointer. However, the initial sampling record output is still completed, allowing subsequent steps to continue trigger binding and resampling processing based on the same session identifier. This initial sampling record, after being generated, is called as the "initial sampling record" input for S320 and is associated with the archive checksum of the delayed expiration sequence structure in the cross-main step link, providing traceable input evidence for subsequent insertion of the judgment result structure.

[0052] S320. Extract the resampling trigger condition from the initial sampling record, bind the de-jitter delay expiration trigger, and generate a resampling record; Specifically, this step is automatically triggered by the microcontroller unit after the initial sampling record is written into the session queue entry. The microcontroller unit reads the session identifier, detection point set reference, three-way detection point status field, sampling method identifier, and noise marker field from the initial sampling record, and simultaneously reads the de-jitter delay expiration marker entry in the delay expiration sequence structure. Both are arranged under the same session identifier for trigger condition orchestration, thereby completing the extraction of resampling trigger conditions and the binding of de-jitter delay expiration triggers. The resampling trigger conditions are a set of structured conditions required to initiate the resampling action, which includes at least the detection point set consistency condition, the initial sampling stability condition, and the session status condition: the detection point set consistency condition means that resampling must reuse the detection point set reference in the initial sampling record and reuse the polarity binding marker to prevent inconsistencies between the input space of resampling and the initial sampling; the initial sampling stability condition means that the noise marker field has not reached the jitter event counting threshold or, although it has reached the threshold, the abnormal handling strategy allows entry into the reconfirmation process; the session status condition means that the session queue entry status field is in a non-back-off state and the main power rail conduction feedback is effective. The resampling trigger condition is a minimum set of parameters required for core improvements. When bound to the debouncing delay expiration flag entry, it forms the entry point for the "sampling-delay-reconfirmation" decision logic.

[0053] During the debouncing delay expiration trigger binding process, the microcontroller establishes a trigger subscription relationship based on the expiration write timestamp of the debouncing delay expiration marker entry. This trigger subscription relationship is maintained by the session queue management module, which maps the arrival event of the debouncing delay expiration marker entry to a trigger event for the resampling action. Specifically, the microcontroller writes a trigger subscription field into the session queue entry. This field includes a session identifier, a debouncing window identifier, an expiration marker write address, and a callback action identifier. The callback action identifier points to the resampling action execution routine. When the session queue management module detects that the debouncing delay expiration marker entry has been written and the archive checksum verification has passed, the trigger subscription field drives the callback action identifier to take effect, and the microcontroller enters the resampling action execution. This trigger subscription field writing action is bound to the policy version record switch field. The policy version record switch field is controlled by the version number field, which is fixed by the terminology dictionary entry set registration processing. The version number field is written into the session queue entry and enters the log area pointed to by the audit record pointer, thereby maintaining the stability and auditability of the trigger binding rules during system evolution.

[0054] The resampling action is continued on the hardware side by the detection point sampling unit, reusing the sampling method identifier and sampling window parameters from the initial sampling record as the default configuration. In some engineering scenarios, the resampling action allows loading extended sampling window parameters. These extended parameters are used to increase the sampling hold time during the contact bounce attenuation phase. This parameter is an optional extended function, loaded only when the policy version record switch field is enabled, and does not constitute the minimum set required for the core improvement of this invention. Before executing the resampling action, the microcontroller first writes the resampling trigger condition into the condition latch field of the sampling control register. The condition latch field is used to record whether the current resampling action is triggered by the debouncing delay expiration event, whether it passes the session state condition verification, and whether it passes the initial sampling stability condition verification. Subsequently, the detection point sampling unit continuously samples the three detection points according to the sampling window parameters and outputs the normalized state. The microcontroller reads the sampling output buffer and generates a resampling record as the output field name for this step. The resampling record includes at least a session identifier, sampling timestamp, detection point set reference, three-way detection point status field, sampling method identifier, noise marker field, trigger subscription field summary, and condition latch field. The trigger subscription field summary records the debouncing window identifier and expiration write timestamp, while the condition latch field records the trigger condition verification result. For exception handling, if the session status condition fails during resampling, such as the main power rail conduction feedback becoming invalid, the microcontroller unit writes the failure status to the resampling record and synchronously writes it to the log area, while maintaining the session identifier unchanged. This ensures that subsequent consistency comparison processing can complete the decision branch based on the same session identifier. After generation, this resampling record is used as input to the S330's "resampling record" and forms a paired input with the initial sampling record under the same session identifier, for subsequent insertion of the decision result structure.

[0055] S330. Perform consistency comparison processing on the first sampling record and the re-sampling record to generate the insertion determination result structure; Specifically, this step is automatically triggered by the microcontroller unit after the resampling record is written into the session queue entry. The microcontroller unit reads the detection point set reference, the three-way detection point status field, the noise marker field, and the power supply feedback field from the initial sampling record, and reads the detection point set reference, the three-way detection point status field, the noise marker field, the condition latch field, and the trigger subscription field summary from the resampling record. It also reads the entry order field and the archive check code in the delayed expiration sequence structure, and then enters the consistency comparison processing link. The consistency comparison processing is a process of jointly judging the input consistency and state consistency of two samples under the same session identifier. It includes three consecutive links: input consistency verification, state consistency verification, and result solidification. The input consistency verification link first verifies whether the detection point set references of the two records are consistent, whether the polarity binding markers are consistent, and whether the sampling method identifiers are consistent. If any verification fails, the microcontroller unit sets the judgment result to invalid and writes the input inconsistency exception code, and writes the exception code to the log area pointed to by the audit record pointer. The state consistency verification step is executed after the input consistency verification is passed. It aligns the state fields of the three detection points item by item and generates consistency tags according to the consistency rules. The consistency rules are referenced by the judgment rule version field in the insertion detection session configuration structure. The judgment rule version field is registered, processed, solidified by the terminology dictionary entry set and written into the session queue entry, so that the consistency comparison process has auditable rule anchors in different version evolutions.

[0056] There are multiple ways to implement consistency rules in engineering. This embodiment provides three implementation methods and selects and binds them through the rule version field. In technical solution one, the consistency rule adopts strict consistency discrimination. When the status fields of the three detection points are both valid in two sampling records and the power supply feedback field remains valid, the consistency flag is set to true. When any detection point alternates between valid and invalid in two samplings, the consistency flag is set to false, and the difference of the corresponding detection point is written into the difference location field. The difference location field records the detection point number and the difference type. In technical solution two, the consistency rule adopts master-slave consistency discrimination. The power line detection point signal is used as the master discrimination item, and the positive and negative data line detection point signals are used as slave discrimination items. When the master discrimination item is valid in both samplings and the power supply feedback field remains valid, the consistency flag enters a temporary state. Then, it is confirmed by combining the consistency of the two samplings of the slave discrimination item. If the slave discrimination item has jitter but the noise flag field is within the allowable range, the consistency flag is set to true and the jitter fragment is written into the jitter annotation field. The jitter annotation field records the number of flips and the sampling timestamp range. In technical solution three, the consistency rule adopts conditional latch constraint discrimination. The conditional latch field in the resampled record is used as the pre-constraint of the consistency rule. Only when the pre-constraint shows that the resampling is triggered by the debouncing delay expiration event and the session state condition verification passes, does it enter the consistency verification of the three-way detection point state field. If the pre-constraint is not met, the consistency flag is set to invalid and the trigger link exception code is recorded. The trigger link exception code is bound to the trigger subscription field summary for easy subsequent audit playback and location. None of the above three technical solutions introduce additional hardware units. They only reuse the detection point sampling unit and the session queue management module. The core minimum set parameters are still the detection point set reference, the three-way detection point state fields of the two sampling records, the archive check code of the delay expiration sequence structure and the judgment rule version field. The jitter annotation field and the difference location field are optional extended fields used for debugging and tracing. When the policy version record switch field is closed, the insertion judgment result structure is still output but not written to the extended fields.

[0057] In the decision result solidification stage, the microcontroller writes the consistency flag, consistency rule version, session identifier, decision timestamp, and decision evidence summary into the inserted decision result structure as the output field name for this step. The inserted decision result structure includes at least the session identifier, decision status field, decision timestamp, decision rule version field, evidence chain field, and exception code field. The evidence chain field includes the archive checksum of the delayed expiration sequence structure, the reference index of the first sampling record and the resampling record, the power supply feedback field summary, and the trigger subscription field summary. The exception code field is used to record situations such as input consistency verification failure, trigger link anomaly, or status consistency verification failure. The inserted decision result structure is written to the decision area of ​​the session queue entry and simultaneously written to the log area pointed to by the audit record pointer. It is then called as the "inserted decision result structure" input of S410 for power latch control field generation processing. Simultaneously, the decision rule version field and the decision evidence summary in the inserted decision result structure continue to be referenced in the subsequent enumeration of session configuration structure generation and startup status record structure archiving, thus maintaining a data loop under the same session identifier across the main step links.

[0058] In summary, the technical effects of this step are as follows: The consistency comparison process performs input consistency verification and state consistency verification on the two sampling records under the same session identifier, and incorporates the archive check code of the delayed expiration sequence structure into the evidence chain field, thereby isolating the sampling differences between the power supply transient and contact bounce phases within the scope of the judgment rules. After inserting the judgment result structure output, it provides a stable judgment input for power supply latching and enumeration triggering.

[0059] Step S400 includes at least steps S410-S430: S410. Based on the insertion determination result structure, perform power latch control field generation processing to obtain the power latch control field; Specifically, this step is triggered after the previous steps generate the insertion determination result structure and complete the writing of the session queue entries. The microcontroller unit reads the session identifier, determination status field, determination rule version field, evidence chain field, and exception code field from the insertion determination result structure, and simultaneously reads the main power enable signal binding relationship and exception handling strategy from the insertion detection session configuration structure. The power latch control field generation process is completed collaboratively by the microcontroller unit and the switch control unit in the USB interface hardware unit list. The switch control unit includes a power switching device drive channel, a latch feedback channel, and a shutdown control channel. The microcontroller unit locates these three types of channels through a hardware mapping table and loads the latch control template. The latch control template is a structured set of fields, including at least the latch enable bit, latch hold condition set, latch release condition set, latch status verification field, and latch log field. The latch hold condition set is used to constrain the validity of the trigger source and the consistency of the session state during the main power rail conduction hold period. The latch release condition set is used to define the shutdown path when triggering rollback, timeout, or exception code. The latch status verification field is used to record the feedback from the switch control unit at the moment of latch action. The latch log field is used to record the latch action sequence number, version number, and audit record pointer.

[0060] When generating the latch control template, the microcontroller unit first performs branch matching on the judgment status field. If the judgment status field is true, it enters the latch enable bit writing path; if the judgment status field is false or the exception code field exists, it enters the latch release condition set preset path. In the latch enable bit writing path, the microcontroller unit sets the latch enable bit to be valid and writes the session identifier into the latch log field, then sends a latch request command to the switch control unit. After receiving the latch request command, the switch control unit switches the main power switch device drive channel to latch conduction mode and outputs the latch feedback level in the latch feedback channel. The microcontroller unit reads the latch feedback level and writes it into the latch status verification field. The latch holding condition set is generated synchronously in this path. The generation process includes three types of condition solidification: first, the session identifier consistency condition, which requires that subsequent enumeration of session configuration generation and startup status archiving all reference the same session identifier; second, the power supply feedback validity condition, which requires that the main power rail conduction feedback channel is in a valid state; and third, the judgment evidence closure condition, which requires that the archived verification code in the evidence chain field exists and passes verification with the sampling record index. The above three types of conditions constitute the minimum set of latching actions. Temperature compensation release conditions and retry count limit conditions are optional extended functions, which are only written into the latch holding condition set when the policy version record switch field is enabled.

[0061] In the preset path of the latch release condition set, the microcontroller invalidates the latch enable position and generates a release condition set field. This field contains at least four types of conditions: exception code-triggered release, power supply feedback failure release, trigger source drop release, and timeout release. Exception code-triggered release is driven by the exception code field; power supply feedback failure release is driven by the switch control unit feedback channel; trigger source drop release is driven by the USB insertion trigger level readback channel; and timeout release is driven by the timeout counter maintained by the session queue management module. The timeout counter's start time references the judgment timestamp of the insertion judgment result structure and is written to the latch log field, forming an auditable start point. After writing the release condition set field, the microcontroller issues a shutdown preparation command to the switch control unit. The switch control unit puts the shutdown control channel in standby mode, and the microcontroller executes the shutdown action according to the conditions before and after the subsequent S420 enumeration trigger flag generation, thereby maintaining the consistency between the power latch control field and the enumeration link.

[0062] Once the latch control template is generated, the microcontroller unit (MCU) embeds it as the power latch control field as the output field name for this step and writes it to the latch control area of ​​the session queue entry. Simultaneously, the latch status verification field and latch log field are written to the log area pointed to by the audit record pointer. After being written, the power latch control field is read by the S420's "Power Latch Control Field" and used for enumerating trigger flag extraction and session configuration generation. Furthermore, the latch holding condition set in the power latch control field establishes a reference relationship with the status link field of the startup status record structure in the S430 status archive, thus ensuring that latching actions, enumeration actions, and archiving actions remain connected under the same session identifier.

[0063] S420. Extract the enumeration trigger flag from the power latch control field, generate the enumeration session configuration, and generate the enumeration session configuration structure. Specifically, this step is triggered after the power latch control field is written to the session queue entry. The microcontroller reads the latch enable bit, latch hold condition set, latch status verification field, and latch log field from the power latch control field, and simultaneously reads the judgment status field and judgment rule version field of the insertion judgment result structure. Then, it performs enumeration trigger flag extraction processing. The enumeration trigger flag is a structured event flag that drives the Universal Serial Bus (USB) device enumeration process. It includes at least a session identifier, trigger type field, trigger timestamp, latch verification field, and trigger evidence summary field. The trigger type field distinguishes between first-time insertion triggers, retry triggers, and recovery triggers. The trigger timestamp is written by the session queue management module. The latch verification field is generated by mapping the latch status verification field, and the trigger evidence summary field is generated by mapping the judgment evidence closure condition.

[0064] In the enumeration trigger flag extraction process, the microcontroller unit verifies the validity of the latch enable bit and performs item-by-item verification of the latch holding condition set. Each item-by-item verification includes at least session identifier consistency verification, power supply feedback validity verification, and decision evidence closure verification. If any verification fails, the microcontroller unit sets the trigger type field of the enumeration trigger flag to a suppressed state, writes the suppression reason code to the trigger evidence summary field, and simultaneously calls the latch release condition set in the power latch control field, issuing a shutdown command to the switch control unit and writing it to the log. If the verification passes, the microcontroller unit generates an enumeration trigger flag and writes it to the trigger area of ​​the session queue entry, then proceeds to the enumeration session configuration generation process. The enumeration session configuration generation process is completed collaboratively by the microcontroller unit and the interface control path in the USB interface hardware unit manifest. The interface control path is a set of control register mappings corresponding to the microcontroller unit's internal peripheral control module or independent interface control chip. The microcontroller unit locates and loads this control register mapping through a hardware mapping table.

[0065] The enumeration session configuration structure is a structured data structure that carries the parameters required for the enumeration process execution, the state machine entry point, and the exception rollback strategy. It includes at least the session identifier, enumeration trigger flag reference, bus reset configuration field, speed negotiation configuration field, address allocation configuration field, descriptor read configuration field, retry policy field, and log policy field. The bus reset configuration field defines the reset pulse generation method, reset hold time, and reset completion wait time; the speed negotiation configuration field defines the discrimination entry point and discrimination sampling window for full-speed mode, low-speed mode, or high-speed mode; the address allocation configuration field defines the address write sequence number and address conflict handling; the descriptor read configuration field defines the read order and buffer write position of device descriptors, configuration descriptors, and interface descriptors; the retry policy field defines the number of retries, retry interval, and retry trigger type field when enumeration fails; and the log policy field defines the granularity of writing audit record pointers for key enumeration events. Among the above fields, the bus reset configuration field, address allocation configuration field, and descriptor read configuration field constitute the minimum set of enumerated parameters. The speed negotiation configuration field and retry policy field are optional extended functions, but they can be enabled in multi-model host compatibility scenarios and are controlled by the policy version record switch field.

[0066] In one engineering embodiment, after the printer is inserted into the host via a USB cable, insertion is determined and the power latch state is entered. The microcontroller unit generates an enumeration trigger flag and loads the enumeration session configuration structure. Subsequently, the microcontroller unit generates a reset pulse according to the bus reset configuration field driving the interface control path, and enters the speed discrimination sampling window after the reset completion waiting time has elapsed. If the speed negotiation configuration field is in the closed state, execution continues according to the default full-speed mode entry. Next, the microcontroller unit completes the address writing sequence number registration according to the address allocation configuration field, and initiates a descriptor read request according to the descriptor read configuration field. The read descriptor data is written to the descriptor buffer of the enumeration session configuration structure. The descriptor buffer contains the data buffer address, length field, and verification field. If a timeout or verification failure occurs during the descriptor read process, the microcontroller unit triggers a retry according to the retry policy field and writes it to the retry log. When the number of retries reaches the upper limit or the latch holding condition set fails, the microcontroller unit calls the latch release condition set to execute the main power rail shutdown and exit the session queue. In this engineering embodiment, both the enumeration trigger flag reference and the descriptor cache reference are written into the enumeration session configuration structure, thereby enabling subsequent state archiving to have a traceable enumeration evidence chain.

[0067] After the enumeration session configuration generation process is completed, the microcontroller writes the generated enumeration session configuration structure as the output field name of this step into the enumeration configuration area of ​​the session queue entry, and writes the enumeration trigger flag and retry log into the log area pointed to by the audit record pointer. After being written, the enumeration session configuration structure is read by the "Enumeration Session Configuration Structure" of S430 and used for status archiving. At the same time, the retry policy field and log policy field in the enumeration session configuration structure establish cross-field references with the latch log field of the power latch control field, so that the enumeration link and the latch link have a consistent audit anchor point under the same session identifier.

[0068] S430. Perform state archiving processing on the enumerated session configuration structure to generate a startup state record structure; Specifically, this step is triggered after the session queue entry is written into the enumerated session configuration structure. The microcontroller reads the session identifier, enumeration trigger flag reference, bus reset configuration field, address allocation configuration field, descriptor read configuration field, retry policy field, and descriptor buffer reference from the enumerated session configuration structure. Simultaneously, it reads the latch hold condition set and latch status verification field from the power latch control field, and simultaneously reads the judgment rule version field and evidence chain field from the insertion judgment result structure. Then, it performs status archiving. This status archiving is completed collaboratively by the session queue management module and the audit record module. The session queue management module is responsible for aggregating the relevant fields of this startup link according to the session identifier, and the audit record module is responsible for generating the archiving verification code and writing it to the archiving area pointed to by the audit record pointer.

[0069] The state archiving process consists of three consecutive actions: state snapshot acquisition, state link concatenation, and archive writing. In the state snapshot acquisition phase, the microcontroller reads the enumeration state registers of the main power rail conduction feedback channel, latch feedback channel, and interface control path, maps them to state snapshot fields, and writes them to the running state field of the startup state record structure. The running state field includes at least the power latch state, enumeration phase state, descriptor reading phase state, and error code field. In the state link concatenation phase, the session queue management module sequentially writes the evidence chain field of the inserted judgment result structure, the archive checksum of the delayed expiration sequence structure, the index of the two sampling records, the enumeration trigger flag reference, and the descriptor buffer reference into the state link field. The state link field is an auditable link summary field, used to reproduce the key input-output relationships of this session in power-down restart or audit playback scenarios. During the archiving and writing phase, the audit log module generates an archiving verification code for the startup status record structure and writes it into the archiving verification code field. At the same time, it writes it into the version record field. The version record field references the terminology dictionary entry set version record, the judgment rule version field, and the log strategy field of the enumerated session configuration structure, so that the records at different version evolution stages have stable anchor points.

[0070] During state archiving, exception handling and rollback strategies are also written into the startup state record structure. Specifically, when the retry strategy field indicates that the enumerated retries have reached the upper limit or the latch holding condition set has failed, the microcontroller writes the rollback status into the running state field and calls the latch release condition set to execute a shutdown action. Simultaneously, it writes the shutdown trigger source field and shutdown timestamp into the state link field. When the verification field of the descriptor reading configuration field continuously fails, the microcontroller writes the failure reason code into the error code field and retains the descriptor cache reference, enabling subsequent troubleshooting to pinpoint the failure stage. When the exception code field of the inserted judgment result structure exists, the microcontroller still generates the startup state record structure but writes the judgment state field summary into the running state field, thus maintaining record integrity under the same session identifier. The above exception handling paths do not change the step link order; they only change the execution branches of the running state field and the shutdown action, ensuring the system maintains a consistent data structure output across multiple scenarios.

[0071] After the status archiving process is completed, the microcontroller outputs the startup status record structure as the output field name for this step and writes it to the status archiving area of ​​the session queue entry. Simultaneously, the archiving checksum field is written to the archiving area pointed to by the audit record pointer. After archiving, the startup status record structure serves as the audit input for the system startup link, invoked by the log policy of the insertion detection session configuration structure. Subsequently, after S110 generates the insertion detection session configuration structure, it is loaded into the session queue entry of the insertion detection session configuration structure by the session queue management module, serving as the source for retry triggering version comparison. This forms a closed data link with the preceding delay circuit parameter group, the dual delay window configuration structure, and the enumerated session configuration structure.

[0072] In summary, the technical effects of this step are as follows: The status archiving process aggregates key fields such as insertion judgment, delay expiration, double sampling, latch control, and enumeration session configuration by session identifier and generates an archive verification code. This enables the startup chain to have a reproducible evidence chain summary in power failure restart and audit playback scenarios. At the same time, the shutdown branch and error code are written into the running status field, so that subsequent retry triggers have traceable status input.

[0073] Example 2: Figure 2 A structural block diagram of a printer USB insertion detection device based on a dual delay mechanism according to an embodiment of the present invention is shown. Figure 2 As shown, the structure may include: The insertion detection session configuration module 01 is used to acquire the USB insertion trigger level, the main power enable signal, and the USB interface hardware unit list, and perform terminology dictionary entry set registration processing to obtain the insertion detection session configuration structure. Specifically, the insertion detection session configuration module receives the externally input USB insertion trigger level and main power enable signal, and synchronously receives the USB interface hardware unit list as the input object of the same session. It performs level type registration and trigger edge registration for the USB insertion trigger level, enable caliber registration and hold caliber registration for the main power enable signal, and list entry registration and checklist registration for the USB interface hardware unit list. The terminology dictionary entry set registration process writes the terminology entries of the USB insertion trigger level, the main power enable signal, and the USB interface hardware unit list into the same registration set and forms corresponding reference relationships within the insertion detection session configuration structure. The insertion detection session configuration structure is provided as an output product to the dual delay window configuration module and read by the dual delay window configuration module. At the same time, the insertion detection session configuration structure provides the loading reference of the USB interface hardware unit list to the insertion determination module, so that the detection point set loading process is consistent with the USB interface hardware unit list.

[0074] The dual delay window configuration module 02 is used to extract the resistor and capacitor component parameter groups from the insertion detection session configuration structure and register the power-on delay parameters and debouncing delay parameters to generate a delay circuit parameter group. It then performs dual delay window arrangement processing on the delay circuit parameter group to generate a dual delay window configuration structure. Specifically, the dual delay window configuration module receives the insertion detection session configuration structure output by the insertion detection session configuration module as input, extracts the resistor and capacitor component parameter groups from the insertion detection session configuration structure, and completes parameter caliber verification and parameter group entry merging. The power-on delay parameter registration registers power-on delay parameter entries within the delay circuit parameter group and binds them to the... The registration caliber of the main power enable signal, the registration of the debouncing delay parameter in the delay circuit parameter group, and the binding of the trigger edge registration of the USB insertion trigger level; the dual delay window orchestration process establishes the window order relationship between the power-on delay window and the debouncing delay window in the delay circuit parameter group, and registers the window reference, expiration mark output caliber, and window switching conditions in the dual delay window configuration structure, so that the dual delay window configuration structure is provided as an output product to the delay expiration sequence generation module and read by the delay expiration sequence generation module, and the dual delay window configuration structure retains the reference relationship with the insertion detection session configuration structure for subsequent archiving association.

[0075] The delayed expiration sequence generation module 03 is used to obtain the dual delayed window configuration structure and perform charge / discharge sequence startup processing to obtain a power-on delayed expiration mark, extract a de-jittering delayed start mark from the power-on delayed expiration mark and perform delayed battery life processing to generate a de-jittering delayed expiration mark, and perform sequence archiving processing on the de-jittering delayed expiration mark to generate a delayed expiration sequence structure. Specifically, the delayed expiration sequence generation module receives the dual delayed window configuration structure output by the dual delayed window configuration module as an input object, reads the window order relationship and expiration mark output caliber from the dual delayed window configuration structure and performs charge / discharge sequence startup processing. When the first window in the window order relationship corresponds to the power-on delayed window, the charge / discharge sequence startup processing generates a power-on delayed expiration mark and registers the expiration time. The information is as follows: the de-jitter delay start flag is extracted by the window switching condition within the power-on delay expiration flag; the delay continuation processing continues to generate de-jitter delay expiration flags along the de-jitter delay window while maintaining the window order relationship and registers the expiration time information; the sequence archiving processing writes the power-on delay expiration flag and the de-jitter delay expiration flag into the delay expiration sequence structure according to the window order relationship and registers the archiving order information; when the de-jitter delay expiration flag is not generated, a missing flag is registered in the delay expiration sequence structure; the delay expiration sequence structure is provided to the insertion determination module as an output product and is read by the insertion determination module; the delay expiration sequence structure also maintains a reference association with the dual delay window configuration structure for subsequent state archiving processing to read.

[0076] The insertion determination module 04 is used to perform detection point set loading processing based on the delayed expiration sequence structure to obtain the first sampling record, extract the resampling trigger condition from the first sampling record and perform de-jittering delayed expiration trigger binding to generate a resampling record, and perform consistency comparison processing between the first sampling record and the resampling record to generate an insertion determination result structure. Specifically, the insertion determination module receives the delayed expiration sequence structure output by the delayed expiration sequence generation module as an input object, and reads the USB interface hardware unit list registered in the insertion detection session configuration structure for detection point set loading processing. The detection point set loading processing starts loading and forms the loading relationship of the detection point set when there is a power-on delayed expiration mark in the delayed expiration sequence structure. After the first sampling record is processed by the detection point set loading process, the first sampling is performed on the detection point set. The sample registration is formed and associated with the power-on delay expiration mark; the resampling trigger condition is extracted from the first sampling record and the trigger condition entry is registered; the dejitter delay expiration trigger binding binds the resampling trigger condition entry with the dejitter delay expiration mark; when the dejitter delay expiration mark arrives, a resampling record is generated and the resampling trigger association is registered; the consistency comparison processing performs consistency verification on the first sampling record and the resampling record and registers the consistency result; the insertion determination result structure is formed by the consistency result registration and retains the archiving association with the delay expiration sequence structure; the insertion determination result structure is provided to the power latch control module as an output product and read by the power latch control module; and the insertion determination result structure is synchronously retained as a reference to the startup status record module for subsequent status archiving processing association writing.

[0077] The power latch control module 05 is used to generate a power latch control field based on the insertion determination result structure. Specifically, the power latch control module receives the insertion determination result structure output by the insertion determination module as an input object and reads the main power enable signal aperture registered in the insertion detection session configuration structure. The power latch control field generation process performs branch registration on the insertion determination result of the insertion determination result structure and generates the latch registration content of the power latch control field. When the insertion determination result of the insertion determination result structure is yes, the power latch control field registers the latch state and maintains a consistent association with the main power enable signal registration. When the insertion determination result of the insertion determination result structure is no, the power latch control field registers the non-latch state and maintains a consistent association with the main power enable signal registration. The power latch control field is provided to the enumeration session configuration module as an output product and is read by the enumeration session configuration module. The power latch control field retains the reference relationship with the insertion determination result structure for the status archiving processing of the startup status recording module to write the association.

[0078] The enumeration session configuration module 06 is used to extract enumeration trigger flags from the power latch control field and generate enumeration session configuration structures. Specifically, the enumeration session configuration module receives the power latch control field output from the power latch control module as an input object, extracts the enumeration trigger flags from the power latch control field and registers the trigger source and trigger state. Enumeration session configuration generation starts when the enumeration trigger flag is registered as triggered, and writes the enumeration trigger flags into the configuration association content of the enumeration session configuration structure. During the generation process, the enumeration session configuration structure registers session configuration entries and maintains the reference relationship with the insertion detection session configuration structure and the insertion determination result structure, so that the enumeration session configuration structure is consistently associated with the preceding determination link. The enumeration session configuration structure is provided to the startup status recording module as an output product and is read by the startup status recording module. When the enumeration trigger flag is registered as not triggered, the enumeration session configuration structure is registered as not started configuration and still provides archive input to the startup status recording module.

[0079] The startup state recording module 07 is used to perform state archiving processing on the enumeration session configuration structure to generate a startup state recording structure. Specifically, the startup state recording module receives the enumeration session configuration structure output by the enumeration session configuration module as an input object, and simultaneously receives the reference information of the power latch control field and the insertion judgment result structure. The state archiving processing performs archiving registration on the configuration entries of the enumeration session configuration structure and writes the enumeration trigger flag, the insertion judgment result structure reference, and the power latch control field reference into the same archiving association content, generating a startup state recording structure as the output product. After generation, the startup state recording structure establishes a reference association with the insertion detection session configuration structure and completes the archiving registration, so that the insertion detection session configuration module reads the archiving association content of the startup state recording structure and maintains the consistency of the session registration caliber when performing subsequent terminology dictionary entry set registration processing. The startup state recording structure also maintains a reference association with the dual delay window configuration structure and the delay expiration sequence structure, forming a closed-loop archiving link from the insertion detection session configuration structure to the startup state recording structure.

Claims

1. A printer USB insertion detection method based on a dual delay mechanism, characterized in that, include: Obtain the USB insertion trigger level, main power enable signal, and USB interface hardware unit list; register terminology dictionary entries, delay circuit parameter groups, and perform dual delay window arrangement processing to generate a dual delay window configuration structure. Obtain the dual delay window configuration structure, perform charge / discharge sequence startup, delayed endurance and expiration mark sequence archiving processing, and generate the delayed expiration sequence structure; Based on the delayed expiration sequence structure, the operations of generating the first sampling record, binding the de-shaking delayed expiration trigger, and generating the re-sampling record are performed to construct the insertion judgment result structure. Based on the insertion judgment result structure, the power latch control field is generated, the session configuration is enumerated and the status is archived, and the startup status record structure is generated.

2. The method according to claim 1, characterized in that, The process of registering the delay circuit parameter group also includes: The delay circuit parameter group registration process includes component list entries to form a resistor and capacitor component parameter group. The first threshold group of the threshold discrimination unit is read from the parameter group to register the power-on delay parameters, and the second threshold group is read to register the debouncing delay parameters. The power-on delay parameters include a power-on delay threshold identifier, a power-on delay window start event defined as the write time of the main power enable signal trigger edge, a power-on delay window termination event defined as the write time of the first expiration mark output by the delay unit, and a power-on delay rollback condition. The debouncing delay parameters include a debouncing delay threshold identifier, a debouncing delay window start event defined as the completion time of the first sampling record generation action, a debouncing delay window termination event defined as the write time of the second expiration mark output by the delay unit, a debouncing delay trigger dependency defined as the power-on delay expiration mark having been generated and the session not rolled back, and a debouncing delay rollback condition defined as the number of jitter toggles exceeding a threshold. Subsequently, the power-on delay parameters and the debouncing delay parameters are merged.

3. The method according to claim 1, characterized in that, The process of dual-delay window arrangement also includes: The dual delay window orchestration process includes constructing the timing relationship of the dual delay windows using delay circuit parameter groups, generating window identifiers, window start and end event sets, threshold group reference sets, expiration mark write address sets, expiration mark circular buffers in running memory, window state fields, rollback condition field groups, and jitter monitoring rule references for the power-on delay window and debouncing delay window, and registering window trigger dependencies and mutual exclusion rules for the debouncing delay window.

4. The method according to claim 1, characterized in that, The process of initiating the charge / discharge sequence also includes: The charge / discharge sequence startup process includes: after detecting the main power enable signal trigger edge write, placing the delay unit into the charging working channel, and turning on the main power rail and turning off the discharge unit release channel through the power supply path linkage link; making the threshold discrimination unit discriminate according to the first threshold group through the threshold discrimination linkage link and outputting the first expiration mark when the threshold is met; and continuously reading the rollback condition field group through the abnormal rollback linkage link and triggering rollback when the condition is met.

5. The method according to claim 1, characterized in that, The process of extending battery life also includes: The delayed battery life processing includes extracting the de-jitter delay start marker and performing trigger dependency verification. After the verification passes, the threshold discrimination unit is switched to the second threshold group by writing the threshold group selection control field, or the charging path is switched to the second charging path by writing the path switching control field, or the loop is switched to the de-jitter delay loop by writing the loop switching control field, so that the delay unit continues to charge and evolves towards the second threshold group. When the threshold discrimination unit determines that the condition is met.

6. The method according to claim 1, characterized in that, The process of generating the initial sampling record also includes: The initial sampling record generation process includes performing a detection point set loading process. This process involves loading three types of detection points—power line detection point signals, positive data line detection point signals, and negative data line detection point signals—by performing port binding, polarity binding, and de-glitch configuration. Subsequently, the detection point sampling unit performs continuous sampling according to the sampling window parameters. The microcontroller unit reads the sampling results and binds them to a noise marker field.

7. The method according to claim 1, characterized in that, The process of triggering binding upon the expiration of the de-shake delay also includes: The de-jitter delay expiration trigger binding process includes reading the de-jitter delay expiration flag entry in the delay expiration sequence structure, establishing a trigger subscription relationship, and extracting the resampling trigger conditions. The resampling trigger conditions include the consistency condition of the detection point set, the stability condition of the first sampling, and the session state condition.

8. The method according to claim 1, characterized in that, The process of resampling and generating records also includes: The resampling record generation process includes writing the resampling trigger condition into the condition latch field of the sampling control register, the detection point sampling unit continuously samples the three detection points again according to the sampling window parameters, and the microcontroller reads the sampling results and generates a record containing a summary of the trigger subscription field and the condition latch field.

9. The method according to claim 1, characterized in that, The process of generating the power latch control field also includes: The power latch control field generation process includes generating a latch control template, which includes a latch enable bit, a latch holding condition set including a session identifier consistency condition, a power supply feedback valid condition and a judgment evidence closure condition, and a latch release condition set including an exception code triggered release, a power supply feedback failure release, a trigger source drop release and a timeout release. The microcontroller sets the latch enable bit according to the judgment status field branch matching result and issues a latch request command or a shutdown preparation command.

10. A printer USB insertion detection device based on a dual delay mechanism, applied to the method of any one of claims 1-9, characterized in that, include: The insertion detection session configuration module is used to obtain the USB insertion trigger level, the main power enable signal, the USB interface hardware unit list, and perform terminology dictionary entry set registration processing to obtain the insertion detection session configuration structure. The dual delay window configuration module is used to extract the parameter group of resistor and capacitor components from the insertion detection session configuration structure and register the power-on delay parameter and the debounce delay parameter to generate the delay circuit parameter group; The delayed expiration sequence generation module is used to obtain the dual delay window configuration structure and perform charge / discharge sequence start-up processing to obtain the power-on delayed expiration mark and generate the delayed expiration sequence structure; The insertion determination module is used to load the detection point set into the delayed expiration sequence structure to obtain the first sampling record and generate the insertion determination result structure. The power latch control module is used to insert the judgment result structure to generate the power latch control field. The enumeration session configuration module is used to extract the enumeration trigger flag from the power latch control field and generate the enumeration session configuration structure. The startup state recording module is used to perform state archiving processing on the enumerated session configuration structure and generate a startup state recording structure.

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