PCIe physical link signal conditioning circuit
By designing a PCIe physical link signal conditioning circuit on a PCIe circuit board and utilizing a path switching module and impedance matching network, the link failure problem caused by the failure to debug the Retimer chip was solved, thus achieving the maintenance of signal integrity and stable communication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG HANWEI INFORMATION TECH CO LTD
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-15
AI Technical Summary
The Retimer chip integrated on the PCIe circuit board is prone to hardware failure, timing mismatch, and configuration parameter errors during debugging, which can lead to PCIe link failure and affect R&D debugging and mass production testing.
Design a PCIe physical link signal conditioning circuit, including PCIe upstream and downstream interfaces, a Retimer chip, a signal conditioning direct connection circuit and a path switching module. The circuit selectively conducts the Retimer chip or the signal conditioning direct connection circuit by switching the switch, and maintains signal integrity by using an impedance matching network.
When the Retimer chip fails to debug, a link is established through a direct connection to maintain signal integrity, avoid PCIe link failure, and ensure stable communication.
Smart Images
Figure CN122045117A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer hardware technology, and in particular to a PCIe physical link signal conditioning circuit. Background Technology
[0002] With the development of PCIe (High-Speed Serial Computer Extended Bus standard), it has become the core bus architecture for high-speed data transmission between devices in fields such as servers, industrial control, and high-performance computing. PCIe circuit boards typically integrate a Retimer chip, which uses built-in equalization, de-emphasis, and Clock Data Recovery (CDR) functions to shape and optimize signals, ensuring stable communication in the PCIe link. However, during the R&D, debugging, and mass production testing phases of PCIe circuit boards, problems can easily arise due to hardware faults in the Retimer chip itself, timing mismatches between the Retimer chip and the PCIe link, or incorrect configuration parameters. These issues can lead to Retimer chip debugging failures, causing PCIe link failures and impacting the R&D, debugging, and mass production testing of the PCIe circuit board. Summary of the Invention
[0003] The technical problem to be solved by this invention is how to prevent the PCIe link from failing due to the inability to debug the retimer chip integrated on the PCIe circuit board.
[0004] To solve the above-mentioned technical problems, the present invention provides a PCIe physical link signal conditioning circuit, comprising: PCIe upstream interface, which is used to connect PCIe upstream devices; PCIe downstream interface, which is used to connect PCIe downstream devices; The Retimer chip has its input connected to the PCIe upstream interface and its output connected to the PCIe downstream interface. The signal conditioning direct connection circuit has its input end connected to the PCIe upstream interface and its output end connected to the PCIe downstream interface. It includes a coupling capacitor, a common-mode choke and an impedance matching network connected in sequence. The impedance matching network includes a first resistor and a second resistor connected in series, and an RC filter connected between the first resistor and the second resistor. The path switching module includes one input interface and two output interfaces. The input interface is connected to the PCIe upstream interface, and the two output interfaces are connected to the Retimer chip and the signal conditioning direct connection respectively, for selectively turning on the Retimer chip or the signal conditioning direct connection.
[0005] Furthermore, the path switching module is equipped with a switching switch, which is connected to the input interface and selectively turns on one of the output interfaces to selectively turn on the Retimer chip or the signal conditioning direct connection circuit.
[0006] Furthermore, the switching switch is a high-speed analog switch, and its control terminal is connected to an external DIP switch to perform switching operations in response to external commands.
[0007] Furthermore, the first resistor and the second resistor have the same resistance value, ranging from 35Ω to 50Ω.
[0008] Furthermore, it can be integrated into server motherboards, test backplanes, or PCIe adapter cards.
[0009] The present invention has the following beneficial effects: when the Retimer chip fails to debug, the Retimer chip can be disconnected by selectively conducting the signal conditioning direct connection through the path switching module, so that a direct link can be established between PCIe upstream devices, and the differential impedance of the signal conditioning direct connection can be matched with the PCIe specification requirements through the impedance matching network, thereby maintaining the basic signal integrity of PCIe differential signals under the direct link and avoiding PCIe link failure. Attached Figure Description
[0010] Figure 1 This is the circuit schematic of the PCIe physical link signal conditioning circuit.
[0011] Figure labeling: 1. PCIe upstream interface; 2. PCIe downstream interface; 3. Retimer chip; 4. Coupling capacitor; 5. Common mode choke; 6. First resistor; 7. Second resistor; 8. Filter inductor; 9. Filter capacitor; 10. Path switching module. Detailed Implementation
[0012] The present invention will be further described in detail below with reference to specific embodiments.
[0013] This embodiment provides a PCIe physical link signal conditioning circuit, which is integrated on a server motherboard, test backplane, or PCIe adapter card. Figure 1As shown, the PCIe physical link signal conditioning circuit includes a PCIe upstream interface 1, a PCIe downstream interface 2, a Retimer chip 3, a signal conditioning direct connection path, and a path switching module 10. The signal conditioning direct connection path includes a coupling capacitor 4, a common-mode choke 5, and an impedance matching network connected in sequence. The common-mode choke 5 is specifically a common-mode inductor, used to suppress common-mode noise. The impedance matching network includes a first resistor 6 and a second resistor 7 connected in series, and an RC filter connected between the first resistor 6 and the second resistor 7. The first resistor 6 and the second resistor 7 have equal resistance values, ranging from 35Ω to 50Ω, and are configured to match the differential impedance of the signal conditioning direct connection path to the PCIe specification requirement of 85Ω ± 10%. The RC filter includes a filter inductor 8 and a filter capacitor 9. The filter inductor 8 is specifically connected between the first resistor 6 and the second resistor 7, and the filter capacitor 9 is connected between the filter inductor 8 and ground. The RC filter can compensate for the insertion loss of high-frequency PCIe signals in the signal conditioning direct connection path.
[0014] In this embodiment, PCIe upstream interface 1 is used to connect PCIe upstream devices, and PCIe downstream interface 2 is used to connect PCIe downstream devices. The input terminal of the Retimer chip 3 is connected to PCIe upstream interface 1, and the output terminal is connected to PCIe downstream interface 2. The input terminal of the signal conditioning direct connection is connected to PCIe upstream interface 1, and the output terminal is connected to PCIe downstream interface 2. The path switching module 10 includes one input interface and two output interfaces. The input interface is connected to PCIe upstream interface 1, and the two output interfaces are connected to the Retimer chip 3 and the signal conditioning direct connection respectively, for selectively turning on the Retimer chip 3 or the signal conditioning direct connection. Specifically, the path switching module 10 has an internal switching switch, which is a high-speed analog switch. Its control terminal is connected to an external DIP switch to switch in response to external commands. This switching switch is connected to the input interface and selectively turns on one of the output interfaces to selectively turn on the Retimer chip 3 or the signal conditioning direct connection.
[0015] During normal use, the path switching module's switch activates the Retimer chip 3 and disconnects the signal conditioning direct connection. The Retimer chip 3 then shapes and optimizes the PCIe signal, ensuring stable communication across the PCIe link. If the Retimer chip 3 fails to connect, the path switching module can selectively activate the signal conditioning direct connection and disconnect the Retimer chip 3, establishing a direct link between upstream PCIe devices. An impedance matching network then ensures the differential impedance of the signal conditioning direct connection matches PCIe specifications, maintaining basic signal integrity of the PCIe differential signal under a direct link and preventing PCIe link failure.
[0016] The above description is merely an embodiment of the present invention and does not limit the scope of patent protection. Any non-substantial changes or substitutions made by those skilled in the art based on the present invention will still fall within the scope of patent protection.
Claims
1. A PCIe physical link signal conditioning circuit, characterized in that, include: PCIe upstream interface (1), which is used to connect PCIe upstream devices; PCIe downstream interface (2), which is used to connect PCIe downstream devices; The Retimer chip (3) has its input end connected to the PCIe upstream interface (1) and its output end connected to the PCIe downstream interface (2). The signal conditioning direct connection circuit has its input end connected to the PCIe upstream interface (1) and its output end connected to the PCIe downstream interface (2). It includes a coupling capacitor (4), a common-mode choke (5) and an impedance matching network connected in sequence. The impedance matching network includes a first resistor (6) and a second resistor (7) connected in series, and an RC filter connected between the first resistor (6) and the second resistor (7). The path switching module (10) includes an input interface and two output interfaces. The input interface is connected to the PCIe upstream interface (1), and the two output interfaces are connected to the Retimer chip (3) and the signal conditioning direct connection circuit, respectively, for selectively turning on the Retimer chip (3) or the signal conditioning direct connection circuit.
2. The PCIe physical link signal conditioning circuit according to claim 1, characterized in that, The path switching module (10) is equipped with a switching switch. The switching switch is connected to the input interface and selectively connects one of the output interfaces to selectively connect the Retimer chip (3) or the signal conditioning direct connection circuit.
3. The PCIe physical link signal conditioning circuit according to claim 1, characterized in that, The switching switch is a high-speed analog switch, and its control terminal is connected to an external DIP switch to perform switching operations in response to external commands.
4. The PCIe physical link signal conditioning circuit according to claim 1, characterized in that, The first resistor (6) and the second resistor (7) have the same resistance value, which ranges from 35Ω to 50Ω.
5. The PCIe physical link signal conditioning circuit according to claim 1, characterized in that, It is integrated into the server motherboard, test backplane, or PCIe adapter card.