Signal transmission method and device, equipment and medium

Abstract

The embodiment of the invention provides a signal transmission method, device and equipment and a medium, and relates to the technical field of signal transmission, the method is applied to a signal transmission system, and the signal transmission system comprises a first chip and a second chip. The method comprises the following steps: writing a plurality of transmission signals to be transmitted into a first asynchronous buffer in a first chip through the first chip, so that the first asynchronous buffer caches the plurality of transmission signals in a first clock domain; sending a plurality of transmission signals to a second asynchronous buffer of a second chip through the first asynchronous buffer; receiving and caching a plurality of transmission signals in a second clock domain through a second asynchronous buffer; and each transmission signal is stored in the channel buffer corresponding to the transmission signal through the second chip, so that the second chip reads the transmission signals from the plurality of channel buffers for processing. Therefore, the transmission speed of the ACE protocol signal is effectively improved.

Description

Technical Field

[0001] This disclosure relates to the field of signal transmission technology, and in particular to a signal transmission method, apparatus, device and medium. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs) serve as circuit prototyping tools, enabling the evaluation of key metrics such as functionality and timing performance by deploying circuits within FPGAs. However, as chip design scales continue to increase, the resource capacity of a single FPGA is often insufficient to accommodate a complete circuit. In such cases, it is necessary to partition the circuit and deploy it across multiple FPGAs interconnected by physical links (such as fiber optic cables) for collaborative verification.

[0003] In existing technologies, a complete circuit typically consists of multiple intellectual property core (IP) modules with standard interfaces, including the AXI Coherency Extensions (ACE) protocol. However, when the interfaces with the ACE protocol in a circuit are cut off and the cut-off modules are deployed on different FPGAs, this can easily lead to slower transmission speeds of ACE protocol signals in the aforementioned scenarios. Summary of the Invention

[0004] This disclosure provides a signal transmission method, apparatus, device, and medium to at least solve the above-mentioned technical problems existing in the prior art.

[0005] In a first aspect, embodiments of this disclosure provide a signal transmission method applied to a signal transmission system, the signal transmission system including a first chip and a second chip, the method comprising:

[0006] The first chip writes multiple transmission signals to be transmitted into the first asynchronous buffer in the first chip, so that the first asynchronous buffer buffers multiple transmission signals in the first clock domain; Multiple transmission signals are sent from the first asynchronous register to the second asynchronous register of the second chip; Multiple transmitted signals are received and buffered in the second clock domain through a second asynchronous buffer; The second chip stores each transmission signal in the corresponding channel buffer, enabling the second chip to read transmission signals from multiple channel buffers for processing.

[0007] Secondly, embodiments of this disclosure provide a signal transmission device applied to a signal transmission system, the signal transmission system including a first chip and a second chip, the device comprising: The writing module is used to write multiple transmission signals to be transmitted into the first asynchronous buffer in the first chip through the first chip, so that the first asynchronous buffer buffers multiple transmission signals in the first clock domain; The transmitting module is used to send multiple transmission signals to the second asynchronous buffer of the second chip through the first asynchronous buffer; The receiving module is used to receive and buffer multiple transmitted signals in the second clock domain via a second asynchronous buffer. The storage module is used to store each transmission signal into the channel buffer corresponding to the transmission signal through the second chip, so that the second chip can read the transmission signal from multiple channel buffers for processing.

[0008] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the signal transmission method of the first aspect.

[0009] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the signal transmission method according to the first aspect.

[0010] Based on the signal transmission method provided in this disclosure, multiple transmission signals to be transmitted can be written into a first asynchronous buffer in a first chip, enabling the first asynchronous buffer to buffer the multiple transmission signals in a first clock domain. The first asynchronous buffer can then send the multiple transmission signals to a second asynchronous buffer in a second chip, which in turn can receive and buffer the multiple transmission signals in a second clock domain. Furthermore, the second chip can store each transmission signal in its corresponding channel buffer, allowing the second chip to read and process the corresponding transmission signal from the multiple channel buffers. Thus, decoupled transmission is achieved through channel buffers, allowing the transmitting end to continuously transmit without waiting for real-time feedback from the receiving end, significantly improving signal transmission efficiency. Furthermore, asynchronous buffers are used to complete cross-clock domain signal transmission, ensuring clock domain isolation and signal integrity. The multi-channel parallel buffering and processing mechanism effectively improves overall bandwidth and throughput.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] Figure 1This is a schematic diagram of the structure of a signal transmission system provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a signal handshake in a signal transmission system provided in an embodiment of this disclosure; Figure 3 This is a schematic flowchart of a signal transmission method provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of a signal transmission device provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0013] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0014] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0015] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0017] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms involved in the embodiments of this disclosure will be explained, and the nouns and terms involved in the embodiments of this disclosure shall be interpreted as follows.

[0018] In existing technologies, when circuit interfaces containing the ACE protocol are segmented and deployed on different FPGAs, the transmission speed of ACE protocol signals is prone to being slow. The specific reasons are as follows: Firstly, since the ACE protocol originally relies on parallel multi-channel signal transmission within the chip, while physical links between FPGA modules (such as optical fibers) typically use serial communication, all channel signals must be queued and transmitted sequentially through this serial link, resulting in a decrease in the transmission speed of ACE signals. Secondly, during the above transmission process, if requests from high-priority channels fail to receive timely responses—for example, if a write address request from the Address Write Channel (AW) has not yet received a response signal from the corresponding Write Response Channel (B)—this may cause the above transmission process to be blocked, leading to a low ACE protocol signal transmission rate.

[0019] Based on this, the present disclosure provides a signal transmission method to at least solve the technical problem of low transmission rate of ACE protocol signals in scenarios where circuits are split and deployed on different chips, as described in the prior art.

[0020] It should be noted that, since the signal transmission method provided in this disclosure involves a signal transmission system, in order to facilitate understanding of the signal transmission method provided in this disclosure, a detailed description of the signal transmission system provided in this disclosure is required in conjunction with the accompanying drawings before introducing the signal transmission method provided in this disclosure.

[0021] Figure 1 This is a schematic diagram of the structure of a signal transmission system provided in an embodiment of this disclosure.

[0022] like Figure 1 As shown, the circuit architecture of this signal transmission system can be divided into two parts, which are deployed separately in... Figure 1 On FPGA0 and FPGA1 as shown.

[0023] According to the ACE protocol standard, only the master module can initiate read / write requests to the slave module. Therefore, in the signal transmission method provided in this disclosure embodiment, it is necessary to distinguish whether the segmented module performs the function of the master module in the circuit. For example, as... Figure 1 As shown, the main module can be deployed in FPGA0, and the slave module can be deployed in FPGA; no specific restrictions are made here.

[0024] Furthermore, according to the ACE protocol standard, the transmitted signal can be divided into eight channels: Address Write Channel (AW), Write Data Channel (W), Write Response Channel (B), Address Read Channel (AR), Read Data Channel (R), Snoop Address Channel (AC), Snoop Response Channel (CR), and Snoop Data Channel (CD). Based on this, as... Figure 1 As shown, the master module and slave module can each be configured with the above 8 channels, i.e. Figure 1 The letters CD, CR, AR, AW, W, AC, R, and B are also mentioned. It should also be noted that... Figure 1 As shown, the signal transmission directions for the above 8 channels can be specifically defined as follows: For channels CD, CR, AR, AW, and W, the signal transmission direction is from the master module to the slave module. For channels AC, R, and B, the signal transmission direction is from the slave module to the master module. Each channel contains a set of handshake signals, namely a valid signal and a ready signal handshake.

[0025] Continue as Figure 1 As shown, FPGA0 can also be deployed with a priority sorting module, a signal flag determination module, a transmit asynchronous first-in-first-out buffer (TX_FIFO), a receive asynchronous first-in-first-out buffer (RX_FIFO), a channel buffer (AC_FIFO) for the AC channel, a channel buffer (R_FIFO) for the R channel, a channel buffer (B_FIFO) for the B channel, and an Aurora interface.

[0026] Correspondingly, FPGA1 can also be deployed with a channel buffer (AW_FIFO) for the AW channel, a channel buffer (AR_FIFO) for the AR channel, a channel buffer (W_FIFO) for the W channel, a channel buffer (CR_FIFO) for the CR channel, a channel buffer (CD_FIFO) for the CD channel, a write judgment module, a transmit asynchronous first-in-first-out buffer (TX_FIFO), and a receive asynchronous first-in-first-out buffer (RX_FIFO).

[0027] Based on the above Figure 1The structure of the signal transmission system shown is illustrated to facilitate subsequent understanding of the signal transmission method provided in this embodiment. In one example, if the master module transmits a signal to the slave module, the signal transmission system can first transmit the transmission signals corresponding to the CD, CR, AR, AW, and W channels in the master module to the priority sorting module. The priority sorting module determines the signal priority of the received multiple transmission signals. Then, it can determine the signal flags corresponding to the multiple transmission signals based on the signal flag determination module. The signal flags corresponding to the transmission signals are used to determine which channel the corresponding transmission signal originates from. Then, according to the signal priority of the multiple transmission signals, each transmission signal and its corresponding signal flag are sequentially bound and stored in the TX-FIFO in FGPA0. The clock domains corresponding to the input and output terminals of the TX-FIFO in FGPA0 are different. Specifically, its input terminal is synchronized with the ACE clock, and its output terminal is synchronized with the Aurora clock. Subsequently, the multiple transmission signals and their signal flags can be transmitted via the TX-FIFO in FGPA0 to the RX-FIFO in FGPA1 for buffering through Aurora. The input and output clock domains of the RX-FIFO in FGPA1 are different; its input is synchronized with the Aurora clock, and its output is synchronized with the ACE clock. Thus, the write judgment module can sequentially read the transmission signals and their signal flags from the RX-FIFO in FGPA1, and determine which channel buffer to place the transmission signal in based on the signal flags, so that the slave module can read and process the corresponding transmission signal. If the channel buffer corresponding to the data to be output from the RX-FIFO in FGPA1 is full, the write operation will wait until the channel buffer is full before proceeding.

[0028] In addition, such as Figure 2 As shown, for the Aurora TX user interface, when the TX-FIFO is not empty and the user interface's ready signal is high, the rd_en signal is enabled, and tx_valid is set high. This completes the handshake between the user interface's valid and ready signals, and data is simultaneously sent from the TX_FIFO to the Aurora. Continuing as... Figure 2 As shown, for the Aurora RX user interface, since there is no ready signal, the valid signal is used as the write enable signal for RX_FIFO. At the same time, data is also transferred from Aurora to RX_FIFO.

[0029] It should be noted that, since the process of transmitting signals from the slave module to the master module in the signal transmission method provided in this embodiment is similar to the process of transmitting signals from the master module to the slave module, it will not be described in detail here.

[0030] It should also be noted that the depths of TX_FIFO and RX_FIFO can be set to a preset bit depth, for example, 256 bits; no specific limitation is made here. Additionally, the buffer depth of each channel buffer is related to the user-defined maximum ACE lead-ahead depth. The buffer depths of AW_FIFO, AR_FIFO, W_FIFO, CR_FIFO, and CD_FIFO can be determined based on actual conditions. While ensuring no data loss, the bit width can be reduced to decrease chip area. The buffer depths of AC_FIFO, B_FIFO, and R_FIFO can be determined based on actual conditions. The buffer depths of AW_FIFO, AR_FIFO, and B_FIFO can be no greater than the user-defined lead-ahead depth, while the depth of W_FIFO can be appropriately greater than the AW_FIFO channel depth. Since the AC channel does not support lead-ahead, the depths of AC_FIFO, CR_FIFO, and CD_FIFO can be set to 1.

[0031] Based on the above Figure 1 The diagram shows the structure of the signal transmission system. The signal transmission method provided in this disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] Figure 3 This is a schematic flowchart of a signal transmission method provided in an embodiment of this disclosure.

[0033] like Figure 3 As shown, the execution entity of the signal transmission method provided in this embodiment of the disclosure may be... Figure 1 Based on the signal transmission system shown, the signal transmission method provided in this embodiment of the disclosure may specifically include the following steps: S310: The first chip writes multiple transmission signals to be transmitted into the first asynchronous buffer in the first chip, so that the first asynchronous buffer buffers multiple transmission signals in the first clock domain.

[0034] S320 sends multiple transmission signals to the second asynchronous register of the second chip through the first asynchronous register.

[0035] S330 receives and buffers multiple transmission signals in the second clock domain through a second asynchronous buffer.

[0036] S340 stores each transmission signal into the corresponding channel buffer through the second chip, enabling the second chip to read transmission signals from multiple channel buffers for processing.

[0037] It should be noted here that, as Figure 1 As shown, in the signal transmission method provided in this embodiment, the master module can transmit signals to the slave module, and the slave module can also transmit signals to the master module. The master module is deployed on FPGA0, and the slave module is deployed on FPGA1. Based on this, if the transmission direction is from the master module to the slave module, the first chip can be FPGA0, the second chip can be FPGA1, and the multiple transmission signals to be transmitted can be... Figure 1 For the signals corresponding to the CD, CR, AR, AW, W, etc. channels shown, the first asynchronous buffer is the TX-FIFO in FPGA0, the second asynchronous buffer is the RX-FIFO in FPGA1, and vice versa. No specific limitation is made here.

[0038] Furthermore, the first asynchronous buffer, the second asynchronous buffer, and the channel buffer mentioned above can be configured as first-in-first-out buffers. The cache depth of the first asynchronous buffer, the second asynchronous buffer, and the channel buffer can be determined according to the actual situation, and no specific limitation is made here. It should also be noted that the first clock domain and the second clock domain mentioned above are different clock domains. For example, the first clock domain could be the ACE clock domain, and the second clock domain could be the Aurora clock domain; no specific limitation is made here.

[0039] Specifically, such as Figure 1 As shown, the signal transmission system may include a first chip and a second chip. Based on this, the signal transmission system can write multiple transmission signals to be transmitted into a first asynchronous buffer in the first chip through the first chip, so that the first asynchronous buffer can buffer the multiple transmission signals in a first clock domain, and can send the multiple transmission signals to a second asynchronous buffer in the second chip through the first asynchronous buffer in a second clock domain. Then, the second asynchronous buffer can receive and buffer the multiple transmission signals in the second clock domain, and can store each transmission signal into a channel buffer corresponding to the transmission signal through the second chip, so that the second chip can read the corresponding transmission signal from the multiple channel buffers for processing.

[0040] In this embodiment, multiple transmission signals to be transmitted can be written into a first asynchronous buffer in a first chip, enabling the first asynchronous buffer to buffer the multiple transmission signals in a first clock domain. The first asynchronous buffer can then send the multiple transmission signals to a second asynchronous buffer in a second chip, which in turn can receive and buffer the multiple transmission signals in a second clock domain. The second chip can then store each transmission signal in its corresponding channel buffer, allowing it to read and process the corresponding transmission signal from the multiple channel buffers. This decoupled transmission is achieved through the structure of the asynchronous buffer and the channel buffer. The transmitting end (i.e., the first chip) can continuously transmit without waiting for feedback from the receiving end (i.e., the second chip), effectively avoiding data writing blockage in the asynchronous buffer and significantly improving signal transmission efficiency. Furthermore, the asynchronous buffer can be used to complete cross-clock domain signal transmission, ensuring clock domain isolation and signal integrity. The multi-channel parallel buffering and processing mechanism effectively improves overall bandwidth and throughput.

[0041] In order to describe the signal transmission method provided by the embodiments of this disclosure in detail, in one embodiment, before S310 above, the signal transmission method provided by the embodiments of this disclosure may specifically include the following steps: The signal transmission module of the first chip obtains the transmission signals sent by multiple first transmission channels respectively.

[0042] The signal transmission module of the aforementioned first chip can be configured with multiple transmission channels, which may include multiple first transmission channels. It should be noted that if the signal transmission direction is from the master module to the slave module, then the signal transmission module of the aforementioned first chip is... Figure 1 The main module is configured with multiple transmission channels, such as CD, CR, AR, AW, and W, and vice versa; no specific limitation is made here.

[0043] Based on this, the above-mentioned step of storing each transmission signal into the channel buffer corresponding to the transmission signal through the second chip can specifically include the following steps: The second chip stores each transmitted signal into the channel buffer of the first receiving channel corresponding to the transmitted signal.

[0044] The signal receiving module of the second chip is configured with receiving channels corresponding to multiple transmission channels, including the first receiving channel. It should be noted that the transmission type of the first transmission channel corresponding to the transmitted signal and the first receiving channel corresponding to the transmitted signal are the same. Continuing with the example of signal transmission from the master module to the slave module, in the case of signal transmission from the master module to the slave module, the signal receiving module of the second chip is... Figure 1 In the slave module, the multiple transmission channels in the first chip are CD, CR, AR, AW and W, etc., used for transmitting signals, and the multiple receiving channels in the second chip are CD, CR, AR, AW and W, etc., used for receiving signals. No specific limitation is made here.

[0045] Specifically, the signal transmission system can obtain the transmission signals corresponding to multiple first transmission channels through the signal transmission module of the first chip. Based on this, after sending the multiple transmission signals to the second asynchronous buffer of the second chip through the first asynchronous buffer in the first chip, the signal transmission system can store each of the multiple transmission signals into the channel buffer corresponding to the transmission signal through the second chip.

[0046] In this embodiment, various transmission signals from multiple first transmission channels can be acquired through the signal transmission module of the first chip. These signals are then transmitted across chips, received by the second chip, and accurately distributed and stored in their respective channel buffers. This allows for the classification and buffering of signals from different channels at the receiving end, facilitating subsequent parallel signal processing and improving the signal transmission rate.

[0047] In order to provide a comprehensive and detailed description of the signal transmission method provided in the embodiments of this disclosure, in one embodiment, before storing each transmission signal into the channel buffer corresponding to the transmission signal by the second chip, so that the first asynchronous buffer buffers multiple transmission signals in the first clock domain, the signal transmission method provided in the embodiments of this disclosure may further include the following steps: The priority of multiple transmitted signals is determined by the priority sorting module of the first chip.

[0048] The signal priority of the aforementioned multiple transmission signals can include the priority of each transmission signal. The higher the priority of a signal, the more likely it is to be written into the first asynchronous buffer, and vice versa.

[0049] Based on this, the above-mentioned method of storing each transmission signal into the channel buffer corresponding to the transmission signal through the second chip, so that the first asynchronous buffer buffers multiple transmission signals in the first clock domain, may specifically include the following steps: The priority sorting module of the first chip writes multiple transmission signals into the first asynchronous buffer according to their signal priorities, so that the first asynchronous buffer buffers multiple transmission signals in the first clock domain.

[0050] Specifically, the signal processing method can first determine the signal priority of multiple transmission signals through the priority sorting module in the first chip, and then write the multiple transmission signals into the first asynchronous buffer in sequence according to the signal priority of the multiple transmission signals through the priority sorting module of the first chip, so that the first asynchronous buffer can buffer the multiple transmission signals in the first clock domain.

[0051] In one example, when determining the priority of multiple transmission signals using the priority sorting module of the first chip, the module first obtains the channel requests corresponding to these signals. The valid signal for the channel corresponding to the request is high. Based on this, the priority sorting module determines the signal priority of the multiple transmission signals and packages the transmission signals with the highest valid signal according to their priority. It should be noted that only the ready signal corresponding to the channel being written to can be pulled high. A single cycle of the ready signal being high completes the valid and ready handshake. After a handshake, if there are no requests for this channel or a higher-priority channel request exists, the ready signal remains low. If there are requests for this channel, and the current request has the highest priority, the ready signal remains high, and data continues to be written to the TX-FIFO. Lower-priority channel requests wait for higher-priority channel write requests to be written to their corresponding channel buffers before being written to them.

[0052] In this embodiment, the priority sorting module of the first chip sequentially writes multiple signals into the first asynchronous buffer according to the priority of each transmitted signal. This ensures that high-priority signals enter the buffer queue first, enabling the first asynchronous buffer to perform ordered buffering of signals within the first clock domain.

[0053] In order to provide a comprehensive and detailed description of the signal transmission method provided in the embodiments of this disclosure, in one embodiment, before storing each transmission signal into the channel buffer corresponding to the transmission signal by the second chip, so that the first asynchronous buffer buffers multiple transmission signals in the first clock domain, the signal transmission method provided in the embodiments of this disclosure may further include the following steps: The signal flag bit of each transmitted signal is determined by the signal flag determination module of the first chip.

[0054] The first chip's signal transmission module is configured with multiple transmission channels. The signal flag bit is used to indicate which channel the signal comes from, that is, the signal flag bit indicates the transmission channel to which the transmitted signal belongs among the multiple transmission channels.

[0055] Based on this, the above-mentioned method of storing each transmission signal into the channel buffer corresponding to the transmission signal through the second chip, so that the first asynchronous buffer buffers multiple transmission signals in the first clock domain, may specifically include the following steps: The signal flag determination module of the first chip writes each transmission signal and its signal flag bit into the first asynchronous buffer, so that the first asynchronous buffer binds and caches each transmission signal and its signal flag bit under the first clock domain.

[0056] In one example, the signal transmission system can determine the signal flag bit of each transmitted signal through the signal flag bit determination module of the first chip, and then write each of the multiple transmitted signals and its signal flag bit into the first asynchronous buffer through the signal flag bit determination module of the first chip, so that the first asynchronous buffer binds and stores each transmitted signal and its signal flag bit in the first clock domain.

[0057] In another example, the signal transmission system can determine the signal priority of multiple transmission signals through the priority sorting module of the first chip, and can determine the signal flag bit of each of the multiple transmission signals through the signal flag bit determination module of the first chip. Then, the signal flag bit determination module of the first chip can write each of the multiple transmission signals and its signal flag bit into the first asynchronous buffer according to the signal priority of the multiple transmission signals, so that the first asynchronous buffer binds and stores each transmission signal and its signal flag bit under the first clock domain.

[0058] In this embodiment, the signal flag determination module of the first chip can generate a corresponding signal flag for each transmission signal and write it together with the corresponding transmission signal into the first asynchronous buffer. In this way, the first asynchronous buffer can bind and store each transmission signal with its signal flag in the first clock domain, so that the second chip can accurately identify the transmission signal and store it in the corresponding channel buffer.

[0059] Based on this, each transmission signal and its signal flag bit are written into the first asynchronous buffer by the signal flag determination module of the first chip, and then transmitted to the first asynchronous buffer in the second chip via the first asynchronous buffer. Thus, the second asynchronous buffer can store multiple transmission signals and their signal flag bits.

[0060] Based on this, before storing each transmission signal to the corresponding channel buffer via the second chip, the signal transmission method provided in this embodiment further includes the following steps: For each transmission signal cached in the second asynchronous buffer, the signal flag bit associated with the transmission signal is read by the write judgment module of the second chip; The write judgment module of the second chip determines the channel buffer corresponding to the transmission signal based on the information indicated by the signal flag bit.

[0061] Specifically, since the second asynchronous buffer stores multiple transmission signals and signal flag bits for each transmission signal, the signal transmission system can read the signal flag bits associated with each transmission signal buffered in the second asynchronous buffer through the write judgment module of the second chip, and can determine the channel buffer corresponding to the transmission signal based on the information indicated by the signal flag bits through the write judgment module of the second chip.

[0062] In this embodiment, since each transmission signal and its signal flag are stored in the second asynchronous buffer, the write judgment module of the second chip can accurately determine the target channel buffer to which each transmission signal should be written based on the channel information indicated by the signal flag of the transmission signal, thereby facilitating parallel processing of signals.

[0063] Based on this, in one embodiment, the signal receiving module of the second chip is configured with receiving channels corresponding to multiple transmission channels respectively, and a channel buffer corresponding to each receiving channel; Based on this, the step of determining the channel buffer corresponding to the transmission signal based on the signal flag bit of the transmission signal stored in the second asynchronous buffer can specifically include the following steps: The write judgment module of the second chip identifies the transmission channel to which the transmitted signal belongs based on the signal flag bit; Based on the preset correspondence between transmission channels and receiving channels, the transmission channel to which the transmitted signal belongs is matched to determine the receiving channel to which the transmitted signal belongs. Based on the preset correspondence between receiving channels and channel buffers, the receiving channel to which the transmitted signal belongs is matched to determine the channel buffer corresponding to the transmitted signal.

[0064] The pre-defined correspondence between the transmission channel and the receiving channel can be based on practical experience and is not specifically limited here. The pre-defined correspondence between the receiving channel and the channel buffer can be based on the connection relationship between the receiving channel and the channel buffer and is not specifically limited here.

[0065] Specifically, the signal transmission system can identify the transmission channel to which the transmitted signal belongs based on the signal flag bit through the write judgment module of the second chip, and can match the transmission channel to which the transmitted signal belongs based on the preset correspondence between the transmission channel and the receiving channel to determine the receiving channel to which the transmitted signal belongs. Furthermore, it can match the receiving channel to which the transmitted signal belongs based on the preset correspondence between the receiving channel and the channel buffer to determine the channel buffer corresponding to the transmitted signal.

[0066] In this embodiment, the write judgment module of the second chip can identify the original transmission channel to which each transmission signal belongs based on the signal flag bit carried by each transmission signal, and determine the target receiving channel corresponding to it at the receiving end by combining the preset transmission channel and receiving channel mapping relationship. Then, based on the preset receiving channel and channel buffer correspondence relationship, the signal is accurately allocated to the corresponding channel buffer for storage, thereby facilitating the parallel processing of signals.

[0067] Furthermore, since the user receive port of the Aurora protocol lacks a handshake mechanism, data must be received immediately upon arrival. Therefore, it is crucial to ensure that the receiver's RX-FIFO is not full; otherwise, data loss will occur. In traditional designs, to avoid this problem, the sender continuously checks the empty / full status of the receiver's RX-FIFO before sending data to the Aurora interface, allowing transmission only when the RX-FIFO is not full. This mechanism not only introduces frequent status feedback and handshake processes but also increases system load and transmission latency. Based on this, the signal transmission method provided in this disclosure can fundamentally avoid a full FIFO by accurately determining the depth of the asynchronous FIFO buffer, thus eliminating the need to report the empty / full status to the sender and achieving true decoupled transmission. The specific strategy is as follows: Since modules using the ACE protocol as their interface can be configured to control whether lookahead transmission is supported, and if so, the depth of lookahead transmission, each channel has a maximum lookahead transmission depth. Thus, if the maximum number of advance transmissions has been reached and the request still hasn't received a response from another FPGA, the sender will maintain its current state and stop sending requests. For example, the main module supports advance transmissions with a maximum depth of 4. Taking the AR channel as an example, if there's a request on the main module's AR channel and it's passed to the TX-FIFO, the next AR channel transmission request can be initiated without waiting for data from the R channel. The maximum advance transmission depth of 4 means that if the main module has already transmitted data to the TX-FIFO 4 times but still hasn't received data from the R channel, the main module will actively stop the request and wait for the R data to return before initiating the next request. The AW channel uses a similar transmission mechanism, meaning that the AR channel can continue to initiate multiple requests before the B channel responds, with the maximum number of requests equal to the preset maximum depth.

[0068] Based on this, in order to comprehensively and thoroughly describe the signal transmission method provided by the embodiments of this disclosure, in one embodiment, the signal transmission method provided by the embodiments of this disclosure may further include the following steps: Obtain the protocol configuration parameters of the signal transmission system. The protocol configuration parameters include at least the lead transmission depth of the write address channel AW, the lead transmission depth of the read address channel AR, the maximum length of the write burst transmission, and the maximum length of the read burst transmission. Based on the protocol configuration parameters of the signal transmission system, determine the cache depth of the first asynchronous buffer and the cache depth of the second asynchronous buffer.

[0069] The above-mentioned protocol configuration parameters can be ACE protocol parameters, and no specific restrictions are made here.

[0070] Specifically, the signal transmission system can obtain the protocol configuration parameters of the signal transmission system. Since the protocol configuration parameters may include at least parameters such as the lead transmission depth of the write address channel AW, the lead transmission depth of the read address channel AR, the maximum length of the write burst transmission, and the maximum length of the read burst transmission, the cache depth of the first asynchronous buffer and the cache depth of the second asynchronous buffer can be determined based on the protocol configuration parameters.

[0071] Based on this, in one embodiment, when multiple transmission channels include CD channel, CR channel, AR channel, AW channel and W channel, the cache depth of the first asynchronous buffer and the cache depth of the second asynchronous buffer satisfy the relationship shown in the following formula (1): +2 (1) in, The cache depths of the first asynchronous cache and the cache depth of the second asynchronous cache are given. For write address channel AW, For the read address channel AR advance transmission depth, The maximum length for writing burst transmissions.

[0072] In the above formula This indicates the maximum length of the burst transmission in the AW channel (because awlen=0, it means the burst transmission length is 1), which is the maximum number of W requests that need to be written to the FIFO for one AW request. Additionally, since the AC channel does not support forward transmission, according to the ACE protocol standard, an AC request needs to receive a CR or CRCD response before initiating the next AC request. Therefore, CR and CD occupy a maximum of 2 FIFO depths, and the +2 at the end of the formula represents the CR and CD requests respectively.

[0073] In another embodiment, when multiple first transmission channels include AC channel, R channel and B channel, the cache depth of the first asynchronous buffer and the cache depth of the second asynchronous buffer satisfy the relationship shown in the following formula (2): )+1(2) in, The cache depths of the first asynchronous cache and the cache depth of the second asynchronous cache are given. For write address channel AW, For the read address channel AR advance transmission depth, Maximum length for reading burst transmission.

[0074] In the above formula, +1 indicates the maximum length of the burst transmission in the AW channel (because arlen=0, it means the burst transmission length is 1), which means that a single AR request requires a maximum of several R requests to be written to the FIFO. Additionally, the final +1 indicates an AC request. Because the AC channel does not support lookahead transmission, after an AC request is initiated, it is necessary to wait for CR and CD responses before allowing the next AC request.

[0075] In this embodiment, the depth of the asynchronous first-in-first-out buffer can be accurately determined by obtaining the protocol configuration parameters, thereby fundamentally avoiding the situation where the FIFO is full. As a result, there is no need to report the empty or full status to the sending end, achieving true decoupled transmission.

[0076] Based on the same inventive concept, this disclosure provides a signal transmission device that can be applied to a signal transmission system. The signal transmission system includes a first chip and a second chip, which can be specifically described in conjunction with the appendix. Figure 4 A signal transmission device provided in the embodiments of this disclosure will be described in detail.

[0077] Figure 4 This is a schematic diagram of the structure of a signal transmission device provided in an embodiment of this disclosure.

[0078] like Figure 4 As shown, the signal transmission device 500 may include: The writing module 410 is used to write multiple transmission signals to be transmitted into the first asynchronous buffer in the first chip through the first chip, so that the first asynchronous buffer buffers multiple transmission signals in the first clock domain. The transmitting module 420 is used to send multiple transmission signals to the second asynchronous buffer of the second chip through the first asynchronous buffer; The receiving module 430 is used to receive and buffer multiple transmission signals in the second clock domain through the second asynchronous buffer; The storage module 440 is used to store each transmission signal into the channel buffer corresponding to the transmission signal through the second chip, so that the second chip can read the transmission signal from multiple channel buffers for processing.

[0079] In one embodiment, the signal transmission device provided in this disclosure includes: The acquisition module is used to acquire the transmission signals transmitted by multiple first transmission channels through the signal transmission module of the first chip. The signal transmission module of the first chip is configured with multiple transmission channels, including multiple first transmission channels. The storage module is specifically used to store each transmission signal into the channel buffer of the first receiving channel corresponding to the transmission signal through the second chip. The signal receiving module of the second chip is configured with receiving channels corresponding to multiple transmission channels, including the first receiving channel. The transmission type of the first transmission channel corresponding to the transmission signal and the first receiving channel corresponding to the transmission signal are the same.

[0080] In one embodiment, the signal transmission device provided in this disclosure includes: The determining module is used to determine the signal priority of multiple transmitted signals through the priority sorting module of the first chip; The storage module is specifically used to write multiple transmission signals into the first asynchronous buffer in sequence according to the signal priority of the multiple transmission signals through the priority sorting module of the first chip, so that the first asynchronous buffer buffers multiple transmission signals in the first clock domain.

[0081] In one embodiment, the signal transmission device provided in this disclosure includes: The determination module is also used to determine the signal flag bit of each transmitted signal through the signal flag determination module of the first chip. The signal transmission module of the first chip is configured with multiple transmission channels, and the signal flag bit indicates the transmission channel to which the transmitted signal belongs among the multiple transmission channels. The storage module is specifically used to write each transmission signal and its signal flag bit into the first asynchronous buffer through the signal flag determination module of the first chip, so that the first asynchronous buffer binds and caches each transmission signal and its signal flag bit under the first clock domain.

[0082] In one embodiment, the second asynchronous buffer stores multiple transmission signals and a signal flag bit for each transmission signal; the signal transmission device provided in this disclosure includes: The read module is used to read the signal flag bit associated with each transmission signal cached in the second asynchronous buffer through the write judgment module of the second chip; The determination module is also used to determine the channel buffer corresponding to the transmission signal based on the information indicated by the signal flag bit through the write judgment module of the second chip.

[0083] In one embodiment, the signal receiving module of the second chip is configured with receiving channels corresponding to multiple transmission channels, and each receiving channel is connected to a channel buffer; the signal transmission device provided in this embodiment includes: The identification module is used to identify the transmission channel to which the transmitted signal belongs based on the signal flag bit through the write judgment module of the second chip; The matching module is used to match the transmission channel to which the transmitted signal belongs based on a preset correspondence between the transmission channel and the receiving channel, and to determine the receiving channel to which the transmitted signal belongs. The matching module is also used to match the receiving channel to which the transmitted signal belongs based on the preset correspondence between the receiving channel and the channel buffer, and to determine the channel buffer corresponding to the transmitted signal.

[0084] In one embodiment, the signal transmission device provided in this disclosure includes: The acquisition module is also used to acquire the protocol configuration parameters of the signal transmission system. The protocol configuration parameters include at least the lead transmission depth of the write address channel AW, the lead transmission depth of the read address channel AR, the maximum length of the write burst transmission, and the maximum length of the read burst transmission. The determination module is also used to determine the cache depth of the first asynchronous buffer and the cache depth of the second asynchronous buffer based on the protocol configuration parameters of the signal transmission system.

[0085] In one embodiment, the plurality of first transmission channels include a snooping data channel CD, a snooping response channel CR, a read address channel AR, a write address channel AW, and a write data channel W; the cache depth of the first asynchronous cache and the cache depth of the second asynchronous cache satisfy the following relationship:

[0086] in, For write address channel AW, For the read address channel AR advance transmission depth, To write the maximum length of burst transmission In one embodiment, the plurality of first transmission channels include a snooping address channel AC, a read data channel R, and a write response channel B, and the cache depth of the first asynchronous cache and the cache depth of the second asynchronous cache satisfy the following relationship: )+1 in, For write address channel AW, For the read address channel AR advance transmission depth, Maximum length for reading burst transmission.

[0087] It is understood that, when implementing the corresponding signal transmission method, the signal transmission device provided in the above embodiments can allocate the above processing to different program modules as needed to complete all or part of the processing described above. Furthermore, the device and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0088] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a signal transmission method.

[0089] This application provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored and when executed by a processor, they will cause the processor to execute the signal transmission method provided in this application.

[0090] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0091] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0092] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0093] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0094] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; as shown below. Figure 5 As shown, the electronic device 50 includes: a processor 501, and a memory 502 communicatively connected to the processor 501; the memory 502 stores instructions executable by the processor 501. The instructions are executed by the processor 501 to enable the processor 501 to perform: The first chip writes multiple transmission signals to be transmitted into the first asynchronous buffer in the first chip, so that the first asynchronous buffer buffers the multiple transmission signals in the first clock domain; The first asynchronous buffer sends the plurality of transmission signals to the second asynchronous buffer of the second chip; The second asynchronous buffer receives and buffers the plurality of transmission signals in the second clock domain; The second chip stores each of the transmission signals into the channel buffer corresponding to the transmission signal, so that the second chip can read the transmission signals from the multiple channel buffers for processing.

[0095] The electronic devices and corresponding signal transmission methods provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0096] In practical applications, the electronic device 50 may further include at least one network interface 503. The various components of the electronic device 50 are coupled together via a bus system 504. It is understood that the bus system 504 is used to implement communication between these components. In addition to a data bus, the bus system 504 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 5 All buses are labeled as bus system 504. The number of processors 501 and the number of memories 502 can be at least one. The network interface 503 is used for wired or wireless communication between the electronic device 50 and other devices.

[0097] The memory 502 in this embodiment is used to store various types of data to support the operation of the electronic device 50.

[0098] The methods disclosed in the above embodiments of this disclosure can be applied to processor 501, or implemented by processor 501. Processor 501 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 501 or by instructions in the form of software. The processor 501 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 501 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 502. Processor 501 reads the information in memory 502 and, in conjunction with its hardware, completes the steps of the aforementioned signal transmission method.

[0099] In some embodiments, the electronic device 50 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0100] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0101] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0102] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0103] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0104] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0105] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A signal transmission method, characterized in that, Applied to a signal transmission system, the signal transmission system including a first chip and a second chip, the method includes: The first chip writes multiple transmission signals to be transmitted into the first asynchronous buffer in the first chip, so that the first asynchronous buffer buffers the multiple transmission signals in the first clock domain; The first asynchronous buffer sends the plurality of transmission signals to the second asynchronous buffer of the second chip; The second asynchronous buffer receives and buffers the plurality of transmission signals in the second clock domain; The second chip stores each of the transmission signals into the channel buffer corresponding to the transmission signal, so that the second chip can read the transmission signals from the multiple channel buffers for processing.

2. The method according to claim 1, characterized in that, Before the step of storing each of the transmission signals into the channel buffer corresponding to the transmission signal via the second chip, so that the first asynchronous buffer buffers the plurality of transmission signals in the first clock domain, the method further includes: The first chip obtains transmission signals transmitted by multiple first transmission channels through its signal transmission module. The first chip's signal transmission module is configured with multiple transmission channels, including the multiple first transmission channels. The step of storing each of the transmission signals into the channel buffer corresponding to the transmission signal through the second chip, so that the first asynchronous buffer buffers the plurality of transmission signals in the first clock domain, includes: The second chip stores each of the transmission signals into the channel buffer of the first receiving channel corresponding to the transmission signal. The signal receiving module of the second chip is configured with receiving channels corresponding to the plurality of transmission channels respectively. The plurality of receiving channels include the first receiving channel. The transmission type of the first transmission channel corresponding to the transmission signal and the first receiving channel corresponding to the transmission signal are the same.

3. The method according to claim 1, characterized in that, Before the step of storing each of the transmission signals into the channel buffer corresponding to the transmission signal via the second chip, so that the first asynchronous buffer buffers the plurality of transmission signals in the first clock domain, the method further includes: The signal priority of the plurality of transmitted signals is determined by the priority sorting module of the first chip; The step of storing each of the transmission signals into the channel buffer corresponding to the transmission signal through the second chip, so that the first asynchronous buffer buffers the plurality of transmission signals in the first clock domain, includes: The priority sorting module of the first chip sequentially writes the multiple transmission signals into the first asynchronous buffer according to their signal priorities, so that the first asynchronous buffer buffers the multiple transmission signals in the first clock domain.

4. The method according to any one of claims 1 to 3, characterized in that, Before the step of writing multiple transmission signals to be transmitted into a first asynchronous buffer in the first chip via the first chip, so that the first asynchronous buffer buffers the multiple transmission signals in the first clock domain, the method further includes: The signal flag bit of each transmitted signal is determined by the signal flag determination module of the first chip. The signal transmission module of the first chip is configured with multiple transmission channels. The signal flag bit indicates the transmission channel to which the transmitted signal belongs among the multiple transmission channels. The step of writing multiple transmission signals to be transmitted into a first asynchronous buffer in the first chip via the first chip, so that the first asynchronous buffer buffers the multiple transmission signals in a first clock domain, includes: The signal flag determination module of the first chip writes each of the transmitted signals and the signal flag bits of the transmitted signals into the first asynchronous buffer, so that the first asynchronous buffer binds and caches each of the transmitted signals and the signal flag bits of the transmitted signals under the first clock domain.

5. The method according to claim 4, characterized in that, The second asynchronous buffer stores multiple transmission signals and a signal flag bit for each transmission signal; Before storing each of the transmission signals into the channel buffer corresponding to the transmission signal via the second chip, the method further includes: For each transmission signal cached in the second asynchronous buffer, the signal flag bit associated with the transmission signal is read by the write judgment module of the second chip; The write judgment module of the second chip determines the channel buffer corresponding to the transmission signal based on the information indicated by the signal flag bit.

6. The method according to claim 5, characterized in that, The signal receiving module of the second chip is configured with receiving channels corresponding to the plurality of transmission channels respectively, and each receiving channel is connected to a channel buffer; The step of determining the channel buffer corresponding to the transmission signal by the write judgment module of the second chip based on the information indicated by the signal flag bit includes: The write judgment module of the second chip identifies the transmission channel to which the transmission signal belongs based on the signal flag bit; Based on the preset correspondence between transmission channels and receiving channels, the transmission channel to which the transmitted signal belongs is matched to determine the receiving channel to which the transmitted signal belongs. Based on the preset correspondence between receiving channels and channel buffers, the receiving channel to which the transmitted signal belongs is matched to determine the channel buffer corresponding to the transmitted signal.

7. The method according to claim 2, characterized in that, The method includes: Obtain the protocol configuration parameters of the signal transmission system. The protocol configuration parameters include at least the lead transmission depth of the write address channel AW, the lead transmission depth of the read address channel AR, the maximum length of the write burst transmission, and the maximum length of the read burst transmission. The cache depth of the first asynchronous buffer and the cache depth of the second asynchronous buffer are determined according to the protocol configuration parameters of the signal transmission system.

8. The method according to claim 7, characterized in that, The plurality of transmission channels include CD channel, CR channel, AR channel, AW channel, and W channel; the cache depth of the first asynchronous buffer and the cache depth of the second asynchronous buffer satisfy the following relationship: in, For write address channel AW, For the read address channel AR advance transmission depth, The maximum length for writing burst transmissions.

9. The method according to claim 7, characterized in that, The plurality of first transmission channels include an AC channel, an R channel, and a B channel, and the cache depth of the first asynchronous buffer and the cache depth of the second asynchronous buffer satisfy the following relationship: )+1 in, For write address channel AW, For the read address channel AR advance transmission depth, Maximum length for reading burst transmission.

10. A signal transmission device, characterized in that, The device is applied to a signal transmission system, which includes a first chip and a second chip, and includes: The writing module is used to write multiple transmission signals to be transmitted into a first asynchronous buffer in the first chip through the first chip, so that the first asynchronous buffer buffers the multiple transmission signals in a first clock domain; A transmitting module is used to send the plurality of transmission signals to a second asynchronous buffer of the second chip via the first asynchronous buffer; The receiving module is configured to receive and buffer the plurality of transmission signals in the second clock domain via the second asynchronous buffer; The storage module is used to store each of the transmission signals into the channel buffer corresponding to the transmission signal through the second chip, so that the second chip reads the transmission signals from the multiple channel buffers for processing.

11. The apparatus according to claim 10, characterized in that, The device includes: The acquisition module is used to acquire transmission signals transmitted by multiple first transmission channels through the signal transmission module of the first chip. The signal transmission module of the first chip is configured with multiple transmission channels, and the multiple transmission channels include the multiple first transmission channels. The storage module is specifically used to store each of the transmission signals into the channel buffer of the first receiving channel corresponding to the transmission signal through the second chip. The signal receiving module of the second chip is configured with receiving channels corresponding to the plurality of transmission channels respectively. The plurality of receiving channels include the first receiving channel. The transmission type of the first transmission channel corresponding to the transmission signal and the first receiving channel corresponding to the transmission signal are the same.

12. The apparatus according to claim 10, characterized in that, The device includes: The determining module is used to determine the signal priority of the plurality of transmitted signals through the priority sorting module of the first chip; The storage module is specifically used to write the plurality of transmission signals into the first asynchronous buffer in sequence according to the signal priority of the plurality of transmission signals through the priority sorting module of the first chip, so that the first asynchronous buffer buffers the plurality of transmission signals in the first clock domain.

13. The apparatus according to any one of claims 10 to 12, characterized in that, The device includes: The determining module is further configured to determine the signal flag bit of each of the transmitted signals through the signal flag determining module of the first chip, wherein the signal transmitting module of the first chip is configured with multiple transmission channels, and the signal flag bit indicates the transmission channel to which the transmitted signal belongs in the multiple transmission channels; The storage module is specifically used to write each of the transmission signals and the signal flag bits of the transmission signals into the first asynchronous buffer through the signal flag determination module of the first chip, so that the first asynchronous buffer binds and caches each of the transmission signals and the signal flag bits of the transmission signals under the first clock domain.

14. The apparatus according to claim 13, characterized in that, The second asynchronous buffer stores multiple transmission signals and a signal flag bit for each transmission signal; the device includes: The read module is used to read the signal flag bit associated with each transmission signal cached in the second asynchronous buffer through the write judgment module of the second chip; The determination module is also used to determine the channel buffer corresponding to the transmission signal based on the information indicated by the signal flag bit through the write judgment module of the second chip.

15. The apparatus according to claim 14, characterized in that, The signal receiving module of the second chip is configured with receiving channels corresponding to the plurality of transmission channels respectively, and each receiving channel is connected to a channel buffer; The identification module is used to identify the transmission channel to which the transmission signal belongs based on the signal flag bit through the write judgment module of the second chip; The matching module is used to match the transmission channel to which the transmitted signal belongs based on a preset correspondence between transmission channels and receiving channels, and to determine the receiving channel to which the transmitted signal belongs. The matching module is also used to match the receiving channel to which the transmitted signal belongs based on a preset correspondence between the receiving channel and the channel buffer, and to determine the channel buffer corresponding to the transmitted signal.

16. The apparatus according to claim 11, characterized in that, The device includes: The acquisition module is also used to acquire the protocol configuration parameters of the signal transmission system. The protocol configuration parameters include at least the lead transmission depth of the write address channel AW, the lead transmission depth of the read address channel AR, the maximum length of the write burst transmission, and the maximum length of the read burst transmission. The determining module is further configured to determine the cache depth of the first asynchronous buffer and the cache depth of the second asynchronous buffer based on the protocol configuration parameters of the signal transmission system.

17. The apparatus according to claim 16, characterized in that, The plurality of transmission channels include a snooping data channel CD, a snooping response channel CR, a read address channel AR, a write address channel AW, and a write data channel W; the cache depth of the first asynchronous cache and the cache depth of the second asynchronous cache satisfy the following relationship: in, For write address channel AW, For the read address channel AR advance transmission depth, The maximum length for writing burst transmissions.

18. The apparatus according to claim 16, characterized in that, The plurality of transmission channels include a snooping address channel AC, a read data channel R, and a write response channel B. The cache depth of the first asynchronous cache and the cache depth of the second asynchronous cache satisfy the following relationship: )+1 in, For write address channel AW, For the read address channel AR advance transmission depth, Maximum length for reading burst transmission.

19. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the signal transmission method according to any one of claims 1 to 9.

20. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the signal transmission method according to any one of claims 1 to 9.

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