Power module reliability optimization design method, system and equipment based on solder layer thickness and medium

Abstract

The invention belongs to the technical field of power module design, discloses a power module reliability optimization design method, system and equipment based on the thickness of a solder layer and a medium, and aims to solve the problem that the optimal thickness of the solder layer cannot be accurately determined in the prior art. The method comprises the steps that a thermal-mechanical coupling simulation model is constructed, and thermal stress distribution data are obtained through simulation with the thickness of a solder layer as a variable; selecting a theoretical optimal thickness and a rapid change area representative thickness based on a simulation result to prepare a sample, and determining the thickness with a slow aging speed as a first optimal thickness through a power cycle experiment; scanning the aged sample to calculate the porosity, and determining the thickness with smaller porosity as a second optimal thickness; and carrying out collaborative analysis on the three, directly determining if the three are consistent, otherwise, taking the first optimal thickness as the criterion. According to the method, simulation-experiment-observation integrated optimization is realized, and the scientificity and the accuracy of the thickness design of the solder layer are remarkably improved.

Description

Technical Field

[0001] This invention belongs to the field of power module design technology, and specifically relates to a power module reliability optimization design method, system, equipment and medium based on solder layer thickness. Background Technology

[0002] Currently, power modules, with their high power density, high efficiency, and compact design, have become key components in power electronic systems such as new energy vehicles, industrial frequency converters, and photovoltaic inverters. As system requirements for power levels and switching frequencies continue to increase, power modules are constantly evolving towards miniaturization and higher power density, which places higher demands on their heat dissipation performance and long-term reliability.

[0003] However, with the reduction in chip size and the increase in power density, the thermal stress problem caused by the mismatch of the thermal expansion coefficients of materials within the module is becoming increasingly prominent. During power cycling, repeated temperature differences occur between the chip and the solder layer, substrate, and other packaging structures, causing plastic strain within the solder layer. Long-term accumulation can lead to defects such as microcracks and voids, resulting in increased thermal resistance and deterioration of the heat conduction path, thus affecting the module's lifespan and reliability. Especially in high-power applications, solder layer failure not only directly causes module performance degradation but may also trigger localized overheating, threatening the safe operation of the entire system. Therefore, optimizing solder layer design and improving its resistance to thermal fatigue has become a crucial aspect of power module reliability design.

[0004] In existing solder layer research methods, finite element simulation and power cycling experiments are commonly used analytical tools to evaluate the impact of different structural parameters on solder layer stress and lifespan. However, existing simulation models often follow the analytical approach of traditional packaging, failing to fully capture the actual operating characteristics of power modules, such as small size, high heat flux density, and large junction temperature fluctuations. This leads to deviations in simulation results regarding stress distribution and failure prediction in critical areas. Furthermore, traditional methods often focus on overall average stress or macroscopic thermal resistance changes, making it difficult to accurately capture the degradation behavior of local stress concentration areas such as solder layer edges. They also cannot effectively identify the critical point of solder layer thickness that achieves the optimal balance between thermo-mechanical properties. Moreover, simulation analysis and experimental verification are often conducted in isolation, lacking a systematic collaborative design method, resulting in insufficient accuracy and systematic guidance in the design process.

[0005] In summary, for power modules, how to accurately analyze the relationship between chip solder layer thickness and thermal stress and reliability, and how to efficiently and accurately determine the optimal solder layer thickness in the initial design stage of module packaging, have become urgent technical problems to be solved in this field. Summary of the Invention

[0006] Based on the aforementioned shortcomings and deficiencies in the prior art, one of the objectives of this invention is to at least solve one or more of the aforementioned problems in the prior art. In other words, one of the objectives of this invention is to provide a power module reliability optimization design method, system, device, and medium based on solder layer thickness that meets one or more of the aforementioned requirements, so as to scientifically lock the optimal solder layer thickness and improve the long-term operational reliability of the power module in the initial design stage of module packaging.

[0007] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a power module reliability optimization design method based on solder layer thickness, comprising the following steps: S1. Construct a thermal-mechanical coupling simulation model of the power module, and perform simulation with the thickness of the chip solder layer as a variable to obtain thermal stress distribution data of the chip solder layer under different thicknesses. S2. Based on the thermal stress distribution data, the thickness corresponding to the global minimum value of thermal stress is selected as the theoretical optimal thickness, and the thickness located in the maximum gradient range where thermal stress decreases with increasing thickness is selected as the representative thickness of the rapid change zone. Experimental samples are prepared using the theoretical optimal thickness and the representative thickness of the rapid change zone. Power cycle aging experiments are conducted under different preset working conditions to obtain thermal resistance change data. Based on the thermal resistance change data, the thickness corresponding to the experimental sample with a slower actual aging rate is determined as the first optimal thickness. S3. Scan the experimental samples after the power cycle aging test to obtain the internal structure image of the chip solder layer of each experimental sample, and process the internal structure image to calculate the porosity of the chip solder layer of each experimental sample, and determine the thickness corresponding to the experimental sample with smaller porosity as the second optimal thickness. S4. Perform a joint analysis on the theoretical optimal thickness, the first optimal thickness, and the second optimal thickness. If the three are consistent, the consistent thickness is determined as the final optimal thickness; if the three are inconsistent, the first optimal thickness is determined as the final optimal thickness.

[0008] As a preferred option: The thermo-mechanical coupling simulation model includes the chip, the chip solder layer, and the DBC substrate; The chip is soldered onto the DBC substrate through the chip solder layer.

[0009] As a preferred option: During the simulation, a constant heat flux density is applied to the upper surface of the chip, a high convective heat transfer coefficient is applied to the bottom of the DBC substrate to simulate water cooling conditions, and a fixed surface is defined on one side of the heat sink in the mechanical simulation.

[0010] As a preferred option: The power cycling aging test was conducted using a power cycling test platform. The power cycling test platform adopts a parallel test topology with one arm for heating and the other for cooling.

[0011] As a preferred option: In step S2, the thermal resistance change data is obtained by a thermal resistance test method based on structure function, and the actual aging rate is evaluated by using a 20% increase in thermal resistance as a failure criterion.

[0012] As a preferred embodiment, step S3, calculating the porosity of the chip solder layer, includes: The internal structure image is then converted to grayscale and denoised. Set a grayscale threshold to distinguish solder material from voids; Count the number of pixels in the gaps and the total number of pixels in the solder layer; The porosity is calculated based on the ratio of the number of void pixels to the total number of pixels in the solder layer.

[0013] In a second aspect, the present invention provides a power module reliability optimization design system based on solder layer thickness, used to implement the power module reliability optimization design method as described in the first aspect, including: The simulation module is used to build a thermal-mechanical coupling simulation model of the power module, and to perform simulation with the thickness of the chip solder layer as a variable, outputting thermal stress distribution data of the chip solder layer under different thicknesses; The experimental platform is used to conduct power cycle aging experiments on power module experimental samples with at least two chip solder layers of different thicknesses, and output the thermal resistance change data of each experimental sample during the aging process. The scanning and analysis module is used to scan the chip solder layer of the power module experimental sample, obtain its internal structure image, and process the internal structure image to output the porosity of the chip solder layer. The decision module is connected to the simulation module, the experimental platform, and the scanning and analysis module, respectively, and is used to receive the thermal stress distribution data, the thermal resistance change data, and the porosity, and determine the final optimal thickness according to the preset decision logic.

[0014] As a preferred embodiment, the preset decision logic of the decision module includes: The theoretically optimal thickness is determined based on the thermal stress distribution data. The first optimal thickness is determined based on the thermal resistance variation data; The second optimal thickness is determined based on the porosity; A collaborative analysis is performed on the theoretical optimal thickness, the first optimal thickness, and the second optimal thickness. If the three are consistent, the consistent thickness is determined as the final optimal thickness; if the three are inconsistent, the first optimal thickness is determined as the final optimal thickness.

[0015] Thirdly, the present invention provides an electronic device, the computer device including a memory, a processor and a computer program, wherein when the computer program is executed by the processor, it implements the power module reliability optimization design method as described in the first aspect.

[0016] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the power module reliability optimization design method as described in the first aspect.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention overcomes the shortcomings of traditional silicon-based module-based simulation methods in application scenarios by constructing a thermo-mechanical coupling simulation model tailored to the characteristics of power modules, accurately inputting real material parameters, and setting boundary conditions that fit their high power density operation. The simulation model can accurately capture the stress distribution in local stress concentration areas such as solder layer edges, providing a reliable theoretical prediction basis for subsequent experimental verification.

[0018] 2. In the experimental verification stage, this invention adopts a parallel testing topology of "one arm heating and one arm cooling," enabling simultaneous aging tests on multiple module samples, significantly shortening the verification cycle and reducing testing costs. Simultaneously, combined with a periodic thermal resistance monitoring method based on structure functions, it can accurately identify changes in solder layer thermal resistance, objectively assessing the actual aging rate of solder layers of different thicknesses based on the rate of increase in thermal resistance.

[0019] 3. This invention introduces high-resolution 3D X-ray scanning technology to perform non-destructive testing on the internal structure of the aged solder layer, accurately capturing microscopic defects such as voids and cracks. Image processing technology is used to statistically analyze the porosity of these microscopic defects, transforming morphological differences into objective quantitative data. This achieves precise quantification of the degree of solder layer degradation, providing microscopic-level data support for failure mechanism analysis.

[0020] 4. This invention integrates simulation prediction, experimental verification, and microscopic observation data for collaborative analysis. This ensures that the final optimal thickness conclusion is based on theoretical predictions of minimum stress, experimental verification of the slowest aging rate, and microscopic morphology support of the lowest porosity. When the results from the three dimensions conflict, the power cycle experimental data, which most directly reflects the module's lifespan, is used as the primary decision-making basis. This approach balances theoretical foresight with engineering practicality, fundamentally avoiding the limitations of a single analytical dimension.

[0021] Further or more detailed beneficial effects will be described in conjunction with specific embodiments in the detailed implementation. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating the power module reliability optimization design method provided in Embodiment 1 of the present invention.

[0024] Figure 2 This is a graph showing the variation of the maximum equivalent stress of the solder layer with thickness as described in Embodiment 1 of the present invention.

[0025] Figure 3 This is the temperature diagram under a thickness of 0.20 mm as described in Embodiment 1 of the present invention.

[0026] Figure 4 This is the stress distribution diagram under a thickness of 0.20 mm as described in Embodiment 1 of the present invention.

[0027] Figure 5 This is a graph showing the change of thermal resistance with aging cycle under operating condition 1 as described in Embodiment 1 of the present invention.

[0028] Figure 6 This is a graph showing the change of thermal resistance with aging cycle under operating condition 2 as described in Embodiment 1 of the present invention.

[0029] Figure 7 This is a graph showing the change of thermal resistance with aging cycle under operating condition 3 as described in Embodiment 1 of the present invention.

[0030] Figure 8 This is a graph showing the change of thermal resistance with aging cycle under operating condition 4 as described in Embodiment 1 of the present invention.

[0031] Figure 9 This is a comparison image of 3D X-ray pore scanning as described in Embodiment 1 of the present invention.

[0032] Figure 10 This is a structural diagram of the electronic device provided in Embodiment 3 of the present invention.

[0033] Icon labels: 1000. Electronic devices; 1001. Processor; 1002. Communication bus; 1003. User interface; 1004. Network interface; 1005. Memory. Detailed Implementation

[0034] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0035] In the following description, several embodiments of the present invention are provided. Different embodiments can be substituted or combined. Therefore, the present invention can also be considered to include all possible combinations of the same and / or different embodiments described. Thus, if one embodiment includes features A, B, and C, and another embodiment includes features B and D, then the present invention should also be considered to include embodiments containing one or more other possible combinations of A, B, C, and D, even if such embodiments are not explicitly described in the following text.

[0036] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the described elements without departing from the scope of the invention. Various processes or components may be appropriately omitted, substituted, or added to the various examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.

[0037] To facilitate a better understanding of the embodiments of the present invention, its application scenarios will be explained before providing a detailed explanation of the specific implementation methods.

[0038] The power module reliability optimization design method described in the embodiments of this specification is applied to the packaging design of power modules, especially in situations where the thickness of the chip solder layer needs to be optimized during the initial design stage of the power module. In these scenarios, the application of the power module reliability optimization design method aims to scientifically and efficiently determine the solder layer thickness that ensures the optimal reliability of the power module under long-term power cycling conditions through an integrated approach combining simulation prediction, experimental verification, and microscopic observation. This improves the module's resistance to thermal fatigue from the source of module design, avoiding module performance degradation and system operation risks caused by solder layer failure.

[0039] The following is a brief explanation of the power modules, thermo-mechanical coupling simulation models, thermal stress, power cycling aging experiments, parallel test topologies, and structure functions involved in several embodiments of this specification: A power module is a power electronic device that integrates multiple power chips (such as IGBTs, MOSFETs, and diodes) into a single unit using packaging materials such as solder layers, DBC substrates, bonding wires, and housings. Its typical structure involves the chips being soldered onto a DBC substrate via a solder layer, the DBC substrate being soldered to a base plate via another solder layer, and the chips being electrically connected via bonding wires. Power modules are characterized by high power density, high efficiency, and compact design, and are widely used in power electronic systems such as new energy vehicles, industrial frequency converters, photovoltaic inverters, wind power generation, and rail transportation, serving as core components for power conversion and control.

[0040] A thermo-mechanical coupling simulation model is a computer simulation model established using the finite element method that can simultaneously simulate the temperature distribution of a power module during the heating process and the distribution of thermal stress caused by temperature changes. This model first performs a thermal analysis to calculate the temperature field distribution of the module under given heat source and boundary conditions. Then, the temperature field results are imported as loads into the structural mechanics analysis to calculate the thermal stress distribution caused by the mismatch in the thermal expansion coefficients of the materials. Through thermo-mechanical coupling simulation, the thermodynamic behavior of the power module under different structural parameters and operating conditions can be predicted, providing a theoretical basis for reliability design.

[0041] Thermal stress refers to the internal stress generated between different material layers due to the mismatch in their coefficients of thermal expansion, resulting from the different degrees of expansion or contraction when the temperature changes. In a power module, the chip (with a lower coefficient of thermal expansion), the solder layer (with a higher coefficient of thermal expansion), and the DBC substrate (with a moderate coefficient of thermal expansion) are tightly soldered together. When the module is powered on and heats up, each layer expands, but to different degrees—the solder layer wants to expand more, while the chip wants to expand less. However, they are firmly fixed together by the solder and cannot deform freely, thus generating tensile or compressive forces within the materials; this is thermal stress. Long-term, repeated thermal stress can cause plastic strain in the solder layer, accumulating to form microcracks and voids, ultimately leading to fatigue failure.

[0042] Power cycle aging testing is an experimental method that accelerates module aging and assesses its reliability by periodically switching heating current on and off, causing the junction temperature of the power module to fluctuate between a set minimum and maximum junction temperature. During the experiment, the amplitude and on / off time of the heating current are controlled to raise the module temperature to the set maximum junction temperature during the conduction phase and lower it to the set minimum junction temperature during the turn-off phase, repeating this cycle repeatedly. With increasing cycle count, fatigue damage gradually accumulates in the solder layer and other packaging structures, manifesting as increased thermal resistance and saturation voltage drop. By periodically monitoring changes in these key parameters, the reliability level of the power module under different structural parameters or process conditions can be evaluated.

[0043] Parallel testing topology refers to an experimental platform topology capable of simultaneously performing power cycle aging tests on multiple power module samples. Traditional power cycle testing typically only tests one sample at a time, resulting in low testing efficiency. Parallel testing topology employs a "one-arm heating, one-arm cooling" design, meaning that while one sample is being heated, another is being cooled. Through precise timing staggered scheduling, the testing equipment can alternately perform heating and cooling operations on multiple samples. This topology can fully utilize the power capacity and heat dissipation capabilities of the testing equipment, significantly shortening the overall testing cycle and improving testing efficiency, making it particularly suitable for research scenarios requiring multiple sets of comparative experiments.

[0044] Structure function (SFC) is a mathematical method that extracts thermal resistance and thermal capacity information of each material layer within a power module by analyzing its temperature-time response curve during the cooling process. When the heating current is turned off, the junction temperature decreases exponentially; this cooling curve contains information about the entire heat conduction path from the chip to the heat sink within the module. By mathematically transforming the cooling curve, a structure function curve representing the cumulative thermal capacity versus cumulative thermal resistance can be obtained. Each "plateau" or "inflection point" on the curve corresponds to a material layer within the module (such as the chip, chip solder layer, DBC ceramic layer, DBC solder layer, baseplate, etc.). By comparing the SFC curves before and after aging, the specific material layer where thermal resistance changes significantly can be identified, thus accurately locating the failure site. This is an important tool for power module failure analysis.

[0045] Example 1: like Figure 1 As shown, this embodiment provides a power module reliability optimization design method based on solder layer thickness, including the following steps: S1. Construct a thermo-mechanical coupling simulation model of the power module, and perform simulation with the thickness of the chip solder layer as a variable to obtain thermal stress distribution data of the chip solder layer under different thicknesses.

[0046] In this embodiment, a three-dimensional finite element model is established using a certain type of IGBT power module as a prototype, including the chip, the chip solder layer, and the DBC substrate. The chip is soldered to the DBC substrate through the chip solder layer. The model omits structures such as bonding lines that have little impact on the stress distribution of the solder layer, in order to focus on the core heat conduction path and key stress areas.

[0047] The material parameters were set with full consideration of the actual characteristics of the power module: the chip uses silicon material with a thermal conductivity of 150 W / m·K, an elastic modulus of 190,000 MPa, and a coefficient of thermal expansion of 4.2E-6 / ℃; the solder layer uses SAC305 solder with a thermal conductivity of 53 W / m·K, an elastic modulus of 33,550 MPa, and a coefficient of thermal expansion of 23.0E-6 / ℃; the copper layer of the DBC substrate has a thermal conductivity of 393 W / m·K and a coefficient of thermal expansion of 16.7E-6 / ℃, and the ceramic layer (Al2O3) has a thermal conductivity of 28 W / m·K and a coefficient of thermal expansion of 6.9E-6 / ℃.

[0048] The boundary conditions were set to match the actual operating environment of the power module: the initial temperature was set to 60℃, a constant heat flux density of 50W was applied to the upper surface of the chip to simulate chip heating, and a 3.3×10⁻⁶ W heat flux density was applied to the bottom of the DBC substrate. - A high convective heat transfer coefficient of 2W / mm²·℃ was used to simulate water-cooled heat dissipation conditions, and one side of the radiator was fixed in the mechanical simulation.

[0049] The thickness of the chip solder layer was used as a variable, and parametric scanning simulations were performed in increments of 0.03 mm within the range of 0.10 mm to 0.40 mm. Through thermo-mechanical coupling analysis, the maximum equivalent stress (Von Mises stress) of the solder layer at each thickness was extracted, resulting in... Figure 2 The curve shown illustrates the variation of the maximum equivalent stress of the solder layer with thickness. Figure 3 and Figure 4 The simulation results further demonstrate the temperature and stress distribution cloud maps obtained at a thickness of 0.20 mm, showing that there is a significant stress concentration phenomenon at the edge of the solder layer.

[0050] S2. Based on the thermal stress distribution data, the thickness corresponding to the global minimum value of thermal stress is selected as the theoretical optimal thickness, and the thickness located in the maximum gradient range where thermal stress decreases with increasing thickness is selected as the representative thickness of the rapid change zone. Experimental samples are prepared using the theoretical optimal thickness and the representative thickness of the rapid change zone. Power cycle aging experiments are conducted under different preset working conditions to obtain thermal resistance change data. Based on the thermal resistance change data, the thickness corresponding to the experimental sample with a slower actual aging rate is determined as the first optimal thickness.

[0051] In this embodiment, based on the simulation results of S1, such as Figure 2 As shown, the thermal stress reaches its global minimum when the solder layer thickness is 0.20 mm, therefore 0.20 mm is determined as the theoretically optimal thickness. Meanwhile, the gradient of thermal stress decreases is largest within the range where the thickness increases from 0.15 mm to 0.20 mm, indicating that this range is the most sensitive region to the stress effect of thickness changes. Therefore, 0.15 mm is selected as the representative thickness for the rapidly changing region.

[0052] Power module experimental samples were prepared using chip solder layers of 0.15 mm and 0.20 mm thickness, and aging tests were conducted on a power cycling test platform. This test platform adopts a parallel test topology with "one arm heating and one arm cooling," which can test multiple samples simultaneously. While one sample is heated, another sample is cooled, significantly shortening the overall test cycle.

[0053] The experiment included four typical operating conditions covering real-world application scenarios for power modules: Tjmin / ΔTj were 40 / 40℃, 40 / 60℃, 40 / 80℃, and 80 / 60℃, respectively. During the experiment, the chip-to-casing thermal resistance Rthjc of each sample was periodically monitored using a structure function-based thermal resistance testing method. A 20% increase in thermal resistance was used as the failure criterion. The number of cycles required for each sample to reach the failure criterion was recorded, and the rate of increase in thermal resistance under different thicknesses was compared across the various operating conditions.

[0054] Figures 5-8 The curves showing the change in thermal resistance of samples with thicknesses of 0.15 mm and 0.20 mm as a function of aging cycles under different operating conditions are presented. Figure 5 For the operating condition corresponding to Tjmin / ΔTj=40 / 40℃, Figure 6 For operating conditions of 40 / 60℃, Figure 7 For operating conditions of 40 / 80℃, Figure 8 This corresponds to operating conditions of 80 / 60℃. As can be clearly seen from the figure, under all four operating conditions, the thermal resistance increase rate of the 0.20mm thick sample is significantly slower than that of the 0.15mm sample, demonstrating superior anti-aging performance. Therefore, based on the thermal resistance change data, 0.20mm is determined as the first optimal thickness.

[0055] S3. Scan the experimental samples after the power cycle aging test to obtain the internal structure image of the chip solder layer of each experimental sample, process the internal structure image to calculate the porosity of the chip solder layer of each experimental sample, and determine the thickness corresponding to the experimental sample with smaller porosity as the second optimal thickness.

[0056] In this embodiment, a 330kV 3D X-ray scanner is used to scan the sample that has completed the power cycle aging test to obtain a three-dimensional internal structure image of the chip solder layer. Figure 9 The images show a comparison of 3D X-ray scans of samples with thicknesses of 0.15mm (left) and 0.20mm (right). The images clearly show that the 0.15mm solder layer contains more microcracks and voids, while the 0.20mm solder layer has a relatively intact internal structure with fewer defects.

[0057] To further quantify the analysis, the scanned images were processed using image processing software as follows: Perform grayscale conversion and noise reduction on the internal structure image; A grayscale threshold is set based on the grayscale difference between the solder and the voids, and pixels below the threshold are identified as void regions. Count the number of pixels in the gaps and the total number of pixels in the solder layer; Porosity is calculated based on the proportion of void pixels to the total number of pixels in the solder layer.

[0058] The calculation results show that the solder layer porosity of the 0.15 mm thick sample is 5.2%, while that of the 0.20 mm thick sample is only 1.1%. The 0.20 mm sample with lower porosity corresponds to better microstructure integrity, and therefore it is determined to be the second optimal thickness.

[0059] S4. Perform a joint analysis on the theoretical optimal thickness, the first optimal thickness, and the second optimal thickness. If the three are consistent, the consistent thickness is determined as the final optimal thickness; if the three are inconsistent, the first optimal thickness is determined as the final optimal thickness.

[0060] In this embodiment, the theoretically optimal thickness (from S1 simulation) is 0.20 mm, the first optimal thickness (from S2 experiment) is 0.20 mm, and the second optimal thickness (from S3 microscopic observation) is 0.20 mm. Since all three are identical, 0.20 mm is determined as the final optimal thickness.

[0061] Through the above-mentioned integrated "simulation-experiment-observation" collaborative optimization method, this embodiment successfully determined the optimal thickness of the solder layer of the power module chip to be 0.20 mm. This thickness exhibits the best performance in terms of thermal stress distribution, anti-aging performance, and microstructure integrity.

[0062] Example 2: This embodiment provides a power module reliability optimization design system based on solder layer thickness, characterized in that it is used to implement the power module reliability optimization design method as described in Embodiment 1, including: The simulation module is used to build a thermal-mechanical coupling simulation model of the power module, and to perform simulation with the thickness of the chip solder layer as a variable, outputting thermal stress distribution data of the chip solder layer under different thicknesses; The experimental platform is used to conduct power cycle aging experiments on power module experimental samples with at least two chip solder layers of different thicknesses, and output the thermal resistance change data of each experimental sample during the aging process. The scanning and analysis module is used to scan the chip solder layer of the power module experimental sample, obtain its internal structure image, and process the internal structure image to output the porosity of the chip solder layer. The decision module is connected to the simulation module, the experimental platform, and the scanning and analysis module, respectively, and is used to receive the thermal stress distribution data, the thermal resistance change data, and the porosity, and determine the final optimal thickness according to the preset decision logic.

[0063] Specifically, the preset decision logic of the decision module includes: The theoretically optimal thickness is determined based on the thermal stress distribution data. The first optimal thickness is determined based on the thermal resistance variation data; The second optimal thickness is determined based on the porosity; A collaborative analysis is performed on the theoretical optimal thickness, the first optimal thickness, and the second optimal thickness. If the three are consistent, the consistent thickness is determined as the final optimal thickness; if the three are inconsistent, the first optimal thickness is determined as the final optimal thickness.

[0064] Example 3: like Figure 10 As shown, this embodiment provides an electronic device, which may include: at least one processor, at least one network interface, a user interface, a memory, and at least one communication bus.

[0065] The communication bus can be used to enable communication between the various components mentioned above.

[0066] The user interface may include buttons, and optional user interfaces may also include standard wired interfaces and wireless interfaces.

[0067] The network interface may include, but is not limited to, Bluetooth modules, NFC modules, Wi-Fi modules, etc.

[0068] The processor may include one or more processing cores. It connects various parts of the electronic device via various interfaces and lines, executing instructions, programs, code sets, or instruction sets stored in memory, and accessing data stored in memory to perform various functions and process data. Optionally, the processor can be implemented using at least one hardware form of DSP, FPGA, or PLA. The processor may integrate one or more of the following: CPU, GPU, and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip without being integrated into the processor.

[0069] The memory may include RAM or ROM. Optionally, the memory may include a non-transitory computer-readable medium. The memory can be used to store instructions, programs, code, code sets, or instruction sets. The memory may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor. The memory, as a computer storage medium, may include an operating system, a network communication module, a user interface module, and design applications. The processor can be used to call the design applications stored in the memory and execute the steps of the power module reliability optimization design method mentioned in the foregoing embodiments.

[0070] Example 4: This embodiment provides a computer-readable storage medium storing instructions that, when executed on a computer or processor, cause the computer or processor to perform the above-described instructions. Figure 1 One or more steps in the illustrated embodiment. If the constituent modules of the above-described electronic device are implemented as software functional units and sold or used as independent products, they can be stored in the computer-readable storage medium.

[0071] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this specification are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in or transmitted through a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., Digital Versatile Discs (DVDs)), or semiconductor media (e.g., Solid State Disks (SSDs)).

[0072] Those skilled in the art will understand that all or part of the processes in the method of Embodiment 1 described above can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks. Unless otherwise specified, the technical features of this embodiment and the implementation scheme can be combined arbitrarily.

[0073] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0074] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0075] The above description is merely an exemplary embodiment of the present invention and should not be construed as limiting the scope of the invention. Any equivalent changes and modifications made in accordance with the teachings of this invention are still within the scope of this invention. Those skilled in the art will readily conceive of embodiments of the invention upon considering the specification and practicing the disclosure herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of the invention are defined by the claims.

Claims

1. A power module reliability optimization design method based on solder layer thickness, characterized in that, Includes the following steps: S1. Construct a thermal-mechanical coupling simulation model of the power module, and perform simulation with the thickness of the chip solder layer as a variable to obtain thermal stress distribution data of the chip solder layer under different thicknesses. S2. Based on the thermal stress distribution data, the thickness corresponding to the global minimum value of thermal stress is selected as the theoretical optimal thickness, and the thickness located in the maximum gradient range where thermal stress decreases with increasing thickness is selected as the representative thickness of the rapid change zone. Experimental samples are prepared using the theoretical optimal thickness and the representative thickness of the rapid change zone. Power cycle aging experiments are conducted under different preset working conditions to obtain thermal resistance change data. Based on the thermal resistance change data, the thickness corresponding to the experimental sample with a slower actual aging rate is determined as the first optimal thickness. S3. Scan the experimental samples after the power cycle aging test to obtain the internal structure image of the chip solder layer of each experimental sample, and process the internal structure image to calculate the porosity of the chip solder layer of each experimental sample, and determine the thickness corresponding to the experimental sample with smaller porosity as the second optimal thickness. S4. Perform a joint analysis on the theoretical optimal thickness, the first optimal thickness, and the second optimal thickness. If the three are consistent, the consistent thickness is determined as the final optimal thickness; if the three are inconsistent, the first optimal thickness is determined as the final optimal thickness.

2. The power module reliability optimization design method based on solder layer thickness according to claim 1, characterized in that: The thermo-mechanical coupling simulation model includes the chip, the chip solder layer, and the DBC substrate; The chip is soldered onto the DBC substrate through the chip solder layer.

3. The power module reliability optimization design method based on solder layer thickness according to claim 2, characterized in that: During the simulation, a constant heat flux density is applied to the upper surface of the chip, a high convective heat transfer coefficient is applied to the bottom of the DBC substrate to simulate water cooling conditions, and a fixed surface is defined on one side of the heat sink in the mechanical simulation.

4. The power module reliability optimization design method based on solder layer thickness according to claim 1, characterized in that: The power cycling aging test was conducted using a power cycling test platform. The power cycling test platform adopts a parallel test topology with one arm for heating and the other for cooling.

5. The power module reliability optimization design method based on solder layer thickness according to claim 1, characterized in that: In step S2, the thermal resistance change data is obtained by a thermal resistance test method based on structure function, and the actual aging rate is evaluated by using a 20% increase in thermal resistance as a failure criterion.

6. The power module reliability optimization design method based on solder layer thickness according to claim 1, characterized in that, Step S3 involves calculating the porosity of the chip solder layer, including: The internal structure image is then converted to grayscale and denoised. Set a grayscale threshold to distinguish solder material from voids; Count the number of pixels in the gaps and the total number of pixels in the solder layer; The porosity is calculated based on the ratio of the number of void pixels to the total number of pixels in the solder layer.

7. A power module reliability optimization design system based on solder layer thickness, characterized in that, A method for implementing the power module reliability optimization design as described in any one of claims 1 to 6 includes: The simulation module is used to build a thermal-mechanical coupling simulation model of the power module, and to perform simulation with the thickness of the chip solder layer as a variable, outputting thermal stress distribution data of the chip solder layer under different thicknesses; The experimental platform is used to conduct power cycle aging experiments on power module experimental samples with at least two chip solder layers of different thicknesses, and output the thermal resistance change data of each experimental sample during the aging process. The scanning and analysis module is used to scan the chip solder layer of the power module experimental sample, obtain its internal structure image, and process the internal structure image to output the porosity of the chip solder layer. The decision module is connected to the simulation module, the experimental platform, and the scanning and analysis module, respectively, and is used to receive the thermal stress distribution data, the thermal resistance change data, and the porosity, and determine the final optimal thickness according to the preset decision logic.

8. The power module reliability optimization design system based on solder layer thickness according to claim 7, characterized in that, The preset decision logic of the decision module includes: The theoretically optimal thickness is determined based on the thermal stress distribution data. The first optimal thickness is determined based on the thermal resistance variation data; The second optimal thickness is determined based on the porosity; A collaborative analysis is performed on the theoretical optimal thickness, the first optimal thickness, and the second optimal thickness. If the three are consistent, the consistent thickness is determined as the final optimal thickness; if the three are inconsistent, the first optimal thickness is determined as the final optimal thickness.

9. A computer device, the computer device comprising a memory, a processor, and a computer program, characterized in that, When the computer program is executed by the processor, it implements the power module reliability optimization design method as described in any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the power module reliability optimization design method as described in any one of claims 1 to 6.

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