Clock constraint generation method, electronic equipment and storage medium
By establishing a relational database for clock source traversal and propagation path reconstruction, the reliability and accuracy issues of clock constraint generation in VLSI design are resolved, achieving efficient and accurate clock constraint generation and improving the reliability and efficiency of the design process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-02-04
- Publication Date
- 2026-05-15
AI Technical Summary
Existing technologies suffer from low reliability and accuracy in clock constraint generation during VLSI design, leading to incomplete clock propagation path analysis and the introduction of errors, omissions, or redundancies, which in turn affects the convergence of the design flow.
A relational database based on hierarchical design information is established. The clock source is traversed and the propagation path is reconstructed through the relational database to generate clock constraint files, thereby achieving automated and efficient clock constraint generation.
It improves the efficiency and accuracy of clock constraint generation, reduces the human error rate, ensures the integrity and consistency of clock propagation paths, and simplifies the engineer's workflow.
Smart Images
Figure CN122047124A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and in particular to a clock constraint generation method, an electronic device, and a storage medium. Background Technology
[0002] In the physical implementation stage of chips, clock network analysis and constraint generation are required for the complex hierarchical structure design of VLSI. The current mainstream implementation method relies on Static Timing Analysis (STA) tools and scripts to process each block and Top-only SDC (Synopsys Design Constraints) to generate Chip Flatten SDC.
[0003] However, in practical applications, because chip designs span multiple levels, the above implementation methods often require collaboration among multiple people or the use of complex cross-file scripts to assemble various modules and the Top-Only SDC. This process is not only cumbersome but also prone to introducing inconsistencies. Furthermore, the generation of clock constraints based on this is mostly done through manual editing or script templates, which is prone to errors, omissions, or redundancy. Summary of the Invention
[0004] This invention provides a clock constraint generation method, an electronic device, and a storage medium to address the shortcomings of low reliability and accuracy in clock constraint generation in related technologies.
[0005] This invention provides a clock constraint generation method, comprising: Based on the hierarchical design information of the chip, a relational database is established, which includes the instantiation module relationships in the chip and the port connection relationships across modules; The clock source is determined from the relational database, and the propagation path of the clock source is traversed in the relational database starting from the clock source; Based on the propagation path of the clock source, a clock constraint file for the chip is generated.
[0006] According to a clock constraint generation method provided by the present invention, determining the clock source from the relational database includes: Based on the clock position and clock type of each clock in the relational database, each potential clock source is determined from each clock. The clock source is determined from the potential clock sources based on the upstream connection relationships of each potential clock source in the relational database.
[0007] According to a clock constraint generation method provided by the present invention, the propagation path that traverses the clock source in the relational database starting from the clock source includes: For each clock source, starting from the clock source, search the relational database for the outgoing clock port connected to the clock source until the clock propagation endpoint is reached, thus obtaining the initial propagation path of the clock source; The initial propagation paths of each clock source are integrated and deduplicated by at least one of the following methods to obtain the propagation path of the clock source.
[0008] According to a clock constraint generation method provided by the present invention, the step of integrating and deduplicating the initial propagation paths of the clock sources includes at least one of the following: If there is a shared port node in the two initial propagation paths, the two initial propagation paths will be integrated into one propagation path; If two initial propagation paths are identical, delete one of the two initial propagation paths; If two initial propagation paths have an inclusion relationship, delete the initial propagation path that is included in the inclusion relationship.
[0009] According to a clock constraint generation method provided by the present invention, generating a clock constraint file for the chip based on the propagation path of the clock source includes: Identify the key clock nodes in the propagation path and find the initial clock constraints of the key clock nodes from the clock configuration file; The validity of the initial clock constraint is determined based on the identifiability of the constraint object at the top level. The initial clock constraints, which are deemed invalid, are rewritten to obtain the clock constraint file for the chip.
[0010] According to a clock constraint generation method provided by the present invention, rewriting the initial clock constraint whose validity is invalid includes: For the initial clock constraint whose validity is invalid, determine the source clock of the initial clock constraint; Based on the propagation path, the clock source of the source clock is traced back in reverse until the clock source with valid validity is obtained, which is then used as the target clock source. The source clock in the initial clock constraint is rewritten as the target clock source, and the source pin of the source clock in the initial clock constraint is rewritten in the top-level design.
[0011] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the clock constraint generation method as described above.
[0012] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the clock constraint generation method as described above.
[0013] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the clock constraint generation method as described above.
[0014] The clock constraint generation method, electronic device, and storage medium provided by this invention convert hierarchical design information into a dynamic, queryable, and depth-traversable relational database, and reconstruct the complete clock propagation path based on the relational database, thereby driving the automatic generation of clock constraint files. While retaining the complete hierarchical design information, it achieves efficient, accurate, and complete propagation path reconstruction, thereby improving the efficiency and accuracy of clock constraint generation. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is one of the flowcharts illustrating the clock constraint generation method provided by the present invention.
[0017] Figure 2 This is a flowchart illustrating the method for establishing a relational database provided by the present invention.
[0018] Figure 3 This is a flowchart illustrating the initial propagation path traversal method provided by the present invention.
[0019] Figure 4 This is the second flowchart of the clock constraint generation method provided by the present invention.
[0020] Figure 5 This is a schematic diagram of the clock constraint generation device provided by the present invention.
[0021] Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0023] In VLSI design, clock network analysis and constraint generation are particularly important given the complex hierarchical structure. Typically, this design relies heavily on Static Timing Analysis (STA) tools and scripts, requiring engineers to process each module block and top-only SDC separately to generate a Chip Flatten SDC.
[0024] SDC is a standard format file used to describe integrated circuit design constraints, and it is widely used by mainstream EDA (Electronic Design Automation) tools in the industry for synthesis, placement and routing, and static timing analysis. The integrated circuit design constraints here include clock, input / output delay, and other design constraints. Chip FlattenSDC refers to the final clock constraint file, after top-level integration and processing, which can be directly used for the entire chip flattened view.
[0025] However, this traditional approach reveals serious technical bottlenecks when faced with increasingly complex chip architectures. Because chip design spans multiple layers, the aforementioned implementation often requires collaborative intervention from multiple people or relies on extremely complex cross-file scripts to assemble various modules and the Top-Only SDC. This approach is not only cumbersome but also highly prone to introducing data inconsistencies, resulting in a weak foundation for clock propagation path analysis and consequently affecting the reliability and accuracy of clock constraint generation.
[0026] Specifically, this reliance on manual or semi-automatic script integration leads to incomplete clock propagation path analysis. In VLSI design, clock paths are complex and dispersed, and the above methods struggle to effectively handle connections within modules, between modules, and between upper and lower layers, causing clock path interruptions at design boundaries. This means designers cannot obtain complete and accurate end-to-end clock path information.
[0027] This flaw in path analysis directly impacts subsequent clock constraint generation. Because constraint generation heavily relies on the accuracy of the initial analysis, manually edited or script-template-based clock constraints are highly subjective and their quality is difficult to guarantee, especially when clock paths are prone to interruption or loss. In practical engineering, this often manifests as errors, omissions, or redundancy in constraint files. These clock constraint errors can lead to timing convergence difficulties in subsequent design processes, and may even cause the entire design to fail to converge.
[0028] To address the above problems, embodiments of the present invention provide a clock constraint generation method. Figure 1 This is one of the flowcharts illustrating the clock constraint generation method provided by the present invention, such as... Figure 1 As shown, the method includes: Step 110: Based on the hierarchical design information of the chip, establish a relational database, which includes the instantiation module relationships in the chip and the port connection relationships across modules.
[0029] Here, "chip" refers to a type of very large-scale integrated circuit design that requires the generation of clock constraint files. This could be an artificial intelligence chip, a mobile processor chip, or a baseband chip. Specifically, an artificial intelligence chip can be at least one of the following: GPU (Graphics Processing Unit), GPGPU (General-Purpose computing on Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural network Processing Unit), DPU (Deep learning Processing Unit), or APU (Accelerated Processing Unit).
[0030] For chips, hierarchical design information exists. This hierarchical design information refers to the design information applied to implement the chip's hierarchical design. For example, hierarchical design information can include hierarchy information, port connection information, and interface definition information. Hierarchical information is a complete description of the instantiation tree structure in the chip design, defining the parent-child relationship between modules and instances. Port connection information is a description of the physical connectivity and topology of all cross-module boundaries in the chip design, reflecting the connection relationships between instance pins and nets. Interface definition information is metadata that logically groups, functionally classifies, and tags protocol attributes for each port in the chip design.
[0031] After obtaining the hierarchical design information, it can be read in and used to construct a hierarchical in-memory database, namely the relational database in this embodiment of the invention. Here, the relational database is a hierarchical in-memory database that transforms static design files such as hierarchical design information into a dynamic relational architecture, supporting depth-first traversal and real-time querying. The relational database can include instantiated module relationships within the chip and port connection relationships across modules.
[0032] Among them, the instantiation module relationship refers to the relationship between modules and instances from the TOP layer to the bottom logic in chip design; the cross-module port connection relationship can be represented as the port connection matrix relationship across the design boundary in chip design, which can reflect the signal path between ports of different levels of modules.
[0033] In addition, the relational database can also include the attributes of each port, such as the type of each port, the direction of signal transmission, and key attributes, among which key attributes may include whether the current port has a specified or bound clock source, etc.
[0034] Here, the construction of a relational database can be understood as the process of obtaining information from various files containing hierarchical design information, tagging the information, and then integrating the information through the tags. For example, a Python library can be used to integrate hierarchical design information according to internal relationships, thereby obtaining a relational database.
[0035] Step 120: Determine the clock source from the relational database, and traverse the propagation path of the clock source in the relational database starting from the clock source.
[0036] Specifically, after obtaining the relational database, the clock propagation path can be traced and constructed by traversing the relational database. In this process, the relational database can provide clock information of each module in the chip, as well as the signal connection relationships between each module, for the construction of the clock propagation path.
[0037] To construct a tracking path for clock propagation, the clock source can first be determined from a relational database. Here, the clock source is the starting point where the clock signal is generated. After obtaining the clock source, the system can traverse the signal connection relationships provided by the relational database, starting from the clock source, to obtain the nodes that propagate the clock signal generated by that clock source, as well as the order in which the clock signal propagates at each node. This allows us to obtain the propagation path starting from the clock source, which is the clock propagation path.
[0038] Understandably, this allows us to identify one or more clock sources, and each clock source can have one or more propagation paths.
[0039] Step 130: Generate the clock constraint file for the chip based on the propagation path of the clock source.
[0040] Specifically, after traversing the propagation path of the clock source, a clock constraint file can be generated based on the propagation path. This clock constraint file can be a Chip Flatten SDC. For example, associated clock constraints can be processed for each propagation path obtained through traversal, and then the clock constraints of each node on the propagation path can be found from the clock configuration file of the original module, thereby generating the chip's clock constraint file. The resulting clock constraint file can contain complete, accurate, and unique clock definitions across the entire flattened chip network, and can be directly loaded and used by timing analysis tools to complete the timing analysis in the signoff stage.
[0041] Furthermore, it should be noted that the solution provided by the embodiments of the present invention can generate clock-related constraints in Chip Flatten SDC, without including Timing Exceptions, such as Multicycle, false_path, etc.
[0042] In the method provided in the embodiments of the present invention, hierarchical design information is converted into a dynamic, queryable, and depth-traversable relational database, and the complete clock propagation path is reconstructed based on the relational database, thereby driving the automatic generation of clock constraint files. While retaining the complete hierarchical design information, efficient, accurate, and complete propagation path reconstruction is achieved, thereby improving the efficiency and accuracy of clock constraint generation.
[0043] The method provided in this invention breaks away from the "flatten first, then analyze" or "layer-by-layer script splicing" patterns of related technologies. It establishes a relational database based on hierarchical design information, fundamentally structuring and relationalizing the hierarchical design information. The resulting dynamic, queryable, and deeply traversable relational database can provide the hierarchical context of the intelligent identification module and penetrate the module's internal structure without loss based on port attributes. Thus, while preserving the complete hierarchical design information, it can efficiently and accurately reconstruct all clock propagation paths.
[0044] Furthermore, the method provided in this embodiment of the invention automates the entire process from data reading to path analysis and clock constraint generation, thereby freeing engineers from tedious and error-prone manual script writing and path splicing. In a typical large-scale system-on-a-chip design containing millions of instances, the method provided in this embodiment of the invention can significantly improve the efficiency of clock path analysis and reduce the human error rate to near zero.
[0045] Based on the above embodiments, Figure 2 This is a flowchart illustrating the relational database creation method provided by the present invention, as shown below. Figure 2 As shown, hierarchical design information can include hierarchical information, port connection information, interface definition information, etc. A relational database can be established by processing this hierarchical design information. Specifically, this data processing can include parsing the hierarchical design information to extract various types of information, and constructing relationships within the hierarchical design information, integrating various types of information according to their internal relationships to obtain a relational database. This relational database can include instantiated module relationships, cross-module port connection relationships, and the attributes of each port.
[0046] Based on any of the above embodiments, step 120, determining the clock source from the relational database, includes: Based on the clock position and clock type of each clock in the relational database, each potential clock source is determined from each clock. The clock source is determined from the potential clock sources based on the upstream connection relationships of each potential clock source in the relational database.
[0047] Specifically, after obtaining the relational database, the clock position and clock type of all clocks inside the chip can be retrieved from the relational database. Here, for any clock, the clock position refers to the location where the clock is created inside the chip, such as on a pin or a port. The clock type can be CC (create_clock, master clock) or CGC (create_generated_clock, generated clock).
[0048] For any given clock, its location and type can be used to determine if it is a potential clock source. For example, a clock located on a pin and of type CC can be identified as a potential clock source; a clock located on a port and of type CC can be identified as a potential clock source; and a clock of type CGC can be identified as a potential clock source. CGC type clocks are commonly used for clocks created to meet requirements such as frequency division and multiplication, and these clocks typically have clock dependencies.
[0049] This allows us to obtain one or more potential clock sources.
[0050] After obtaining the potential clock sources, for each potential clock source, it can be determined whether the potential clock source is a real clock source based on the upstream connections of that potential clock source in the relational database. Here, the upstream connections of the potential clock source can be obtained by analyzing the connection relationships of the potential clock source in the relational database. The upstream connections are used to indicate whether the potential clock source is connected to an upstream clock.
[0051] If the upstream connection relationship indicates the existence of an upstream clock connection, it means that there are other clock sources providing clock signals to the potential clock source. The potential clock source is not an independent clock source, that is, the potential clock source is not a real clock source. If the upstream connection relationship indicates that there is no upstream clock connection, it means that there are no other clock sources that provide clock signals to the potential clock source, and the potential clock source is a real and independent clock source.
[0052] Based on any of the above embodiments, step 120, which involves traversing the propagation path of the clock source in the relational database starting from the clock source, includes: For each clock source, starting from the clock source, search the relational database for the outgoing clock port connected to the clock source until the clock propagation endpoint is reached, thus obtaining the initial propagation path of the clock source; The initial propagation paths of each clock source are integrated and deduplicated by at least one of the following methods to obtain the propagation path of the clock source.
[0053] Specifically, after identifying one or more clock sources in the chip, for each clock source, its propagation path can be traversed in the relational database, starting with that clock source. During the traversal, all outgoing clock ports of the module containing that clock source can be found in the relational database. Here, an outgoing clock port refers to a port in the module that outputs a clock signal to the outside.
[0054] If an outgoing clock port exists within the module, the system continues to search for downstream connections across modules of that outgoing clock port in the relational database. Then, it continues to traverse the nodes through which the clock signal generated by the clock source propagates within the modules connected downstream of that outgoing clock port, and searches for outgoing clock ports within those modules. This process continues until no outgoing clock port exists within the module. The node to which the clock signal finally propagates is marked as the propagation endpoint. Thus, the propagation path originating from the clock source is obtained through this traversal; this is referred to as the initial propagation path.
[0055] It is understandable that for each clock source, one or more initial propagation paths can be obtained. Based on this, at least one operation such as integration and deduplication can be performed on all initial propagation paths to optimize them. The initial propagation path obtained after integration and deduplication can be denoted as the propagation path.
[0056] In the method provided in this embodiment of the invention, the propagation path of the clock source can be quickly obtained by tracing the path in the relational database starting from the clock source. Furthermore, the end-to-end integrity of the propagation path is guaranteed through this path tracing method, thereby achieving the acquisition of a propagation path without omissions or interruptions. Based on this, a clock constraint file can be generated, ensuring accuracy and completeness from the source, thus effectively reducing the error rate of the clock constraint file and significantly improving the generation efficiency of the clock constraint file.
[0057] Based on any of the above embodiments Figure 3 This is a flowchart illustrating the initial propagation path traversal method provided by the present invention, as follows: Figure 3 As shown, the method may include the following steps: First, determine the clock source, which can be one or more.
[0058] Next, iterate through the clock sources.
[0059] For a clock source obtained through traversal, the system searches the relational database to see if an outgoing clock port exists in the module containing that clock source. If it does, it traverses the outgoing connections of that clock port based on its attributes in the relational database, thus performing cross-module tracing—that is, path tracing based on the modules downstream of the outgoing clock port. Furthermore, for each downstream connected module, the system searches the relational database to see if an outgoing clock port exists in that module. If it does, it continues to traverse the outgoing connections of that clock port based on its attributes, thus performing cross-module tracing.
[0060] If there is no outgoing clock port, then the node to which the clock source eventually propagates is marked as the propagation endpoint.
[0061] Once the propagation endpoint is obtained, the physical propagation path starting from the clock source and ending at the propagation endpoint can be used as the initial propagation path.
[0062] After obtaining the initial propagation path of a clock source, it can be determined whether there are other untraversed clock sources. If there are, the traversal of clock sources is returned; if not, it is determined that all clock sources have been traversed and the corresponding initial propagation paths have been obtained. Here, the set of initial propagation paths can be output, which includes all the initial propagation paths obtained in the above steps.
[0063] Based on any of the above embodiments, in step 120, the integration and deduplication of the initial propagation paths of each clock source includes at least one of the following: If there is a shared port node in the two initial propagation paths, the two initial propagation paths will be integrated into one propagation path; If two initial propagation paths are identical, delete one of the two initial propagation paths; If two initial propagation paths have an inclusion relationship, delete the initial propagation path that is included in the inclusion relationship.
[0064] Specifically, when there are multiple initial propagation paths, at least one of the following can be performed: integration and deduplication for each pair of initial propagation paths.
[0065] During this process, it can be determined whether any two initial propagation paths share a port node. Here, a shared port node refers to a node that is the end point of propagation in one initial propagation path and the start point of propagation in another. For two initial propagation paths with a shared port node, the shared port nodes of the two initial propagation paths can be merged, that is, the two initial propagation paths can be spliced into one propagation path through the shared port node, thereby realizing the integration of the initial propagation paths.
[0066] It can also determine whether two initial propagation paths are the same. Here, "two initial propagation paths are the same" means that the propagation start point, propagation end point, and every node along the path between the start point and the end point are exactly the same in both initial propagation paths. If two initial propagation paths are exactly the same, one initial propagation path can be kept and the other deleted, thereby achieving deduplication of initial propagation paths.
[0067] It can also determine whether there is an inclusion relationship between two initial propagation paths. Specifically, it can determine whether one initial propagation path is a subsequence of another initial propagation path, that is, whether one initial propagation path is a part of another initial propagation path. In cases where there is an inclusion relationship between two initial propagation paths, the included initial propagation path can be deleted, retaining only the initial propagation path that includes the deleted one. For example, this can be manifested as deleting the shorter initial propagation path and retaining the longer one, thereby achieving deduplication of initial propagation paths.
[0068] For example, path 1 is Subsys_A.clk_in→[Tile_X]A_in, and path 2 is Chip.clk_src→Subsys_A.clk_in→[Tile_X]A_in. There is an inclusion relationship between path 1 and path 2; specifically, path 1 is contained within path 2, and path 2 is more complete than path 1. Therefore, path 1 can be deleted, keeping only path 2.
[0069] By integrating and deduplicating at least one of the two initial propagation paths, the remaining initial propagation paths can be obtained as optimized propagation paths without redundancy or omissions. Each propagation path thus obtained represents a complete clock propagation chain from one clock source to its propagation endpoint.
[0070] Based on any of the above embodiments, step 130, generating the clock constraint file for the chip based on the propagation path of the clock source, includes: Identify the key clock nodes in the propagation path and find the initial clock constraints of the key clock nodes from the clock configuration file; The validity of the initial clock constraint is determined based on the identifiability of the constraint object at the top level. The initial clock constraints, which are deemed invalid, are rewritten to obtain the clock constraint file for the chip.
[0071] Specifically, for each propagation path, key clock nodes can be identified. These key clock nodes can include the clock ports of each module, as well as the internal pins that generate the clock. Each of these key clock nodes has corresponding clock constraints.
[0072] After identifying the critical clock nodes in the propagation path, the corresponding clock constraints can be found in the original clock configuration file. These clock constraints will be referred to as the initial clock constraints. For example, the CC or CGC clock constraints of the critical clock nodes can be found in the original clock configuration file.
[0073] After obtaining the initial clock constraints, their validity can be determined, i.e., whether they remain valid in the chip-faltten design. This can be specifically determined by assessing the identifiability of the constraint objects at the top level. Here, the identifiability of the constraint objects at the top level reflects whether they can be uniquely identified at that level.
[0074] Therefore, the validity of each initial clock constraint can be obtained. For valid initial clock constraints, they can be directly written into the chip's clock constraint file; for invalid initial clock constraints, the clock constraint needs to be rewritten and written into the chip's clock constraint file.
[0075] Furthermore, for initial clock constraints that are invalid, it can be further analyzed whether it is necessary to rewrite them.
[0076] For example, for CC clock constraints, the source object is usually a top-level port or a pin of a module instance. If the source object is a top-level port within a module, the initial clock constraint is invalid, does not need to be integrated, and therefore does not need to be rewritten; it can be deleted directly. If the source object is a pin of a module instance, it is valid and needs to be integrated; it can be directly written into the clock constraint file. This type of situation is common for output pins of PLLs (Phase-Locked Loops) or PMAs (Physical Media Attachments).
[0077] For CGC clock constraints, the source clock master_clock and source pin usually refer to ports or pins inside the module. For example, if the source clock of CGC_B is CGC_A of the current module, these objects have lost their original hierarchical context after being flattened, so they are invalid in most cases and need to be rewritten specifically.
[0078] In the method provided in this embodiment of the invention, the clock constraints that need to be rewritten are filtered out, avoiding unnecessary operations and helping to improve the efficiency of clock constraint generation.
[0079] Based on any of the above embodiments, in step 130, rewriting the initial clock constraint whose validity is invalid includes: For the initial clock constraint whose validity is invalid, determine the source clock of the initial clock constraint; Based on the propagation path, the clock source of the source clock is traced back in reverse until the clock source with valid validity is obtained, which is then used as the target clock source. The source clock in the initial clock constraint is rewritten as the target clock source, and the source pin of the source clock in the initial clock constraint is rewritten in the top-level design.
[0080] Specifically, for an initial clock constraint that is invalid and needs to be rewritten, the source clock master_clock of the initial clock constraint can be obtained first.
[0081] Based on this, the propagation path obtained in step 120 can be used to trace back to the true physical source of the master clock, that is, the clock source of the master clock, until a valid CC clock or a valid CGC clock is found. In this embodiment of the invention, the valid clock source found through reverse tracing can be denoted as the target clock source.
[0082] After obtaining the target clock source, the initial clock constraints can be rewritten, specifically including rewriting the source clock in the initial clock constraints and rewriting the source pin in the initial clock constraints.
[0083] Specifically, rewriting the source clock in the initial clock constraint means rewriting the master_clock in the initial clock constraint to the target clock source obtained by reverse tracing; rewriting the physical point in the initial clock constraint means rewriting the source pin in the initial clock constraint to the actual physical point under the top-level design, which can be obtained by querying the database.
[0084] For example, in module_A.sdc, the initial clock constraint is: <sdc> create_generated_clock -name clk_div2 –master_clock CLK_IN –source[port clk_in] -divide_by 2 [pin core_reg / CP] The initial clock constraints described above are rewritten to obtain the clock constraints in Chip_Flatten.sdc: <sdc> create_generated_clock -name clk_div2 –master_clock PLL_CLKA –source[pin top / PLL / CLKOUT] -divide_by 2 [pin top / inst_A / core_reg / CP] In the method provided in the embodiments of the present invention, by rewriting the clock constraint, the hierarchical remapping of the constraint object and the namespace is realized, thereby converting the originally ambiguous or invalid local constraints into global constraints that are physically and logically correct and conflict-free in the top-level view.
[0085] Based on any of the above embodiments, the propagation path includes multiple ports through which the clock signal propagates, as well as the hierarchical information and instance information of the multiple ports.
[0086] Specifically, the propagation path obtained in step 120 can be in the form of a structured path record. That is, when recording the propagation path, not only are the multiple ports through which the clock signal propagates recorded, but also the hierarchical information and instance information of each port are recorded. Thus, the propagation path is not a flat list of cells, but a structured information chain. The propagation path represented in the form of a structured information chain provides rich information for the subsequent automatic generation of clock constraint files.
[0087] For example, the propagation path can be represented as: Chip.clk_src → Subsys_A.clk_in → [Tile_X]A_in → [Tile_X]clk_buf_A → [Tile_X]B_out. Here, Chip, Subsys, and Tile represent hierarchical information; Chip, Subsys_A, and Tile_X represent instance information; and clk_src, clk_in, A_in, clk_buf_A, and B_out are port names.
[0088] In the method provided in this embodiment of the invention, the hierarchy is preserved during the acquisition of the propagation path, thus possessing strong traceability. The resulting structured propagation path can perfectly reconstruct the physical and logical hierarchy of the chip design, making the path analysis results clear at a glance. Engineers can quickly locate the module and instance where the problem occurs, thereby greatly reducing the difficulty and time of timing debugging.
[0089] Based on any of the above embodiments Figure 4 This is the second flowchart illustrating the clock constraint generation method provided by the present invention, as shown below. Figure 4 As shown, the method includes: S41, Build a relational database: Specifically, it can obtain the hierarchical design information of the chip and establish a relational database based on the hierarchical design information.
[0090] S42, Initiate recursive path tracing: Specifically, the clock source can be determined based on a relational database, and a hierarchical recursive path tracing can be performed in the relational database to obtain the initial propagation path of each clock source.
[0091] S43, Reconstruct the clock propagation path: After obtaining the initial propagation paths of each clock source, the propagation paths can be reconstructed based on the initial propagation paths. Specifically, optimization methods such as integration and deduplication can be applied to the initial propagation paths to obtain the propagation paths of each clock source, thus forming a propagation path set.
[0092] S44, Automated constraint generation: Specifically, based on each propagation path in the propagation path set, the corresponding clock constraints can be obtained, and invalid clock constraints can be rewritten to generate a clock constraint file.
[0093] The clock constraint generation apparatus provided by the present invention is described below. The clock constraint generation apparatus described below and the clock constraint generation method described above can be referred to in correspondence.
[0094] Figure 5 This is a schematic diagram of the clock constraint generation device provided by the present invention, as shown below. Figure 5 As shown, the device includes: The relationship establishment unit 510 is used to establish a relationship database based on the hierarchical design information of the chip. The relationship database includes the instantiation module relationship in the chip and the port connection relationship across modules. The path traversal unit 520 is used to determine the clock source from the relational database and traverse the propagation path of the clock source in the relational database starting from the clock source. The constraint generation unit 530 is used to generate a clock constraint file for the chip based on the propagation path of the clock source.
[0095] In the apparatus provided in this embodiment of the invention, hierarchical design information is converted into a dynamic, queryable, and depth-traversable relational database, and the complete clock propagation path is reconstructed based on the relational database, thereby driving the automatic generation of clock constraint files. While retaining the complete hierarchical design information, efficient, accurate, and complete propagation path reconstruction is achieved, thereby improving the efficiency and accuracy of clock constraint generation.
[0096] Based on the above embodiments, the path traversal unit is specifically used for: Based on the clock position and clock type of each clock in the relational database, each potential clock source is determined from each clock. The clock source is determined from the potential clock sources based on the upstream connection relationships of each potential clock source in the relational database.
[0097] Based on any of the above embodiments, the path traversal unit is specifically used for: For each clock source, starting from the clock source, search the relational database for the outgoing clock port connected to the clock source until the clock propagation endpoint is reached, thus obtaining the initial propagation path of the clock source; The initial propagation paths of each clock source are integrated and deduplicated by at least one of the following methods to obtain the propagation path of the clock source.
[0098] Based on any of the above embodiments, the path traversal unit is specifically used for: If there is a shared port node in the two initial propagation paths, the two initial propagation paths will be integrated into one propagation path; If two initial propagation paths are identical, delete one of the two initial propagation paths; If two initial propagation paths have an inclusion relationship, delete the initial propagation path that is included in the inclusion relationship.
[0099] Based on any of the above embodiments, the constraint generation unit is specifically used for: Identify the key clock nodes in the propagation path and find the initial clock constraints of the key clock nodes from the clock configuration file; The validity of the initial clock constraint is determined based on the identifiability of the constraint object at the top level. The initial clock constraints, which are deemed invalid, are rewritten to obtain the clock constraint file for the chip.
[0100] Based on any of the above embodiments, the constraint generation unit is specifically used for: For the initial clock constraint whose validity is invalid, determine the source clock of the initial clock constraint; Based on the propagation path, the clock source of the source clock is traced back in reverse until the clock source with valid validity is obtained, which is then used as the target clock source. The source clock in the initial clock constraint is rewritten as the target clock source, and the source pin of the source clock in the initial clock constraint is rewritten in the top-level design.
[0101] Based on any of the above embodiments, the propagation path includes multiple ports through which the clock signal propagates, as well as the hierarchical information and instance information of the multiple ports.
[0102] Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6 As shown, the electronic device may include: a processor 610, a communications interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communications interface 620, and the memory 630 communicate with each other via the communication bus 640. The processor 610 can call logical instructions in the memory 630 to execute a clock constraint generation method, which includes: Based on the hierarchical design information of the chip, a relational database is established, which includes the instantiation module relationships in the chip and the port connection relationships across modules; The clock source is determined from the relational database, and the propagation path of the clock source is traversed in the relational database starting from the clock source; Based on the propagation path of the clock source, a clock constraint file for the chip is generated.
[0103] Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0104] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program that can be stored on a non-transitory computer-readable storage medium, wherein when the computer program is executed by a processor, the computer is capable of executing the clock constraint generation method provided by the above methods, the method comprising: Based on the hierarchical design information of the chip, a relational database is established, which includes the instantiation module relationships in the chip and the port connection relationships across modules; The clock source is determined from the relational database, and the propagation path of the clock source is traversed in the relational database starting from the clock source; Based on the propagation path of the clock source, a clock constraint file for the chip is generated.
[0105] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the clock constraint generation method provided by the above methods, the method comprising: Based on the hierarchical design information of the chip, a relational database is established, which includes the instantiation module relationships in the chip and the port connection relationships across modules; The clock source is determined from the relational database, and the propagation path of the clock source is traversed in the relational database starting from the clock source; Based on the propagation path of the clock source, a clock constraint file for the chip is generated.
[0106] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0107] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.< / sdc> < / sdc>
Claims
1. A method for generating clock constraints, characterized in that, include: Based on the hierarchical design information of the chip, a relational database is established, which includes the instantiation module relationships in the chip and the port connection relationships across modules; The clock source is determined from the relational database, and the propagation path of the clock source is traversed in the relational database starting from the clock source; Based on the propagation path of the clock source, a clock constraint file for the chip is generated.
2. The clock constraint generation method according to claim 1, characterized in that, Determining the clock source from the relational database includes: Based on the clock position and clock type of each clock in the relational database, each potential clock source is determined from each clock. The clock source is determined from the potential clock sources based on the upstream connection relationships of each potential clock source in the relational database.
3. The clock constraint generation method according to claim 1, characterized in that, The propagation path that traverses the clock source in the relational database, starting from the clock source, includes: For each clock source, starting from the clock source, search the relational database for the outgoing clock port connected to the clock source until the clock propagation endpoint is reached, thus obtaining the initial propagation path of the clock source; The initial propagation paths of each clock source are integrated and deduplicated by at least one of the following methods to obtain the propagation path of the clock source.
4. The clock constraint generation method according to claim 3, characterized in that, The integration and deduplication of the initial propagation paths of the clock sources includes at least one of the following: If there is a shared port node in the two initial propagation paths, the two initial propagation paths will be integrated into one propagation path; If two initial propagation paths are identical, delete one of the two initial propagation paths; If two initial propagation paths have an inclusion relationship, delete the initial propagation path that is included in the inclusion relationship.
5. The clock constraint generation method according to claim 1, characterized in that, The generation of the clock constraint file for the chip based on the propagation path of the clock source includes: Identify the key clock nodes in the propagation path and find the initial clock constraints of the key clock nodes from the clock configuration file; The validity of the initial clock constraint is determined based on the identifiability of the constraint object at the top level. The initial clock constraints, which are deemed invalid, are rewritten to obtain the clock constraint file for the chip.
6. The clock constraint generation method according to claim 5, characterized in that, The rewriting of the invalid initial clock constraint includes: For the initial clock constraint whose validity is invalid, determine the source clock of the initial clock constraint; Based on the propagation path, the clock source of the source clock is traced back in reverse until the clock source with valid validity is obtained, which is then used as the target clock source. The source clock in the initial clock constraint is rewritten as the target clock source, and the source pin of the source clock in the initial clock constraint is rewritten in the top-level design.
7. The clock constraint generation method according to any one of claims 1 to 6, characterized in that, The propagation path includes multiple ports through which the clock signal propagates, as well as the hierarchical and instance information of these multiple ports.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the clock constraint generation method as described in any one of claims 1 to 7.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the clock constraint generation method as described in any one of claims 1 to 7.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the clock constraint generation method as described in any one of claims 1 to 7.