A layout design method and layout design system of a semiconductor chip

Abstract

The application discloses a layout design method and system of a semiconductor chip, and belongs to the technical field of semiconductors. The layout design method comprises the following steps: obtaining a layout data file of a semiconductor chip, and extracting a gate layer file containing a gate structure and a self-aligned metal silicide layer file from the layout data file; generating pseudo gate information according to the self-aligned metal silicide layer file and the gate layer file; generating a metal high-resistance layer file according to the pseudo gate information, and forming the metal high-resistance layer to cover the pseudo gate. Through the application, the position of the metal high-resistance layer in the metal high-resistance layer file and the position of the pseudo gate and the active region where the pseudo gate is located can be overlapped, the compatibility of the layout and the manufacturing process is realized, and therefore the manufacturing yield is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a semiconductor chip layout design method and layout design system. Background Technology

[0002] As semiconductor technology shrinks further to 28nm and below, the demands on devices are increasing, placing ever higher demands on layout design. However, current layout design rules rely on the automatic generation of the main pattern based on requirements, along with other auxiliary patterns. When these are combined, mismatches may occur at the process level, leading to device performance degradation. For example, introducing high-resistance resistors (HiR) at advanced technology nodes can provide voltage divider protection for MOS devices operating at different voltages. However, in current layout design rules, mismatches exist between the HiR's main pattern, the underlying gate structure, and the active area (AA), resulting in errors during electrical testing. This is because when the layout of the high-resistance resistor and the gate structure and active area layout do not perfectly correspond, some high-resistance resistors lack support from the gate structure and active area at their bottom. This causes the high-resistance resistors to bend during manufacturing, leading to electrical test distortion in wafer acceptance testing (WAT) and ultimately, manufacturing yield losses. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor chip layout design method and system. The semiconductor chip layout design method and system provided by this invention can ensure that the position of the high-resistivity layer in the high-resistivity layer file overlaps with the position of the dummy gate and the active region where the dummy gate is located. This ensures that the bottom of the high-resistivity layer has the support of the gate structure and the active region, avoids bending of the high-resistivity layer, achieves compatibility between the layout and the manufacturing process, and thus improves the manufacturing yield.

[0004] To address the aforementioned technical problems, this invention provides a semiconductor chip layout design method, comprising: acquiring a semiconductor chip layout data file, and extracting a gate layer file containing a gate structure and a self-aligned metal silicide layer file from the layout data file; generating pseudo-gate information based on the self-aligned metal silicide layer file and the gate layer file; generating a high-resistivity metal layer file based on the pseudo-gate information, wherein the formed high-resistivity metal layer covers the pseudo-gate.

[0005] In one embodiment of the present invention, the gate layer file includes at least the location information of the gate structure, the location information including the location information for forming the metal gate.

[0006] In one embodiment of the present invention, the self-aligned metal silicide layer file includes at least location information, which exposes at least the active region where the semiconductor device is located and the gate structure on the active region.

[0007] In one embodiment of the present invention, at least a portion of the gate structure outside the overlapping region of the gate layer file and the self-aligned metal silicide layer file is defined as a pseudo gate, and the pseudo gate information is obtained.

[0008] In one embodiment of the present invention, the sum of the number of gate structures and the number of dummy gates in the self-aligned metal silicide layer file is less than or equal to the number of gate structures in the gate layer file.

[0009] In one embodiment of the present invention, the high-resistivity metal layer in the high-resistivity metal layer file overlaps with the dummy gate.

[0010] In one embodiment of the present invention, the high-resistivity metal layer in the high-resistivity metal layer file overlaps with the dummy gate and the active region where the dummy gate is located.

[0011] In one embodiment of the present invention, the high-resistivity metal layer comprises a titanium nitride thin film.

[0012] The present invention also provides a layout design system, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described semiconductor chip layout design method.

[0013] In summary, this invention provides a layout design method and system for semiconductor chips. Through improvements to the layout design method, the unexpected technical effect of this application is that it ensures the position of the high-resistivity layer in the high-resistivity layer file overlaps with the position of the dummy gate and the active region where the dummy gate is located. Therefore, during the fabrication of the high-resistivity layer, it ensures that the entire formed high-resistivity layer is located on the dummy gate and the active region where the dummy gate is located, ensuring that the bottom of the high-resistivity layer has the support of the gate structure and the active region, preventing bending of the high-resistivity layer, achieving compatibility between the layout and the manufacturing process, and thus improving manufacturing yield. According to the layout design method provided by this invention, during the design process, the dummy gate information can be automatically and timely adjusted according to the layout of the semiconductor device, thereby adapting to various layout requirements of the process, and the adjustment process is compatible with the design process.

[0014] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a semiconductor chip layout design method according to an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of a gate structure formed according to a layout design method in one embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of forming a high-resistivity metallic layer according to a layout design method in one embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram illustrating the formation of pseudo-gate information based on a layout design method in one embodiment of the present invention.

[0020] Figure 5 This is a structural principle block diagram of a layout design system according to an embodiment of the present invention.

[0021] Figure 6 This is a structural principle block diagram of a computer-readable storage medium according to an embodiment of the present invention.

[0022] Figure descriptions: 100, Substrate; 101, Active region; 102, Isolation structure; 103, Gate structure; 104, Self-aligned metal silicide formation region; 105, Dummy gate; 106, High-resistivity metal layer; 200, Processor; 300, Memory; 400, Computer instructions; 401, Computer-readable storage medium. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0025] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0026] In semiconductor chips, high-resistance resistors are widely used in analog circuits due to their important role in voltage division and current limiting. In polysilicon gate structure semiconductor chips, high-resistance resistors are typically formed by ion doping a portion of the polysilicon. In metal gate structure semiconductor chips, high-resistance resistors (metal high-resistance resistors) are usually prepared using titanium nitride (TiN) thin films, and their resistance value can be controlled by adjusting the resistivity, area, and thickness of the TiN film. When designing metal high-resistance resistors, after forming the metal gate structure on the substrate, an insulating dielectric layer and a titanium nitride thin film are sequentially grown on the substrate surface. The titanium nitride thin film is then formed into the desired high-resistance resistor layer using photolithography and etching processes. This invention provides a semiconductor chip layout design method and system for forming the layout of high-resistance resistors. During chip manufacturing, when forming the metal high-resistance resistors, it ensures that the bottom of the metal high-resistance resistor is supported by the gate structure and active region, thereby preventing bending of the high-resistance resistor and improving manufacturing yield.

[0027] Please see Figure 1 As shown, the semiconductor chip layout design method includes steps S10 to S30.

[0028] Step S10: Obtain the layout data file of the semiconductor chip, and extract the gate layer file containing the gate structure and the self-aligned metal silicide layer file from the layout data file.

[0029] Step S20: Generate pseudo gate information based on the self-aligned metal silicide layer file and the gate layer file.

[0030] Step S30: Generate a high-resistivity metal layer file based on the pseudo-gate information, and the formed high-resistivity metal layer covers the pseudo-gate.

[0031] Please see Figure 1As shown, in one embodiment of the present invention, in step S10, the semiconductor chip layout data file (Graphic Data System, GDS) records every detail of the chip layout, including the geometry of chip elements, hierarchical relationships, and metal interconnection information, clearly defining the location, size, and connection method of the elements. For example, it specifically includes the graphic shapes of elements such as active regions, gate structures, source and drain electrodes, self-aligned metal silicide layers, vias, and interconnections, as well as how the circuits are connected, laying the foundation for copying the design onto the silicon wafer during the manufacturing stage. In this embodiment, after obtaining the layout data file, a gate layer file containing the gate structure can be extracted. The gate layer file includes the geometry of the gate structure, layer number and data type, location and transformation information, and associated text annotations. The location information of the gate structure, for example, is the location information for forming the metal gate.

[0032] Please see Figure 1 As shown, in one embodiment of the present invention, in step S10, after obtaining the layout data file, a self-aligned metal silicide layer file containing self-aligned metal silicides is simultaneously extracted. When the gate structure is a metal gate, self-aligned metal silicides need to be formed on the source / drain surfaces on both sides of the gate structure of the semiconductor device to reduce the contact resistance of the conductive plugs and source / drain electrodes formed later. When forming the self-aligned metal silicide, a metal layer is formed on the surface of the substrate. Through annealing, the metal layer reacts with the silicon on the source / drain surfaces to form the self-aligned metal silicide, but does not react with the metal gate. After the reaction is complete, the unreacted metal layer is removed. Therefore, the self-aligned metal silicide layer file includes at least a layer number, data type, geometry, and location. The location information precisely describes the coverage area of ​​the self-aligned metal silicide on the chip. In this embodiment, the location information at least exposes the active region where the semiconductor device is located and the gate structure on the active region to ensure that self-aligned metal silicides are formed on the source / drain surfaces.

[0033] Please see Figure 1As shown, in one embodiment of the present invention, in step S20, after obtaining the gate layer file and the self-aligned metal silicide layer file, pseudo-gate information is generated based on the self-aligned metal silicide layer file and the gate layer file. The pseudo-gate is a gate structure added to an inactive region to improve process uniformity, stress control, or electrical performance; it is not a device with actual electrical connections but participates in process steps such as photolithography and etching. In this embodiment, at least a portion of the gate structure outside the overlapping area of ​​the gate layer file and the self-aligned metal silicide layer file is defined as a pseudo-gate, and pseudo-gate information is obtained. The pseudo-gate information at least includes the location information of the pseudo-gate in the gate layer file. That is, the sum of the number of gate structures and the number of pseudo-gates in the self-aligned metal silicide layer file is less than or equal to the number of gate structures in the gate layer file. According to the layout design method provided by the present invention, during the design process, the pseudo-gate information can be automatically and timely adjusted according to the layout of the semiconductor device, thereby adapting to various layout requirements of the process, and the adjustment process is compatible with the design process.

[0034] Please see Figure 1 As shown, in one embodiment of the present invention, in step S30, after obtaining the dummy gate information in step S20, a high-resistivity metal layer file is generated based on the dummy gate information. The high-resistivity metal layer file includes at least the geometric shape and position information of the high-resistivity metal layer. In this embodiment, the high-resistivity metal layer in the high-resistivity metal layer file overlaps with, for example, the dummy gate, or the dummy gate and the active region where the dummy gate is located; that is, the shape and position of the high-resistivity metal layer in the high-resistivity metal layer file are consistent with the shape and position of the dummy gate and the active region where the dummy gate is located. In this application, the high-resistivity metal layer covers, for example, the dummy gate and the active region where the dummy gate is located on an insulating dielectric layer, wherein the insulating dielectric layer covers the surfaces of the dummy gate and the metal gate, or for example, covers the entire surface of the substrate. By selecting the dummy gate as the position difference between the gate structure in the gate layer file and the gate structure in the self-aligned metal silicide layer file, and then generating a high-resistivity metal layer file based on the dummy gate information, it is ensured that the entire high-resistivity metal layer is located on the dummy gate and the active region where the dummy gate is located. This ensures that the bottom of the high-resistivity metal layer is supported by the gate structure and the active region, preventing the high-resistivity metal layer from bending, achieving compatibility between the layout and the manufacturing process, and thus improving the manufacturing yield.

[0035] Please see Figure 1As shown, in one embodiment of the present invention, after obtaining the high-resistivity metal layer file, each layer of the semiconductor chip layout data file is processed by adding virtual structures (dummy structures) according to rules, for example, to balance local pattern density differences and reduce defects. This application does not limit the method of adding virtual structures; any existing rules for virtual structures can be followed. Then, Electronic Design Automation (EDA) software (such as Calibre, Hercules, etc.) is used to automatically check all rules and verify the layout and circuitry. Figure 1 Layout Versus Schematic (LVA) is performed to ensure correct connections. An antenna check is conducted and repairs are made. Once everything is confirmed to be correct, the wafer fabrication and mask fabrication are carried out.

[0036] Please see Figure 2 As shown, in one embodiment of the present invention, an embodiment of fabricating a high-resistivity metal layer using the above-described layout is provided. Specifically, a substrate 100 is provided. The substrate 100 can be any material suitable for forming semiconductor devices, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other III / V compound semiconductor materials, etc. It also includes a stacked structure composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, and germanium-on-insulator, etc. In this embodiment, the substrate 100 is, for example, a silicon wafer semiconductor substrate, and the substrate 100 can be an N-type substrate or a P-type substrate. Multiple active regions 101 are formed in the substrate 100 through the layout of the active regions, and adjacent active regions 101 are isolated by an isolation structure 102. The active region 101 is, for example, an N-type or P-type well region formed on the substrate 100 by ion implantation, and the isolation structure 102 is, for example, a shallow trench isolation structure formed in the substrate 100. A semiconductor device is formed on the active region. This application does not limit the type of semiconductor device; the specific type is selected based on the design of the semiconductor chip.

[0037] Please see Figure 2 As shown, in one embodiment of the present invention, a gate structure 103 is formed on the active region 101 on the substrate 100 using a gate layer file. The gate structure 103 is, for example, a metal gate, and is fabricated, for example, using a back-gate process. In this embodiment, sidewall structures (not shown) are also formed on both sides of the gate structure 103, and active / drain electrodes are formed within the substrate 100 on both sides of the gate structure 103. The fabrication processes of the metal gate, sidewall structures, and source / drain electrodes are conventional methods in the art and will not be elaborated upon here.

[0038] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after forming the gate structure 103, a self-aligned metal silicide formation region 104 is defined using self-aligned metal silicide layer file information. Figure 3 In the middle, the self-aligned metal silicide formation region 104 is Figure 3 The area enclosed by the red dashed box. In this embodiment, the self-aligned metal silicide formation region 104 exposes the active region 101 where the semiconductor device is located, the gate structure 103 on the active region 101, and the isolation structure of the region where the semiconductor device is located. A photoresist layer is formed in the area outside the self-aligned metal silicide formation region 104. A metal layer (not shown in the figure) is formed in the self-aligned metal silicide formation region 104 by means of chemical vapor deposition or physical vapor deposition. After annealing, the metal layer reacts with the silicon on the surface of the active region 101 to form a self-aligned metal silicide, but does not react with the gate structure 103. After the reaction is completed, the unreacted metal layer is removed.

[0039] Please see Figure 3 As shown, in one embodiment of the present invention, after forming a self-aligned metal silicide, based on the self-aligned metal silicide layer file and the gate layer file, the gate structure located in the gate layer file but not in the self-aligned metal silicide layer file is defined as a pseudo gate 105, and pseudo gate information is generated. In this embodiment, the sum of the pseudo gate 105 and the gate structure 103 in the semiconductor device is equal to the gate structure in the gate layer file.

[0040] Please see Figures 3 to 4As shown, in one embodiment of the present invention, after confirming the position information of the dummy gate 105, a high-resistivity metal layer file is generated based on the dummy gate information. The high-resistivity metal layer in the high-resistivity metal layer file covers the dummy gate 105 and the active region 101 where the dummy gate 105 is located; that is, the position of the high-resistivity metal layer in the high-resistivity metal layer file overlaps with the positions of the dummy gate and the active region where the dummy gate is located. When preparing the high-resistivity metal layer, an insulating dielectric layer and a titanium nitride thin film are first deposited. The insulating dielectric layer is, for example, a silicon oxide layer, and is formed, for example, by chemical vapor deposition. The titanium nitride thin film is formed, for example, by chemical vapor deposition or physical vapor deposition. Then, a photolithography and etching process is performed using a mask prepared from the high-resistivity metal layer file to etch the titanium nitride thin film, forming the high-resistivity metal layer 106. After forming the high-resistivity metal layer 106, vias, metal wiring layers, and interconnects are fabricated using the layout data file of the semiconductor chip, which will not be further elaborated here. By using the above layout design method, it can be ensured that the formed high-resistivity metal layer is located entirely on the dummy gate 105 and the active region 101 where the dummy gate 105 is located, and that the bottom of the high-resistivity metal layer 106 has the support of the gate structure and the active region, thus avoiding bending of the high-resistivity metal layer, achieving compatibility between the layout and the manufacturing process, and thereby improving the manufacturing yield.

[0041] Please see Figure 5As shown, the present invention also provides a layout design system, which includes a processor 200 and a memory 300. The memory 300 stores program instructions, and the processor 200 executes the program instructions to implement the layout design method described above. The processor 200 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The memory 300 may include random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. The memory 300 can also be an internal memory of the random access memory (RAM) type. The processor 200 and the memory 300 can be integrated into one or more independent circuits or hardware, such as application-specific integrated circuits (ASICs). It should be noted that the computer program in the aforementioned memory 300, when implemented as a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a layout design system, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention.

[0042] Please see Figure 6As shown, the present invention also proposes a computer-readable storage medium 401, which stores computer instructions 400 for causing the computer to execute the above-described layout design method. The computer-readable storage medium 401 can be an electronic medium, magnetic medium, optical medium, electromagnetic medium, infrared medium, or semiconductor system or propagation medium. The computer-readable storage medium 401 may also include semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and optical disk. Optical disks may include optical disc-read-only memory (CD-ROM), optical disc-read / write (CD-RW), and DVD.

[0043] In summary, this invention provides a layout design method and system for semiconductor chips. Through improvements to the layout design method, the unexpected technical effect of this application is that it ensures the position of the high-resistivity layer in the high-resistivity layer file overlaps with the position of the dummy gate and the active region where the dummy gate is located. Therefore, during the fabrication of the high-resistivity layer, it ensures that the entire formed high-resistivity layer is located on the dummy gate and the active region where the dummy gate is located, ensuring that the bottom of the high-resistivity layer has the support of the gate structure and the active region, preventing bending of the high-resistivity layer, achieving compatibility between the layout and the manufacturing process, and thus improving manufacturing yield. According to the layout design method provided by this invention, during the design process, the dummy gate information can be automatically and timely adjusted according to the layout of the semiconductor device, thereby adapting to various layout requirements of the process, and the adjustment process is compatible with the design process.

[0044] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A layout design method for a semiconductor chip, characterized in that, include: Obtain the layout data file of the semiconductor chip, and extract the gate layer file containing the gate structure and the self-aligned metal silicide layer file from the layout data file; The gate layer file includes the location of the gate structure; The self-aligned metal silicide layer file includes location information that describes the coverage area of ​​the self-aligned metal silicide on the chip, and the location information at least exposes the active region where the semiconductor device is located and the gate structure on the active region. At least a portion of the gate structures outside the overlapping area between the position of the gate structure in the gate layer file and the position information in the self-aligned metal silicide layer file are defined as pseudo gates, and pseudo gate information is obtained; the sum of the number of gate structures and the number of pseudo gates in the self-aligned metal silicide layer file is less than or equal to the number of gate structures in the gate layer file. A high-resistivity metal layer file is generated based on the pseudo-gate information, and the formed high-resistivity metal layer covers the pseudo-gate.

2. The semiconductor chip layout design method according to claim 1, characterized in that, The gate layer file includes at least the location information of the gate structure, including the location information for forming the metal gate.

3. The semiconductor chip layout design method according to claim 1, characterized in that, The high-resistivity metal layer in the high-resistivity metal layer file overlaps with the dummy gate and the active region where the dummy gate is located.

4. The semiconductor chip layout design method according to claim 1, characterized in that, The high-resistivity metal layer includes a titanium nitride thin film.

5. The semiconductor chip layout design method according to claim 1, characterized in that, An insulating dielectric layer is disposed between the high-resistivity metal layer and the dummy gate.

6. A layout design system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the layout design method for a semiconductor chip as described in any one of claims 1 to 5.

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