Method and apparatus for duty cycle adjustment for receive-side parallel interface

Abstract

The application relates to the technical field of digital signal processing and provides a method and device for duty cycle adjustment of a receiving-side parallel interface. The method comprises the following steps: receiving a differential read enable signal and a differential data strobe signal through a physical interface of a memory; obtaining an eye diagram data sequence associated with a T-phase data strobe signal and an eye diagram data sequence associated with a C-phase data strobe signal through a duty cycle detection module; converting the eye diagram data sequence associated with the T-phase data strobe signal to obtain a clock cycle length sequence associated with the T-phase data strobe signal, and converting the eye diagram data sequence associated with the C-phase data strobe signal to obtain a clock cycle length sequence associated with the C-phase data strobe signal; and adjusting an analog parameter for adapting the duty cycle of the differential data strobe signal by using the clock cycle length sequence associated with the T-phase data strobe signal and the clock cycle length sequence associated with the C-phase data strobe signal. In this way, the eye diagram margin and performance are improved.

Description

Technical Field

[0001] This application relates to the field of digital signal processing technology, and in particular to a method and apparatus for adjusting the duty cycle of a parallel interface on the receiving side. Background Technology

[0002] In applications such as large-scale artificial intelligence models, data centers, and high-performance servers, high-performance memory with parallel interfaces is required. Examples include fourth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR4 SDRAM), fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR5 SDRAM), and High Bandwidth Memory (HBM). These memories typically support the Double Data Rate Memory Physical Layer Interface (DFI) protocol version 5.1, also known as DFI 5.1. With the increase in data transmission rates and operating frequencies, factors such as external environmental conditions or improper adjustment of analog parameters may affect the duty cycle of the differential signal. A poor duty cycle can lead to decreased edge detection accuracy, creating a performance bottleneck. Existing duty cycle adjustment schemes only target duty cycle detection and adjustment at the physical interface, i.e., the pins, of the storage device. For example, an oscilloscope is used to measure the duty cycle of the signal at a distant point. However, even if the duty cycle is adjusted at the storage device's pins or physical interface, the differential signal may still exhibit poor duty cycle performance from the physical interface to the physical layer, influenced by factors such as operating voltage (VDD) and process voltage temperature (PVT). Because this occurs within the physical layer of the memory, it's impossible to capture and analyze the signal waveform using an oscilloscope. A poor duty cycle means lower margin, which can become a performance bottleneck in high-frequency, high-speed applications. One existing duty cycle adjustment scheme discards a segment of the signal at the initial stage of transmission, as the signal waveform at the beginning of transmission faces even more severe duty cycle issues. However, this introduces delays in signal processing and transmission, which can also create performance bottlenecks in high-frequency, high-speed applications, making it difficult to meet the demands of high-performance memories such as DDR5 and HBM3. In addition, the detection and adjustment of the signal duty cycle may need to be performed frequently, such as during the gaps in data transmission services. Then, it may be necessary to optimize the analog parameters, which requires the duty cycle adjustment scheme to be streamlined in terms of hardware resources and algorithm complexity.

[0003] To address this, this application provides a method and apparatus for adjusting the duty cycle of a parallel interface on the receiving side, which overcomes the technical difficulties in the prior art. It not only achieves efficient and accurate detection of the duty cycle of the differential signal inside the physical layer, but also simplifies the hardware implementation and algorithm details, supports higher eye diagram margin, and is conducive to improving performance. Summary of the Invention

[0004] Firstly, this application provides a method for adjusting the duty cycle of a parallel interface on the receiving side. The method includes: receiving a differential read enable signal and a differential data gating signal through a physical interface of a memory, wherein the differential read enable signal includes a T-phase read enable signal and a C-phase read enable signal, and the differential data gating signal includes a T-phase data gating signal and a C-phase data gating signal; the T-phase read enable signal is used to gate the T-phase data gating signal to obtain a gated T-phase data gating signal; the C-phase read enable signal is used to gate the C-phase data gating signal to obtain a gated C-phase data gating signal; the gated T-phase data gating signal and the gated C-phase data gating signal are used by a data sampling module inside the physical layer of the memory to sample multiple data signals received by the physical interface to obtain a data sampling result; and through a duty cycle detection module, using the zero-delay T-phase read enable signal as a sampling signal, the T-phase data gating signal is sampled according to a preset step size to obtain the T-phase data gating signal. The eye diagram data sequence associated with the phase data gating signal is obtained by sampling the C-phase data gating signal using the zero-delay C-phase read enable signal according to the preset step size. Based on the preset step size, consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the T-phase data gating signal are transformed to obtain the clock cycle length sequence associated with the T-phase data gating signal. Similarly, consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the C-phase data gating signal are transformed to obtain the clock cycle length sequence associated with the C-phase data gating signal. Using the clock cycle length sequence associated with the T-phase data gating signal and the clock cycle length sequence associated with the C-phase data gating signal, multiple analog parameters of the memory are adjusted to adapt to the duty cycle of the differential data gating signal.

[0005] Through the first aspect of this application, not only is the duty cycle of the differential signal inside the physical layer efficiently and accurately detected, but the hardware implementation and algorithm details are also simplified, supporting higher eye diagram margin, which is beneficial to improving performance.

[0006] In one possible implementation of the first aspect of this application, the preset step size is one-Nth of the unit time interval associated with the differential data gating signal, where N is a positive integer greater than or equal to 8.

[0007] In one possible implementation of the first aspect of this application, each 0 and each 1 in the eye diagram data sequence associated with the T-phase data gating signal represents a time width corresponding to the preset step size, a continuous 1 segment in the eye diagram data sequence associated with the T-phase data gating signal corresponds to the distribution of high-level regions in the T-phase data gating signal, and a continuous 0 segment in the eye diagram data sequence associated with the T-phase data gating signal corresponds to the distribution of low-level regions in the T-phase data gating signal.

[0008] In one possible implementation of the first aspect of this application, converting consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the T-phase data strobe signal to obtain a clock cycle length sequence associated with the T-phase data strobe signal includes:

[0009] Multiply the number of consecutive 0 segments in the eye diagram data sequence associated with the T-phase data strobe signal by the preset step size, and multiply the number of consecutive 1 segments in the eye diagram data sequence associated with the T-phase data strobe signal by the preset step size to obtain the clock cycle length sequence associated with the T-phase data strobe signal.

[0010] In one possible implementation of the first aspect of this application, the method further includes determining, based on the configuration of the preamble mode of the memory, whether the length of the first consecutive 0 segment in the eye diagram data sequence associated with the T-phase data strobe signal has reached a preset length; if not, determining that the preamble mode of the memory is faulty, wherein the preset length is determined based on the preamble length configured in the preamble mode and the trace length of the memory from the physical interface to the data sampling module.

[0011] In one possible implementation of the first aspect of this application, when the length of the first consecutive 0 segment in the eye diagram data sequence associated with the T-phase data strobe signal reaches the preset length, it is determined that the preamble mode of the memory is correct, and the first consecutive 1 segment after the first consecutive 0 segment in the eye diagram data sequence associated with the T-phase data strobe signal is used as the start of valid data in the eye diagram data sequence associated with the T-phase data strobe signal.

[0012] In one possible implementation of the first aspect of this application, each 0 and each 1 in the eye diagram data sequence associated with the C-phase data gating signal represents a time width corresponding to the preset step size, a continuous 1 segment in the eye diagram data sequence associated with the C-phase data gating signal corresponds to the distribution of high-level regions in the C-phase data gating signal, and a continuous 0 segment in the eye diagram data sequence associated with the C-phase data gating signal corresponds to the distribution of low-level regions in the C-phase data gating signal.

[0013] In one possible implementation of the first aspect of this application, converting consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the C-phase data strobe signal to obtain a clock cycle length sequence associated with the C-phase data strobe signal includes:

[0014] Multiply the number of consecutive 0 segments in the eye diagram data sequence associated with the C-phase data strobe signal by the preset step size, and multiply the number of consecutive 1 segments in the eye diagram data sequence associated with the C-phase data strobe signal by the preset step size to obtain the clock cycle length sequence associated with the C-phase data strobe signal.

[0015] In one possible implementation of the first aspect of this application, the method further includes determining, based on the configuration of the preamble mode of the memory, whether the length of the first consecutive 0 segment in the eye diagram data sequence associated with the C-phase data strobe signal has reached a preset length; if not, determining that the preamble mode of the memory is faulty, wherein the preset length is determined based on the preamble length configured in the preamble mode and the trace length of the memory from the physical interface to the data sampling module.

[0016] In one possible implementation of the first aspect of this application, when the length of the first consecutive 0 segment in the eye diagram data sequence associated with the C-phase data strobe signal reaches the preset length, it is determined that the preamble mode of the memory is correct, and the first consecutive 1 segment after the first consecutive 0 segment in the eye diagram data sequence associated with the C-phase data strobe signal is used as the start of valid data in the eye diagram data sequence associated with the C-phase data strobe signal.

[0017] In one possible implementation of the first aspect of this application, the multiple analog parameters of the memory include a duty cycle adjuster, automated test equipment, on-chip termination, and a forward device power supply.

[0018] In one possible implementation of the first aspect of this application, the duty cycle adjuster is used to adjust the static duty cycle of the clock tree associated with the memory, the automated test equipment is used for memory quality testing of the memory, the on-chip termination is used for characteristic impedance matching of the transmission lines associated with the memory, and the positive device power supply is used to adjust the operating voltage of the memory.

[0019] In one possible implementation of the first aspect of this application, the method further includes scanning and adjusting multiple analog parameters of the memory based on a machine learning model using at least one computer to adapt to the duty cycle of the differential data strobe signal.

[0020] In one possible implementation of the first aspect of this application, the memory is DDR4, DDR5, or HBM.

[0021] Secondly, embodiments of this application also provide a device for adjusting the duty cycle of a parallel interface on the receiving side. The device includes a duty cycle detection module and an analog parameter adjustment module. The device is communicatively connected to a memory or located within the physical layer of the memory. The physical interface of the memory is used to receive differential read enable signals and differential data gating signals. The differential read enable signals include a T-phase read enable signal and a C-phase read enable signal. The differential data gating signals include a T-phase data gating signal and a C-phase data gating signal. The T-phase read enable signal is used to gate the T-phase data gating signal to obtain a gated T-phase data gating signal. The C-phase read enable signal is used to gate the C-phase data gating signal to obtain a gated C-phase data gating signal. The gated T-phase data gating signal and the gated C-phase data gating signal are used by a data sampling module within the physical layer of the memory to sample multiple data signals received by the physical interface to obtain a data sampling result. The duty cycle detection module is configured to: use the zero-delay T-phase read enable signal as a sampling signal, sample the T-phase data gating signal according to a preset step size, to obtain an eye diagram data sequence associated with the T-phase data gating signal; and use the zero-delay C-phase read enable signal as a sampling signal, sample the C-phase data gating signal according to the preset step size, to obtain an eye diagram data sequence associated with the C-phase data gating signal. The duty cycle detection module is further configured to: based on the preset step size, convert consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the T-phase data gating signal to obtain a clock cycle length sequence associated with the T-phase data gating signal; and convert consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the C-phase data gating signal to obtain a clock cycle length sequence associated with the C-phase data gating signal. The analog parameter adjustment module is used to adjust multiple analog parameters of the memory to adapt to the duty cycle of the differential data gating signal by using the clock cycle length sequence associated with the T-phase data gating signal and the clock cycle length sequence associated with the C-phase data gating signal.

[0022] The second aspect of this application not only enables efficient and accurate detection of the duty cycle of differential signals within the physical layer, but also simplifies the hardware implementation and algorithm details, supports higher eye diagram margin, and is beneficial to improving performance. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart illustrating a method for adjusting the duty cycle of a parallel interface on the receiving side, provided in an embodiment of this application;

[0025] Figure 2 A schematic diagram of the duty cycle of the differential data strobe signal at the data sampling module inside the physical layer of the memory before duty cycle adjustment, provided for an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of an apparatus provided in an embodiment of this application, used for adjusting the duty cycle of a parallel interface on the receiving side. Detailed Implementation

[0027] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0028] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0029] Figure 1 This is a flowchart illustrating a method for adjusting the duty cycle of a parallel interface on the receiving side, provided as an embodiment of this application. Figure 1 As shown, the method for adjusting the duty cycle of the parallel interface on the receiving side includes the following steps.

[0030] Step S101: Receive differential read enable signal and differential data gating signal through the physical interface of the memory. The differential read enable signal includes a T-phase read enable signal and a C-phase read enable signal. The differential data gating signal includes a T-phase data gating signal and a C-phase data gating signal. The T-phase read enable signal is used to gate the T-phase data gating signal to obtain a gated T-phase data gating signal. The C-phase read enable signal is used to gate the C-phase data gating signal to obtain a gated C-phase data gating signal. The gated T-phase data gating signal and the gated C-phase data gating signal are used by the data sampling module inside the physical layer of the memory to sample multiple data signals received by the physical interface to obtain data sampling results.

[0031] Step S103: Using the duty cycle detection module, the zero-delay T-phase read enable signal is used as the sampling signal, and the T-phase data gating signal is sampled according to a preset step size to obtain the eye diagram data sequence associated with the T-phase data gating signal. Also, the zero-delay C-phase read enable signal is used as the sampling signal, and the C-phase data gating signal is sampled according to the preset step size to obtain the eye diagram data sequence associated with the C-phase data gating signal.

[0032] Step S105: Based on the preset step size, convert the continuous 0 segments and continuous 1 segments in the eye diagram data sequence associated with the T-phase data strobe signal to obtain the clock cycle length sequence associated with the T-phase data strobe signal; and convert the continuous 0 segments and continuous 1 segments in the eye diagram data sequence associated with the C-phase data strobe signal to obtain the clock cycle length sequence associated with the C-phase data strobe signal.

[0033] Step S107: Using the clock cycle length sequence associated with the T-phase data gating signal and the clock cycle length sequence associated with the C-phase data gating signal, adjust multiple analog parameters of the memory to adapt to the duty cycle of the differential data gating signal.

[0034] Figure 1 The method shown for adjusting the duty cycle of the parallel interface on the receiving side is applicable to fields such as large-scale artificial intelligence models, data centers, and high-performance servers. It supports high-performance memories with parallel interfaces, such as fourth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR4 SDRAM), fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR5 SDRAM), and High Bandwidth Memory (HBM). These memories generally support the Double Data Rate Memory Physical Layer Interface (DFI) protocol version 5.1, also known as DFI5.1. With the increase in data transmission rate and operating frequency, factors such as external environment or improper adjustment of analog parameters may affect the duty cycle of the differential signal. A poor duty cycle may lead to a decrease in the accuracy of edge detection, causing a performance bottleneck. Figure 1 The method shown for duty cycle adjustment of the receiver-side parallel interface takes into account that even if the duty cycle adjustment is completed at the pins of the storage device or the physical interface, the differential signal may still have a poor duty cycle from the physical interface to the physical layer, for example, due to factors such as operating voltage (VDD) and process voltage temperature (PVT) variations. Furthermore, to minimize latency, Figure 1The method shown for adjusting the duty cycle of the parallel interface on the receiving side does not directly discard a segment of the signal at the beginning of the transmission. Instead, it efficiently and accurately detects the length of each clock cycle of the differential signal, thereby detecting the duty cycle of the differential signal in real time, providing a reliable basis for subsequent adjustment of analog parameters.

[0035] In step S101, a differential read enable signal and a differential data gating signal are received through the physical interface of the memory. The differential read enable signal includes a T-phase read enable signal and a C-phase read enable signal. The differential data gating signal includes a T-phase data gating signal and a C-phase data gating signal. The T-phase read enable signal is used to gate the T-phase data gating signal to obtain a gated T-phase data gating signal. The C-phase read enable signal is used to gate the C-phase data gating signal to obtain a gated C-phase data gating signal. The gated T-phase data gating signal and the gated C-phase data gating signal are used by the data sampling module inside the physical layer of the memory to sample multiple data signals received by the physical interface to obtain a data sampling result. Here, the physical interface of the memory refers to the external pins of the memory. From the physical interface of the memory to the data sampling module inside the physical layer of the memory, the duty cycle of the differential data gating signal may be affected by factors such as operating voltage, process corner voltage, and temperature variations. By providing a differential read enable signal, subsequent sampling and duty cycle detection are achieved separately and independently for the T-phase data gating signal and the C-phase data gating signal.

[0036] In step S103, the duty cycle detection module uses the zero-delay T-phase read enable signal as a sampling signal and samples the T-phase data gating signal according to a preset step size to obtain the eye diagram data sequence associated with the T-phase data gating signal. Similarly, the zero-delay C-phase read enable signal is used as a sampling signal, and the C-phase data gating signal is sampled according to the preset step size to obtain the eye diagram data sequence associated with the C-phase data gating signal. Here, the duty cycle detection module is communicatively connected to the memory or located inside the physical layer of the memory. It should be noted that the memory typically uses preamble and postamble modes to adjust the phase of the differential read enable signal and the differential data gating signal at the physical interface of the memory. Therefore, at the data sampling module inside the physical layer of the memory, the T-phase data gating signal and the C-phase data gating signal may each have a certain degree of delay adjustment. Here, to achieve duty cycle detection at the data sampling module within the physical layer of the memory, zero-latency T-phase read enable signals and zero-latency C-phase read enable signals are required. As mentioned above, the T-phase read enable signal is used to gate the T-phase data gating signal to obtain a gated T-phase data gating signal, and the C-phase read enable signal is used to gate the C-phase data gating signal to obtain a gated C-phase data gating signal. Therefore, using the zero-latency T-phase read enable signal as the sampling signal, the T-phase data gating signal is sampled according to a preset step size to obtain the eye diagram data sequence associated with the T-phase data gating signal. Similarly, using the zero-latency C-phase read enable signal as the sampling signal, the C-phase data gating signal is sampled according to the preset step size to obtain the eye diagram data sequence associated with the C-phase data gating signal. The preset step size is pre-set and has a small time length, for example, 1 / 64th of a unit time interval. By introducing a preset step size and using the corresponding read enable signal as the sampling signal to sample the corresponding data strobe signal (the corresponding read enable signal is used to gate the corresponding data strobe signal for data signal sampling), the eye diagram data sequence associated with the corresponding data strobe signal can be obtained without using waveform capture on an oscilloscope. An example of eye diagram data is: "000000000000000000000000111111000001111111111110000000001 ...

[0037] In this way, the data strobe signal can be sampled by adjusting the read enable signal. The low level is latched into the register as 0 for software to read, and the high level is latched into the register as 1 for software to read. Thus, the sampling result presented in the form of 0 and 1 is obtained, which serves as the eye diagram data sequence of the data strobe signal.

[0038] In step S105, based on the preset step size, consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the T-phase data strobe signal are converted to obtain the clock cycle length sequence associated with the T-phase data strobe signal. Similarly, consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the C-phase data strobe signal are converted to obtain the clock cycle length sequence associated with the C-phase data strobe signal. Thus, by parsing the eye diagram data sequence and converting consecutive 0 segments and consecutive 1 segments into corresponding clock cycle lengths according to the preset step size, the clock cycle length sequence associated with the data strobe signal is obtained. Here, each 0 and each 1 in the eye diagram data sequence is a sampling result based on the preset step size; therefore, each 0 and each 1 corresponds to a preset step size of time. For example, assuming the preset step size is 8 basic units, where the basic unit can be set to 5% or 10% of the unit time interval, then 5 consecutive 0 segments correspond to 5 multiplied by 8, which equals 40 basic units. Therefore, based on consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the data gating signal, by analyzing the number of 0s in the consecutive 0 segments and the number of 1s in the consecutive 1 segments, combined with a preset step size, the variation pattern of the clock cycle length can be conveniently determined. For example, the above eye diagram data example can be converted into:

[0039] “30 40 64 64 64 64 64 64 64 64 64 64 64 64 64 64”.

[0040] In step S107, multiple analog parameters of the memory are adjusted to adapt to the duty cycle of the differential data strobe signal using the clock cycle length sequences associated with the T-phase data strobe signal and the C-phase data strobe signal. Thus, the clock cycle length sequences associated with the data strobe signal represent the duty cycle result, which can be determined by a corresponding signal scan, providing a basis for analog parameter adjustment. In some embodiments, the multiple analog parameters of the memory include a duty cycle adjuster (DCA), automatic testing equipment (ATE), on-die termination (ODT), and forward device power (VDD). It can be seen that a clock cycle length of 64 represents a better duty cycle, while clock cycle lengths of 30 and 40 represent poorer duty cycles. By analyzing the clock cycle length sequences associated with the data strobe signal, the overall duty cycle situation can be quickly determined, and the location of poor duty cycle can be quickly identified. The duty cycle can be affected by adjusting simulation parameters such as DCA, ATE, ODT, and VDD. Therefore, the simulation parameters can be scanned and combined with the duty cycle results to determine which parameter configurations are suitable for the duty cycle results.

[0041] See Figure 2 , Figure 2 This is a schematic diagram illustrating the duty cycle of the differential data strobe signal at the data sampling module inside the physical layer of the memory before duty cycle adjustment, as provided in an embodiment of this application. Figure 2As shown, the differential read enable signal includes a T-phase read enable signal and a C-phase read enable signal, and the differential data gating signal includes a T-phase data gating signal and a C-phase data gating signal. The T-phase read enable signal is used to gate the T-phase data gating signal to obtain a gated T-phase data gating signal, and the C-phase read enable signal is used to gate the C-phase data gating signal to obtain a gated C-phase data gating signal. The gated T-phase data gating signal and the gated C-phase data gating signal are used by the data sampling module inside the physical layer of the memory to sample multiple data signals received by the physical interface to obtain data sampling results. It can be seen that even if the duty cycle is adjusted at the pins of the storage device or the physical interface, the differential signal may still have a poor duty cycle from the physical interface to the physical layer. By comparing the waveforms of the T-phase read enable signal and the T-phase data gating signal, it can be seen that regions 3 to 16 of the T-phase data gating signal have a better duty cycle. However, regions 1 and 2 of the T-phase data gating signal have a poorer duty cycle, which will seriously affect the eye diagram margin and lead to a performance bottleneck in high-frequency applications. Furthermore, by comparing the waveforms of the C-phase read enable signal and the C-phase data gating signal, it can be seen that the first two regions of the C-phase data gating signal also have a poor duty cycle. Generally, at the beginning of each transmission cycle, the electrical characteristics of the circuit components and the influence of resistors, capacitors, and other components may lead to a poor initial duty cycle. Therefore, directly discarding regions 1 and 2 of the T-phase data gating signal can ensure a more stable duty cycle result, but this inevitably increases the overall delay and is not conducive to further performance improvement.

[0042] in this way, Figure 1 The method for duty cycle adjustment of the parallel interface on the receiving side, as shown, does not directly discard a segment of the signal established at the beginning of transmission. Through simplified design in hardware implementation and algorithm details, it first uses the corresponding read enable signal with zero delay as the sampling signal to sample the corresponding data strobe signal (this corresponding read enable signal is used to gate the corresponding data strobe signal for data signal sampling). This eliminates the need for waveform capture using an oscilloscope to obtain the eye diagram data sequence associated with the corresponding data strobe signal. Then, by analyzing the number of 0s in consecutive 0 segments and the number of 1s in consecutive 1 segments in the eye diagram data sequence associated with the corresponding data strobe signal, combined with a preset step size, the variation pattern of the clock cycle length can be conveniently determined. Furthermore, based on achieving efficient and accurate detection of the duty cycle of the differential signal within the physical layer, combined with analog parameter scanning and optimization, a good duty cycle can be achieved at the beginning of transmission. For example, through duty cycle detection and analog parameter optimization, the... Figure 2The duty cycles of region 1 and region 2 of the T-phase data gating signal are determined. This not only enables efficient and accurate detection of the duty cycle of the differential signal within the physical layer, but also simplifies the hardware implementation and algorithm details, supports higher eye diagram margins, and improves performance.

[0043] See Figure 1 In some embodiments, the preset step size is one-Nth of the unit time interval associated with the differential data gating signal, where N is a positive integer greater than or equal to 8.

[0044] In this way, a smaller preset step size can be set, allowing for more refined scanning. In addition, considering the overall computing power burden, a basic unit can be set first, such as 5% of the unit time interval, and then the preset step size can be flexibly controlled to be a certain multiple of the basic unit, such as 8 basic units. This allows the duty cycle detection and the computing power burden to be adjusted according to actual needs, achieving a balance between computing power burden and duty cycle detection effect.

[0045] See Figure 1 In some embodiments, each 0 and each 1 in the eye diagram data sequence associated with the T-phase data gating signal represents a time width corresponding to the preset step size, a consecutive 1 segment in the eye diagram data sequence associated with the T-phase data gating signal corresponds to the distribution of high-level regions in the T-phase data gating signal, and a consecutive 0 segment in the eye diagram data sequence associated with the T-phase data gating signal corresponds to the distribution of low-level regions in the T-phase data gating signal.

[0046] Thus, through the adjustment mechanism of the read enable signal, the data strobe signal is sampled using the read enable signal. Low-level signals are latched into a register as 0s for software reading, and high-level signals are latched into a register as 1s for software reading, resulting in a sampling result presented as 0s and 1s, which serves as the eye diagram data sequence for the data strobe signal. It should be noted that the memory typically uses preamble and postamble modes to adjust the phase of the differential read enable signal and differential data strobe signal at the physical interface of the memory. Therefore, at the data sampling module inside the physical layer of the memory, the T-phase data strobe signal and the C-phase data strobe signal may each have a certain degree of delay adjustment. Here, to achieve duty cycle detection at the data sampling module inside the physical layer of the memory, zero-delay T-phase read enable signal and zero-delay C-phase read enable signal are required.

[0047] See Figure 1In some embodiments, converting consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the T-phase data strobe signal to obtain the clock cycle length sequence associated with the T-phase data strobe signal includes:

[0048] Multiply the number of consecutive 0 segments in the eye diagram data sequence associated with the T-phase data strobe signal by the preset step size, and multiply the number of consecutive 1 segments in the eye diagram data sequence associated with the T-phase data strobe signal by the preset step size to obtain the clock cycle length sequence associated with the T-phase data strobe signal.

[0049] Thus, by analyzing the eye diagram data sequence, consecutive 0 segments and consecutive 1 segments are converted into corresponding clock cycle lengths according to a preset step size, resulting in a clock cycle length sequence associated with the data strobe signal. Here, each 0 and each 1 in the eye diagram data sequence is a sampling result based on a preset step size; therefore, each 0 and each 1 corresponds to a preset step size of time. For example, assuming the preset step size is 8 basic units, where the basic unit can be set to 5% or 10% of the unit time interval, then 5 0 segments correspond to 5 multiplied by 8, which equals 40 basic units. Therefore, based on the consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the data strobe signal, by analyzing the number of 0s in the consecutive 0 segments and the number of 1s in the consecutive 1 segments, combined with the preset step size, the variation pattern of the clock cycle length can be easily determined.

[0050] See Figure 1 In some embodiments, the method further includes determining, based on the configuration of the preamble mode of the memory, whether the length of the first consecutive 0 segment in the eye diagram data sequence associated with the T-phase data strobe signal has reached a preset length; if not, determining that the preamble mode of the memory is faulty, wherein the preset length is determined based on the preamble length configured in the preamble mode and the trace length of the memory from the physical interface to the data sampling module.

[0051] Therefore, the configuration of the memory's preamble can be referenced. For example, the memory might use a two-clock-cycle preamble plus a half-clock-cycle postamble. Upon entering the physical layer, because the zero-delay T-phase read enable signal and the zero-delay C-phase read enable signal are used, the first consecutive 0 segment in the eye diagram data sequence will have a certain length. Only the first consecutive 1 segment following the first consecutive 0 segment is valid sampled data. Therefore, by detecting whether the length of the first consecutive 0 segment in the eye diagram data sequence reaches a preset length, it can be determined whether a memory preamble mode error has occurred. Possible causes of this error include incorrect preamble configuration or inadequate delay adjustment of the read enable signal. When a memory preamble mode error is detected, it can be fed back to the delay adjustment mechanism at the physical interface, thus improving the system's error correction capability and performance. The preset length takes into account the configuration of the memory's preamble and the routing delay from the physical interface to the data sampling module inside the physical layer. Therefore, the preset length is determined based on the preamble length configured in the preamble mode and the routing length of the memory from the physical interface to the data sampling module. For example, assuming the calculated preset length is 128 preset steps, if the length of the first consecutive 0 segment is not 128 preset steps, it can be determined that the memory's preamble mode is faulty.

[0052] See Figure 1 In some embodiments, when the length of the first consecutive 0 segment in the eye diagram data sequence associated with the T-phase data strobe signal reaches the preset length, it is determined that the preamble mode of the memory is correct, and the first consecutive 1 segment after the first consecutive 0 segment in the eye diagram data sequence associated with the T-phase data strobe signal is used as the start of valid data in the eye diagram data sequence associated with the T-phase data strobe signal.

[0053] Thus, the configuration of the memory preamble provides additional system error detection and correction functions, and improves the efficiency of duty cycle detection and adjustment by using effective sampling data.

[0054] See Figure 1 In some embodiments, each 0 and each 1 in the eye diagram data sequence associated with the C-phase data gating signal represents a time width corresponding to the preset step size, a continuous 1 segment in the eye diagram data sequence associated with the C-phase data gating signal corresponds to the distribution of high-level regions in the C-phase data gating signal, and a continuous 0 segment in the eye diagram data sequence associated with the C-phase data gating signal corresponds to the distribution of low-level regions in the C-phase data gating signal.

[0055] Thus, through the adjustment mechanism of the read enable signal, the data strobe signal is sampled using the read enable signal. Low-level signals are latched into a register as 0s for software reading, and high-level signals are latched into a register as 1s for software reading, resulting in a sampling result presented as 0s and 1s, which serves as the eye diagram data sequence for the data strobe signal. It should be noted that the memory typically uses preamble and postamble modes to adjust the phase of the differential read enable signal and differential data strobe signal at the physical interface of the memory. Therefore, at the data sampling module inside the physical layer of the memory, the T-phase data strobe signal and the C-phase data strobe signal may each have a certain degree of delay adjustment. Here, to achieve duty cycle detection at the data sampling module inside the physical layer of the memory, zero-delay T-phase read enable signal and zero-delay C-phase read enable signal are required.

[0056] See Figure 1 In some embodiments, converting consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the C-phase data strobe signal to obtain a clock cycle length sequence associated with the C-phase data strobe signal includes:

[0057] Multiply the number of consecutive 0 segments in the eye diagram data sequence associated with the C-phase data strobe signal by the preset step size, and multiply the number of consecutive 1 segments in the eye diagram data sequence associated with the C-phase data strobe signal by the preset step size to obtain the clock cycle length sequence associated with the C-phase data strobe signal.

[0058] Thus, by analyzing the eye diagram data sequence, consecutive 0 segments and consecutive 1 segments are converted into corresponding clock cycle lengths according to a preset step size, resulting in a clock cycle length sequence associated with the data strobe signal. Here, each 0 and each 1 in the eye diagram data sequence is a sampling result based on a preset step size; therefore, each 0 and each 1 corresponds to a preset step size of time. For example, assuming the preset step size is 8 basic units, where the basic unit can be set to 5% or 10% of the unit time interval, then 5 0 segments correspond to 5 multiplied by 8, which equals 40 basic units. Therefore, based on the consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the data strobe signal, by analyzing the number of 0s in the consecutive 0 segments and the number of 1s in the consecutive 1 segments, combined with the preset step size, the variation pattern of the clock cycle length can be easily determined.

[0059] See Figure 1In some embodiments, the method further includes determining, based on the configuration of the preamble mode of the memory, whether the length of the first consecutive 0 segment in the eye diagram data sequence associated with the C-phase data strobe signal has reached a preset length; if not, determining that the preamble mode of the memory is faulty, wherein the preset length is determined based on the preamble length configured in the preamble mode and the trace length of the memory from the physical interface to the data sampling module.

[0060] Therefore, the configuration of the memory's preamble can be referenced. For example, the memory might use a two-clock-cycle preamble plus a half-clock-cycle postamble. Upon entering the physical layer, because the zero-delay T-phase read enable signal and the zero-delay C-phase read enable signal are used, the first consecutive 0 segment in the eye diagram data sequence will have a certain length. Only the first consecutive 1 segment following the first consecutive 0 segment is valid sampled data. Therefore, by detecting whether the length of the first consecutive 0 segment in the eye diagram data sequence reaches a preset length, it can be determined whether a memory preamble mode error has occurred. Possible causes of this error include incorrect preamble configuration or inadequate delay adjustment of the read enable signal. When a memory preamble mode error is detected, it can be fed back to the delay adjustment mechanism at the physical interface, thus improving the system's error correction capability and performance. The preset length takes into account the configuration of the memory's preamble and the routing delay from the physical interface to the data sampling module inside the physical layer. Therefore, the preset length is determined based on the preamble length configured in the preamble mode and the routing length of the memory from the physical interface to the data sampling module. For example, assuming the calculated preset length is 128 preset steps, if the length of the first consecutive 0 segment is not 128 preset steps, it can be determined that the memory's preamble mode is faulty.

[0061] It can be seen that by providing a differential read enable signal, subsequent sampling and duty cycle detection are performed separately and independently for the T-phase data gating signal and the C-phase data gating signal, and error detection and correction functions based on the preamble configuration of the T-phase data gating signal and the C-phase data gating signal are provided.

[0062] See Figure 1 In some embodiments, when the length of the first consecutive 0 segment in the eye diagram data sequence associated with the C-phase data strobe signal reaches the preset length, it is determined that the preamble mode of the memory is correct, and the first consecutive 1 segment after the first consecutive 0 segment in the eye diagram data sequence associated with the C-phase data strobe signal is used as the start of valid data in the eye diagram data sequence associated with the C-phase data strobe signal.

[0063] Thus, the configuration of the memory preamble provides additional system error detection and correction functions, and improves the efficiency of duty cycle detection and adjustment by using effective sampling data.

[0064] See Figure 1 In some embodiments, the multiple analog parameters of the memory include a duty cycle adjuster, automated test equipment, on-chip termination, and a forward device power supply.

[0065] Thus, multiple analog parameters are involved, including the duty cycle adjuster (DCA), automatic testing equipment (ATE), on-die termination (ODT), and the forward device power supply (VDD). By analyzing the clock cycle length sequence associated with the data strobe signal, the overall duty cycle can be quickly determined, and the location of poor duty cycle can be quickly pinpointed. Adjusting analog parameters such as DCA, ATE, ODT, and VDD can affect the duty cycle; therefore, the analog parameters can be scanned, and combined with the duty cycle results, it can be determined which parameter configurations are suitable for the desired duty cycle.

[0066] See Figure 1 In some embodiments, the duty cycle adjuster is used to adjust the static duty cycle of the clock tree associated with the memory, the automated test equipment is used for memory quality testing of the memory, the on-chip termination is used for characteristic impedance matching of the transmission lines associated with the memory, and the positive device power supply is used to adjust the operating voltage of the memory.

[0067] Thus, by analyzing the number of 0s in consecutive 0 segments and the number of 1s in consecutive 1 segments of the eye diagram data sequence associated with the corresponding data strobe signal, and combining this with a preset step size, the variation pattern of the clock cycle length can be easily determined. Furthermore, based on achieving efficient and accurate detection of the duty cycle of the differential signal within the physical layer, and by combining analog parameter scanning and optimization, a better duty cycle can be achieved in the early stages of transmission. For example, through duty cycle detection and analog parameter optimization, the... Figure 2 The duty cycles of region 1 and region 2 of the T-phase data gating signal are determined. This not only enables efficient and accurate detection of the duty cycle of the differential signal within the physical layer, but also simplifies the hardware implementation and algorithm details, supports higher eye diagram margins, and improves performance.

[0068] See Figure 1In some embodiments, the method further includes scanning and adjusting multiple analog parameters of the memory based on a machine learning model using at least one computer to adapt to the duty cycle of the differential data strobe signal.

[0069] In this way, by using machine learning models, such as deep learning algorithms or reinforcement learning algorithms, duty cycle detection and simulation parameter scanning and optimization are achieved.

[0070] See Figure 1 In some embodiments, the memory is DDR4, DDR5, or HBM.

[0071] In this way, high-performance memory with parallel interface is supported, duty cycle detection can be performed during the gaps in data transmission, and then the simulation parameters can be optimized. Furthermore, the duty cycle adjustment scheme has been simplified in terms of hardware resources and algorithm complexity.

[0072] Figure 3 This is a schematic diagram of a device for adjusting the duty cycle of a parallel interface on the receiving side, provided as an embodiment of this application. Figure 3 As shown, the device 310 includes a duty cycle detection module 312 and an analog parameter adjustment module 314. The device 310 is communicatively connected to the memory or located within the physical layer of the memory. The physical interface of the memory is used to receive differential read enable signals and differential data gating signals. Specifically, the differential read enable signals include a T-phase read enable signal and a C-phase read enable signal; the differential data gating signals include a T-phase data gating signal and a C-phase data gating signal. The T-phase read enable signal is used to gate the T-phase data gating signal to obtain a gated T-phase data gating signal; the C-phase read enable signal is used to gate the C-phase data gating signal to obtain a gated C-phase data gating signal; the gated T-phase data gating signal and the gated C-phase data gating signal are used by the data sampling module within the physical layer of the memory to sample multiple data signals received by the physical interface to obtain a data sampling result.

[0073] The duty cycle detection module 312 is used to: use the zero-delay T-phase read enable signal as a sampling signal, sample the T-phase data gating signal according to a preset step size, and obtain an eye diagram data sequence associated with the T-phase data gating signal; and use the zero-delay C-phase read enable signal as a sampling signal, sample the C-phase data gating signal according to the preset step size, and obtain an eye diagram data sequence associated with the C-phase data gating signal.

[0074] The duty cycle detection module 312 is further configured to: based on the preset step size, convert consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the T-phase data gating signal to obtain the clock cycle length sequence associated with the T-phase data gating signal; and convert consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the C-phase data gating signal to obtain the clock cycle length sequence associated with the C-phase data gating signal.

[0075] The analog parameter adjustment module 314 is used to: adjust multiple analog parameters of the memory to adapt to the duty cycle of the differential data gating signal by using the clock cycle length sequence associated with the T-phase data gating signal and the clock cycle length sequence associated with the C-phase data gating signal.

[0076] in this way, Figure 3 The device shown for adjusting the duty cycle of the parallel interface on the receiving side does not directly discard a segment of the signal established at the beginning of transmission. Through simplified design in hardware implementation and algorithm details, it first uses the corresponding read enable signal with zero delay as the sampling signal to sample the corresponding data strobe signal (this corresponding read enable signal is used to gate the corresponding data strobe signal for data signal sampling). This eliminates the need for waveform capture using an oscilloscope to obtain the eye diagram data sequence associated with the corresponding data strobe signal. Then, by analyzing the number of 0s in consecutive 0 segments and the number of 1s in consecutive 1 segments in the eye diagram data sequence associated with the corresponding data strobe signal, combined with a preset step size, the variation pattern of the clock cycle length can be conveniently determined. Furthermore, based on achieving efficient and accurate detection of the duty cycle of the differential signal within the physical layer, combined with analog parameter scanning and optimization, a good duty cycle can be achieved at the beginning of transmission. For example, through duty cycle detection and analog parameter optimization, the clock cycle length can be improved. Figure 2 The duty cycles of region 1 and region 2 of the T-phase data gating signal are determined. This not only enables efficient and accurate detection of the duty cycle of the differential signal within the physical layer, but also simplifies the hardware implementation and algorithm details, supports higher eye diagram margins, and improves performance.

[0077] The methods and devices provided in this application are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, the embodiments, implementation methods, examples, or methods of implementation of the methods and devices can be referred to each other, and repeated details will not be repeated. This application also provides a system comprising multiple computer devices, the structure of each computer device of which can refer to the structure of the computer devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0078] This application also provides a computer-readable storage medium storing computer instructions. When these computer instructions are executed on a computer device (such as one or more processors), they can implement the method steps described in the above method embodiments. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0079] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this application can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical, digital subscriber line) or wireless (e.g., infrared, wireless network communication, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0080] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0081] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A method for adjusting the duty cycle of a parallel interface on the receiving side, characterized in that, The method includes: Through the physical interface of the memory, differential read enable signals and differential data gating signals are received. The differential read enable signals include T-phase read enable signals and C-phase read enable signals, and the differential data gating signals include T-phase data gating signals and C-phase data gating signals. The T-phase read enable signals are used to gate the T-phase data gating signals to obtain gated T-phase data gating signals, and the C-phase read enable signals are used to gate the C-phase data gating signals to obtain gated C-phase data gating signals. The gated T-phase data gating signals and the gated C-phase data gating signals are used by the data sampling module inside the physical layer of the memory to sample multiple data signals received by the physical interface to obtain data sampling results. Using the duty cycle detection module, the zero-delay T-phase read enable signal is used as the sampling signal, and the T-phase data gating signal is sampled according to a preset step size to obtain the eye diagram data sequence associated with the T-phase data gating signal. Also, the zero-delay C-phase read enable signal is used as the sampling signal, and the C-phase data gating signal is sampled according to the preset step size to obtain the eye diagram data sequence associated with the C-phase data gating signal. Based on the preset step size, the continuous 0 segments and continuous 1 segments in the eye diagram data sequence associated with the T-phase data gating signal are converted to obtain the clock cycle length sequence associated with the T-phase data gating signal; and the continuous 0 segments and continuous 1 segments in the eye diagram data sequence associated with the C-phase data gating signal are converted to obtain the clock cycle length sequence associated with the C-phase data gating signal. Using the clock cycle length sequence associated with the T-phase data gating signal and the clock cycle length sequence associated with the C-phase data gating signal, multiple analog parameters of the memory are adjusted to adapt to the duty cycle of the differential data gating signal.

2. The method according to claim 1, characterized in that, The preset step size is one-Nth of the unit time interval associated with the differential data gating signal, where N is a positive integer greater than or equal to 8.

3. The method according to claim 1, characterized in that, Each 0 and each 1 in the eye diagram data sequence associated with the T-phase data gating signal represents the time width corresponding to the preset step size. A continuous 1 segment in the eye diagram data sequence associated with the T-phase data gating signal corresponds to the distribution of the high-level region in the T-phase data gating signal, and a continuous 0 segment in the eye diagram data sequence associated with the T-phase data gating signal corresponds to the distribution of the low-level region in the T-phase data gating signal.

4. The method according to claim 3, characterized in that, Transforming consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the T-phase data gating signal to obtain the clock cycle length sequence associated with the T-phase data gating signal includes: Multiply the number of consecutive 0 segments in the eye diagram data sequence associated with the T-phase data strobe signal by the preset step size, and multiply the number of consecutive 1 segments in the eye diagram data sequence associated with the T-phase data strobe signal by the preset step size to obtain the clock cycle length sequence associated with the T-phase data strobe signal.

5. The method according to claim 4, characterized in that, The method further includes determining, based on the configuration of the preamble mode of the memory, whether the length of the first consecutive 0 segment in the eye diagram data sequence associated with the T-phase data strobe signal has reached a preset length; if not, determining that the preamble mode of the memory is faulty, wherein the preset length is determined based on the preamble length configured in the preamble mode and the trace length of the memory from the physical interface to the data sampling module.

6. The method according to claim 5, characterized in that, When the length of the first consecutive 0 segment in the eye diagram data sequence associated with the T-phase data strobe signal reaches the preset length, it is determined that the preamble mode of the memory is correct, and the first consecutive 1 segment after the first consecutive 0 segment in the eye diagram data sequence associated with the T-phase data strobe signal is used as the start of valid data in the eye diagram data sequence associated with the T-phase data strobe signal.

7. The method according to claim 1, characterized in that, Each 0 and each 1 in the eye diagram data sequence associated with the C-phase data gating signal represents a time width corresponding to the preset step size. A continuous 1 segment in the eye diagram data sequence associated with the C-phase data gating signal corresponds to the distribution of the high-level region in the C-phase data gating signal, and a continuous 0 segment in the eye diagram data sequence associated with the C-phase data gating signal corresponds to the distribution of the low-level region in the C-phase data gating signal.

8. The method according to claim 7, characterized in that, Transforming consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the C-phase data gating signal to obtain the clock cycle length sequence associated with the C-phase data gating signal includes: Multiply the number of consecutive 0 segments in the eye diagram data sequence associated with the C-phase data strobe signal by the preset step size, and multiply the number of consecutive 1 segments in the eye diagram data sequence associated with the C-phase data strobe signal by the preset step size to obtain the clock cycle length sequence associated with the C-phase data strobe signal.

9. The method according to claim 8, characterized in that, The method further includes determining, based on the configuration of the preamble mode of the memory, whether the length of the first consecutive 0 segment in the eye diagram data sequence associated with the C-phase data strobe signal has reached a preset length; if not, determining that the preamble mode of the memory is faulty, wherein the preset length is determined based on the preamble length configured in the preamble mode and the trace length of the memory from the physical interface to the data sampling module.

10. The method according to claim 9, characterized in that, When the length of the first consecutive 0 segment in the eye diagram data sequence associated with the C-phase data strobe signal reaches the preset length, it is determined that the preamble mode of the memory is correct, and the first consecutive 1 segment after the first consecutive 0 segment in the eye diagram data sequence associated with the C-phase data strobe signal is used as the start of valid data in the eye diagram data sequence associated with the C-phase data strobe signal.

11. The method according to claim 1, characterized in that, The memory's analog parameters include a duty cycle adjuster, automated test equipment, on-chip termination, and a forward device power supply.

12. The method according to claim 11, characterized in that, The duty cycle adjuster is used to adjust the static duty cycle of the clock tree associated with the memory; the automated test equipment is used for memory quality testing of the memory; the on-chip termination is used for characteristic impedance matching of the transmission lines associated with the memory; and the forward device power supply is used to adjust the operating voltage of the memory.

13. The method according to claim 12, characterized in that, The method further includes scanning and adjusting multiple analog parameters of the memory using at least one computer, based on a machine learning model, to adapt to the duty cycle of the differential data gating signal.

14. The method according to claim 1, characterized in that, The memory is DDR4, DDR5, or HBM.

15. A device for adjusting the duty cycle of a parallel interface on the receiving side, characterized in that, The device includes a duty cycle detection module and an analog parameter adjustment module. The device is communicatively connected to the memory or located within the physical layer of the memory. The physical interface of the memory receives differential read enable signals and differential data gating signals. The differential read enable signals include a T-phase read enable signal and a C-phase read enable signal. The differential data gating signals include a T-phase data gating signal and a C-phase data gating signal. The T-phase read enable signal is used to gate the T-phase data gating signal to obtain a gated T-phase data gating signal. The C-phase read enable signal is used to gate the C-phase data gating signal to obtain a gated C-phase data gating signal. The gated T-phase data gating signal and the gated C-phase data gating signal are used by a data sampling module within the physical layer of the memory to sample multiple data signals received by the physical interface to obtain a data sampling result. The duty cycle detection module is used to: use the zero-delay T-phase readout enable signal as a sampling signal, sample the T-phase data gating signal according to a preset step size, to obtain an eye diagram data sequence associated with the T-phase data gating signal; and use the zero-delay C-phase readout enable signal as a sampling signal, sample the C-phase data gating signal according to the preset step size, to obtain an eye diagram data sequence associated with the C-phase data gating signal. The duty cycle detection module is further configured to: based on the preset step size, convert consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the T-phase data gating signal to obtain a clock cycle length sequence associated with the T-phase data gating signal; and convert consecutive 0 segments and consecutive 1 segments in the eye diagram data sequence associated with the C-phase data gating signal to obtain a clock cycle length sequence associated with the C-phase data gating signal. The analog parameter adjustment module is used to adjust multiple analog parameters of the memory to adapt to the duty cycle of the differential data gating signal by using the clock cycle length sequence associated with the T-phase data gating signal and the clock cycle length sequence associated with the C-phase data gating signal.

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