In-memory computing circuit and chip based on 6T-SRAM and local arithmetic unit
By employing a 6T-SRAM and local arithmetic unit in the in-memory computing circuit, sharing the LCC to process sign bits and value bits, and utilizing a switched capacitor array module for charge sharing weighting, the adaptability and area overhead issues of the in-memory computing circuit are resolved, enabling low-power signed multiply-accumulate operations and multi-bit operations.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-02
- Publication Date
- 2026-05-15
AI Technical Summary
Existing in-memory computing circuits suffer from poor adaptability and large area overhead, especially in analog domain CIM circuits where the adaptability of signed weights and inputs is poor, and the addition of transistors in each memory cell leads to large area overhead.
An in-memory computing circuit based on 6T-SRAM and local arithmetic units is adopted. By setting first and second type column cells in each array block, and using the local arithmetic units (LCCs) located at the ends of the column cells to process the operations of the sign bits and the value bits respectively, a local arithmetic unit (LCC) is shared. Combined with the switched capacitor array module, charge sharing weighting is performed to reduce chip area overhead, and signed multiplication and accumulation operations are implemented in the analog domain.
It achieves support for signed multiplication and accumulation operations while reducing power consumption, simplifies the circuit structure of signed operations, reduces circuit complexity, and completes multi-bit operations without adding an additional ADC, thus adapting to the needs of complex neural networks.
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Figure CN122050459A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an in-memory computing circuit in the field of integrated circuit technology, and more particularly to an in-memory computing circuit based on 6T-SRAM and local arithmetic units, and also to an in-memory computing chip. Background Technology
[0002] In recent years, with the rapid development and deepening application of artificial intelligence and edge computing, there has been an urgent need for low-power consumption and high-speed read capabilities in hardware systems. However, in the traditional von Neumann architecture, data needs to be frequently migrated between memory and processor, leading to a serious "memory wall problem." This problem restricts the system's computing speed and energy efficiency, becoming a major bottleneck for improving overall performance. To overcome this computational bottleneck, the concept of Computing in Memory (CIM) has emerged. By integrating storage and computing functions, CIM architecture significantly reduces the overhead of data migration, achieving both ultra-low power operation and rapid response. It is widely recognized as one of the most promising solutions to overcome the limitations of the traditional von Neumann architecture.
[0003] Based on differences in signal processing methods, in-memory computing (CIM) is mainly divided into two branches: the digital domain and the analog domain. Digital domain CIM uses binary digital signals as the computational medium. While it boasts advantages such as high computational accuracy and stability, data still needs to be transferred between storage and computation units, failing to completely overcome the "memory wall" bottleneck. Furthermore, it suffers from low energy efficiency and high hardware area overhead. Analog domain CIM, on the other hand, utilizes the physical characteristics of analog signals to perform computations directly within the storage array, exhibiting extremely high energy efficiency and parallelism, making it the core choice for current low-power parallel computing. However, existing analog domain CIM circuits have compatibility issues with signed weights and signed inputs, and their implementation requires adding transistors to individual units, significantly increasing area overhead. Summary of the Invention
[0004] To address the technical problems of poor adaptability and large area overhead in existing in-memory computing circuits, this invention provides an in-memory computing circuit and chip based on 6T-SRAM and a local arithmetic unit.
[0005] This invention is implemented using the following technical solution: an in-memory computing circuit based on 6T-SRAM and a local arithmetic unit, comprising an in-memory computing array module; the in-memory computing array module comprises multiple array blocks arranged in rows and columns, each array block comprising multiple column units arranged along the row direction, each column unit comprising: Multiple 6T-SRAM memory cells are arranged along the column direction and used to store multi-bit weighted data; A local processing unit (LCC) is located at the end of the column cell and is connected to all 6T-SRAM memory cells in the corresponding column cell via local bit lines LBL and LBLB. The in-memory computing array module is configured as follows: (1) Receive multiple bits of input data through the LCC of each column cell; (2) The LCC of the first type of column cell determines the sign control signal of the multiplication and accumulation result based on the weight sign bit loaded by the local bit line and the sign bit of the input data, and outputs it to other column cells in the same array block; (3) The LCC of the second type column unit performs a signed multiplication operation based on the symbol control signal, the loaded weight value bits and the input data value bits, and accumulates the operation result to the corresponding calculation bit line to represent the accumulated value of the weight and the input.
[0006] This invention sets up a first type of column unit and a second type of column unit within each array block, and utilizes the local arithmetic unit (LCC) located at the end of the column unit to process the operations of the sign bit and the value bit respectively. The LCC of the first type of column unit generates a sign control signal based on the weight sign bit and the input sign bit. The LCC of the second type of column unit performs signed multiplication based on the sign control signal, the weight value bit, and the input value bit, and accumulates the result to the calculation bit line. By sharing a single local arithmetic unit (LCC) among multiple 6T-SRAM memory cells, the chip area overhead is reduced. This invention solves the technical problems of poor adaptability of existing in-memory computing circuits to signed weights and signed inputs, as well as the large area overhead caused by adding transistors in each memory cell. It achieves the effect of supporting signed multiplication and accumulation operations while reducing power consumption.
[0007] As a further improvement to the above scheme, each array block includes eight column units arranged along the row direction, wherein: the column units in the first column are first type column units, and the corresponding LCC is the symbol control unit SC; the column units in the remaining seven columns are second type column units, and the corresponding local arithmetic units are multiply-accumulate units MAC.
[0008] Furthermore, the symbol control unit SC includes: NMOS transistors N1, N2, N3, and N4; the gates of N1 and N2 are both connected to the global word line HWL, the source and drain of N1 are connected to LBL and the global bit line GBL respectively, and the source and drain of N2 are connected to LBLB and the global bit line GBLB respectively; for N3 and N4, their gates are connected to LBLB and LBL respectively, their sources receive the input symbol signal SIGN and the inverted signal SIGNF respectively, and their drains are connected to the symbol control signal line X. PMOS transistors P1 and P2 have their gates connected to LBL and LBLB, respectively, their sources receiving input signals SIGN and SIGNF, respectively, and their drains connected to the symbol control signal line X. In this configuration, N3 and P1 form the first transmission pair, and N4 and P2 form the second transmission pair. When LBL is high and LBLB is low, N4 and P2 are turned on, and P1 and N3 are turned off, outputting the signal SIGNF to the symbol control signal line X. When LBL is low and LBLB is high, N1 and P3 are turned on, and N2 and P4 are turned off, outputting the signal SIGN to the symbol control signal line X.
[0009] Furthermore, the multiply-accumulate unit MAC includes: The first transmission gate has its input connected to N5 and P3, its output connected to the first node, and its control terminal connected to the local bit lines LBL and LBLB, and is used to turn the bit on or off according to the stored weight value. The second transmission gate has its input end connected to the first node, its output end connected to the calculation bit line CBL, and its control end receiving the externally input time pulse signal ΔT and using it to control the conduction time according to the input value bit. NMOS transistors N5, N6, and N7; the gates of N6 and N7 are connected to the global word line HWL, the source and drain of N6 are connected to LBL and the global bit line GBL respectively, and the source and drain of N7 are connected to LBLB and the global bit line GBLB respectively; the source of N5 is connected to ground, the drain is connected to the first transmission gate, and the gate is connected to the symbol control signal X. PMOS transistor P3 has its source connected to the power supply voltage VDD, its drain connected to the first transmission gate, and its gate connected to the symbol control signal X. Specifically, when the first transmission gate and the second transmission gate are both turned on, if the symbol control signal X is low, P3 is turned on and N5 is turned off, and the power supply voltage VDD charges the computation bit line CBL through P3, the first transmission gate, and the second transmission gate to achieve positive multiplication accumulation; if the symbol control signal X is high, P3 is turned off and N5 is turned on, and the computation bit line CBL discharges to ground through the second transmission gate, the first transmission gate, and N5 to achieve negative multiplication accumulation.
[0010] As a further improvement to the above solution, the in-memory computing circuit further includes: A switched capacitor array module connects the computation bit lines of each column unit and is used to perform inter-column charge sharing weighting on the accumulated results on the corresponding computation bit lines.
[0011] Furthermore, the switched capacitor array module includes multiple column capacitors, inter-column connection switches, and ground switches; one end of each column capacitor is connected to the corresponding computation bit line through a first switch; the inter-column connection switches are connected between the computation bit lines of two adjacent columns; and the ground switches are connected between the other end of the column capacitor and ground.
[0012] Furthermore, the in-memory computing circuit also includes: An ADC quantization module is connected to the output of the switched capacitor array module and is used to quantize the weighted analog signal into digital code. The digital shift adder module is connected to the output of the ADC quantization module and is used to shift and accumulate the quantized digital code to output the final multiplication and accumulation result.
[0013] As a further improvement to the above scheme, the in-memory computing array module further includes a pre-charge circuit array module and a read / write control module; the pre-charge circuit array module connects the local bit line and the computing bit line, and is used to pre-charge the local bit line to the power supply voltage VDD before the operation starts, and also pre-charge the computing bit line to 1 / 2 VDD; the read / write control module connects to the 6T-SRAM storage unit, and is used to control the writing and reading of the weight data.
[0014] As a further improvement to the above scheme, the 6T-SRAM memory cell includes two cross-coupled inverters and two access transistors connected to the two inverters respectively, and has a pair of complementary memory nodes: Q and QB.
[0015] The present invention also provides an in-memory computing chip, which includes any of the in-memory computing circuits based on 6T-SRAM and local arithmetic units described above.
[0016] Compared to existing in-memory computing circuits, the in-memory computing circuit and chip based on 6T-SRAM and local arithmetic units of the present invention have the following advantages: 1. This in-memory computing circuit based on 6T-SRAM and local arithmetic units (LCCs) sets up first-class and second-class column units in each array block, and uses local arithmetic units (LCCs) located at the ends of the column units to process the operations of the sign bits and the value bits respectively. The LCC of the first-class column unit generates a sign control signal based on the weighted sign bit and the input sign bit. The LCC of the second-class column unit performs signed multiplication based on the sign control signal, the weighted value bit, and the input value bit, and accumulates the result to the calculation bit line. By sharing a local arithmetic unit (LCC) among multiple 6T-SRAM memory cells, the chip area overhead is reduced. This solves the technical problems of poor adaptability of existing in-memory computing circuits to signed weights and signed inputs, as well as the large area overhead caused by adding transistors in each memory cell. It achieves the effect of supporting signed multiplication and accumulation operations while reducing power consumption.
[0017] 2. The in-memory computing circuit based on 6T-SRAM and local arithmetic unit has a transmission pair consisting of NMOS and PMOS transistors in the first column unit. It selects to output the input symbol signal or its inverted signal to the symbol control signal line according to the level state of the local bit line, realizing the multiplication operation of the weighted symbol and the input symbol. It solves the problem of complex symbol operation in existing circuits and achieves the effect of simplifying the symbol operation circuit structure and reducing circuit complexity.
[0018] 3. The in-memory computing circuit based on 6T-SRAM and local arithmetic unit sets up a first transmission gate, a second transmission gate, and a charging and discharging path composed of PMOS transistor P3 and NMOS transistor N5 in the multiply-accumulate unit MAC of the second type column unit. It can select to charge or discharge the computing bit line according to the level of the sign control signal, realize the analog domain calculation of signed multiplication in a single cycle, solve the problem that the analog domain circuit is difficult to process positive and negative accumulated values at the same time, and achieve the effect of directly realizing signed multiply-accumulate operation in the analog domain.
[0019] 4. This in-memory computing circuit based on 6T-SRAM and local arithmetic unit achieves charge sharing weighting between adjacent columns by setting up a switched capacitor array module and using the timing control of the first switch, inter-column connection switch and ground switch. It can complete analog domain weighting between high-order and low-order columns without adding an additional ADC, solving the problem of increased power consumption and area caused by the need for a large number of ADCs in multi-bit operations. It performs weighting operations between two columns without changing the peripheral circuit, saving ADC overhead and reducing circuit power consumption and layout area overhead.
[0020] 5. This in-memory computing circuit based on 6T-SRAM and a local arithmetic unit stores 1 bit of weight data in the 6T-SRAM memory cell and feeds 8 bits of signed input into the LCC in cycles, thereby accumulating the weights on the computation bit line CBL. Furthermore, it employs a sign column + operation column method, pre-storing the sign of the weights and performing a multiplication operation with the input sign in the first step of the computation to determine the sign of the multiplication-accumulation result, which is then reflected on the computation bit line. This enables the multiplication-accumulation operation of signed weights with signed inputs, adapting to the demands of current complex neural networks.
[0021] 6. The beneficial effects of this in-memory computing chip are the same as those of the in-memory computing circuit based on 6T-SRAM and local arithmetic unit mentioned above, and will not be repeated here. Attached Figure Description
[0022] Figure 1 This is a circuit diagram of the in-memory computing circuit based on 6T-SRAM and a local arithmetic unit according to Embodiment 1 of the present invention.
[0023] Figure 2 for Figure 1 A schematic diagram of the system architecture of the in-memory computing array module of the in-memory computing circuit.
[0024] Figure 3 for Figure 1 The circuit diagram of the 6T-SRAM storage cell and the symbol control unit SC of the in-memory computing array module in the in-memory computing circuit.
[0025] Figure 4 for Figure 1 The circuit diagram of the 6T-SRAM storage unit and the multiply-accumulate unit MAC of the in-memory computing array module in the in-memory computing circuit. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0027] Example 1 Please see Figure 1-4This embodiment provides an in-memory computing circuit based on 6T-SRAM and a local arithmetic unit. This in-memory computing circuit can perform MAC calculation by multiplying a multi-bit signed input by a multi-bit signed weight. It should be noted that this embodiment uses an 8-bit signed input multiplied by an 8-bit signed weight as an example for calculation. The in-memory computing circuit includes an in-memory computing array module, and may also include a pre-charge circuit array module, a switched capacitor array module, a voltage-to-time conversion module, an input signal column channel module, an ADC quantization module, a digital shift adder module, and a calculation output module.
[0028] The in-memory computing array module comprises multiple array blocks arranged in rows and columns. Each array block includes multiple column cells arranged along the row direction. Each column cell includes multiple 6T-SRAM memory cells and a local computing cell (LCC). The multiple 6T-SRAM memory cells are arranged along the column direction and are used to store multi-bit weighted data. Each 6T-SRAM memory cell includes two cross-coupled inverters and two access transistors connected to the two inverters respectively, and has a pair of complementary memory nodes: Q and QB. The LCC is located at the end of the column cell and is connected to all 6T-SRAM memory cells in the corresponding column cell via local bit lines LBL and LBLB.
[0029] The in-memory computing array module is configured to: (1) receive multi-bit input data through the LCC of each column unit; (2) the LCC of the first type of column unit determines the sign control signal of the multiplication and accumulation result according to the weight sign bit loaded on the local bit line and the sign bit of the input data, and outputs it to other column units in the same array block; (3) the LCC of the second type of column unit performs signed multiplication operation according to the sign control signal, the loaded weight value bit and the value bit of the input data, and accumulates the operation result to the corresponding computing bit line to represent the multiplication and accumulation value of the weight and the input.
[0030] Specifically, to implement signed 8-bit input and weighted multiply-accumulate operations, each array block includes eight column units arranged along the row direction, where: the column units in the first column are first-type column units, and the corresponding LCC is the Sign Control (SC); the column units in the remaining seven columns are second-type column units, and the corresponding local arithmetic units are multiply-accumulate units (MAC).
[0031] In this embodiment, every eight 6T-SRAM memory cells share a single LCC in the column direction and are connected via local bit lines LBL and LBLB to form a column. The column is connected to global bit lines GBL and GBLB via transistor switches in the column direction. Eight such columnar units are arranged in the row direction to form a block (i.e., an array block). The shared local computing units are of two types: a symbol control unit (SC) responsible for symbolic operations and a multiply-accumulate unit (MAC) responsible for multiply-accumulate operations. In a block, the eight 6T-SRAM memory cells of the first column share a single symbol control unit (SC), while the 7x8 6T-SRAM memory cells of the remaining seven columns share seven multiply-accumulate units in their respective columns. The SRAM cells in the first column store 1 bit of symbolic information for the weights, while the SRAM cells in the remaining seven columns store 1 bit of weight information.
[0032] During multiply-accumulate calculations, one row of each block is enabled at a time via the row word line WL. First, a sign bit operation is performed. The 6T-SRAM storage cell in the first column of the block stores the sign of the weights. After enabling WL, it is multiplied by the input sign SIGN in SC via local bit lines LBL and LBLB to obtain the sign of the final multiply-accumulate result, which is then sent to the MAC on the right via signal X. Next, the multiply-accumulate operation is performed. The weight information stored in one row of the remaining seven columns of the block is loaded into the LCC module via local bit lines LBL and LBLB. After multiplication with the 4-bit input signal IN, it is accumulated on the calculation bit line CBL before entering the switched capacitor array module. The switched capacitor array module uses three switches to adjust the capacitance ratio of the two columns to 1:2 and performs charge-sharing weighting between the two columns of CBL. Finally, after ADC quantization and digital shift adder weighting, the digital multiply-accumulate result is obtained.
[0033] The circuit structure of the symbol control unit SC and the multiply-accumulate unit MAC is described in detail below.
[0034] The symbol control unit SC includes NMOS transistors N1, N2, N3, and N4, and PMOS transistors P1 and P2. The gates of N1 and N2 are both connected to the global word line HWL. The source and drain of N1 are connected to LBL and the global bit line GBL, respectively. The source and drain of N2 are connected to LBLB and the global bit line GBLB, respectively. For N3 and N4, their gates are connected to LBLB and LBL, respectively. Their sources receive the input symbol signal SIGN and the inverted signal SIGNF, respectively. Their drains are connected to the symbol control signal line X. The gates of PMOS transistors P1 and P2 are connected to LBL and LBLB, respectively. Their sources receive the input signals SIGN and SIGNF, respectively. Their drains are connected to the symbol control signal line X.
[0035] In this configuration, N3 and P1 form the first transmission pair, and N4 and P2 form the second transmission pair. When LBL is high and LBLB is low, N4 and P2 in the transmission transistors are turned on, while P1 and N3 are turned off, outputting the signal SIGNF to the symbol control signal line X. When LBL is low and LBLB is high, N1 and P3 in the transmission transistors are turned on, while N2 and P4 are turned off, outputting the signal SIGN to the symbol control signal line X.
[0036] The multiply-accumulate unit (MAC) includes a first transmission gate, a second transmission gate, NMOS transistors N5, N6, and N7, and a PMOS transistor P3. The input of the first transmission gate is connected to transistors N5 and P3, and its output is connected to the first node. The control terminal of the first transmission gate is connected to local bit lines LBL and LBLB, and is used to determine its on / off state based on the stored weighted value bits. The input of the second transmission gate is connected to the aforementioned first node, and its output is connected to the calculation bit line CBL. The control terminal of the second transmission gate receives an externally input time pulse signal ΔT and is used to control the conduction time based on the input value bits.
[0037] The gates of N6 and N7 are both connected to the global word line HWL. The source and drain of N6 are connected to LBL and the global bit line GBL, respectively. The source and drain of N7 are connected to LBLB and the global bit line GBLB, respectively. The source of N5 is connected to ground, the drain is connected to the first transmission gate, and the gate is connected to the symbol control signal X (the inverted signal content is omitted). The source of PMOS transistor P3 is connected to the power supply voltage VDD, the drain is connected to the first transmission gate, and the gate is connected to the symbol control signal X.
[0038] When both the first and second transmission gates are turned on, if the symbol control signal X is low, P3 is on and N5 is off. The power supply voltage VDD charges the computation bit line CBL through P3, the first transmission gate, and the second transmission gate, achieving positive multiplication accumulation. If the symbol control signal X is high, P3 is off and N5 is on. The computation bit line CBL discharges to ground through the second transmission gate, the first transmission gate, and N5, achieving negative multiplication accumulation.
[0039] Transistors N1 and N2 are responsible for the connection between the local bit lines and the global bit lines. The sign information of the weights is pre-stored in the SRAM cell. The input weights are controlled by the external signal SIGN and its inverse signal SIGNF. At the start of the operation, the word line WL is turned on to load the weight sign into the local bit lines LBL / LBLB. The multiplication operation is completed by four transistors N3, N4, P1, and P2. The result is a high or low level, which is reflected on the signal line X. X is connected to the rightmost 7 columns of its block.
[0040] The column responsible for multiply-accumulate (MAC) consists of eight standard 6T-SRAM memory cells, three NMOS transistors, one PMOS transistor, and two transmission gates. The N1 and N2 transistors, controlled by the global word line HWL, handle signal transmission between the local bit lines LBL / LBLB and the global bit lines GBL / GBLB. Before the operation begins, the calculation bit line CBL is precharged to 1 / 2 VDD. The 1-bit weight "Q" and its inverse "QB" stored in the 6T-SRAM memory cells control the opening and closing of the upper transmission gate via the local bit lines LBL and LBLB. An externally applied 4-bit input signal controls the opening and closing of the lower transmission gate. The specific opening time ΔT is the value of the 4-bit input signal. The signal line X generated by the sign control unit selects to turn on one of the upper NMOS transistors or one of the PMOS transistors. If X is low, the PMOS transistor is on and the NMOS transistor is off, indicating a positive sign bit; otherwise, it is negative.
[0041] For example, if the sign bit input is negative, meaning signal line X is high, then the NMOS is on and the PMOS is off. When the first row's 1-bit weight stores "1", meaning "Q" = 1 and "QB" = 0, then WL is enabled. <0> When LBL is high and LBLB is low, the first transmission gate in LCC is turned on, and then the input signals IN and INF are applied. If the 4-bit input signal is 0011 (decimal number 3) at this time, the lower transmission gate will be open for 3 ΔT. CBL will discharge through the transmission gate and the NMOS transistor on the right for 3 ΔT, thereby changing its charge value.
[0042] In some embodiments, the in-memory computing array module may further include a precharge circuit array module and a read / write control module. The precharge circuit array module connects the local bit lines and the computing bit lines, and is used to precharge the local bit lines to the power supply voltage VDD before the operation begins, and also precharge the computing bit lines to 1 / 2 VDD. The read / write control module connects to the 6T-SRAM storage cell and is used to control the writing and reading of weight data, enabling normal reading and writing of the 6T-SRAM cell, and also implementing the function of writing weight bit signs and weight values.
[0043] The switched capacitor array module connects the computation bit lines of each column unit and is used to perform inter-column charge-sharing weighting on the accumulated results on the corresponding computation bit lines. In this embodiment, the switched capacitor array module includes multiple column capacitors, inter-column connection switches, and ground switches. One end of each column capacitor is connected to the corresponding computation bit line through a first switch, the inter-column connection switch is connected between the computation bit lines of two adjacent columns, and the ground switch is connected between the other end of the column capacitor and ground.
[0044] The 8-bit signed data input signal is loaded into the array periodically through the input signal column channel module. The ADC quantization module is connected to the output of the switched capacitor array module and is used to quantize the weighted analog signal into digital code. Within one cycle, the ADC quantization module quantizes the voltage value on the accumulated calculation bit line, converting the voltage into signed binary code. The digital shift adder module is connected to the output of the ADC quantization module and is used to shift and accumulate the quantized digital code to output the final multiplication and accumulation result. The digital shift adder shifts and weights the 7-bit multiplication and accumulation value (excluding the sign bit) in a column, realizing the multiplication and accumulation of the 8-bit signed weight and the 8-bit signed input.
[0045] The following describes the various stages of the in-memory computing circuit operation in this embodiment.
[0046] Preparation phase: First, the weight values to be calculated are stored in the array. The 8-bit weight values are stored in one row of eight 6T cells in the block, with the first column storing the sign value of the weight. After the weight information is stored, the pre-charge unit operates to pre-charge the local bit lines and calculation bit lines of the circuit. Specifically, the local bit line LBL / LBLB is pre-charged to VDD, and the calculation bit line CBL is pre-charged to 1 / 2VDD.
[0047] Sign operation phase: The first step in the calculation phase is to perform sign bit operations. By turning on the word line WL, the sign bit of the weight is loaded onto the local bit line LBL / LBLB. Depending on the weight value stored in the SRAM, the voltage of LBL / LBLB will present a high level and a low level, thus causing one pair of transistors P1 / N3 and P2 / N4 to conduct and the other pair to be cut off. This allows one of the input sign bit signals SIGN / SIGNF to be loaded onto signal line X. Here, the high or low level of X represents the result of the sign bit operation; a high level means the sign of the input multiplied by the weight is negative, and vice versa.
[0048] Charge sharing phase: The input 8-bit number consists of a 1-bit sign bit and 7-bit value bits. The sign bit is determined by the external signals SIGN and SIGNF. The input 7-bit value is divided into two cycles, with the lower four bits (4 bits) and the higher three bits (3 bits), which are converted into the signal IN / INF on-time ΔT. Before the multiplication and accumulation calculation of the lower four bits is completed, switches S1 / S2 are closed and S3 is open, with an equivalent capacitance of 2C on each calculation bit line CBL. After the multiplication and accumulation operation is completed, S2 is opened and then S3 is closed. At this time, since the capacitance on the left column (high-order bits) CBL is 2C and the capacitance on the right column (low-order bits) CBL is C, closing S3 to perform charge sharing achieves a 2:1 weighted average between the high and low bits, which is then sent to the ADC for quantization. When the higher three three-bit value is input in the second cycle, the precharge is completed and S1 / S2 / S3 is opened to perform the multiplication and accumulation operation. At this time, the capacitance on both CBLs is C. After the operation is completed, S2 is closed first to allow the CBL on the right column to share charge with the capacitor on S2. Then S2 is opened and S3 is closed to achieve a 2:1 weighting of the two columns. The result is then sent to the ADC for quantization.
[0049] The input 8-bit signal has 7 bits after removing the sign bit, so it is input in two cycles: the lower four bits and the higher three bits.
[0050] First cycle: During the precharge phase, switches S1 / S2 are closed and S3 is opened. The local bit line LBL / LBLB is precharged to a high level, and the calculation bit line CBL is precharged to 1 / 2 VDD. Then, HWL is turned off for multiply-accumulate operations. At the start of multiply-accumulate, the word line WL is turned high, thereby loading the data stored in the SRAM in the corresponding row onto the local bit line LBL / LBLB. The data stored in the first column of each block is the sign of the weight. Q=0 represents a positive weight sign, and vice versa. If Q=0, i.e., the weight sign is positive, then transistors N3 / P1 are turned on, and the input sign bit SIGN is loaded into signal line X. If Q=1, i.e., the weight sign is negative, then transistors N4 / P2 are turned on, and the input sign bit SIGNF is loaded into signal line X. SIGN and SIGNF are an inverted pair of signals, where SIGN high represents a negative input signal, and vice versa. Subsequently, in the MAC module, the input 4-bit value is converted into a corresponding time signal ΔT, controlling the lower transmission gate to open for ΔT time intervals. Since the weight values have been loaded onto the local bit lines to control the opening or closing of the upper transmission gate, the calculation bit line will choose to discharge to ground via N5 for ΔT time intervals or charge CBL via P3 from VDD for ΔT time intervals, depending on the level of signal line X. Multiple rows of WL can be opened at once, so multiple cells on CBL will perform multiplication operations simultaneously, and then accumulate on CBL. The final value is reflected in the voltage on the calculation bit line CBL. After the multiplication and accumulation operations are completed, charge sharing is performed between columns. The left column is the high-order bit, and the right column is the low-order bit, with a weight difference of 2. At this time, switch S2 is opened, and then switch S3 is closed to achieve a 2:1 weighting of the high-order and low-order bits, which is then sent to the ADC array for quantization.
[0051] The second cycle: The pre-charge phase is the same as the first cycle. It's important to note that after the pre-charge, S1 / S2 needs to be disconnected before performing the multiplication-accumulation operation. This is because the input in the second cycle is 3-bit data. Without changing the external circuitry, the capacitor connected to CBL is C, which is half of the 2C in the first cycle. Therefore, the margin of the 3-bit data in the second cycle is increased. That is, for the same 1 ΔT change in the second cycle, the corresponding voltage change on CBL is twice that of the first cycle. After the multiplication-accumulation operation, S2 needs to be closed first, then S2 opened and S3 closed to achieve a 2:1 weighted average between the high and low bits of the two columns. The data is then sent to the ADC array for quantization.
[0052] In summary, compared with existing in-memory computing circuits, the in-memory computing circuit based on 6T-SRAM and local arithmetic units in this embodiment has the following advantages: 1. This in-memory computing circuit based on 6T-SRAM and local arithmetic units (LCCs) sets up first-class and second-class column units in each array block, and uses local arithmetic units (LCCs) located at the ends of the column units to process the operations of the sign bits and the value bits respectively. The LCC of the first-class column unit generates a sign control signal based on the weighted sign bit and the input sign bit. The LCC of the second-class column unit performs signed multiplication based on the sign control signal, the weighted value bit, and the input value bit, and accumulates the result to the calculation bit line. By sharing a local arithmetic unit (LCC) among multiple 6T-SRAM memory cells, the chip area overhead is reduced. This solves the technical problems of poor adaptability of existing in-memory computing circuits to signed weights and signed inputs, as well as the large area overhead caused by adding transistors in each memory cell. It achieves the effect of supporting signed multiplication and accumulation operations while reducing power consumption.
[0053] 2. The in-memory computing circuit based on 6T-SRAM and local arithmetic unit has a transmission pair consisting of NMOS and PMOS transistors in the first column unit. It selects to output the input symbol signal or its inverted signal to the symbol control signal line according to the level state of the local bit line, realizing the multiplication operation of the weighted symbol and the input symbol. It solves the problem of complex symbol operation in existing circuits and achieves the effect of simplifying the symbol operation circuit structure and reducing circuit complexity.
[0054] 3. The in-memory computing circuit based on 6T-SRAM and local arithmetic unit sets up a first transmission gate, a second transmission gate, and a charging and discharging path composed of PMOS transistor P3 and NMOS transistor N5 in the multiply-accumulate unit MAC of the second type column unit. It can select to charge or discharge the computing bit line according to the level of the sign control signal, realize the analog domain calculation of signed multiplication in a single cycle, solve the problem that the analog domain circuit is difficult to process positive and negative accumulated values at the same time, and achieve the effect of directly realizing signed multiply-accumulate operation in the analog domain.
[0055] 4. This in-memory computing circuit based on 6T-SRAM and local arithmetic unit achieves charge sharing weighting between adjacent columns by setting up a switched capacitor array module and using the timing control of the first switch, inter-column connection switch and ground switch. It can complete analog domain weighting between high-order and low-order columns without adding an additional ADC, solving the problem of increased power consumption and area caused by the need for a large number of ADCs in multi-bit operations. It performs weighting operations between two columns without changing the peripheral circuit, saving ADC overhead and reducing circuit power consumption and layout area overhead.
[0056] 5. This in-memory computing circuit based on 6T-SRAM and a local arithmetic unit stores 1 bit of weight data in the 6T-SRAM memory cell and feeds 8 bits of signed input into the LCC in cycles, thereby accumulating the weights on the computation bit line CBL. Furthermore, it employs a sign column + operation column method, pre-storing the sign of the weights and performing a multiplication operation with the input sign in the first step of the computation to determine the sign of the multiplication-accumulation result, which is then reflected on the computation bit line. This enables the multiplication-accumulation operation of signed weights with signed inputs, adapting to the demands of current complex neural networks.
[0057] Example 2 This embodiment provides an in-memory computing chip, which includes the in-memory computing circuit based on 6T-SRAM and local arithmetic units provided in Embodiment 1. This chip can integrate modules such as an in-memory computing array module, a switched-capacitor array module, an ADC quantization module, and a digital shift adder module. It may also include an input / output interface unit, a timing control unit, an address decoding unit, and a power management unit. The input / output interface unit receives multi-bit signed data and weighted data from external input and outputs the final calculation result to the outside of the chip. The timing control unit is connected to the local arithmetic unit (LCC) of each column unit, and is used to generate and control the time pulse signal ΔT for loading input data, as well as control the closing and opening timing of each switch in the switched-capacitor array module. The address decoding unit is connected to the word lines and bit lines of the in-memory computing array module, and is used to implement the weighted data writing operation to a specified 6T-SRAM memory cell. The power management unit provides a stable operating voltage for each module inside the chip, including providing VDD voltage for pre-charging local bit lines and providing 1 / 2 VDD voltage for pre-charging computing bit lines.
[0058] This in-memory computing chip integrates multiple array blocks, enabling parallel processing of multiple sets of multiply-accumulate operations, significantly improving computing throughput. Meanwhile, based on the low-area-overhead circuit structure of Embodiment 1, the overall chip area is effectively controlled, making it suitable for applications in scenarios such as IoT terminal devices, edge computing nodes, and wearable devices that are sensitive to power consumption and area.
[0059] Example 3 This embodiment provides a memory that includes the in-memory computing circuit based on 6T-SRAM and a local arithmetic unit as described in Embodiment 1. This memory is a static random access memory (SRAM), suitable for artificial intelligence and machine learning. The inference and training processes of neural networks involve a large number of multiply-accumulate operations; in-memory computing in SRAM can significantly accelerate these operations and improve overall performance. The in-memory computing of SRAM in this embodiment reduces chip area overhead and power consumption, improves system stability and computational accuracy, and enables multiple computing modes, thereby improving the utilization efficiency of hardware resources.
[0060] Example 4 This embodiment provides an electronic device including a memory and a processor. The memory includes the in-memory computing circuit based on 6T-SRAM and a local arithmetic unit as described in Embodiment 1. Compared to existing electronic devices, this electronic device significantly improves computing efficiency, reduces power consumption, reduces hardware complexity, and enhances computing flexibility.
[0061] Example 5 This embodiment provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. The memory is the same as the memory in Embodiment 4.
[0062] The computer device can take many forms, including embedded chips or modules, or general-purpose data processing devices, such as smart terminals, tablets, laptops, desktop computers, rack servers, blade servers, tower servers, or cabinet servers (including standalone servers or server clusters composed of multiple servers).
[0063] The computer device of this embodiment includes, but is not limited to, a memory and a processor that can be interconnected via a system bus. The memory (i.e., the readable storage medium) includes flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory may be an internal storage unit of the computer device, such as the hard disk or RAM of the computer device.
[0064] In some embodiments, a processor may be a central processing unit (CPU), a graphics processing unit (GPU), a controller, a microcontroller, a microprocessor, or other data processing chip. The processor is typically used to control the overall operation of a computer device. In this embodiment, the processor is used to run program code stored in memory or process data.
[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. An in-memory computing circuit based on 6T-SRAM and a local arithmetic unit, characterized in that, It includes an in-memory computing array module; The internal computing array module includes multiple array blocks arranged in rows and columns. Each array block includes multiple column units arranged along the row direction. Each column unit includes: Multiple 6T-SRAM memory cells are arranged along the column direction and used to store multi-bit weighted data; A local processing unit (LCC) is located at the end of the column cell and is connected to all 6T-SRAM memory cells in the corresponding column cell via local bit lines LBL and LBLB. The in-memory computing array module is configured as follows: (1) Receive multiple bits of input data through the LCC of each column cell; (2) The LCC of the first type of column cell determines the sign control signal of the multiplication and accumulation result based on the weight sign bit loaded by the local bit line and the sign bit of the input data, and outputs it to other column cells in the same array block; (3) The LCC of the second type column unit performs a signed multiplication operation based on the symbol control signal, the loaded weight value bits and the input data value bits, and accumulates the operation result to the corresponding calculation bit line to represent the accumulated value of the weight and the input.
2. The in-memory computing circuit based on 6T-SRAM and a local arithmetic unit as described in claim 1, characterized in that, Each array block includes eight column units arranged along the row direction, where: the column units in the first column are first-type column units, and the corresponding LCC is the symbol control unit SC; the column units in the remaining seven columns are second-type column units, and the corresponding local arithmetic units are multiply-accumulate units MAC.
3. The in-memory computing circuit based on 6T-SRAM and a local arithmetic unit as described in claim 2, characterized in that, The symbol control unit SC includes: NMOS transistors N1, N2, N3, and N4; the gates of N1 and N2 are both connected to the global word line HWL, the source and drain of N1 are connected to LBL and the global bit line GBL respectively, and the source and drain of N2 are connected to LBLB and the global bit line GBLB respectively; for N3 and N4, their gates are connected to LBLB and LBL respectively, their sources receive the input symbol signal SIGN and the inverted signal SIGNF respectively, and their drains are connected to the symbol control signal line X. PMOS transistors P1 and P2 have their gates connected to LBL and LBLB, respectively, their sources receiving input signals SIGN and SIGNF, respectively, and their drains connected to the symbol control signal line X. In this configuration, N3 and P1 form the first transmission pair, and N4 and P2 form the second transmission pair. When LBL is high and LBLB is low, N4 and P2 are turned on, and P1 and N3 are turned off, outputting the signal SIGNF to the symbol control signal line X. When LBL is low and LBLB is high, N1 and P3 are turned on, and N2 and P4 are turned off, outputting the signal SIGN to the symbol control signal line X.
4. The in-memory computing circuit based on 6T-SRAM and a local arithmetic unit as described in claim 3, characterized in that, The multiply-accumulate unit (MAC) includes: The first transmission gate has its input connected to N5 and P3, its output connected to the first node, and its control terminal connected to the local bit lines LBL and LBLB, and is used to turn the bit on or off according to the stored weight value. The second transmission gate has its input end connected to the first node, its output end connected to the calculation bit line CBL, and its control end receiving the externally input time pulse signal ΔT and using it to control the conduction time according to the input value bit. NMOS transistors N5, N6, and N7; the gates of N6 and N7 are connected to the global word line HWL, the source and drain of N6 are connected to LBL and the global bit line GBL respectively, and the source and drain of N7 are connected to LBLB and the global bit line GBLB respectively; the source of N5 is connected to ground, the drain is connected to the first transmission gate, and the gate is connected to the symbol control signal X. PMOS transistor P3 has its source connected to the power supply voltage VDD, its drain connected to the first transmission gate, and its gate connected to the symbol control signal X. Specifically, when the first transmission gate and the second transmission gate are both turned on, if the symbol control signal X is low, P3 is turned on and N5 is turned off, and the power supply voltage VDD charges the computation bit line CBL through P3, the first transmission gate, and the second transmission gate to achieve positive multiplication accumulation; if the symbol control signal X is high, P3 is turned off and N5 is turned on, and the computation bit line CBL discharges to ground through the second transmission gate, the first transmission gate, and N5 to achieve negative multiplication accumulation.
5. The in-memory computing circuit based on 6T-SRAM and a local arithmetic unit as described in claim 1, characterized in that, The in-memory computing circuit also includes: A switched capacitor array module connects the computation bit lines of each column unit and is used to perform inter-column charge sharing weighting on the accumulated results on the corresponding computation bit lines.
6. The in-memory computing circuit based on 6T-SRAM and a local arithmetic unit as described in claim 5, characterized in that, The switched capacitor array module includes multiple column capacitors, inter-column connection switches, and ground switches; one end of each column capacitor is connected to the corresponding computation bit line through a first switch; the inter-column connection switches are connected between the computation bit lines of two adjacent columns; and the ground switches are connected between the other end of the column capacitor and ground.
7. The in-memory computing circuit based on 6T-SRAM and a local arithmetic unit as described in claim 5, characterized in that, The in-memory computing circuit also includes: An ADC quantization module is connected to the output of the switched capacitor array module and is used to quantize the weighted analog signal into digital code. The digital shift adder module is connected to the output of the ADC quantization module and is used to shift and accumulate the quantized digital code to output the final multiplication and accumulation result.
8. The in-memory computing circuit based on 6T-SRAM and a local arithmetic unit as described in claim 1, characterized in that, The in-memory computing array module further includes a pre-charge circuit array module and a read / write control module; the pre-charge circuit array module connects the local bit line and the computing bit line, and is used to pre-charge the local bit line to the power supply voltage VDD before the operation starts, and also pre-charge the computing bit line to 1 / 2 VDD; the read / write control module connects to the 6T-SRAM storage unit, and is used to control the writing and reading of the weight data.
9. The in-memory computing circuit based on 6T-SRAM and a local arithmetic unit as described in claim 1, characterized in that, The 6T-SRAM memory cell includes two cross-coupled inverters and two access transistors connected to the two inverters respectively, and has a pair of complementary memory nodes: Q and QB.
10. An in-memory computing chip, characterized in that, It includes the in-memory computing circuit based on 6T-SRAM and local arithmetic unit as described in any one of claims 1-9.