Multi-terminal direct-current circuit breaker meeting N-1 safety constraint and control method of multi-terminal direct-current circuit breaker

Abstract

The invention discloses a multi-terminal direct current circuit breaker meeting N-1 safety constraints and a control method thereof. The multi-terminal direct current circuit breaker comprises m ports, m main connection branches MC, two main disconnection branches MB, two energy absorption branches EA, m residual current switches RCB and 2m transfer branches TB. According to the multi-terminal direct current circuit breaker, three different working modes can be adopted to remove fault lines according to failure conditions of internal devices of the circuit breaker, and fault isolation is achieved. According to the multi-terminal direct-current circuit breaker and the control method thereof provided by the invention, the fault current can still be cut off under the condition that any branch has device failure, namely, the N-1 safety constraint is met, so that the cut-off reliability of the multi-terminal direct-current circuit breaker is effectively improved, and the safe operation of a direct-current system is ensured.

Description

Technical Field

[0001] This invention relates to the field of DC power transmission in power systems, and specifically to a multi-terminal DC circuit breaker that satisfies the N-1 safety constraint and its control method. Background Technology

[0002] As a key component of flexible DC power grids, DC circuit breakers can quickly and selectively disconnect faulty lines after a fault occurs on the DC side, without affecting power transmission between non-faulty lines. For example... Figure 1 As shown, compared with multiple two-terminal DC circuit breakers, multi-terminal DC circuit breakers (MTCBs) can effectively reduce investment costs by sharing some expensive device branches or device units. In recent years, domestic and international research on MTCBs has mainly focused on topology innovation, control strategies, economics, and fault isolation performance.

[0003] 1. Topology and Performance Optimization

[0004] To improve the technical and economic efficiency of MTCBs (Multi-Port Hybrid DC Circuit Breakers), researchers have proposed various topology schemes. For example, modular cascaded multi-port hybrid DC circuit breakers, through modular series technology, reduce the number of control devices while ensuring breaking capacity, thus improving equipment utilization. Multi-port hybrid DC circuit breakers with adaptive reclosing capabilities achieve fault isolation by sharing a main circuit breaker and utilize capacitor voltage differences to identify the nature of the fault, thereby shortening isolation time and reducing arrester energy stress. Furthermore, research has optimized fault current limiting capabilities, resulting in a 38% reduction in peak fault current and a 61% reduction in arrester energy dissipation stress.

[0005] 2. Preliminary Exploration of Reliability Modeling

[0006] Despite continuous improvements in topology and control strategies, the problem of fault isolation failure caused by the failure of devices in branches (such as IGBTs, diodes, and surge arresters) has received little systematic research. It wasn't until 2021 that a team from South China University of Technology first pointed out that most existing research only involves two-port DC circuit breakers (MTCBs), and there is a lack of reliability modeling work specifically for MTCBs, especially reliability models based on device circuit structure. This team proposed a multi-state reliability model considering different operating states and quantified the reliability index of MTCBs through Markov processes, laying the foundation for subsequent research. However, such work remains rare and has not yet delved into the correlation analysis between device-level failure mechanisms and fault isolation failure.

[0007] 3. Summary of the current research status

[0008] Current research on MTCBs (Mechanical, Material, and Circuit) primarily focuses on improving operational performance and reducing costs, with related review articles systematically summarizing the working principles, advantages, and disadvantages of various topologies. However, systematic research on fault isolation failures caused by device failures remains scarce.

[0009] Therefore, it is necessary to propose a multi-terminal DC circuit breaker topology and its control strategy that satisfies the N-1 safety constraint, so that the multi-terminal DC circuit breaker can still work normally and achieve fault isolation even if any internal branch becomes unavailable due to device failure or maintenance. Summary of the Invention

[0010] The purpose of this invention is to overcome the shortcomings and deficiencies of the prior art and to provide a multi-terminal DC circuit breaker and its control strategy that meet the N-1 safety constraint. This enables the multi-terminal DC circuit breaker and its control strategy that meet the N-1 safety constraint to still work normally even if any internal branch becomes unavailable due to device failure or maintenance of the multi-terminal DC circuit breaker, thus achieving fault isolation.

[0011] Specifically, the first aspect of the present invention provides a multi-terminal DC circuit breaker that satisfies the N-1 safety constraint, comprising: m ports, m main conducting branches MC, 2 main discontinuing branches MB, 2 energy absorbing branches EA, m residual current switches RCB and 2m transfer branches TB;

[0012] Port of multi-terminal DC circuit breaker i Used to connect to a DC line i i = 1, 2, ..., m;

[0013] Residual current switch RCB i Used to isolate faulty lines after fault current is cleared; the left port serves as a port for a multi-terminal DC circuit breaker. i The right port is connected to the main branch MC. i The left port;

[0014] Main branch MC i It is used to conduct system current under normal conditions, and the left port is connected to the residual current switch RCB. i The right ports of m main branches MC are connected to the same bus L.

[0015] 2m transfer branches are used to transfer fault current, including m upper transfer branches SU and m lower transfer branches SD;

[0016] Upward transfer branch SU i The cathode is connected to the residual current switch RCB i On the right port, the m upper transfer branches SU are connected using a common anode.

[0017] Downward transfer branch SD i The anode is connected to the residual current switch RCB i On the right port, the m down transfer branches SD adopt a common cathode connection;

[0018] The main interruption branch MB1 interrupts the fault current and transfers the fault current to the energy absorption branch EA1, one end of which is connected to the bus L and the other end is connected to the common anode of the transfer branch SU.

[0019] The main interruption branch MB2 interrupts the fault current and transfers the fault current to the energy absorption branch EA2, one end of which is connected to the bus L and the other end is connected to the common cathode of the lower transfer branch SD.

[0020] The energy-absorbing branch EA1 is used to absorb the energy of the fault current and is connected in parallel across the two ends of the main disconnection branch MB1.

[0021] The energy-absorbing branch EA2 is used to absorb the energy of the fault current and is connected in parallel across the two ends of the main disconnect branch MB2.

[0022] The multi-terminal DC circuit breaker of the present invention realizes the interconnection of multiple DC network points through a multi-port structure; the main pass branch provides normal power transmission, and the main break branch is responsible for rapid isolation during faults or maintenance; the energy absorption branch is used to absorb electromagnetic energy at the moment of breaking, thereby realizing arc-free breaking; the transfer branch undertakes power redistribution after the branch fails, realizing the self-healing and redundancy of the system.

[0023] Traditional DC circuit breakers are prone to arcing under high voltage and high current, leading to equipment damage and system instability. By introducing an energy-absorbing branch, the magnetic energy stored in the line can be converted into heat energy or stored in the capacitor at the moment of breaking; the transfer branch immediately switches the power to other channels to avoid voltage surges and achieve true arc-free breaking.

[0024] With redundant main and transfer branches, the system can quickly reconfigure power flow after a single point of failure, achieving an N-1 (i.e., any branch failure) safety constraint. This feature is particularly suitable for environments with difficult maintenance, such as offshore wind farms, because it can delay downtime for maintenance and improve availability.

[0025] Traditional DC power distribution systems often require a complete power outage to maintain a single branch, leading to power interruptions. This invention addresses this by dynamically removing branches from the maintenance list at the controller level and utilizing the remaining branches for power compensation. This enables "online" or "hot-swappable" maintenance, significantly improving equipment availability and operational efficiency.

[0026] Based on the above, the main branch MC i UFD (Ultra-fast Mechanical Switch) i and load commutation switch LCS iThe load commutation switch is configured in series; it includes two fully controlled semiconductor devices connected in reverse series, and each fully controlled semiconductor device has a diode connected in reverse parallel.

[0027] Both the main disconnection branch MB1 and the main disconnection branch MB2 use fully controlled semiconductor devices;

[0028] Both energy-absorbing branches EA1 and EA2 are equipped with surge arresters;

[0029] Upward transfer branch SU i and the down transfer branch SD i All of them use semi-controlled semiconductor devices.

[0030] Based on the above, the main branch MC i Mechanical switch MS i ;

[0031] The main disconnect branch MB1 includes a pre-charge capacitor C1, an inductor L1, and a semi-controlled semiconductor device SSD1. The anodes of the pre-charge capacitor C1, the inductor L1, and the semi-controlled semiconductor device SSD1 are connected in series. The unconnected end of the pre-charge capacitor C1 is connected to the bus L, and the cathode of SSD1 is connected to the common anode of the transfer branch SU.

[0032] The main disconnect branch MB2 includes a pre-charge capacitor C2, an inductor L2, and a semi-controlled semiconductor device SSD2. The anodes of the pre-charge capacitor C2, the inductor L2, and the semi-controlled semiconductor device SSD2 are connected in series. The unconnected end of the pre-charge capacitor C2 is connected to the common cathode of the lower transfer branch SD, and the cathode of SSD2 is connected to the bus L.

[0033] Both energy-absorbing branches EA1 and EA2 are equipped with surge arresters;

[0034] Upward transfer branch SU i and the down transfer branch SD i All of them use semi-controlled semiconductor devices.

[0035] Based on the above, semi-controlled semiconductor devices use, but are not limited to, thyristors and bidirectional thyristors; fully controlled semiconductor devices use, but are not limited to, insulated gate bipolar transistors (IGBTs) and gate turn-off thyristors (GTOs).

[0036] Based on the above, the rated current of semi-controlled and fully controlled semiconductor devices is designed according to the maximum current under the most severe fault and an appropriate current margin is set, and the rated voltage is designed according to the maximum voltage that it can withstand under fault and an appropriate voltage margin is set; the rated voltage of the surge arrester is selected as 1.5 times the system voltage of the DC power grid where the multi-terminal DC circuit breaker is located.

[0037] A second aspect of the present invention provides a control method for a multi-terminal DC circuit breaker that satisfies the N-1 safety constraint, wherein the control method is in relation to the port. i connected DC line i When a single-pole ground fault occurs, the multi-terminal DC circuit breaker operates in the following three modes:

[0038] Mode 1: No device failure; SU i SD x MC y Or MB2 short circuit; SU y SD x MC x Or MB2 can be used as a roadblock;

[0039] Mode 2: SU y MC i Or MB1 short circuit; SU i Or MB1 open circuit;

[0040] Mode 3: UFD i Refusal to move;

[0041] Where x is 1, 2, ..., m; y is 1, 2, ..., i-1, i+1, i+2, ..., m;

[0042] In Mode 1, the control method for multi-terminal DC circuit breakers is as follows:

[0043] After the multi-terminal DC circuit breaker receives the opening command from the protection device, the upper transfer branch SU is connected. i Connect the main branch MB1 and close the faulty port. i Load commutation switch LCS i ;

[0044] When flowing through the main branch MC i Chinese Super League High-Speed ​​Mechanical Switch UFD i When the fault current drops to 0, the ultra-fast mechanical switch UFD is disconnected. i Achieve arc-free segmentation;

[0045] When ultra-fast mechanical switch UFD i After the contacts are completely separated, the main disconnection branch MB1 is closed, and the fault current is transferred to the energy-absorbing branch EA1 connected in parallel with the main disconnection branch MB1. The energy-absorbing branch EA1 absorbs the fault current energy, causing the fault current to decrease.

[0046] When the fault current drops to 0, open the port. i Residual current switch RCB i , transfer the faulty line iCompletely isolated from the system, while power exchange continues between non-faulty ports;

[0047] In Mode 2, the control method for multi-terminal DC circuit breakers is as follows:

[0048] After the multi-terminal DC circuit breaker receives the opening command from the protection device, the lower transfer branch SD is connected. y And disconnect the main branch MB2, and shut down the load commutation switch LCS on the non-faulty port. y ;

[0049] When the flow passes through the non-faulty port, the ultra-fast mechanical switch UFD y When the fault current drops to 0, the ultra-fast mechanical switch UFD is disconnected. y Achieve arc-free segmentation;

[0050] When waiting for ultra-fast mechanical switch UFD y After all the contacts are completely separated, the main circuit breaker MB2 is turned off, and the fault current is transferred to the energy-absorbing branch EA2 connected in parallel with the main circuit breaker MB2. The energy-absorbing branch EA2 absorbs the fault current energy, causing the fault current to decrease.

[0051] When the fault current drops to 0, open the port. i Residual current switch RCB i This completely isolates the faulty port from the system.

[0052] When port i Residual current switch RCB i When fully open, the ultra-fast mechanical switch (UFD) connects the non-faulty ports. y and load commutation switch LCS y Power exchange continues between non-faulty branches;

[0053] In Mode 3, the control method for multi-terminal DC circuit breakers is as follows:

[0054] After the multi-terminal DC circuit breaker receives the opening command from the protection device, the upper transfer branch SU is connected. i Connect the main branch MB1 and close the faulty port. i Load commutation switch LCS i ;

[0055] When flowing through the main branch MC i Chinese Super League High-Speed ​​Mechanical Switch UFD i When the fault current drops to 0, the ultra-fast mechanical switch (UFD) i Unable to perform segmentation;

[0056] If an ultra-fast mechanical switch (UFD) that should have disconnected is detected... iIf a failure to operate occurs, the downstream transfer branch SD connected to the non-faulty port will be activated. y And the main branch MB2, shutting off the load commutation switch LCS on the non-faulty port. y ;

[0057] When the ultra-fast mechanical switch UFD flows through the non-faulty port y When the fault current drops to 0, the ultra-fast mechanical switch UFD on the non-faulty port is disconnected. y Achieve arc-free segmentation;

[0058] When the non-faulty port of the ultra-fast mechanical switch UFD y After the contacts are completely separated, the main circuit MB2 is closed;

[0059] When the fault current drops to 0, the residual current switch RCB at port i is opened. i This completely isolates the faulty port from the system.

[0060] When the residual current switch RCB at port i i When fully open, the ultra-fast mechanical switch (UFD) connects the non-faulty ports. y and load commutation switch LCS y Power exchange continues between non-faulty branches.

[0061] A third aspect of the present invention provides a control method for a multi-terminal DC circuit breaker that satisfies the N-1 safety constraint, wherein the control method is in relation to the port. i connected DC line i When a single-pole ground fault occurs, the multi-terminal DC circuit breaker operates in the following three modes:

[0062] Mode 1: No device failure; SU i SD x MS y MB2 or EA2 short circuit; SU y SD x MS y MB2 or EA2 open circuit;

[0063] Mode 2: SU y MS i MB1 or EA1 short circuit; SU i MB1 or EA1 open circuit;

[0064] Mode 3: MS i Refusal to move;

[0065] Where x is 1, 2, ..., m; y is 1, 2, ..., i-1, i+1, i+2, ..., m;

[0066] In Mode 1, the control method for multi-terminal DC circuit breakers is as follows:

[0067] After the multi-terminal DC circuit breaker receives the opening command from the protection device, the arc-operated mechanical switch branch MS... i ;

[0068] When the mechanical switch branch MS i After the contacts separate to a sufficient insulation gap, the upper transfer branch SU is turned on. i and semi-controlled semiconductor device SSD1;

[0069] The pre-charge capacitor C1 immediately discharges along the following path: C1-L1-SSD1-SU i -MS i -C1, flows through the mechanical switch branch MS i The fault current is transferred to the main disconnect branch MB1 and begins to reverse charge the pre-charge capacitor C1.

[0070] When the voltage of the pre-charge capacitor C1 reaches the set value U0, the semi-controlled semiconductor device SSD1 is naturally turned off, and the fault current begins to decrease.

[0071] When the fault current drops to 0, the residual current switch RCB is opened. i This completely isolates the faulty line from the system, while allowing power exchange to continue between the non-faulty ports.

[0072] In Mode 2, the control method for multi-terminal DC circuit breakers is as follows:

[0073] After the multi-terminal DC circuit breaker receives the opening command from the protection device, the mechanical switch branch MS, which is connected to the non-faulty line by arc tripping,... y ;

[0074] When the mechanical switch branch MS y After the contacts separate to a sufficient insulation gap, the lower transfer branch SD is turned on. y and semi-controlled semiconductor device SSD2;

[0075] Immediate edge path of pre-charge capacitor C2: C2-L2-SSD2-MS y -SD y -C2 discharges, flowing through the mechanical switch branch MS. y The fault current is transferred to the main disconnect branch MB2 and begins to reverse charge the pre-charge capacitor C2.

[0076] When the voltage of the pre-charge capacitor C2 reaches the set value U0, the semi-controlled semiconductor device SSD2 is turned off naturally, and the fault current begins to decrease.

[0077] When the fault current drops to 0, first open the mechanical switch branch MS. iThen turn on the residual current switch RCB. i Semi-controlled semiconductor devices SD y Natural shutdown, shutting down the faulty port. i Completely isolate the system, and then close the mechanical switch branch MS on the non-faulty port. y Power exchange continues between non-faulty ports;

[0078] In Mode 3, the control method for multi-terminal DC circuit breakers is as follows:

[0079] After a multi-terminal DC circuit breaker receives an opening command from the protection device, if it detects that the mechanical switch branch MS, which should have performed arc-assisted tripping, is... i If a failure to operate occurs, the mechanical switch branch MS connected to the non-faulty line will trip with arcing. y ;

[0080] When the mechanical switch branch MS y After the contacts separate to a sufficient insulation gap, the lower transfer branch SD is turned on. y And the pre-charge capacitor C2 of the semi-controlled semiconductor device SSD2 immediately follows the path C2-L2-SSD2-MS y -SD y -C2 discharges, flowing through the mechanical switch branch MS. y The fault current is transferred to the main disconnect branch MB2 and begins to reverse charge the pre-charge capacitor C2.

[0081] When the voltage of the pre-charge capacitor C2 reaches the set value U0, the semi-controlled semiconductor device SSD2 is turned off naturally, and the fault current begins to decrease.

[0082] When the fault current drops to 0, open the mechanical switch branch MS. i and residual current switch RCB i Semi-controlled semiconductor devices SD y Natural shutdown, shutting down the faulty port. i Completely isolated from the system, port i After completely isolating the system, close the mechanical switch branch MS on the non-faulty port. y Power exchange continues between non-faulty ports.

[0083] Based on the above, in the main disconnection branch MB1 and the main disconnection branch MB2, the pre-charging capacitors C1 and C2 are both C, the inductors L1 and L2 are both L, and the pre-charging voltage of the pre-charging capacitors C1 and C2 is U0.

[0084] The selection principles for C, L, and U0 are as follows:

[0085] The discharge current of the pre-charge capacitor C1 or C2 during the period from t2 to t3 is:

[0086] (1)

[0087] The discharge current i of the pre-charge capacitor C1 or C2 c The maximum value and the maximum rate of change of current are respectively: and i c The maximum value is greater than the maximum fault current; time t2 is the time when the multi-terminal DC circuit breaker receives the opening command from the protection device; time t3 is the time when the contacts of the mechanical switch branch that performs arc tripping separate to a sufficient insulation gap.

[0088] U0, L, and C should satisfy the constraints in (2):

[0089] (2)

[0090] In the formula, M1, M2, and M3 are safety margins, and all are greater than 1; I max This represents the maximum value of the fault current; (di / dt) max Let di / dt be the maximum rate of change of current that the mechanical switch branch can withstand; (du / dt) max Du / dt is the maximum rate of voltage change that the mechanical switch branch can withstand.

[0091] A fourth aspect of the present invention provides a DC power grid, including a modular multilevel converter (MMC) and a DC line, and also includes the multi-terminal DC circuit breaker that satisfies the N-1 safety constraint.

[0092] The multi-terminal DC circuit breaker that meets the N-1 safety constraint is connected to the same bus as the modular multilevel converter (MMC) and connected to the DC line through a port.

[0093] The fifth aspect of the present invention provides a DC power grid control method, wherein the DC power grid includes a modular multilevel converter (MMC) and a DC line, and also includes the multi-terminal DC circuit breaker that satisfies the N-1 safety constraint.

[0094] The multi-terminal DC circuit breaker that meets the N-1 safety constraint is connected to the same bus as the modular multilevel converter (MMC) and connected to the DC line through the port.

[0095] When controlling the multi-terminal DC circuit breaker that satisfies the N-1 safety constraint, the control method described above is used.

[0096] The advantages and effects of this invention are as follows:

[0097] 1) Compared with configuring multiple two-port DC circuit breakers at the DC bus, the multi-port DC circuit breaker topology group and its control strategy proposed in this invention can effectively reduce investment costs.

[0098] 2) The multi-terminal DC circuit breaker topology group and its control strategy that meet the N-1 safety constraints proposed in this invention can still successfully interrupt the fault current even if a UFD or MS failure to operate occurs suddenly during the interruption process.

[0099] 3) The multi-terminal DC circuit breaker topology group and its control strategy that meet the N-1 safety constraint proposed in this invention can continue to work after detecting any branch fault during non-interruption period without immediately performing interruption maintenance; this feature is very attractive for engineering scenarios such as offshore wind farms where maintenance is inconvenient.

[0100] 4) The multi-terminal DC circuit breaker topology and its control strategy that meet the N-1 safety constraints proposed in this invention can be inspected one by one without affecting the normal operation of the multi-terminal DC circuit breaker, thus realizing online maintenance and effectively improving equipment availability. Attached Figure Description

[0101] Figure 1 It refers to the configuration of multiple two-port DC circuit breakers and multi-terminal DC circuit breakers in a DC power grid.

[0102] Figure 2 This is a topology diagram of the multi-terminal DC circuit breaker proposed in Embodiment 1 of the present invention.

[0103] Figure 3 This is a topology diagram of the multi-terminal DC circuit breaker proposed in Embodiment 2 of the present invention.

[0104] Figure 4 This is the system wiring diagram of the four-terminal bipolar DC power grid in Embodiment 6 of the present invention.

[0105] Figure 5 This is the waveform of the first type of multi-terminal DC circuit breaker in the Mode 1 interruption period in Embodiment 6 of the present invention.

[0106] Figure 6 This is the waveform of the first type of multi-terminal DC circuit breaker in Embodiment 6 of the present invention during the mode 2 interruption period.

[0107] Figure 7 This is the waveform of the second type of multi-terminal DC circuit breaker in embodiment 6 of the present invention during mode 1 interruption.

[0108] Figure 8 This is the waveform of the second type of multi-terminal DC circuit breaker in embodiment 6 of the present invention during mode 3 interruption. Detailed Implementation

[0109] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0110] A note before each embodiment:

[0111] In practical engineering, DC line protection devices identify DC line faults and issue interruption commands to multi-terminal DC circuit breakers. Therefore, when conducting research on the topology and control strategy of multi-terminal DC circuit breakers, DC line faults are usually treated as known events, and how to identify DC line faults is no longer specifically discussed. Similarly, the unavailability of internal branches of a multi-terminal DC circuit breaker caused by device failure can be identified by a dedicated device protection device, which will inform the controller of the multi-terminal DC circuit breaker of the branch unavailability. The unavailability of internal branches of a multi-terminal DC circuit breaker caused by maintenance can be directly signaled to the controller by the maintenance personnel. Therefore, this invention does not discuss how to obtain the unavailability of internal branches of a multi-terminal DC circuit breaker, but treats the unavailability of internal branches as a known event, and then studies the control strategy of the multi-terminal DC circuit breaker.

[0112] Example 1

[0113] This embodiment provides a multi-terminal DC circuit breaker that meets the N-1 safety constraint, denoted as a first-type multi-terminal DC circuit breaker, which has arc-free breaking characteristics, such as... Figure 2 As shown, it includes: m ports, m main pass branches MC, 2 main disconnect branches MB, 2 energy absorption branches EA, m residual current switches RCB and 2m transfer branches TB.

[0114] Port of multi-terminal DC circuit breaker i Used to connect to a DC line i ;i=1,2,...,m.

[0115] Residual current switch RCB i Used to isolate faulty lines after fault current is cleared; the left port serves as a port for a multi-terminal DC circuit breaker. i The right port is connected to the main branch MC. i The left port.

[0116] Main branch MC i It is used to conduct system current under normal conditions, and the left port is connected to the residual current switch RCB. i The right ports of m main branch MCs are connected to the same bus L; the right ports of the main branch MCs are connected to the same bus L. i UFD (Ultra-fast Mechanical Switch) i and load commutation switch LCS iThe load commutation switch is configured in series; it includes two fully controlled semiconductor devices connected in reverse series, and each fully controlled semiconductor device has a diode connected in reverse parallel.

[0117] 2m transfer branches are used to transfer fault current, including m upper transfer branches SU and m lower transfer branches SD;

[0118] Upward transfer branch SU i The cathode is connected to the residual current switch RCB i On the right port, the m upper transfer branches SU are connected using a common anode.

[0119] Downward transfer branch SD i The anode is connected to the residual current switch RCB i On the right port, the m down transfer branches SD adopt a common cathode connection;

[0120] Upward transfer branch SU i and the down transfer branch SD i All of them use semi-controlled semiconductor devices.

[0121] The main interruption branch MB1 interrupts the fault current and transfers the fault current to the energy absorption branch EA1, one end of which is connected to the bus L and the other end is connected to the common anode of the transfer branch SU.

[0122] The main interruption branch MB2 interrupts the fault current and transfers the fault current to the energy absorption branch EA2, one end of which is connected to the bus L and the other end is connected to the common cathode of the lower transfer branch SD.

[0123] Both the main disconnection branch MB1 and the main disconnection branch MB2 use fully controlled semiconductor devices.

[0124] The energy-absorbing branch EA1 is used to absorb the energy of the fault current and is connected in parallel across the two ends of the main disconnection branch MB1.

[0125] The energy-absorbing branch EA2 is used to absorb the energy of the fault current and is connected in parallel across the two ends of the main disconnect branch MB2.

[0126] Both energy-absorbing branches EA1 and EA2 use surge arresters.

[0127] In this embodiment, a semi-controlled semiconductor device refers to a semiconductor device that can be controlled to turn on by an external signal, but cannot be turned off by the same signal after being turned on, and needs to be turned off by external circuit conditions, including thyristors, bidirectional thyristors, etc.; a fully controlled semiconductor device refers to a semiconductor device that can be controlled to turn on and off by an external signal, including insulated gate bipolar transistors (IGBTs), gate turn-off thyristors (GTOs), etc.

[0128] Specifically, the rated current of semi-controlled and fully controlled semiconductor devices is designed based on the maximum current under the most severe fault and an appropriate current margin is set (1.5 to 2 times the maximum current under the most severe fault). The rated voltage is designed based on the maximum voltage that it can withstand under fault and an appropriate voltage margin is set (1.5 to 2 times the maximum voltage that it can withstand under fault). The rated voltage of surge arresters is selected as 1.5 times the system voltage of the DC power grid where the multi-terminal DC circuit breaker is located.

[0129] The multi-terminal DC circuit breaker with arc-free breaking characteristics in this embodiment can clear faulty lines by adopting three different operating modes according to the failure of internal components of the circuit breaker, thereby achieving fault isolation.

[0130] In relation to port i (i=1,2,...,m) connected DC lines i When a single-pole ground fault occurs, the multi-terminal DC circuit breaker operates in the following three modes:

[0131] Table 1 Mode Operation Status

[0132] model Work situation Mode 1 <![CDATA[SU without any device failure i , SD x , MC y or short circuit of MB2 y , SD x , MC x or open circuit of MB2]]> Mode 2 <![CDATA[SU y MC i Or MB1 short circuit SU i Or MB1 open road]]> Mode 3 <![CDATA[UFD i Refusal to move

[0133] Where x is 1, 2, ..., m; y is 1, 2, ..., i-1, i+1, i+2, ..., m. The fault of the DC line connected to other ports and the port... i The same applies when a fault occurs in a connected DC line.

[0134] In Mode 1, the working process includes the fault current free development stage, the fault current commutation stage, and the fault current clearing stage.

[0135] 1) Fault current free development stage: (t0) <t<t1)

[0136] At time t0, with port i connected DC line i When a single-pole ground fault occurs, the other (m-1) non-faulty ports all feed current to the faulty port through the main branch, and the current at the faulty port rises rapidly.

[0137] Let the fault detection delay be Δt1;

[0138] At time t1, the single-pole ground fault was detected and successfully located.

[0139] 2) Fault current commutation stage: (t2) <t<t3)

[0140] At time t2, the multi-terminal DC circuit breaker receives the opening command from the protection device and connects SU. iAnd MB1, and shut down the LCS on the faulty port. i The fault current begins from the port. i MC i Switch to MB1;

[0141] At time t3, the stream flows through MC i UFD i The fault current drops to 0, disconnecting the UFD. i Achieve arc-free segmentation.

[0142] 3) Fault current clearing stage: (t4) <t<t5)

[0143] At time t4, UFD i The contacts are completely separated, closing MB1, and the fault current is switched from MB1 to EA1. Because the transient interruption voltage of the surge arrester is greater than the system rated voltage, the fault current begins to decrease;

[0144] At time t5, the fault current drops to 0; at this time, port t5 is opened. i Residual current switch RCB i This completely isolates the faulty line from the system, while allowing power exchange to continue between the non-faulty ports.

[0145] In Mode 2, the working process includes the fault current free development stage, the fault current commutation stage, and the fault current clearing stage.

[0146] 1) Fault current free development stage: (t0) <t<t1)

[0147] At time t0, with port i connected DC line i When a single-pole ground fault occurs, the other (m-1) non-faulty ports all feed current to the faulty port through the main branch, and the current at the faulty port rises rapidly.

[0148] Let the fault detection delay be Δt1;

[0149] At time t1, the single-pole ground fault was detected and successfully located.

[0150] 2) Fault current commutation stage: (t) 2a <t<t 3a )

[0151] t 2a At that moment, the multi-terminal DC circuit breaker receives the opening command from the protection device and connects to SD. y And MB2, and shut down the LCS on the non-faulty port. y The fault current starts from MC y Switch to MB2;

[0152] t 3a At any given moment, the UFD flows through the non-faulty port. y The fault currents all dropped to 0, and the UFD was disconnected. y Achieve arc-free segmentation.

[0153] 3) Fault current clearing stage: (t) 4a <t<t 6a )

[0154] t 4a At that moment, UFD y All contacts are completely separated, MB2 is turned off, the fault current is commutated to EA2, and the fault current begins to decrease.

[0155] t 5a At a certain moment, the fault current drops to 0. At this time, the port is opened. i Residual current switch RCB i This completely isolates the faulty port from the system.

[0156] t 6a At any given time, port i Residual current switch RCB i Fully open, conduct the UFD on the non-faulty port. y and LCS y Power exchange continues between non-faulty branches.

[0157] In Mode 3, the working process includes the fault current free development stage, the fault current commutation stage, and the fault current clearing stage.

[0158] 1) Fault current free development stage: (t0) <t<t1)

[0159] At time t0, with port i connected DC line i When a single-pole ground fault occurs, the other (m-1) non-faulty ports all feed current to the faulty port through the main branch, and the current at the faulty port rises rapidly.

[0160] Let the fault detection delay be Δt1;

[0161] At time t1, the single-pole ground fault was detected and successfully located.

[0162] 2) Fault current commutation stage: (t2) <t<t 4b )

[0163] Before time t3, in the ultra-fast mechanical switch UFD iIn the event of failure to operate, the operation process during the fault current commutation stage is the same as that under normal operation in Mode 1.

[0164] At time t3, the UFD flows i The fault current drops to 0. At this point, the UFD, which should have tripped without arcing,... i Refusal to move occurs. Assume t 3b At that moment, the multi-terminal DC circuit breaker detected UFD. i Failed to operate. At this time, the SD card connected to the non-faulty port is activated. y And MB2, disable the LCS on the non-faulty port. y The fault current flows from the MC at the non-faulty port. y Commutation to the series branch of MB2 and MB1;

[0165] t 4b At any given moment, the UFD flowing through the non-faulty port y When the fault current drops to 0, disconnect the UFD from all non-faulty ports. y Achieve arc-free segmentation.

[0166] 3) Fault current clearing stage: (t) 5b <t<t 7b )

[0167] t 5b At any given time, the UFD on the non-faulty port y The contacts are completely separated, MB2 is closed, and the fault current is commutated to EA2;

[0168] t 6b At a certain moment, the fault current drops to 0. At this time, the residual current switch RCB at port i is opened. i This completely isolates the faulty port from the system.

[0169] t 7b At time i, the residual current switch RCB at port i i Fully open, conduct the UFD on the non-faulty port. y and LCS y Power exchange continues between non-faulty branches.

[0170] Example 2

[0171] This embodiment provides a multi-terminal DC circuit breaker that meets the N-1 safety constraint, denoted as a second-type multi-terminal DC circuit breaker, which has extremely low conduction loss characteristics, such as... Figure 3 As shown, it includes: m ports, m main pass branches MC, 2 main disconnect branches MB, 2 energy absorption branches EA, m residual current switches RCB and 2m transfer branches TB.

[0172] Port of multi-terminal DC circuit breakeri Used to connect to a DC line i ;i=1,2,...,m.

[0173] Residual current switch RCB i Used to isolate faulty lines after fault current is cleared; the left port serves as a port for a multi-terminal DC circuit breaker. i The right port is connected to the main branch MC. i The left port.

[0174] Main branch MC i It is used to conduct system current under normal conditions, and the left port is connected to the residual current switch RCB. i The right ports of m main branches MC are connected to the same bus L.

[0175] Main branch MC i Mechanical switch MS i .

[0176] 2m transfer branches are used to transfer fault current, including m upper transfer branches SU and m lower transfer branches SD;

[0177] Upward transfer branch SU i The cathode is connected to the residual current switch RCB i On the right port, the m upper transfer branches SU are connected using a common anode.

[0178] Downward transfer branch SD i The anode is connected to the residual current switch RCB i On the right port, the m down transfer branches SD adopt a common cathode connection;

[0179] Upward transfer branch SU i and the down transfer branch SD i All of them use semi-controlled semiconductor devices.

[0180] The main interruption branch MB1 interrupts the fault current and transfers the fault current to the energy absorption branch EA1, one end of which is connected to the bus L and the other end is connected to the common anode of the transfer branch SU.

[0181] The main interruption branch MB2 interrupts the fault current and transfers the fault current to the energy absorption branch EA2, one end of which is connected to the bus L and the other end is connected to the common cathode of the lower transfer branch SD.

[0182] The main disconnect branch MB1 includes a pre-charge capacitor C1, an inductor L1, and a semi-controlled semiconductor device SSD1. The anodes of the pre-charge capacitor C1, the inductor L1, and the semi-controlled semiconductor device SSD1 are connected in series. The unconnected end of the pre-charge capacitor C1 is connected to the bus L, and the cathode of SSD1 is connected to the common anode of the transfer branch SU.

[0183] The main disconnect branch MB2 includes a pre-charge capacitor C2, an inductor L2, and a semi-controlled semiconductor device SSD2. The anodes of the pre-charge capacitor C2, the inductor L2, and the semi-controlled semiconductor device SSD2 are connected in series. The unconnected end of the pre-charge capacitor C2 is connected to the common cathode of the lower transfer branch SD, and the cathode of SSD2 is connected to the bus L.

[0184] The energy-absorbing branch EA1 is used to absorb the energy of the fault current and is connected in parallel across the two ends of the main disconnection branch MB1.

[0185] The energy-absorbing branch EA2 is used to absorb the energy of the fault current and is connected in parallel across the two ends of the main fault branch MB2.

[0186] Both energy-absorbing branches EA1 and EA2 use surge arresters.

[0187] In this embodiment, a semi-controlled semiconductor device refers to a semiconductor device that can be controlled to turn on by an external signal, but cannot be turned off by the same signal after being turned on, and needs to be turned off by external circuit conditions, including thyristors, bidirectional thyristors, etc.; a fully controlled semiconductor device refers to a semiconductor device that can be controlled to turn on and off by an external signal, including insulated gate bipolar transistors (IGBTs), gate turn-off thyristors (GTOs), etc.

[0188] Specifically, the rated current of semi-controlled and fully controlled semiconductor devices is designed based on the maximum current under the most severe fault and an appropriate current margin is set (1.5 to 2 times the maximum current under the most severe fault). The rated voltage is designed based on the maximum voltage that it can withstand under fault and an appropriate voltage margin is set (1.5 to 2 times the maximum voltage that it can withstand under fault). The rated voltage of surge arresters is selected as 1.5 times the system voltage of the DC power grid where the multi-terminal DC circuit breaker is located.

[0189] Specifically, in the main disconnection branch MB1 and the main disconnection branch MB2, the pre-charge capacitors C1 and C2 are both C, the inductors L1 and L2 are both L, and the pre-charge voltage of the pre-charge capacitors C1 and C2 is U0.

[0190] The selection principles for C, L, and U0 are as follows:

[0191] The discharge current of the pre-charge capacitor C1 or C2 during the period from t2 to t3 is:

[0192] (1)

[0193] The discharge current i of the pre-charge capacitor C1 or C2 c The maximum value and the maximum rate of change of current are respectively: and i cThe maximum value is greater than the maximum fault current; time t2 is the time when the multi-terminal DC circuit breaker receives the opening command from the protection device (semi-controlled semiconductor devices SSD and SU). x or SD x (Conduction); time t3 is the moment when the contacts of the mechanical switch branch performing arc tripping separate to a sufficient insulation gap (MS). x (Current drops to 0)

[0194] U0, L, and C should satisfy the constraints in (2):

[0195] (2)

[0196] In the formula, M1, M2, and M3 are safety margins, and all are greater than 1; I max This represents the maximum value of the fault current; (di / dt) max Let di / dt be the maximum rate of change of current that the mechanical switch branch can withstand; (du / dt) max Du / dt is the maximum rate of voltage change that the mechanical switch branch can withstand.

[0197] The multi-terminal DC circuit breaker with extremely low conduction loss in this embodiment can clear faulty lines by adopting three different operating modes according to the failure of internal components of the circuit breaker, thereby achieving fault isolation.

[0198] In relation to port i (i=1,2,...,m) connected DC lines i When a single-pole ground fault occurs, the multi-terminal DC circuit breaker operates in the following three modes:

[0199] Table 2 Mode Operation Status

[0200] model Work situation Mode 1 <![CDATA[There is no failure of any device, SU i , SD x , MS y , short circuit of CCU2 or EA2, SU y , SD x , MS y , open circuit of CCU2 or EA2]]> Mode 2 <![CDATA[SU y MS i CCU1 or EA1 short circuit SU i CCU1 or EA1 open circuit]]> Mode 3 <![CDATA[MS i Refusal to move

[0201] Where x is 1, 2, ..., m; y is 1, 2, ..., i-1, i+1, i+2, ..., m. The fault of the DC line connected to other ports and the port... i The same applies when a fault occurs in a connected DC line.

[0202] In Mode 1, the working process includes the fault current free development stage, the fault current commutation stage, and the fault current clearing stage.

[0203] 1) Fault current free development stage: (t0) <t<t1)

[0204] At time t0, with port i connected DC line iWhen a single-pole ground fault occurs, the other (m-1) non-faulty ports all feed current to the faulty port through the main branch, and the current at the faulty port rises rapidly.

[0205] Let the fault detection delay be Δt1;

[0206] At time t1, the single-pole ground fault was detected and successfully located.

[0207] 2) Fault current commutation stage: (t2) <t<t4)

[0208] At time t2, the multi-terminal DC circuit breaker receives the opening command from the protection device, MS i Immediately trip the circuit breaker while the arc is still running;

[0209] At time t3, MS i The contacts are separated to a sufficient insulation gap (the physical gap formed between the contacts is sufficient to stably withstand the arrester's operating voltage, i.e., 1.5 times the DC system voltage), and the SU is turned on. i And SSD1; C1 immediately discharges along the following path: C1-L1-SSD1-SU i -MS i -C1, flows through MS i The fault current is transferred to CCU1, and reverse charging of C1 begins.

[0210] At time t4, the MS flows i The current drops to 0, MS i The electric arc in the MS was completely extinguished. i Restore insulation strength.

[0211] 3) Fault current clearing stage: (t5) <t<t6)

[0212] At time t5, the voltage of C1 reaches the set value U0, the current flowing through SSD1 crosses zero, SSD1 turns off naturally, and the fault current is transferred to EA1; since the transient interruption voltage of the surge arrester is greater than the rated voltage of the system, the fault current begins to decrease.

[0213] At time t6, the fault current drops to 0, and RCB is turned on. i This completely isolates the faulty line from the system, while allowing power exchange to continue between the non-faulty ports.

[0214] In Mode 2, the working process includes the fault current free development stage, the fault current commutation stage, and the fault current clearing stage.

[0215] 1) Fault current free development stage: (t0) <t<t1)

[0216] At time t0, with port i connected DC linei When a single-pole ground fault occurs, the other (m-1) non-faulty ports all feed current to the faulty port through the main branch, and the current at the faulty port rises rapidly.

[0217] Let the fault detection delay be Δt1;

[0218] At time t1, the single-pole ground fault was detected and successfully located.

[0219] 2) Fault current commutation stage: (t) 2a <t<t 4a )

[0220] t 2a At that moment, the multi-terminal DC circuit breaker receives the opening command from the protection device, and the MS connected to the non-faulty line... y Immediately trip the circuit breaker while the arc is still running;

[0221] t 3a At that time, MS y After the contacts separate to a sufficient insulation gap (the physical gap formed between the contacts reaches a level that can stably withstand the arrester's operating voltage, i.e., 1.5 times the DC system voltage), SD is turned on. y And SSD2; Immediate Path of C2: C2-L2-SSD2-MS y -SD y -C2 discharges, flowing through MS y The fault current is transferred to CCU2, and reverse charging of C2 begins;

[0222] t 4a Time flows through MS y The current drops to 0, MS y The electric arc in the MS was completely extinguished. y Restore insulation strength.

[0223] 3) Fault current clearing stage: (t) 5a <t<t 6a )

[0224] t 5a At that moment, the voltage of C2 reaches the set value U0, the current flowing through SSD2 crosses zero, SSD2 turns off naturally, and the fault current is transferred to EA2; since the transient interruption voltage of the surge arrester is greater than the system rated voltage, the fault current begins to decrease.

[0225] t 6a At that moment, the fault current dropped to 0, and the MS was turned on sequentially. i and RCB i Semi-controlled semiconductor devices SD y Natural shutdown, shutting down the faulty port. iCompletely isolated from the system, port i After completely isolating the system, close the mechanical switch MS on the non-faulty port. y Power exchange continues between non-faulty ports.

[0226] In Mode 3, the working process includes the fault current free development stage, the fault current commutation stage, and the fault current clearing stage.

[0227] 1) Fault current free development stage: (t0) <t<t1)

[0228] At time t0, with port i connected DC line i A single-pole ground fault occurs in MS i In the event of failure to operate, the operation process during the free development stage of the fault current is consistent with the operation of Mode 1.

[0229] 2) Fault current commutation stage: (t2) <t<t 5b )

[0230] Before time t3, at MS i In the event of failure to operate, the operation process during the fault current commutation stage is the same as under normal operating conditions.

[0231] At time t3, the MS circuit breaker, which should have been tripped by arcing, was detected. i Refusal to move occurs. Assume t 3b At that moment, the multi-terminal DC circuit breaker detected MS i Failure to operate; at this time, the MS connected to the non-faulty line... y Immediately trip the circuit breaker while the arc is still running;

[0232] t 4b At that time, MS y After the contacts separate to a sufficient insulation gap (the physical gap formed between the contacts reaches a level that can stably withstand the arrester's operating voltage, i.e., 1.5 times the DC system voltage), SD is turned on. y And SSD2; C2 immediately follows the path C2-L2-SSD2-MS y -SD y -C2 discharges, flowing through MS y The fault current is transferred to CCU2, and reverse charging of C2 begins;

[0233] t 5b Time flows through MS y The current drops to 0, MS y The electric arc in the MS was completely extinguished. y Restore insulation strength.

[0234] 3) Fault current clearing stage: (t)6b <t<t 7b )

[0235] t 6b At that moment, the voltage of C2 reaches the set value U0, the current flowing through SSD2 crosses zero, SSD2 turns off naturally, and the fault current is transferred to EA2; since the transient interruption voltage of the surge arrester is greater than the system rated voltage, the fault current begins to decrease.

[0236] t 7b At that moment, the fault current dropped to 0, and the MS was turned on sequentially. i and RCB i Semi-controlled semiconductor devices SD y Natural shutdown, shutting down the faulty port. i Completely isolated from the system, port i After completely isolating the system, close the mechanical switch MS on the non-faulty port. y Power exchange continues between non-faulty ports.

[0237] Example 4

[0238] This embodiment provides a DC power grid, including a modular multilevel converter (MMC) and a DC line, and also includes a first type of multi-terminal DC circuit breaker;

[0239] The first type of multi-terminal DC circuit breaker is connected to the same bus as the modular multilevel converter (MMC) and connected to the DC line through a port.

[0240] Example 5

[0241] This embodiment provides a DC power grid, including a modular multilevel converter (MMC) and a DC line, and also includes a second type of multi-terminal DC circuit breaker;

[0242] The second type of multi-terminal DC circuit breaker is connected to the same bus as the modular multilevel converter (MMC) and connected to the DC line through a port.

[0243] Example 6

[0244] This embodiment provides a DC power grid, including a modular multilevel converter (MMC) and a DC line, and also includes at least one first-type multi-terminal DC circuit breaker and at least one second-type multi-terminal DC circuit breaker.

[0245] A Class I multi-terminal DC circuit breaker is connected to the same bus as a modular multilevel converter (MMC) and connected to the DC line via a port.

[0246] A Class II multi-terminal DC circuit breaker is connected to the same bus as a modular multilevel converter (MMC) and connected to the DC line via a port.

[0247] Simulation verification

[0248] A four-terminal bipolar DC power grid is constructed using the PSCAD / EMTDC platform. The system wiring method is as follows: Figure 4 As shown (wherein, either the first or second type of multi-terminal DC circuit breaker can be arbitrarily selected at each converter station port without affecting the selection of multi-terminal DC circuit breakers at other converter station ports), the rated voltage of the DC grid is ±200kV. 15mH and 30mH current-limiting reactors are configured at the MMC outlet and the end of the DC line, respectively. The detailed model of the MMC is taken from the standard model provided by the Cigre working group, and the line adopts a frequency-dependent parameter model. The DC grid parameters are shown in Table 1. It should be noted that the parameters of the second type of multi-terminal DC circuit breaker also include a pre-charge capacitor C with a capacitance of 18uF, a pre-charge voltage U0 of 120kV, and an inductor L of 680uH.

[0249] Table 3 Main parameters of high voltage DC power grid

[0250] parameter Value Converter station power (MW) MMC1: -1000 MMC2: 1000MMC 3: 1000 MMC4: -1000 Length of overhead power lines (km) Line 1: 100 Line 2: 150 Line 3: 200 Line 4: 200 Line 5: 200 Bridge arm inductance Larm (mH) MMC 1:19 MMC 2:58 MMC 3:29 MMC 4:19 <![CDATA[Sub-module capacitance C0 (µF)]]> MMC1:75 MMC2:25MMC3:50 MMC4:75 <![CDATA[Arm resistance r0 (Ω)]]> MMC1: 0.18 MMC2: 0.18 MMC3: 0.27 MMC4: 0.55 <![CDATA[Current-limiting reactor L dc (mH)]]> 200 <![CDATA[Number of arm sub - modules n0]]> 200

[0251] At t0=0ms, a metallic fault occurs at the positive terminal of Line1. Figure 4 The following explanation uses a four-port multi-terminal DC circuit breaker connected to Station 1 as an example. Specific implementations of the two types of multi-terminal DC circuit breakers proposed in this invention are as follows:

[0252] (1) The simulation results of the first type of multi-terminal DC circuit breaker in mode 1 and mode 2 are shown below:

[0253] Mode 1 interruption process: After receiving the interrupt command at t1=2ms, the load switching switch LCS1 is turned off, and SU1 and MB1 are turned on, and the fault current begins to commutate from LCS1 to MB1. For example... Figure 5 As shown in (a), the current i of LCS1 LCS1 The current begins to decrease and reaches 0 at t2 = 2.1 ms. Subsequently, UFD1 begins arc-free interruption and completely interrupts at t3 = 4.1 ms, while MB1 turns off simultaneously. The current i in MB1... M1 The fault current immediately drops to 0, and the fault current is switched to surge arrester EA1. The current i in surge arrester EA1... E1 The value dropped to 0 at t4=11.76ms, indicating that the fault has been isolated.

[0254] Mode 2 interruption process: After receiving the interrupt command at t1=2ms, LCS2-LCS4 is immediately turned off and SD2-SD4 and MB2 are turned on. The fault current begins to commutate from LCS2-LCS4 to MB2. Once the current in UFD2-UFD4 drops to 0, UFD2-UFD4 will interrupt without arcing. Figure 6 As shown in (a), the currents of LCS2 and SD2 are denoted as i LCS2 and i SD2 The fault current at t 2b =2.1ms complete commutation to MB2. At t 3b At 4.1ms, UFD2-UFD4 are fully open, and MB2 is then turned off. Therefore, the current i in MB2... M2 The current suddenly drops to 0, and the fault current commutates to surge arrester EA2. The current i in surge arrester EA2... E2 In t 4b = dropped to 0 at 11.46ms, indicating that the fault has been isolated.

[0255] (2) The simulation results of the second type of multi-terminal DC circuit breaker in mode 1 and mode 3 are shown below:

[0256] Mode 1 interruption process: as follows Figure 7 As shown in (a), a fault was detected at t1=3ms, MS1 began arc-connected disconnection, and the current i of MS1... MS1 As the distance continues to increase, when t2 = 6ms, the contact gap of MS1 has reached a sufficient distance. At this time, SU1 and SSD1 are turned on, and the discharge capacitor C1 immediately discharges (the discharge current is denoted as i). C1 The current flows in the opposite direction through MS1. At t3 = 6.15 ms, i MS1 The fault current drops to 0, and MS1 recovers its insulation strength. The fault current is completely reversed to MB1, and then capacitor C1 is charged, and the fault current i 12 The current continues to increase, reaching its maximum value at t4 = 6.6 ms. When the capacitor is charged to the operating voltage of the surge arrester, the current commutates to the EA1 branch of the surge arrester, denoted as i. E1 At t6 = 17.8 ms, the surge arrester current drops to 0. For example... Figure 7 As shown in (b), after the fault is completely isolated, power continues to be transmitted between the non-faulty ports.

[0257] Mode 3 interruption process: such as Figure 8 As shown in (a), a fault was detected at t1=3ms, MS1 began arc-connected disconnection, and the current i of MS1... MS1 Continue to increase, at t 2b At 5ms, MS1 was detected as refusing to act, so MS1 was immediately shut down and arc-connected MS2-MS4 was initiated. When t 3b At 8ms, the contact gap between MS2 and MS4 reached a sufficient withstand voltage level, at which point SD2-SD4 and SSD2 were turned on. After this, the current i released by C2... C2 It flows through MS2-MS4 in the opposite direction to the fault current. In i MS2 -i MS4After crossing zero, MS2-MS4 completely disconnect and restore their insulation strength. At t 4b At 10.3ms, the fault current i 12 It reaches its maximum value. Simultaneously, the capacitor is charged to the operating voltage of the surge arrester, and the current commutates to the surge arrester branch EA2. The current in the surge arrester branch EA2 is denoted as i. E2 In t 5b At 25.1ms, i E2 It decreases to 0. For example... Figure 8 As shown in (b), after the fault is completely isolated, power continues to be transmitted between the non-faulty ports.

[0258] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A multi-terminal DC circuit breaker that satisfies the N-1 safety constraint, characterized in that, include: m ports, m main pass branches MC, 2 main disconnect branches MB, 2 energy absorption branches EA, m residual current switches RCB and 2m transfer branches TB; Port of multi-terminal DC circuit breaker i Used to connect to a DC line i i = 1, 2, ..., m; Residual current switch RCB i Used to isolate faulty lines after fault current is cleared; the left port serves as a port for a multi-terminal DC circuit breaker. i The right port is connected to the main branch MC. i The left port; Main branch MC i It is used to conduct system current under normal conditions, and the left port is connected to the residual current switch RCB. i The right ports of m main branches MC are connected to the same bus L. 2m transfer branches are used to transfer fault current, including m upper transfer branches SU and m lower transfer branches SD; Upward transfer branch SU i The cathode is connected to the residual current switch RCB i On the right port, the m upper transfer branches SU are connected using a common anode. Downward transfer branch SD i The anode is connected to the residual current switch RCB i On the right port, the m down transfer branches SD adopt a common cathode connection; The main interruption branch MB1 interrupts the fault current and transfers the fault current to the energy absorption branch EA1, one end of which is connected to the bus L and the other end is connected to the common anode of the transfer branch SU. The main interruption branch MB2 interrupts the fault current and transfers the fault current to the energy absorption branch EA2, one end of which is connected to the bus L and the other end is connected to the common cathode of the lower transfer branch SD. The energy-absorbing branch EA1 is used to absorb the energy of the fault current and is connected in parallel across the two ends of the main disconnection branch MB1. The energy-absorbing branch EA2 is used to absorb the energy of the fault current and is connected in parallel across the two ends of the main disconnect branch MB2.

2. The multi-terminal DC circuit breaker satisfying the N-1 safety constraint according to claim 1, characterized in that, Main branch MC i UFD (Ultra-fast Mechanical Switch) i and load commutation switch LCS i The load commutation switch is configured in series; it includes two fully controlled semiconductor devices connected in reverse series, and each fully controlled semiconductor device has a diode connected in reverse parallel. Both the main disconnection branch MB1 and the main disconnection branch MB2 use fully controlled semiconductor devices; Both energy-absorbing branches EA1 and EA2 are equipped with surge arresters; Upward transfer branch SU i and the down transfer branch SD i All of them use semi-controlled semiconductor devices.

3. The multi-terminal DC circuit breaker satisfying the N-1 safety constraint according to claim 1, characterized in that, Main branch MC i Mechanical switch MS i ; The main disconnect branch MB1 includes a pre-charge capacitor C1, an inductor L1, and a semi-controlled semiconductor device SSD1. The anodes of the pre-charge capacitor C1, the inductor L1, and the semi-controlled semiconductor device SSD1 are connected in series. The unconnected end of the pre-charge capacitor C1 is connected to the bus L, and the cathode of SSD1 is connected to the common anode of the transfer branch SU. The main disconnect branch MB2 includes a pre-charge capacitor C2, an inductor L2, and a semi-controlled semiconductor device SSD2. The anodes of the pre-charge capacitor C2, the inductor L2, and the semi-controlled semiconductor device SSD2 are connected in series. The unconnected end of the pre-charge capacitor C2 is connected to the common cathode of the lower transfer branch SD, and the cathode of SSD2 is connected to the bus L. Both energy-absorbing branches EA1 and EA2 are equipped with surge arresters; Upward transfer branch SU i and the down transfer branch SD i All of them use semi-controlled semiconductor devices.

4. The multi-terminal DC circuit breaker satisfying the N-1 safety constraint according to claim 2 or 3, characterized in that, Semi-controlled semiconductor devices use, but are not limited to, thyristors and bidirectional thyristors; fully controlled semiconductor devices use, but are not limited to, insulated gate bipolar transistors (IGBTs) and gate turn-off thyristors (GTOs).

5. The multi-terminal DC circuit breaker satisfying the N-1 safety constraint according to claim 4, characterized in that, The rated current of semi-controlled and fully controlled semiconductor devices is designed based on the maximum current under the most severe fault and an appropriate current margin is set. The rated voltage is designed based on the maximum voltage that it can withstand under fault and an appropriate voltage margin is set. The rated voltage of surge arresters is selected as 1.5 times the system voltage of the DC power grid where the multi-terminal DC circuit breaker is located.

6. A control method for a multi-terminal DC circuit breaker satisfying the N-1 safety constraint as described in claim 2, characterized in that, In relation to port i Connected DC line i When a single-pole ground fault occurs, the multi-terminal DC circuit breaker operates in the following three modes: Mode 1: No device failure; SU i SD x MC y Or MB2 short circuit; SU y SD x MC x Or MB2 can be used as a roadblock; Mode 2: SU y MC i Or MB1 short circuit; SU i Or MB1 open circuit; Mode 3: UFD i Refusal to move; Where x is 1, 2, ..., m; y is 1, 2, ..., i-1, i+1, i+2, ..., m; In Mode 1, the control method for multi-terminal DC circuit breakers is as follows: After the multi-terminal DC circuit breaker receives the opening command from the protection device, the upper transfer branch SU is connected. i Connect the main branch MB1 and close the faulty port. i Load commutation switch LCS i ; When flowing through the main branch MC i Chinese Super League High-Speed ​​Mechanical Switch UFD i When the fault current drops to 0, the ultra-fast mechanical switch UFD is disconnected. i Achieve arc-free segmentation; When ultra-fast mechanical switch UFD i After the contacts are completely separated, the main disconnection branch MB1 is closed, and the fault current is transferred to the energy-absorbing branch EA1 connected in parallel with the main disconnection branch MB1. The energy-absorbing branch EA1 absorbs the fault current energy, causing the fault current to decrease. When the fault current drops to 0, open the port. i Residual current switch RCB i , transfer the faulty line i Completely isolated from the system, while power exchange continues between non-faulty ports; In Mode 2, the control method for multi-terminal DC circuit breakers is as follows: After the multi-terminal DC circuit breaker receives the opening command from the protection device, the lower transfer branch SD is connected. y And disconnect the main branch MB2, and shut down the load commutation switch LCS on the non-faulty port. y ; When the flow passes through the non-faulty port, the ultra-fast mechanical switch UFD y When the fault current drops to 0, the ultra-fast mechanical switch UFD is disconnected. y Achieve arc-free segmentation; When waiting for ultra-fast mechanical switch UFD y After all the contacts are completely separated, the main circuit breaker MB2 is turned off, and the fault current is transferred to the energy-absorbing branch EA2 connected in parallel with the main circuit breaker MB2. The energy-absorbing branch EA2 absorbs the fault current energy, causing the fault current to decrease. When the fault current drops to 0, open the port. i Residual current switch RCB i This completely isolates the faulty port from the system. When port i Residual current switch RCB i When fully open, the ultra-fast mechanical switch (UFD) connects the non-faulty ports. y and load commutation switch LCS y Power exchange continues between non-faulty branches; In Mode 3, the control method for multi-terminal DC circuit breakers is as follows: After the multi-terminal DC circuit breaker receives the opening command from the protection device, the upper transfer branch SU is connected. i Connect the main branch MB1 and close the faulty port. i Load commutation switch LCS i ; When flowing through the main branch MC i Chinese Super League High-Speed ​​Mechanical Switch UFD i When the fault current drops to 0, the ultra-fast mechanical switch (UFD) i Unable to perform segmentation; If an ultra-fast mechanical switch (UFD) that should have disconnected is detected... i If a failure to operate occurs, the downstream transfer branch SD connected to the non-faulty port will be activated. y And the main branch MB2, shutting off the load commutation switch LCS on the non-faulty port. y ; When the ultra-fast mechanical switch UFD flows through the non-faulty port y When the fault current drops to 0, the ultra-fast mechanical switch UFD on the non-faulty port is disconnected. y Achieve arc-free segmentation; When the non-faulty port of the ultra-fast mechanical switch UFD y After the contacts are completely separated, the main circuit MB2 is closed; When the fault current drops to 0, the residual current switch RCB at port i is opened. i This completely isolates the faulty port from the system. When the residual current switch RCB at port i i When fully open, the ultra-fast mechanical switch (UFD) connects the non-faulty ports. y and load commutation switch LCS y Power exchange continues between non-faulty branches.

7. A control method for a multi-terminal DC circuit breaker satisfying the N-1 safety constraint as described in claim 3, characterized in that, In relation to port i Connected DC line i When a single-pole ground fault occurs, the multi-terminal DC circuit breaker operates in the following three modes: Mode 1: No device failure; SU i SD x MS y MB2 or EA2 short circuit; SU y SD x MS y MB2 or EA2 open circuit; Mode 2: SU y MS i MB1 or EA1 short circuit; SU i MB1 or EA1 open circuit; Mode 3: MS i Refusal to move; Where x is 1, 2, ..., m; y is 1, 2, ..., i-1, i+1, i+2, ..., m; In Mode 1, the control method for multi-terminal DC circuit breakers is as follows: After the multi-terminal DC circuit breaker receives the opening command from the protection device, the arc-operated mechanical switch branch MS... i ; When the mechanical switch branch MS i After the contacts separate to a sufficient insulation gap, the upper transfer branch SU is turned on. i and semi-controlled semiconductor device SSD1; The pre-charge capacitor C1 immediately discharges along the following path: C1-L1-SSD1-SU i -MS i -C1, flows through the mechanical switch branch MS i The fault current is transferred to the main disconnect branch MB1 and begins to reverse charge the pre-charge capacitor C1. When the voltage of the pre-charge capacitor C1 reaches the set value U0, the semi-controlled semiconductor device SSD1 is naturally turned off, and the fault current begins to decrease. When the fault current drops to 0, the residual current switch RCB is opened. i This completely isolates the faulty line from the system, while allowing power exchange to continue between the non-faulty ports. In Mode 2, the control method for multi-terminal DC circuit breakers is as follows: After the multi-terminal DC circuit breaker receives the opening command from the protection device, the mechanical switch branch MS, which is connected to the non-faulty line by arc tripping,... y ; When the mechanical switch branch MS y After the contacts separate to a sufficient insulation gap, the lower transfer branch SD is turned on. y and semi-controlled semiconductor device SSD2; Immediate edge path of pre-charge capacitor C2: C2-L2-SSD2-MS y -SD y -C2 discharges, flowing through the mechanical switch branch MS. y The fault current is transferred to the main disconnect branch MB2 and begins to reverse charge the pre-charge capacitor C2. When the voltage of the pre-charge capacitor C2 reaches the set value U0, the semi-controlled semiconductor device SSD2 is turned off naturally, and the fault current begins to decrease. When the fault current drops to 0, first open the mechanical switch branch MS. i Then turn on the residual current switch RCB. i Semi-controlled semiconductor devices SD y Natural shutdown, shutting down the faulty port. i Completely isolate the system, and then close the mechanical switch branch MS on the non-faulty port. y Power exchange continues between non-faulty ports; In Mode 3, the control method for multi-terminal DC circuit breakers is as follows: After a multi-terminal DC circuit breaker receives an opening command from the protection device, if it detects that the mechanical switch branch MS, which should have performed arc-assisted tripping, is... i If a failure to operate occurs, the mechanical switch branch MS connected to the non-faulty line will trip with arcing. y ; When the mechanical switch branch MS y After the contacts separate to a sufficient insulation gap, the lower transfer branch SD is turned on. y And the pre-charge capacitor C2 of the semi-controlled semiconductor device SSD2 immediately follows the path C2-L2-SSD2-MS y -SD y -C2 discharges, flowing through the mechanical switch branch MS. y The fault current is transferred to the main disconnect branch MB2 and begins to reverse charge the pre-charge capacitor C2. When the voltage of the pre-charge capacitor C2 reaches the set value U0, the semi-controlled semiconductor device SSD2 is turned off naturally, and the fault current begins to decrease. When the fault current drops to 0, open the mechanical switch branch MS. i and residual current switch RCB i Semi-controlled semiconductor devices SD y Natural shutdown, shutting down the faulty port. i Completely isolated from the system, port i After completely isolating the system, close the mechanical switch branch MS on the non-faulty port. y Power exchange continues between non-faulty ports.

8. The control method for a multi-terminal DC circuit breaker satisfying the N-1 safety constraint according to claim 7, characterized in that, In the main disconnection branch MB1 and the main disconnection branch MB2, the pre-charge capacitors C1 and C2 are both C, the inductors L1 and L2 are both L, and the pre-charge voltage of the pre-charge capacitors C1 and C2 is U0. The selection principles for C, L, and U0 are as follows: The discharge current of the pre-charge capacitor C1 or C2 during the period from t2 to t3 is: (1) The discharge current i of the pre-charge capacitor C1 or C2 c The maximum value and the maximum rate of change of current are respectively: and i c The maximum value is greater than the maximum fault current; time t2 is the time when the multi-terminal DC circuit breaker receives the opening command from the protection device; time t3 is the time when the contacts of the mechanical switch branch that performs arc tripping separate to a sufficient insulation gap. U0, L, and C should satisfy the constraints in (2): (2) In the formula, M1, M2, and M3 are safety margins, and all are greater than 1; I max This represents the maximum value of the fault current; (di / dt) max Let di / dt be the maximum rate of change of current that the mechanical switch branch can withstand; (du / dt) max Du / dt is the maximum rate of voltage change that the mechanical switch branch can withstand.

9. A DC power grid, comprising a modular multilevel converter (MMC) and a DC line, characterized in that, It also includes the multi-terminal DC circuit breaker that satisfies the N-1 safety constraint as described in claim 2 and / or claim 3; The multi-terminal DC circuit breaker that meets the N-1 safety constraint is connected to the same bus as the modular multilevel converter (MMC) and connected to the DC line through a port.

10. A DC power grid control method, characterized in that, The DC power grid includes a modular multilevel converter (MMC) and a DC line, and also includes a multi-terminal DC circuit breaker that satisfies the N-1 safety constraint as described in claim 2 and / or claim 3. The multi-terminal DC circuit breaker that meets the N-1 safety constraint is connected to the same bus as the modular multilevel converter (MMC) and connected to the DC line through the port. When controlling the multi-terminal DC circuit breaker that satisfies the N-1 safety constraint as described in claim 2, the control method described in claim 6 shall be used; When controlling the multi-terminal DC circuit breaker that satisfies the N-1 safety constraint as described in claim 3, the control method described in claim 7 or 8 shall be used.

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