Boost circuit system bandwidth optimization method and boost circuit system
By detecting changes in duty cycle and modulating the gain of the compensation loop, the bandwidth of the Boost circuit system is optimized, solving the problem of slow response speed under high duty cycle and improving the dynamic performance and stability of the system under high duty cycle.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN KIWI MICROELECTRONICS CO LTD
- Filing Date
- 2026-01-20
- Publication Date
- 2026-05-15
AI Technical Summary
Existing Boost peak control constant current systems have slow response speed and poor dynamic performance at high duty cycles, and cannot meet the system phase margin requirements.
By detecting changes in duty cycle, the gain of the compensation loop is modulated to adjust the system bandwidth, increase the system crossover frequency, and reduce the phase margin, thereby optimizing the system's dynamic performance and stability.
While ensuring system stability, it improves system response speed and bandwidth, and increases the signal transmission frequency range.
Smart Images
Figure CN122052525A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic information, and in particular to a method for optimizing bandwidth in a boost circuit system and a boost circuit system. Background Technology
[0002] Existing solutions design Boost peak control constant current systems based on the compensation loop required at the minimum duty cycle. (See attached diagram) Figure 1 The Boost peak control constant current system and its attachments are shown. Figure 2 The small-signal model shown is known to be calculated as follows:
[0003] The system compensation loop is as follows:
[0004]
[0005] Duty cycle modulation is:
[0006]
[0007] The transfer function from duty cycle to inductor current in a Boost system is:
[0008]
[0009] The transfer function for inductor current sampling is:
[0010]
[0011] The transfer function from inductor current to output current is:
[0012]
[0013] The system open-loop transfer function is:
[0014]
[0015] The loop can be approximated at low frequencies as follows:
[0016]
[0017] The expression for the amplitude-frequency response curve is:
[0018] The phase frequency response curve is expressed as follows: , where ω = 2πf;
[0019] Its Bode diagram is attached. Figure 3 As shown:
[0020] ;
[0021] When the Rc and Cc parameters are set such that ω1 = ω4,
[0022] ;
[0023] Typically, a stable system requires a phase margin of 180° + ψ(ωc) greater than 45°. Therefore, as calculated above, when other parameters remain constant, a larger D value corresponds to a larger system phase margin. Thus, when designing a compensation loop, it's necessary to design it based on the minimum D value to meet the system phase margin requirement, meaning the loop parameters should be designed according to the minimum duty cycle. However, such loop parameters are relatively slow at high duty cycles, ultimately leading to slower response speeds and poor dynamic performance. Summary of the Invention
[0024] This invention addresses the shortcomings of existing technologies by providing a method for optimizing bandwidth in a boost circuit system and a boost circuit system.
[0025] To address the aforementioned technical problems, this invention provides a method for optimizing the bandwidth of a boost circuit system, comprising: acquiring an input signal (Vin), processing it through a system signal, and outputting an output signal (Vo); during the system signal processing, detecting the system's duty cycle, and modulating the compensation loop gain under different duty cycles to adjust the system bandwidth; modulating the compensation loop gain includes: when the duty cycle is detected to be gradually increasing, increasing the compensation loop gain to improve the system crossover frequency and reduce the system phase margin, thereby improving the system response speed; when the duty cycle is detected to be gradually decreasing, decreasing the compensation loop gain to reduce the system crossover frequency and increase the system phase margin, thereby improving system stability.
[0026] Optionally, when the duty cycle is detected to be gradually increasing, when the duty cycle is detected to be less than the first duty cycle, the compensation loop gain is maintained at the first gain; when the duty cycle is detected to be greater than the first duty cycle and less than the third duty cycle, the compensation loop gain is increased; when the duty cycle is detected to be greater than the third duty cycle, the compensation loop gain is increased to the third gain and maintained; the third duty cycle is greater than the first duty cycle, and the third gain is greater than the first gain.
[0027] Optionally, when the duty cycle is detected to be gradually decreasing, when the duty cycle is detected to be greater than the third duty cycle, the compensation loop gain is maintained at the third gain; when the duty cycle is detected to be less than the third duty cycle but greater than the first duty cycle, the compensation loop gain is reduced; when the duty cycle is detected to be less than the first duty cycle, the compensation loop gain is reduced to the first gain and maintained.
[0028] Optionally, the bandwidth adjustment is continuous, and the compensation loop gain changes continuously with the duty cycle.
[0029] Optionally, the bandwidth adjustment is segmented, and the compensation loop gain varies segmentally with the duty cycle.
[0030] Optionally, when it is detected that the duty cycle is gradually increasing, and when it is detected that the duty cycle is greater than the first duty cycle and less than the third duty cycle, the process of increasing the compensation loop gain includes: when the duty cycle is greater than the first duty cycle and less than the second duty cycle, the compensation loop gain is maintained at the first gain; when it is detected that the duty cycle increases to the second duty cycle, the compensation loop gain is increased to the second gain; when the duty cycle is greater than the second duty cycle and less than the third duty cycle, the compensation loop gain is maintained at the second gain; when it is detected that the duty cycle increases to the third duty cycle, the compensation loop gain is increased to the third gain; the second duty cycle is greater than the first duty cycle and less than the third duty cycle; the second gain is greater than the first gain and less than the third gain.
[0031] Optionally, when it is detected that the duty cycle is gradually decreasing, and when it is detected that the duty cycle is less than the third duty cycle and greater than the first duty cycle, the process of reducing the compensation loop gain includes: when the duty cycle is less than the third duty cycle and greater than the second duty cycle, the compensation loop gain is maintained at the third gain; when it is detected that the duty cycle decreases to the second duty cycle, the compensation loop gain is reduced to the second gain; when the duty cycle is less than the second duty cycle and greater than the first duty cycle, the compensation loop gain is maintained at the second gain; when it is detected that the duty cycle decreases to the first duty cycle, the compensation loop gain is reduced to the first gain.
[0032] Optionally, the second gain is twice the first gain, and the third gain is four times the first gain.
[0033] Optionally, the first duty cycle is 55%, the second duty cycle is 65%, and the third duty cycle is 75%.
[0034] Optionally, the gating signal is detected, and the duty cycle is calculated by the proportion of the high-level time of the gating signal within the period.
[0035] Optionally, the input signal (Vin) and the output signal (Vo) are detected. The duty cycle (D) is calculated by the input signal (Vin) and the output signal (Vo) through a relationship with the duty cycle (D), which is: Vo / Vin=1 / (1-D).
[0036] This invention also provides a boost circuit system that uses the aforementioned circuit system bandwidth optimization method to modulate the system bandwidth. It includes an output unit, an input unit, a feedback unit, and a signal transmission processing module. The signal transmission processing module includes a compensation loop unit, a duty cycle detection unit, a frequency modulation unit, and a gain modulation unit. The input unit is used to acquire an input signal and is coupled to the signal transmission processing module to transmit the input signal. The output unit is used to output an output signal and is coupled to the signal transmission processing module. The input signal is processed by the signal transmission processing module and then output through the output unit. The feedback unit is coupled to the output unit and also coupled to the compensation loop unit. The feedback unit is used to feed the output signal back to the compensation loop unit. The compensation loop unit processes the feedback output signal and the reference signal to output an adjustment signal. In the signal transmission processing module, the compensation loop unit is also coupled to the frequency modulation unit and transmits the adjustment signal to the frequency modulation unit. The frequency modulation unit is used to adjust the inductor current peak value and switching frequency during signal transmission according to the adjustment signal. Different inductor current peak values and switching frequencies represent different current system operating states. The duty cycle detection unit is used to detect and obtain the current system operating duty cycle according to the current system operating state. The gain modulation unit is coupled to the duty cycle detection unit and obtains the duty cycle. The gain modulation unit is also coupled to the compensation loop unit and adjusts the compensation loop gain in the compensation loop unit according to the duty cycle.
[0037] This invention modulates the compensation loop gain according to the change of duty cycle, which can optimize dynamic performance while ensuring the system phase margin is met. It can also ensure stable operation of the system when the system loop speed increases, and can improve system stability without slowing down the system loop speed. As a result, the frequency range of the system that can effectively transmit signals is increased and the system bandwidth is improved.
[0038] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0039] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:
[0040] Figure 1 This is a circuit diagram of a Boost peak control constant current system.
[0041] Figure 2 A schematic diagram of the small-signal model of a Boost peak control constant current system;
[0042] Figure 3 Bode plot of a Boost peak control constant current system;
[0043] Figure 4 This is a schematic diagram of the gain modulation variation using segmented adjustment in a bandwidth optimization method for a boost circuit system according to an embodiment of the present invention.
[0044] Figure 5 This is a schematic diagram of the bandwidth modulation using continuously adjusted gain modulation in a bandwidth optimization method for a boost circuit system according to an embodiment of the present invention.
[0045] Figure 6 This is a schematic diagram of the boost circuit system according to an embodiment of the present invention. Detailed Implementation
[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0047] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.
[0048] In this invention, based on the appendix Figure 1 and attached Figure 2 The analysis of the Boost peak control constant current system and its small-signal model diagram shows the following relationship between the system crossover frequency ωc and the compensation loop gain gm and duty cycle D:
[0049]
[0050] Based on the appendix Figure 3 As can be seen from the Bode plot, when other parameters remain constant, the larger the duty cycle D, the smaller the system crossover frequency ωc, and the larger the system phase margin PM = 180° + ψ(ωc). Therefore, by increasing the compensation loop gain gm, the system crossover frequency ωc can be increased, thereby accelerating the system loop speed.
[0051] This invention discloses a method for optimizing the bandwidth of a boost circuit system and a boost circuit system. By detecting the duty cycle and modulating the compensation loop gain, the system bandwidth is improved, which can optimize the dynamic performance of the system when operating at a high duty cycle, while ensuring the system stability throughout the entire duty cycle range.
[0052] Specifically, this invention discloses a bandwidth optimization method for a boost circuit system. The bandwidth adjustment employs segmented adjustment, with the compensation loop gain gm varying segmentally with the duty cycle D. First, under normal operating conditions, the circuit system needs to acquire an input signal and output an output signal after signal transmission processing. Therefore, during signal transmission, the method of bandwidth modulation in this invention includes:
[0053] Step S11: Detect the duty cycle D of the system. In this embodiment, the duty cycle D is obtained through gate detection, that is, by calculating the duty cycle D based on the periodic state of the gate signal (i.e., the proportion of high-level time within the period). In other embodiments, the duty cycle D can also be obtained by detecting the proportion of the input signal (Vin) and the output signal (Vo) within the working cycle, that is, by calculating the duty cycle D using the proportion relationship Vo / Vin=1 / (1-D). In other embodiments, the system duty cycle D can also be obtained using other conventional methods known to those skilled in the art.
[0054] Step S12: When the duty cycle D is detected to be gradually increasing, increase the compensation loop gain gm to appropriately increase the system crossover frequency ωc during signal transmission and appropriately decrease the system phase margin PM. Specifically, when the duty cycle D is detected to be gradually increasing, the system crossover frequency ωc will decrease without changing other parameters. Since the system phase margin PM = 180° + ψ(ωc), the system phase margin PM will increase. A stable system generally requires its system phase margin PM to be greater than the first phase margin. Therefore, as long as the system phase margin PM is greater than the first phase margin under the initial duty cycle D, the system phase margin PM will always meet the requirement of being greater than the first phase margin as the duty cycle D increases. Thus, in this step, there is room for the system phase margin PM to decrease, and the system crossover frequency ωc also has room to increase, thereby providing space for optimizing the system's dynamic performance.
[0055] Specifically, when the duty cycle D is detected to be gradually increasing, the compensation loop gain gm is increased, including the following cases:
[0056] In the first scenario, when the impact of increasing the duty cycle D outweighs the impact of increasing the compensation loop gain gm, the system crossover frequency ωc continues to decrease, but the magnitude of the decrease is smaller, and the system phase margin PM continues to increase, but the magnitude of the increase is smaller. At this time, because the magnitude of the decrease in the system crossover frequency ωc is smaller, the degree of slowdown in the system loop speed is also reduced, thus maintaining the dynamic performance of the system and preventing the system loop speed from decreasing too quickly. Meanwhile, the increase in the system phase margin PM ensures that the system is more stable during operation.
[0057] The second scenario is that when the effect of increasing the duty cycle D is less than the effect of increasing the compensation loop gain gm, the system crossover frequency ωc begins to increase, and the system phase margin PM begins to decrease. Although the system phase margin PM begins to decrease, as long as it is controlled to never be less than the first phase margin, the system can still work stably. At this time, because the system crossover frequency ωc increases, the system loop speed increases, ultimately ensuring that the system phase margin is met while optimizing dynamic performance.
[0058] In this embodiment, the value of the first phase margin is 45°. Generally, a stable system requires a system phase margin PM greater than 45°. However, in other embodiments, due to the influence of various factors such as circuit design structure, parameters, and environment, the specific value of the first phase margin may be other values depending on the actual situation and requirements of the circuit design.
[0059] In step S12, the appendix Figure 4 This is a schematic diagram illustrating the gain modulation variation in a bandwidth optimization method for a boost circuit system according to the present invention. The bandwidth adjustment employs segmented adjustment, with the compensation loop gain gm varying segmentally with the duty cycle D. When a gradual increase in the duty cycle D is detected, and when the duty cycle D is detected to be greater than the first duty cycle and less than the third duty cycle, the variation of the compensation loop gain gm is as shown in the attached diagram. Figure 4 As shown:
[0060] Step S121: When the duty cycle D is detected to be greater than the first duty cycle and less than the second duty cycle, the compensation loop gain gm is maintained at the first gain;
[0061] Step S122: When the duty cycle D is detected to increase to the second duty cycle, increase the compensation loop gain gm to the second gain;
[0062] Step S123: When the duty cycle D is detected to be greater than the second duty cycle and less than the third duty cycle, the compensation loop gain gm is maintained at the second gain;
[0063] Step S124: When the duty cycle D is detected to rise to the third duty cycle, increase the compensation loop gain gm to the third gain. When the duty cycle D is detected to be greater than the third duty cycle, the compensation loop gain gm remains at the third gain.
[0064] Step S13: When the duty cycle D is detected to be gradually decreasing, reduce the compensation loop gain gm to appropriately reduce the system crossover frequency ωc during signal transmission and appropriately increase the system phase margin PM. Specifically, when the duty cycle D is detected to be gradually decreasing, the system crossover frequency ωc will increase, and the system loop speed will increase. Since the system phase margin PM = 180° + ψ(ωc), the system phase margin PM will decrease. A stable system generally requires its system phase margin PM to be greater than the first phase margin. Therefore, it is necessary to ensure that the system phase margin PM always meets the requirement of being greater than the first phase margin as the duty cycle D decreases.
[0065] When the duty cycle D is detected to be gradually decreasing, the reduction of the compensation loop gain gm includes the following situations:
[0066] In the first scenario, when the impact of decreasing the duty cycle D outweighs the impact of decreasing the compensation loop gain gm, the system crossover frequency ωc continues to increase, but at a smaller rate. The system phase margin PM also continues to decrease, but at a smaller rate. In this case, as long as the system control phase margin PM is not less than the first phase margin, the system can still operate stably. Therefore, although the duty cycle D decreases, the system phase margin PM does not rapidly decrease to the first phase margin, and the system remains stable. Simultaneously, the increase in the system crossover frequency ωc accelerates the system loop speed, optimizing the system's dynamic performance. In this embodiment, the first phase margin value is 45°, but in other embodiments, the specific value of the first phase margin can be other values depending on the actual situation and requirements of the circuit design.
[0067] The second scenario is that when the effect of decreasing the duty cycle D is less than the effect of decreasing the compensation loop gain gm, the increase in the system crossover frequency ωc is suppressed and actually decreases, and the decrease in the system phase margin PM is suppressed and begins to increase. It is known that in a circuit system, the larger the system phase margin PM, the more stable the system can be under any load conditions, thus improving the system's stability.
[0068] In other embodiments, based on the circuit system design requirements and operational requirements of the embodiment, when the duty cycle D is detected to be gradually decreasing, by controlling the compensation loop gain gm to decrease to a suitable value, the stability of the system can be improved while ensuring the required dynamic performance conditions (i.e., the system loop speed is reduced but still meets the requirements), and the system can work stably under a wider range of load conditions.
[0069] In step S13, when the duty cycle D is detected to be gradually decreasing, hysteresis is started. When the duty cycle D is detected to be less than the third duty cycle but greater than the first duty cycle, the compensation loop gain gm is reduced. The specific change method of the compensation loop gain gm is shown in the attached figure. Figure 4 As shown:
[0070] Step S131: When the duty cycle D is less than the third duty cycle but greater than the second duty cycle, the compensation loop gain gm remains at the third gain;
[0071] Step S132: When the duty cycle D is detected to decrease to the second duty cycle, reduce the compensation loop gain gm to the second gain;
[0072] Step S133: When the duty cycle D is less than the second duty cycle and greater than the first duty cycle, the compensation loop gain gm remains at the second gain.
[0073] Step S134: When the duty cycle D is detected to have decreased to the first duty cycle, the compensation loop gain gm is reduced to the first gain. When the duty cycle D is detected to be less than the first duty cycle, the compensation loop gain gm is kept at the first gain; this can prevent the unstable situation of the compensation loop gain gm changing back and forth at the switching point when the duty cycle D changes.
[0074] In this embodiment, the third duty cycle is greater than the second duty cycle, the second duty cycle is greater than the first duty cycle, the second gain is greater than the first gain, and the third gain is greater than the second gain. Specifically, in this embodiment, the first duty cycle is 55%, the second duty cycle is 65%, the third duty cycle is 75%, the first gain is gm, the second gain is 2gm, and the third gain is 4gm. In other embodiments, depending on the design and operational requirements of the system circuit, other values for the first duty cycle, second duty cycle, third duty cycle, first gain, second gain, and third gain can be used.
[0075] This invention also discloses another method for optimizing the bandwidth of a boost circuit system, wherein the bandwidth adjustment is continuously adjusted and the compensation loop gain gm changes continuously with the duty cycle.
[0076] Step S21: Detect the duty cycle D of the system.
[0077] Step S22: When the duty cycle D is detected to be gradually increasing, increase the compensation loop gain gm to appropriately increase the system crossover frequency ωc during signal transmission and appropriately decrease the system phase margin PM.
[0078] In step S22, append Figure 5 This is a schematic diagram illustrating the gain modulation variation in a bandwidth optimization method for a boost circuit system according to the present invention. The bandwidth adjustment is continuous. When a gradual increase in the duty cycle D is detected, the change in the compensation loop gain gm is shown in the attached diagram. Figure 5 As shown:
[0079] Step S221: When the duty cycle D is detected to be less than the first duty cycle, the compensation loop gain gm is maintained at the first gain;
[0080] Step S222: When the duty cycle D is detected to be greater than the first duty cycle and less than the third duty cycle, increase the compensation loop gain gm;
[0081] Step S223: When the duty cycle D is detected to be greater than the third duty cycle, the compensation loop gain is increased to the third gain and maintained;
[0082] Step S23: When the duty cycle D is detected to be gradually decreasing, reduce the compensation loop gain gm to appropriately reduce the system crossover frequency ωc during signal transmission and appropriately increase the system phase margin PM.
[0083] In step S23, when the duty cycle D is detected to be gradually decreasing, hysteresis is started. When the duty cycle D is detected to be less than the third duty cycle but greater than the first duty cycle, the compensation loop gain gm is reduced. The specific change method of the compensation loop gain gm is shown in the attached figure. Figure 5 As shown:
[0084] Step S231: When the duty cycle D is detected to be greater than the third duty cycle, the compensation loop gain gm is maintained at the third gain;
[0085] Step S232: When the duty cycle D is detected to be less than the third duty cycle and greater than the first duty cycle, reduce the compensation loop gain gm;
[0086] Step S233: When the duty cycle is detected to be less than the first duty cycle, the compensation loop gain gm is reduced to the first gain and maintained.
[0087] In this embodiment, the third duty cycle is greater than the first duty cycle, the second gain is greater than the first gain, and the third gain is greater than the second gain. Specifically, in this embodiment, the first duty cycle is 55%, the second duty cycle is 65%, the third duty cycle is 75%, the first gain is gm, the second gain is 2gm, and the third gain is 4gm. In other embodiments, depending on the design and operational requirements of the system circuit, other values for the first duty cycle, second duty cycle, third duty cycle, first gain, second gain, and third gain can be used.
[0088] This invention also discloses a boost circuit system, which improves system bandwidth through the aforementioned boost circuit system bandwidth optimization method, as shown in the appendix. Figure 6As shown, the system specifically includes an output unit 300, an input unit 100, a feedback unit 400, and a signal transmission and processing module 200. The signal transmission and processing module 200 includes a compensation loop unit 201, a duty cycle detection unit 203, a frequency modulation unit 204, and a gain modulation unit 202. The signal transmission and processing module 200 processes the input signal through its internal circuit structure and then transmits it to the output unit 300, which ultimately outputs the output signal. It should be understood that the signal transmission and processing module 200 of the boost circuit system should have internal switching elements, and the signal transmission is controlled by the on and off states of these switching elements. The ratio of the on-time of the switching element to the entire cycle is the system's duty cycle D.
[0089] In one embodiment, the input unit 100 is used to acquire an input signal and is coupled to the signal transmission processing module 200 to transmit the input signal. The output unit 300 is used to output an output signal and is coupled to the signal transmission processing module 200. The input signal is processed by the signal transmission processing module 200 and then output through the output unit 300.
[0090] In one embodiment, the feedback unit 400 is coupled to the output unit 300 and is also coupled to the compensation loop unit 201. The feedback unit 400 is used to feed back the output signal to the compensation loop unit 201. The compensation loop unit 201 processes the feedback output signal and the reference signal and then outputs an adjustment signal.
[0091] In one embodiment, the signal transmission processing module 200 includes:
[0092] The compensation loop unit 201 is also coupled to the frequency modulation unit 204 and transmits the adjustment signal to the frequency modulation unit 204. The frequency modulation unit 204 is used to adjust the peak value of the inductor current and the switching frequency during signal transmission according to the adjustment signal. Different peak values of the inductor current and the switching frequency represent different operating states of the current system.
[0093] The duty cycle detection unit 203 is used to detect and obtain the current system duty cycle D based on the current system operating state. In this embodiment, the duty cycle D is obtained through gate detection, that is, by detecting the gated PWM signal and calculating the duty cycle D based on the ratio between the high-level time of the gated PWM signal and the period time. In other embodiments, the duty cycle detection unit 203 can also calculate the duty cycle D based on the ratio of the input signal (Vin) to the output signal (Vo) within the working cycle (Vo / Vin=1 / (1-D)).
[0094] The gain modulation unit 202 is coupled to the duty cycle detection unit 203 to obtain the duty cycle. The gain modulation unit 202 is also coupled to the compensation loop unit 201 and adjusts the compensation loop gain gm in the compensation loop unit 201 according to the duty cycle D.
[0095] In this embodiment, the duty cycle detection unit 203 detects the duty cycle D, and modulates the compensation loop gain gm when a change in duty cycle D is detected. Since the system crossover frequency ωc is positively correlated with the compensation loop gain gm (see attached figure), Figure 3 From the Bode plot and the aforementioned formula for calculating the system crossover frequency ωc, it can be seen that the system phase margin PM is inversely correlated with the compensation loop gain gm (as shown in the appendix). Figure 3 From the Bode plot and the formula for system phase margin PM=180°+ψ(ωc), it can be seen that the modulation compensation loop gain gm changes with the duty cycle D. This can optimize dynamic performance while ensuring the system phase margin is met. It can also ensure stable system operation when the system loop speed increases. It can improve system stability while maintaining a fast system loop speed. As a result, the frequency range of the system that can effectively transmit signals increases, and the system bandwidth is improved.
[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
[0097] In summary, the above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the present invention.
Claims
1. A method for optimizing the bandwidth of a boost circuit system, characterized in that, include: The system acquires the input signal (Vin), processes it through signal processing, and then outputs the output signal (Vo). During system signal processing, the system duty cycle is detected, and the compensation loop gain is modulated under different duty cycles to adjust the system bandwidth. Modulating the gain of the compensation loop includes, When the duty cycle is detected to be gradually increasing, the compensation loop gain is increased to improve the system crossover frequency and reduce the system phase margin, thereby improving the system response speed. When the duty cycle is detected to be gradually decreasing, the gain of the compensation loop is reduced to lower the system crossover frequency and increase the system phase margin, thereby improving system stability.
2. The bandwidth optimization method for boost circuit systems according to claim 1, characterized in that, When it is detected that the duty cycle is gradually increasing When the duty cycle is detected to be less than the first duty cycle, the compensation loop gain remains at the first gain; When the duty cycle is detected to be greater than the first duty cycle and less than the third duty cycle, the gain of the compensation loop is increased; When the duty cycle is detected to be greater than the third duty cycle, the compensation loop gain is increased to the third gain and maintained. The third duty cycle is greater than the first duty cycle, and the third gain is greater than the first gain.
3. The bandwidth optimization method for boost circuit systems according to claim 2, characterized in that, When the duty cycle is detected to be gradually decreasing When the duty cycle is detected to be greater than the third duty cycle, the compensation loop gain is maintained at the third gain; When the duty cycle is detected to be less than the third duty cycle but greater than the first duty cycle, the gain of the compensation loop is reduced. When the duty cycle is detected to be less than the first duty cycle, the compensation loop gain is reduced to the first gain and maintained.
4. The bandwidth optimization method for boost circuit systems according to claim 3, characterized in that, The bandwidth adjustment is continuous, and the compensation loop gain changes continuously with the duty cycle.
5. The bandwidth optimization method for boost circuit systems according to claim 3, characterized in that, The bandwidth adjustment is segmented, and the compensation loop gain varies segmentally with the duty cycle.
6. The bandwidth optimization method for boost circuit systems according to claim 5, characterized in that, When it is detected that the duty cycle is gradually increasing, and when it is detected that the duty cycle is greater than the first duty cycle and less than the third duty cycle, the process of increasing the compensation loop gain includes, When the duty cycle is greater than the first duty cycle and less than the second duty cycle, the compensation loop gain is maintained at the first gain; When the duty cycle is detected to increase to the second duty cycle, the gain of the compensation loop is increased to the second gain; When the duty cycle is greater than the second duty cycle and less than the third duty cycle, the compensation loop gain remains at the second gain; When the duty cycle is detected to increase to the third duty cycle, the gain of the compensation loop is increased to the third gain; The second duty cycle is greater than the first duty cycle and less than the third duty cycle; the second gain is greater than the first gain and less than the third gain.
7. The bandwidth optimization method for boost circuit systems according to claim 6, characterized in that, When it is detected that the duty cycle is gradually decreasing, and when it is detected that the duty cycle is less than the third duty cycle but greater than the first duty cycle, the process of reducing the compensation loop gain includes: When the duty cycle is less than the third duty cycle and greater than the second duty cycle, the compensation loop gain is maintained at the third gain; When the duty cycle is detected to have decreased to the second duty cycle, the compensation loop gain is reduced to the second gain; When the duty cycle is less than the second duty cycle and greater than the first duty cycle, the compensation loop gain is maintained at the second gain; When the duty cycle is detected to decrease to the first duty cycle, the compensation loop gain is reduced to the first gain.
8. The bandwidth optimization method for boost circuit systems according to claim 7, characterized in that, The second gain is twice the first gain, and the third gain is four times the first gain.
9. The bandwidth optimization method for a boost circuit system according to claim 7, characterized in that, The first duty cycle is 55%, the second duty cycle is 65%, and the third duty cycle is 75%.
10. The bandwidth optimization method for a boost circuit system according to claim 1, characterized in that, The gating signal is detected, and the duty cycle is calculated by the proportion of the high-level time of the gating signal within the period.
11. The bandwidth optimization method for a boost circuit system according to claim 1, characterized in that, The input signal (Vin) and the output signal (Vo) are detected. The duty cycle (D) is calculated by the relationship between the input signal (Vin) and the output signal (Vo) and the duty cycle (D). The relationship is: Vo / Vin=1 / (1-D).
12. A boost circuit system, employing the boost circuit system bandwidth optimization method as described in any one of claims 1-11 to modulate the system bandwidth, characterized in that, It includes an output unit, an input unit, a feedback unit, and a signal transmission and processing module. The signal transmission and processing module includes a compensation loop unit, a duty cycle detection unit, a frequency modulation unit, and a gain modulation unit. The input unit is used to acquire the input signal and is coupled to the signal transmission and processing module to transmit the input signal; The output unit is used to output an output signal and is coupled to the signal transmission and processing module. The input signal is processed by the signal transmission and processing module and then output through the output unit. The feedback unit is coupled to the output unit and is also coupled to the compensation loop unit. The feedback unit is used to feed back the output signal to the compensation loop unit. The compensation loop unit performs calculations on the feedback output signal and the reference signal and then outputs an adjustment signal. In the signal transmission and processing module The compensation loop unit is also coupled to the frequency modulation unit and transmits the adjustment signal to the frequency modulation unit. The frequency modulation unit is used to adjust the peak value of the inductor current and the switching frequency during signal transmission according to the adjustment signal. Different peak values of the inductor current and the switching frequency represent different current system operating states. The duty cycle detection unit is used to detect and obtain the current system duty cycle based on the current system operating status. The gain modulation unit is coupled to the duty cycle detection unit and acquires the duty cycle. The gain modulation unit is also coupled to the compensation loop unit and adjusts the compensation loop gain in the compensation loop unit according to the duty cycle.