A segmented current-steering digital-to-analog converter background calibration circuit and method

Abstract

This invention discloses a background calibration circuit and method for a segmented current-controlled digital-to-analog converter (DAC), belonging to the field of DAC calibration technology. The invention generates pulse control signals to sequentially select each of the N currents generated by a thermometer-coded current source array to a current error detection and negative feedback control module for error current detection. The unselected currents are output to a DAC dynamic switch, and under the control of digital signals, are output to the output port of the DAC dynamic switch. The calibration current is passed through the current error detection and negative feedback control module and converted to generate a corresponding feedback voltage. This feedback voltage controls the thermometer-coded current source array to generate a corresponding current. By calibrating each current, this invention corrects the mismatch of the thermometer-coded current source array in real time, ensuring that the high-order current of the segmented current-controlled DAC remains consistent, thereby achieving better DAC performance.

Description

Technical Field

[0001] This invention belongs to the field of digital-to-analog converter correction technology, specifically relating to a segmented current-steering digital-to-analog converter background correction circuit and method. Background Technology

[0002] Current-driven digital-to-analog converters (DACs), with their inherent high-speed response, have been widely used in fields with stringent requirements for signal conversion rates, such as ultra-high-speed communication, high-definition video processing, and high-end high-speed instrumentation. However, as market demands for DAC resolution (e.g., 14 bits and above) and conversion rates continue to rise, random process mismatches in transistors within the current source array, as well as systemic mismatches caused by in-chip process gradients, power supply / ground voltage drops, and ambient temperature fluctuations, are becoming increasingly prominent. These issues have become the core bottlenecks restricting further improvements in the static linearity (e.g., integral non-linearity (INL), differential non-linearity (DNL), and spurious-free dynamic range (SFDR) of current-driven DACs.

[0003] Traditional current source calibration techniques are mainly divided into two categories: front-end calibration and back-end calibration. Front-end calibration requires interrupting the normal signal conversion process of the DAC and completing mismatch correction through offline measurement. It cannot track dynamic mismatch caused by temperature and voltage drift during operation in real time, making it difficult to meet the application requirements of high precision and long-term stable operation. Among existing back-end calibration techniques, the digital error storage method is a typical example. It usually requires constructing a complex analog-to-digital-analog (ADA) closed-loop link: first, current mismatch information is extracted through a detection circuit, then quantized into digital code by an analog-to-digital converter (ADC) and stored in a register; finally, digital compensation logic corrects the input data before driving the DAC core. This scheme has significant inherent drawbacks: 1) Quantization noise introduced during quantization is easily superimposed on the signal path, causing new nonlinear distortion; 2) The digital compensation link adds additional signal delay, which can easily lead to timing errors in ultra-high conversion rate scenarios, affecting system stability; 3) The ADC, digital storage unit, and compensation logic in the closed loop occupy a large chip area and have high power consumption, contradicting the requirements of high-speed, low-power design.

[0004] Another type of background calibration approach is replacement calibration based on redundant current sources. However, existing technologies mostly adopt the implementation mode of "mismatch measurement - digital code storage - digital weighted compensation" or "mismatch measurement - physical switch to replace redundant unit": the former still does not break away from the reliance on digital compensation path and also faces the problems of delay accumulation and limited accuracy; the latter, due to the frequent on and off actions of physical switches, is prone to problems such as contact resistance fluctuations and switch charge injection, which may not only cause dynamic glitches in the output, but also accelerate the aging of switching devices and bring long-term reliability risks.

[0005] Existing correction technologies have significant shortcomings in terms of dynamic tracking capability, system complexity, power consumption, area overhead, and reliability. The industry urgently needs a high-precision current source correction technology that can achieve seamless real-time background tracking, eliminate the need for complex digital compensation links, control power consumption and area overhead, and adapt to changes in environmental parameters (temperature, voltage) in order to break through existing technical bottlenecks and meet the performance improvement requirements of ultra-high resolution and ultra-high speed DACs. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a segmented current-steering digital-to-analog converter background correction circuit and method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] In a first aspect, the present invention provides a segmented current-steering digital-to-analog converter background correction circuit, comprising:

[0008] The current source rotation control module is used to generate pulse control signals;

[0009] A thermometer-coded current source array is used to generate N current streams.

[0010] The multi-channel current selection module is used to select the current from N current channels in sequence as the current to be detected in each cycle under the control of the pulse control signal.

[0011] The current error detection and negative feedback control module is used to detect the error current of each corresponding current to be detected based on the calibration current of each channel, and generate the corresponding feedback voltage through IV conversion.

[0012] The thermometer code controls the current source array, which is also used to correct the current of each output channel under the feedback correction of the feedback voltage corresponding to each current channel.

[0013] The multi-channel current selection module is also used when the first current selection module is used. When the current of the first path is used as the current to be detected, the currents of the first path to the second path will be used. The corrected current corresponding to the path and the first The current output from the Nth channel is sent to the DAC dynamic switch; where, When the current of the first channel is used as the current to be detected, the currents of the second to Nth channels are output to the DAC dynamic switch.

[0014] Reference current and voltage generation module, used to generate reference voltage and reference current;

[0015] The SAR ADC and control logic module are used to generate corresponding control codes based on the feedback voltage and reference voltage.

[0016] A compensation current source array is used to generate compensation current according to a control code; the calibration current is the sum of the reference current and the compensation current.

[0017] A DAC (Dynamic Digital Switch) is a device that, under the control of a digital signal, generates a corrected analog signal in real time based on the current it receives.

[0018] Secondly, the present invention provides a back-end calibration method for a segmented current-driven digital-to-analog converter, comprising:

[0019] Within each cycle, based on the generated pulse control signal, the current from each of the N currents generated by the thermometer code control current source array is selected sequentially as the current to be detected and output.

[0020] The calibration current for each channel is generated based on the reference current and the corresponding compensation current for each channel.

[0021] Based on the calibration current corresponding to each channel, the error current of the current to be detected for each channel is detected, and the corresponding feedback voltage is generated through IV conversion.

[0022] The corresponding control code is generated based on the feedback voltage and reference voltage of each channel to generate the corresponding compensation current for each channel.

[0023] The current generated by the temperature code control current source array is corrected according to the feedback voltage of each channel, and the corrected current of each channel is output.

[0024] Based on the current to be detected for each channel, the corrected current from the first channel to the channel preceding the current to be detected and the current from the channel following the current to the Nth channel are output to the DAC dynamic switch.

[0025] The DAC dynamic switch is controlled by digital signals to generate a corrected analog signal in real time based on the current it receives.

[0026] Specifically, for the current to be detected corresponding to the first channel, the compensation current corresponding to that channel is 0, and the currents corresponding to the second to Nth channels are output to the DAC dynamic switch.

[0027] The beneficial effects of this invention are:

[0028] The solution provided by this invention achieves seamless real-time background tracking without interrupting normal operation by dynamically correcting the high-level current sources corresponding to the thermometer-controlled current source array. This improves the matching degree between high-level power currents, reduces harmonic distortion and power consumption of the segmented current-controlled digital-to-analog converter (DAC), and enhances the spurious-free dynamic range performance of the DAC. The background correction circuit proposed in this invention has a simple structure and significant effects, and can be widely applied in high-performance DACs. During sampling, this invention only involves the basic clock signal, eliminating the need to generate higher-frequency clocks for direction calculation and delay adjustment. This invention can be fully integrated into each module, reducing system-level resource consumption, shrinking the layout area, and requiring minimal constraints on wiring and pins during hardware implementation. Attached Figure Description

[0029] Figure 1 A schematic diagram of the principle of a segmented current-steering digital-to-analog converter background correction circuit provided in an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of a portion of the correction structure in the background correction circuit of a segmented current-steering digital-to-analog converter provided in an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the current selection detection circuit in the multi-channel current selection module provided in an embodiment of the present invention;

[0032] Figure 4 A timing diagram of the rotation control signal in the background correction circuit of a segmented current steering digital-to-analog converter provided in an embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of the structure of the multi-channel current selection circuit in the multi-channel current selection module provided in the embodiment of the present invention;

[0034] Figure 6 A timing diagram of the selection control signal in the background correction circuit of a segmented current-steering digital-to-analog converter provided in an embodiment of the present invention;

[0035] Figure 7 This is a flowchart illustrating the generation of control codes in the background correction circuit of a segmented current-steering digital-to-analog converter provided in an embodiment of the present invention.

[0036] Figure 8 This is a schematic diagram illustrating the steps of a segmented current-steering digital-to-analog converter background calibration method provided in an embodiment of the present invention. Detailed Implementation

[0037] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0038] The core circuit of a traditional segmented current-controlled DAC consists of a set of matched current sources and differential switches. The differential switches control the corresponding current source output to the positive or negative terminal of the differential pair based on each bit of the input digital signal. The currents are linearly superimposed at the output, forming a stepped current waveform, thus achieving the conversion from digital to analog signal. While the full thermometer code structure has excellent linearity, the number of current sources increases exponentially with the number of bits, leading to a surge in area and power consumption. The full binary structure greatly reduces the number of current sources, but "large number jumps" introduce severe glitches and nonlinear errors. Therefore, mainstream high-precision DACs often adopt a segmented decoding structure. For example, in a 16-bit DAC, a combination of 5-bit thermometer code (high-order bits) + 11-bit binary code (low-order bits) is used. In this case, the 5 high-order bits correspond to 31 equally weighted current sources, controlled by the thermometer code, to maintain the monotonicity and linearity of the high-order bit conversion; the 11 low-order bits use binary weighting to control the number of components.

[0039] The performance of current-controlled DACs is primarily limited by the non-ideal characteristics of the current sources and switches. Errors introduced by the current sources can be categorized into static and dynamic types. Static mismatch errors originate from random fluctuations in process parameters during manufacturing, leading to random mismatches between current sources. In high-precision DACs, to meet matching requirements, the current source MOSFETs are typically large in size and numerous, significantly increasing the array area and introducing substantial gradient errors (systematic mismatch), severely impacting the DAC's integral nonlinearity (INL) and differential nonlinearity (DNL).

[0040] Dynamic nonlinear error occurs because the output impedance of a real current source is limited and its impedance value is modulated by the output voltage, resulting in signal-related harmonic distortion and deteriorating the dynamic performance of the DAC, such as spurious-free dynamic range (SFDR).

[0041] In current source design, a trade-off must be struck between matching accuracy and chip area. A common approach is to scale the higher-order current sources proportionally. This approach offers advantages such as significantly saving chip area, reducing layout complexity, decreasing gradient errors in the current source array, and reducing parasitic capacitance at the output nodes, which helps improve conversion rate and dynamic performance.

[0042] However, scaling also brings new design challenges. Due to process variations, the actual current value of the scaled high-level current source deviates from the ideal ratio, potentially exacerbating random mismatch in the array. Therefore, in segmented current-controlled DACs using thermometer codes in the high-level segment, the matching accuracy of the high-level current source array often becomes the key to determining the overall static performance and dynamic linearity. Mismatch compensation is typically achieved through techniques such as common centroid layout, dynamic element matching (DEM), or background calibration.

[0043] To address the aforementioned problems, embodiments of the present invention provide a segmented current-steering digital-to-analog converter background correction circuit and method.

[0044] Below, we will first describe a segmented current-controlled digital-to-analog converter background correction circuit provided in an embodiment of the present invention, such as... Figure 1 As shown, it may include:

[0045] The current source rotation control module is used to generate pulse control signals;

[0046] A thermometer-coded current source array is used to generate N current streams.

[0047] The multi-channel current selection module is used to select the current from N current channels in sequence as the current to be detected in each cycle under the control of the pulse control signal.

[0048] The current error detection and negative feedback control module is used to detect the error current of each corresponding current to be detected based on the calibration current of each channel, and generate the corresponding feedback voltage through IV conversion.

[0049] The thermometer code controls the current source array, which is also used to correct the current of each output channel under the feedback correction of the feedback voltage corresponding to each current channel.

[0050] The multi-channel current selection module is also used when the first current selection module is used. When the current of the first path is used as the current to be detected, the currents of the first path to the second path will be used. The corrected current corresponding to the path and the first The current output from the Nth channel is sent to the DAC dynamic switch; where, When the current of the first channel is used as the current to be detected, the currents of the second to Nth channels are output to the DAC dynamic switch.

[0051] Reference current and voltage generation module, used to generate reference voltage and reference current;

[0052] The SAR ADC and control logic module are used to generate corresponding control codes based on the feedback voltage and reference voltage.

[0053] A compensation current source array is used to generate compensation current according to the control code; the calibration current is the sum of the reference current and the compensation current.

[0054] A DAC (Dynamic Digital Switch) is a device that, under the control of a digital signal, generates a corrected analog signal in real time based on the current it receives.

[0055] The segmented current-controlled digital-to-analog converter (DAC) background correction circuit provided in this embodiment of the invention generates pulse control signals through a current source rotation control module. This controls a multi-channel current selection module to sequentially select one of the N currents generated by the thermometer-code controlled current source array and send it to the current error detection and negative feedback control module for error current detection. The unselected currents are then output to the DAC dynamic switch, and under the control of digital signals, are output to the output ports ioutp and ioutn of the DAC dynamic switch. Here, N in the thermometer-code controlled current source array represents the number of current source branches, N=2. m 'm' represents the bit width of the control temperature code. Taking a 16-bit DAC as an example, if the 16-bit DAC is segmented into a 5+11 architecture, then 'm' is 5 and 'N' is 32.

[0056] Current to be detected and calibration current The current error detection and negative feedback control module generates a corresponding feedback voltage V1, which in turn controls the thermometer code to control the current source array to produce a corresponding current. The minimum detection accuracy of this current error detection and negative feedback control module is determined by the adjustment scale of the compensation current source array. The resistor R is determined by the voltage rating of the SAR ADC and the control logic module. Resistor R is positioned at the front end of the SAR ADC and the control logic module, with the feedback voltage V1 and reference voltage V0 connected to its two ends, respectively. Calibration current. Reference current With compensation current The sum; the SAR ADC and control logic module complete the successive comparisons to generate the corresponding control code A. The relevant current detection formula is as follows:

[0057] ;

[0058] ;

[0059] in, This represents the voltage difference across resistor R, which is also the voltage value quantized by the SAR ADC. The SAR ADC generates the control code A for controlling the compensation current source array through the control logic after successive comparisons of the digital code.

[0060] Compensation current generated by the compensation current source array for: ;

[0061] We can conclude that: ;

[0062] In the background correction circuit of the segmented current-controlled digital-to-analog converter, the feedback voltage is dynamically adjusted through negative feedback. When the absolute value of the difference between the feedback voltage and the reference voltage is less than or equal to the preset voltage, the control code remains unchanged. When the absolute value of the difference between the feedback voltage and the reference voltage is greater than the preset voltage, the positive or negative value of the difference between the feedback voltage and the reference voltage adjusts the control code.

[0063] Specifically, the voltage of V1 is dynamically adjusted through negative feedback when... The absolute value is less than or equal to When, control code A remains unchanged, when The absolute value is greater than At that time, control code A begins to adjust. The sign of the variable determines the direction of adjustment for control code A. When it is positive, the control code A increases; when When the value is negative or 0, the control code A decreases. After multiple cycles of the N current branches, the N currents generated by the feedback voltage V1 remain essentially consistent, reducing the DNL and INL parameters of the thermometer control current source array and enabling dynamic tracking of changes in operating conditions, thus achieving background calibration. After multiple adjustments, the... x The expression for the corrected current corresponding to the path is as follows:

[0064] ;

[0065] in, Indicates the first x The corrected current corresponding to the circuit. Indicates the reference current. Indicates the control code. This indicates the adjustment scale for the compensation current source array.

[0066] After multiple cycles, the current in each path is fixed at... This improves the high-temperature code DNL and INL indicators, thereby enhancing the dynamic SFDR performance. It can also adjust the compensation current in real time to keep the performance stable in response to changes in the working environment.

[0067] For example, to facilitate understanding, the following explanation uses a 16-bit 1.0GHz DAC with a 5+11 segmentation structure. The high 5 bits are encoded as 31 current source units for the thermometer, with one redundant unit added for rotation, enabling real-time current source correction without interrupting normal operation.

[0068] A partial calibration structure diagram is shown in the background calibration circuit of a specific segmented current-controlled digital-to-analog converter, such as... Figure 2 As shown. In Figure 2 In this circuit, MOSFETs M0, M1, M2, M3, M4, M5, M7, and M9, along with operational amplifier AMP, constitute the reference current and voltage generation module. MOSFETs M21-M52 form the detection current selection circuit in the multi-channel current selection module. MOSFETs M61-M92 form the temperature code control current source array. MOSFET M0 is a current mirror transistor. MOSFETs M1, M2, M3, M4, M5, and AMP are used to generate the reference current. MOSFETs M7 and M9 are used to generate the reference voltage based on the reference current. MOSFETs M8 and M10 form the current mirror circuit. Resistor R0 is the error current detection unit. Resistor R0 and capacitor C0 form an RC filter circuit. MOSFET M6 is responsible for generating current-voltage negative feedback. U1 is the compensation current source array; U2 is the SAR ADC and control logic module. Based on the rotation control signal SW... <n:1>Each of the 32 current channels is selected sequentially for feedback correction.

[0069] Reference current and voltage generation module, such as Figure 2 As shown, it may include:

[0070] MOSFETs M0, M1, M2, M3, M4, M5, M7, M9 and operational amplifier AMP;

[0071] The source of MOSFET M0 is grounded, the gate is connected to its own drain, and the drain is connected to current I0.

[0072] The source of MOSFET M1 is grounded, its gate is connected to the drain of MOSFET M0, and its drain is connected to the source of MOSFET M3.

[0073] The source of MOSFET M2 is grounded, its gate is connected to the gate of MOSFET M1, and its drain is connected to the source of MOSFET M4.

[0074] The gate of MOSFET M3 is connected to a bias voltage bias1, and its drain is connected to the source of MOSFET M5.

[0075] The gate of MOSFET M4 is connected to the gate of MOSFET M3, and the drain is used as the current output terminal of the reference current and voltage generation module.

[0076] The gate of MOSFET M5 is connected to the output of operational amplifier AMP, and the drain is connected to the drain of MOSFET M7, serving as the voltage output of the reference current and voltage generation module.

[0077] The source of MOSFET M7 is connected to the drain of MOSFET M9, and the gate is connected to the bias voltage bias2.

[0078] The source of MOSFET M9 is connected to the power supply voltage AVDD, and its gate is connected to the drain of MOSFET M7.

[0079] The non-inverting input of the operational amplifier AMP is connected to the clamping voltage vi, and the inverting input is connected to the drain of the MOSFET M4.

[0080] The pulse control signals generated by the current source rotation control module may include:

[0081] The rotation control signal is used to control the multi-channel current selection module to sequentially select the current from N current channels as the current to be detected and output.

[0082] The selection control signal is used to control the multi-channel current selection module, which outputs the unselected current channels to the DAC dynamic switch.

[0083] Rotation control signals may include SW <n:1>The selection control signal can include SEL_P <n:1>and SEL_N <n:1>Among them, SEL_P <n:1>SEL_P in <1> With SEL_N <n:1>SEL_N in <2> SW is generated after OR <n:1>SW in <1> .

[0084] The current source rotation control module generates a rotation control signal SW<32:1> to control the multi-channel current selection module, which selects one current from N currents to the source node of MOSFET M6.

[0085] The detailed structural diagram of the current detection selection circuit in the multi-channel current selection module is as follows: Figure 3 As shown, the current generated by the thermometer code control current source array corresponds to a MOS transistor for each current path. The source of each MOS transistor is connected to the current of the corresponding path, and the gate is connected to the rotation control signal of the corresponding path. The drains of each MOS transistor are connected to each other, and the current of the selected path is output from the drain of the MOS transistor corresponding to that path.

[0086] Within one cycle, the current is selected sequentially from the current corresponding to the first path to the current corresponding to the Nth path in the first half of the cycle, and sequentially from the current corresponding to the Nth path to the current corresponding to the first path in the second half of the cycle. The current corresponding to each path is selected for correction for two pulse cycles within one cycle, and the selection of each current follows a uniform distribution.

[0087] Specifically, the rotation control signal SW<32:1> is generated by clock frequency division. The timing diagram of the rotation control signal is as follows: Figure 4 As shown, in the thermometer code-controlled current source array, the pulse width of the current selection to the correction loop for each branch is T. c The selection logic sequentially selects from the first half of the loop cycle. , , Select to Then, in the second half of the cycle, sequentially from... Select to The current in each branch is corrected for two pulse cycles within each cycle. The current branch selection follows a uniform distribution. In this embodiment of the invention, each cycle is... .

[0088] At the same time, the current source rotation control module generates selection control signals to select 31 current outputs from 32 currents. The selection control signals are SEL_P<32:1> and SEL_N<32:1>, respectively.

[0089] A schematic diagram of the multi-channel current selection circuit in the multi-channel current selection module, as shown below. Figure 5 As shown, the multi-channel current selection circuit can be composed of 32 pairs of PMOS and NMOS transistors with their drains interconnected. For each PMOS and NMOS transistor pair, the source of the PMOS transistor is connected to the current of the corresponding channel, the source of the NMOS transistor is connected to the current of the previous channel, and the gates of the PMOS and NMOS transistors are respectively connected to the selection control signal of the corresponding channel. For example, taking the PMOS and NMOS transistor pair corresponding to the first current channel as an example, the first current channel's PMOS and NMOS transistor pair includes PMOS transistor MP1 and NMOS transistor MN1. The source of PMOS transistor MP1 is connected to the current of the first channel, and its gate is connected to SEL_P. <1> The drain is connected to the drain of NMOS transistor MN1, the source of NMOS transistor MN1 is connected to the current of channel 32, and the gate is connected to SEL_N. <1> .

[0090] The multi-channel current selection module outputs I1, I2, I3, ..., I 30 I 31 I dum A total of 32 current channels, including I1, I2, I3, ..., I 30 I 31 A total of 31 current channels are used for normal DAC output, I dum Used for dummy branch currents, primarily to ensure that the selection of each branch satisfies uniform distribution and achieves good matching on the layout. SEL_P <1> With SEL_N <1> Control selects the current generation I1, SEL_P <2> With SEL_N <2> The control selects the current I2, and so on, SEL_P <31> With SEL_N <31> Control selection to generate current I 31 SEL_P <32> With SEL_N <32> Control selection to generate current I dum .

[0091] Select the timing diagram of the control signal, such as Figure 6 As shown, SEL_P <1> Select the current of the first channel when the level is low. To I1, SEL_N <2> Select when low level To I2, SEL_P <1> With SEL_N <2> The same or subsequent generation of rotation control signal SW <1> ,choose The correction loop is entered for correction, and the current in other branches is sequentially and systematically selected. SEL_P and SEL_N work together to generate SW, and the current is cyclically selected. Perform corrections.

[0092] MOSFET M0 serves as a reference current mirror, mirroring currents I1 and I2 in MOSFETs M1 and M2 respectively. A high-quality reference current is generated through MOSFETs M3, M4, M5, and M6, along with operational amplifier AMP. This reference current then generates a reference voltage through MOSFETs M7 and M9. R0 and C0 form an RC filter circuit to stabilize the reference voltage during current mirror switching. R0 is used to detect mismatch errors in the current source array. MOSFET M6 converts the selected current into a feedback voltage V1. V1 controls the gate of the current source array, forming current-voltage negative feedback path 1. Additionally, MOSFETs M8 and M10 convert V1 into a current I4 flowing through MOSFET M10, forming current-current negative feedback path 2.

[0093] The Kirchhoff's Current Law (KCL) formula for the drain node of MOSFET M6 is:

[0094] ;

[0095] but: ;

[0096] when hour, To compensate for the minimum adjustment accuracy of the current source array, the converged corrected current... for:

[0097] ;

[0098] in, This is for compensation current. Whether the compensation current flows in or out is determined by control code A, and the magnitude of the compensation current is determined by A and... Jointly determined: .

[0099] The currents of MOSFETs M9 and M10 are expressed as follows:

[0100] ;

[0101] .

[0102] in, This indicates the current of MOSFET M9. , This indicates the surface mobility of MOSFET M9. This represents the gate oxide capacitance per unit area of ​​MOSFET M9. This indicates the effective channel width of MOSFET M9. This indicates the effective channel length of MOSFET M9. This indicates the threshold voltage of MOSFET M9. This indicates the current of MOSFET M10. , This indicates the surface mobility of MOSFET M10. This represents the gate oxide capacitance per unit area of ​​MOSFET M10. Indicates the effective channel width of MOSFET M10. Indicates the effective channel length of MOSFET M10. This indicates the threshold voltage of MOSFET M10.

[0103] In the design, the width-to-length ratio of MOSFETs M0, M1, and M2 is set to 2:2:3. Therefore, the currents flowing through MOSFETs M1 and M2 are respectively... , .

[0104] The width-to-length ratio of MOSFETs M9, M10, and M61~M92 in the thermometer-controlled current source array is set to 2:1:2. When there is no error, the currents for each transistor are as follows:

[0105] ;

[0106] ;

[0107] ;

[0108] ;

[0109] so: .

[0110] SAR ADC Quantization The differential-mode voltage is converted to binary two's complement d<3:0>, and the corresponding control code A is generated through internal control logic. If d <4> When it is high, then Greater than 0, The current flows into the source node of MOSFET M6, and after passing through MOSFET M6, it is converted into an increased feedback voltage V1; if d <4> When it is low level, then Less than or equal to 0 The current flows into the source node of MOSFET M6, and is converted by MOSFET M6 into a feedback voltage V1 that decreases, so as to achieve the purpose of negative feedback adjustment and correction.

[0111] A flowchart for generating control codes, such as Figure 7 As shown, in the specific generation process, the initialization and generation of the corresponding loop control signals are initiated first, followed by SAR ADC quantization. The differential voltage is ,right Make a judgment when If necessary, return to the previous step and continue with the previous step. Quantize the differential-mode voltage when At that time, if ,but ,like ,but This updates control code A. Here, 'e' represents the correction error tolerance.

[0112] The background calibration circuit provided in this invention dynamically calibrates the high-level current sources corresponding to the thermometer-controlled current source array sequentially. This achieves seamless real-time background tracking without interrupting normal operation, improving the matching degree between high-level power currents, reducing harmonic distortion and power consumption of the segmented current-controlled digital-to-analog converter (DAC), and enhancing the spurious-free dynamic range performance of the DAC. This background calibration circuit has a simple structure and significant effects, and can be widely applied in high-performance DACs. During sampling, only the basic clock signal is involved, eliminating the need to generate higher-frequency clocks for direction calculation and delay adjustment. This calibration circuit can be fully integrated into each module, reducing system-level resource consumption, shrinking the layout area, and requiring minimal constraints on wiring and pins during hardware implementation.

[0113] Secondly, corresponding to the above-described embodiment of a segmented current-steering digital-to-analog converter background correction circuit, this embodiment of the invention also provides a segmented current-steering digital-to-analog converter background correction method, such as... Figure 8 As shown, it may include:

[0114] S1, In each cycle, according to the generated pulse control signal, the current of each of the N currents generated by the thermometer code control current source array is selected in sequence as the current to be detected and output.

[0115] S2 generates the corresponding calibration current for each channel based on the reference current and the corresponding compensation current for each channel.

[0116] S3, based on the calibration current of each channel, performs error current detection on the current to be detected for each channel, and generates the corresponding feedback voltage through IV conversion;

[0117] S4 generates corresponding control codes based on the feedback voltage and reference voltage of each channel to generate the corresponding compensation current for each channel.

[0118] S5, based on the feedback voltage of each channel, corrects the current generated by the thermometer code control current source array for each channel, and outputs the corrected current for each channel.

[0119] S6, based on the current to be detected for each channel, output the corrected current from the first channel to the channel preceding the current to be detected and the current from the channel following the current to the Nth channel to the DAC dynamic switch.

[0120] S7 controls the DAC dynamic switch to generate a corrected analog signal in real time based on the current it receives, according to the digital signal.

[0121] Specifically, for the current to be detected corresponding to the first channel, the compensation current corresponding to that channel is 0, and the currents corresponding to the second to Nth channels are output to the DAC dynamic switch.

[0122] The background calibration method for a segmented current-driven digital-to-analog converter with dynamic current source calibration provided in this embodiment of the invention can be understood by referring to the description of each module in the background calibration circuit provided in the first aspect, and will not be repeated here. This background calibration method dynamically corrects the mismatch of the thermometer code-controlled current source array in real time, ensuring that the high-order current of the segmented current-driven digital-to-analog converter remains consistent, thereby achieving better digital-to-analog conversion performance.

[0123] It should be noted that, in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0124] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A segmented current-controlled digital-to-analog converter background correction circuit, characterized in that, include: The current source rotation control module is used to generate pulse control signals; A thermometer-coded current source array is used to generate N current streams. The multi-channel current selection module is used to select the current from N current channels in sequence as the current to be detected in each cycle under the control of the pulse control signal. The current error detection and negative feedback control module is used to detect the error current of each corresponding current to be detected based on the calibration current of each channel, and generate the corresponding feedback voltage through IV conversion. The thermometer code controls the current source array, which is also used to correct the current of each output channel under the feedback correction of the feedback voltage corresponding to each current channel. The multi-channel current selection module is also used when the first current selection module is used to select the current selection module. When the current of the first path is used as the current to be detected, the current of the second path will be used as the current of the third path. The corrected current corresponding to the path and the first The current output from the Nth channel is sent to the DAC dynamic switch; where, When the current of the first channel is used as the current to be detected, the currents of the second to Nth channels are output to the DAC dynamic switch. Reference current and voltage generation module, used to generate reference voltage and reference current; The SAR ADC and control logic module are used to generate corresponding control codes based on the feedback voltage and reference voltage. A compensation current source array is used to generate compensation current according to a control code; the calibration current is the sum of the reference current and the compensation current. A DAC (Dynamic Digital Switch) is a device that, under the control of a digital signal, generates a corrected analog signal in real time based on the current it receives.

2. The segmented current-controlled digital-to-analog converter background correction circuit according to claim 1, characterized in that, The pulse control signal includes: The rotation control signal is used to control the multi-channel current selection module to sequentially select the current from N current channels as the current to be detected and output. The selection control signal is used to control the multi-channel current selection module, which outputs the unselected current channels to the DAC dynamic switch.

3. The segmented current-controlled digital-to-analog converter background correction circuit according to claim 2, characterized in that, The rotation control signal includes SW <n:1>The selection control signal includes SEL_P <n:1>and SEL_N <n:1>Among them, SEL_P <n:1>SEL_P in <1> With SEL_N <n:1>SEL_N in <2> SW is generated after OR <n:1> SW in <1> .

4. The segmented current-controlled digital-to-analog converter background correction circuit according to claim 1, characterized in that, Within one cycle, the current is selected sequentially from the current corresponding to the first path to the current corresponding to the Nth path in the first half of the cycle, and sequentially from the current corresponding to the Nth path to the current corresponding to the first path in the second half of the cycle. The current corresponding to each path is selected for correction for two pulse cycles within one cycle, and the selection of each current follows a uniform distribution.

5. The segmented current-controlled digital-to-analog converter background correction circuit according to claim 1, characterized in that, In the thermometer-controlled current source array, N represents the number of current source branches, N=2. m , m represents the bit width of the control thermometer code.

6. The segmented current-controlled digital-to-analog converter background correction circuit according to claim 1, characterized in that, No. x The expression for the corrected current corresponding to the path is as follows: ； in, Indicates the first x The corrected current corresponding to the circuit. Indicates the reference current. Indicates the control code. This indicates the adjustment scale for the compensation current source array.

7. The segmented current-controlled digital-to-analog converter background correction circuit according to claim 1, characterized in that, In the background correction circuit of the segmented current-controlled digital-to-analog converter, the feedback voltage is dynamically adjusted through negative feedback. When the absolute value of the difference between the feedback voltage and the reference voltage is less than or equal to the preset voltage, the control code remains unchanged. When the absolute value of the difference between the feedback voltage and the reference voltage is greater than the preset voltage, the control code is adjusted according to the sign of the difference between the feedback voltage and the reference voltage.

8. The segmented current-controlled digital-to-analog converter background correction circuit according to claim 1, characterized in that, The reference current and voltage generation module includes: MOSFETs M0, M1, M2, M3, M4, M5, M7, M9 and operational amplifier AMP; The source of the MOS transistor M0 is grounded, the gate is connected to its own drain, and the drain is connected to a current I0. The source of MOS transistor M1 is grounded, its gate is connected to the drain of MOS transistor M0, and its drain is connected to the source of MOS transistor M3. The source of MOS transistor M2 is grounded, its gate is connected to the gate of MOS transistor M1, and its drain is connected to the source of MOS transistor M4. The gate of the MOS transistor M3 is connected to a bias voltage bias1, and its drain is connected to the source of the MOS transistor M5. The gate of the MOS transistor M4 is connected to the gate of the MOS transistor M3, and the drain is used as the current output terminal of the reference current and voltage generation module. The gate of the MOSFET M5 is connected to the output of the operational amplifier AMP, and the drain is connected to the drain of the MOSFET M7, serving as the voltage output of the reference current and voltage generation module. The source of the MOSFET M7 is connected to the drain of the MOSFET M9, and the gate is connected to a bias voltage bias2. The source of the MOSFET M9 is connected to the power supply voltage AVDD, and the gate is connected to the drain of the MOSFET M7. The non-inverting input of the operational amplifier AMP is connected to a clamping voltage vi, and the inverting input is connected to the drain of the MOSFET M4.

9. A segmented current-steering digital-to-analog converter background calibration method, applied in the segmented current-steering digital-to-analog converter background calibration circuit as described in any one of claims 1-8, characterized in that, include: Within each cycle, the current from each of the N currents generated by the thermometer code control current source array is selected sequentially from the generated pulse control signal and used as the current to be detected for output. The calibration current for each channel is generated based on the reference current and the corresponding compensation current for each channel. Based on the calibration current for each channel, the error current of the current to be detected for each channel is detected, and the corresponding feedback voltage is generated through IV conversion. The corresponding control code is generated based on the feedback voltage and reference voltage of each channel to generate the corresponding compensation current for each channel. The current generated by the temperature code control current source array is corrected according to the feedback voltage of each channel, and the corrected current of each channel is output. Based on the current to be detected for each channel, the corrected current from the first channel to the channel preceding the current to be detected and the current from the channel following the current to the Nth channel are output to the DAC dynamic switch. The DAC dynamic switch is controlled by digital signals to generate a corrected analog signal in real time based on the current it receives. Specifically, for the current to be detected corresponding to the first channel, the compensation current corresponding to that channel is 0, and the currents corresponding to the second to Nth channels are output to the DAC dynamic switch.

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