Pulse radar transmitter chip and electronic device
By designing a pulse radar transmitter chip with a fully digital circuit structure, the problem of high power consumption of UWB system transmitter chips was solved, achieving low-power, high-precision radar signal output and extending the system's standby and operating time.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 芯睿微电子(昆山)有限公司
- Filing Date
- 2022-12-13
- Publication Date
- 2026-06-26
AI Technical Summary
Existing UWB systems have high power consumption in their transmitter chips, which limits the system's standby and operating time.
Design a pulse radar transmitter chip including a direct pulse generation circuit, a fully digital power amplifier, and an output matching network. It adopts a fully digital circuit structure, generates pulse signals with different delays through pulse generation sub-circuits and pulse modulation sub-circuits, and outputs high-precision radar pulse signals through a fully digital power amplifier.
It achieves low-power, high-precision radar pulse signal output, improving the standby and operating time of the UWB system.
Smart Images
Figure CN116148774B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to a pulse radar transmitter chip and electronic device. Background Technology
[0002] Ultra-wideband (UWB) radar is generally defined as a radar whose fractional band-width (FBW) of the transmitted signal is greater than 0.25. UWB technology achieves communication, detection, and remote sensing functions by processing very short single pulses, including generation, transmission, reception, and processing. A key characteristic of this technology is its extremely large bandwidth. It can also be referred to as pulse radar, pulse radio, carrier-free technology, and time-domain technology.
[0003] As a short-range wireless communication technology, Ultra-Wideband (UWB) technology caused a sensation when the US and Europe released related standards in 2003, but it faded into obscurity due to the lack of suitable application scenarios. In 2019, Apple brought it back to the forefront by incorporating the U1 positioning chip supporting UWB technology into the iPhone 11, and in 2020, smartphone manufacturers followed suit in adopting UWB technology. Suddenly, UWB positioning technology became a focus of industry discussion.
[0004] Currently, indoor positioning systems based on UWB technology mainly use the DW1000 chip, but its transmitter consumes as much as 162mW. Figure 1 As shown. Due to the existence of UWB technology, the respiratory and heart rate monitoring system mainly uses Novelda's X4 chip, which has a power consumption as high as 120mW, such as... Figure 2 As shown. Therefore, this greatly limits the standby and operating time of the entire UWB system based on this type of chip. Summary of the Invention
[0005] To address the aforementioned technical problems, embodiments of this application provide a low-power pulse radar transmitter chip and electronic device.
[0006] According to a first aspect of the embodiments of this application, a pulse radar transmitter chip is provided, comprising a direct pulse generation circuit, a fully digital power amplifier, and an output matching network connected in sequence. The direct pulse generation circuit operates at an ultra-wideband frequency and includes a pulse generation sub-circuit and a pulse modulation sub-circuit, wherein:
[0007] The pulse generation sub-circuit is used to generate at least n pulse signals with different delays, where n is an integer greater than or equal to 2;
[0008] There are m pulse modulation sub-circuits, which are used to modulate the pulse signals on each pulse signal output terminal of the pulse generation sub-circuit into pulse control signals, where m is an integer greater than or equal to 1. The first pulse signal input terminal and the second pulse signal input terminal of each pulse modulation sub-circuit are electrically connected to each pulse signal output terminal of the pulse generation sub-circuit, respectively. The pulse width control signal input terminal of each pulse modulation sub-circuit is used to receive the pulse width control signal. The pulse control signal output terminal of each pulse modulation sub-circuit is electrically connected to the signal input terminal of the all-digital power amplifier to output the pulse control signal to the all-digital power amplifier.
[0009] According to a second aspect of the embodiments of this application, an electronic device is provided, including the pulse radar transmitter chip described above.
[0010] The pulse radar transmitter chip and electronic device provided in this application include a direct pulse generation circuit, a fully digital power amplifier, and an output matching network connected in sequence. The direct pulse generation circuit operates at an ultra-wideband frequency and includes a pulse generation sub-circuit and a pulse modulation sub-circuit. The pulse generation sub-circuit is used to generate at least two pulse signals with different delays. The pulse modulation sub-circuit is used to modulate each pulse signal output by the pulse generation sub-circuit into a pulse control signal. In this way, the direct pulse generation circuit directly generates a pulse control signal through a radio frequency signal, which is sent to the fully digital power amplifier and then output through the output matching network, thereby generating a high-precision radar pulse signal. Moreover, the entire circuit is a fully digital circuit with low power consumption, thereby improving the standby and working time of the UWB system based on this chip. Attached Figure Description
[0011] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0012] Figure 1 This is a schematic diagram of the transmitter architecture of the DW1000 chip in the prior art;
[0013] Figure 2 This is a schematic diagram of the transmitter architecture of NOVELDA's X4 chip in the prior art;
[0014] Figure 3 A schematic block diagram of a pulse radar transmitter chip provided in an embodiment of this application;
[0015] Figure 4 for Figure 3 Block diagram of the direct pulse generation circuit;
[0016] Figure 5 for Figure 3 The circuit diagrams of the direct pulse generation circuit are shown in Figure 1, where (a) is the circuit diagram of the pulse generation sub-circuit and (b) is the circuit diagram of the pulse modulation sub-circuit.
[0017] Figure 6 for Figure 5 The output waveforms of the direct pulse generation circuit are shown in Figure 1, where (a) is the original output waveform and (b) is the amplified output waveform.
[0018] Figure 7 for Figure 3 Circuit diagram of a fully digital power amplifier and its output matching network;
[0019] Figure 8 To adopt Figure 5-7 The output waveform diagrams of the pulse radar transmitter chip are shown, where (a) is the original output waveform diagram and (b) is the amplified output waveform diagram. Detailed Implementation
[0020] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.
[0021] On the one hand, embodiments of this application provide a pulse radar transmitter chip, such as Figure 3-4 As shown, the system includes a direct pulse generation circuit 10, a fully digital power amplifier (DPA) 20, and an output matching network 30 connected in sequence. The direct pulse generation circuit 10 operates at an ultra-wideband (UWB) frequency and includes a pulse generation sub-circuit 11 and a pulse modulation sub-circuit 12, wherein:
[0022] The pulse generation sub-circuit 11 is used to generate at least n pulse signals with different delays, where n is an integer greater than or equal to 2. Specifically, the pulse generation sub-circuit 11 may include a first pulse signal output terminal, a second pulse signal output terminal to the nth pulse signal output terminal.
[0023] There are m pulse modulation sub-circuits 12, which are used to modulate the pulse signals on each pulse signal output terminal of the pulse generation sub-circuit 11 into pulse control signals, where m is an integer greater than or equal to 1. Each pulse modulation sub-circuit 12 includes a first pulse signal input terminal 121, a second pulse signal input terminal 122, a pulse width control signal input terminal 123, and a pulse control signal output terminal 124. The first pulse signal input terminal 121 and the second pulse signal input terminal 122 of each pulse modulation sub-circuit 12 are electrically connected to each pulse signal output terminal of the pulse generation sub-circuit 11, respectively. The pulse width control signal input terminal 123 is used to receive the pulse width control signal, which is generated by the user as needed. The pulse control signal output terminal 124 is electrically connected to the signal input terminal of the all-digital power amplifier 20 to output the pulse control signal to the all-digital power amplifier 20.
[0024] When the chip is working, the pulse generation sub-circuit 11 of the direct pulse generation circuit 10 generates at least two pulse signals with different delays. Each pulse signal is output to the pulse signal input terminals 121 and 122 of the pulse modulation sub-circuit 12. At the same time, the pulse width control signal input terminal 123 of the pulse modulation sub-circuit 12 receives the pulse width control signal provided by the user, thereby modulating each pulse signal output by the pulse generation sub-circuit 11 into a pulse control signal. Then, the pulse control signal output terminal 124 of the pulse modulation sub-circuit 12 is output to the all-digital power amplifier 20 to output a pulse control signal to the all-digital power amplifier 20. Under the control of the pulse control signal, the all-digital power amplifier 20 outputs the final output signal through the output matching network 30.
[0025] The pulse radar transmitter chip of this application embodiment includes a direct pulse generation circuit, a fully digital power amplifier, and an output matching network connected in sequence. The direct pulse generation circuit operates at an ultra-wideband frequency and includes a pulse generation sub-circuit and a pulse modulation sub-circuit. The pulse generation sub-circuit is used to generate at least two pulse signals with different delays. The pulse modulation sub-circuit is used to modulate each pulse signal output by the pulse generation sub-circuit into a pulse control signal. In this way, the direct pulse generation circuit directly generates a pulse control signal through a radio frequency signal, which is sent to the fully digital power amplifier and then output through the output matching network, thereby generating a high-precision radar pulse signal. Moreover, the entire circuit is a fully digital circuit with low power consumption, thereby improving the standby and working time of the UWB system based on this chip.
[0026] The pulse generation sub-circuit 11 is used to generate at least two pulse signals with different delays. It can take various forms that are easily conceived by those skilled in the art. For ease of implementation, the following structural form is preferred:
[0027] like Figure 5As shown in (a), the pulse generation sub-circuit 11 includes at least two D flip-flops (DFFs). The clock input port clk of each D flip-flop is connected to the same (high-speed) clock signal Clkin. The data input port D of the first D flip-flop is connected to the power supply (i.e., high voltage VDD). The data input ports D of the remaining D flip-flops are respectively connected to the data output port Do of the previous D flip-flop. The signal lines from the data output ports Do of the D flip-flops are sequentially led out as the first pulse signal output terminal, the second pulse signal output terminal to the nth pulse signal output terminal (i.e., the pulse signal Ck in the figure) of the pulse generation sub-circuit 11. <0> 、Ck <1> ...Ck <12> (At this time, n = 13); the number of D flip-flops is greater than or equal to n, so as to generate a sufficient number of pulse signal outputs.
[0028] In this embodiment of the application, to facilitate the generation of multiple pulse signals with different delays, signal lines can be led out from the data output port of the D flip-flop in various ways, which are described below:
[0029] Method 1: In the pulse generation sub-circuit 11, the signal lines of the data output ports of each D flip-flop are sequentially led out as the first pulse signal output terminal, the second pulse signal output terminal, and the nth pulse signal output terminal, respectively.
[0030] Method 2: In the pulse generation sub-circuit 11, starting from the first D flip-flop, the signal lines from the data output ports of the odd-numbered D flip-flops are sequentially used as the first pulse signal output terminal, the second pulse signal output terminal, and so on up to the nth pulse signal output terminal.
[0031] Method 3: In the pulse generation sub-circuit 11, starting from the second D flip-flop, the signal lines from the data output ports of the even-numbered D flip-flops are sequentially used as the first pulse signal output terminal, the second pulse signal output terminal, and so on up to the nth pulse signal output terminal.
[0032] Understandably, the key to the above signal line extraction process is to extract the signals sequentially to avoid signal confusion. This can be done by extracting the signal lines one by one from the data output ports of each D flip-flop (without interrupting the D flip-flops, method one above), or by interrupting one D flip-flop at a time (methods two and three above), or by interrupting any number of D flip-flops. The specific method depends on the waveform requirements of the final output signal from the pulse radar transmitter chip. In method one above, because the differences between the extracted pulse signals are relatively small, it may lead to… Figure 5 The pulse width difference of each pulse control signal output by the direct pulse generation circuit becomes smaller, thereby... Figure 8 The output waveform of the medium-pulse radar transmitter chip has a larger / steeper slope; in methods two and three above, the differences between the extracted pulse signals are relatively large, which will cause... Figure 5The pulse width difference of each pulse control signal output by the direct pulse generation circuit becomes larger, thus... Figure 8 The output waveform of the medium pulse radar transmitter chip has a smaller / flatter slope.
[0033] exist Figure 5 In the embodiment shown in (a), the number of D flip-flops is 23. It is understood that this number can be flexibly increased or decreased as needed. In the figure, the data output ports of the odd-numbered D flip-flops in the D flip-flop chain are sequentially led out as the first pulse signal output terminal, the second pulse signal output terminal, and so on up to the nth pulse signal output terminal, thus obtaining Ck as shown in the figure. <0> To Ck <12> A total of 13 pulse signals are output. Among these 13 pulse signals, except for Ck... <5> To Ck <7> Apart from the two signals being delayed by one high-speed Clkin clock cycle, the remaining adjacent Ck... <0> To Ck <12> The delay is two Clkin clock cycles. The reset port rstn of each D flip-flop in the diagram can be connected to the pulse enable signal pulseEn.
[0034] There are m pulse modulation sub-circuits 12, which are used to modulate the pulse signals at the output terminals of each pulse signal of the pulse generation sub-circuit 11 into pulse control signals. To facilitate the connection of the pulse generation sub-circuit 11, the following connection method is preferred:
[0035] like Figure 5 As shown in (b), the first pulse signal input terminal 121 of each pulse modulation sub-circuit 12 is electrically connected to the first m pulse signal output terminals of the pulse generation sub-circuit 11, that is, electrically connected to the output terminals from the m-th pulse signal to the first pulse signal, corresponding to the pulse signal Ck. <m-1:0>The embodiment shown in the figure is specifically a pulse signal Ck<5:0> (where m=6);
[0036] The second pulse signal input terminal 122 is electrically connected to the last m pulse signal output terminals of the pulse generation sub-circuit 11, that is, electrically connected to the (n-m+1)th pulse signal output terminal to the nth pulse signal output terminal, corresponding to the pulse signal Ck.<n-m+1:n> The embodiment shown in the figure is specifically a pulse signal Ck<7:12> (where n=13);
[0037] Pulse width control signal input terminal 123 is used to receive the m-th pulse width control signal to the first pulse width control signal, corresponding to the pulse signal pulseWidth. <m-1:0>The embodiment shown in the figure specifically uses a pulse signal pulseWidth<5:0>.
[0038] The pulse control signal output terminal 124 is electrically connected to the signal input terminal of the all-digital power amplifier 20 to output the m-th pulse control signal to the all-digital power amplifier 20, corresponding to the pulse signal PActl. <m-1:0>The embodiment shown in the figure specifically uses the pulse signal PActl<5:0>.
[0039] m is the floor function of n / 2. In the embodiment shown in the figure, m = 6, n = 13, and the pulse signal Ck... <6> Not in use yet.
[0040] In this way, the pulse modulation sub-circuit 12 can modulate each pulse signal output by the pulse generation sub-circuit 11 into the required pulse control signal according to the pulse width control signal provided by the user; and the signals at the two pulse signal input terminals of the pulse modulation sub-circuit 12 do not overlap, avoiding confusion and enabling better generation of the required pulse control signal.
[0041] The pulse modulation sub-circuit 12 can take various forms readily conceived by those skilled in the art. For ease of implementation, the following structural form is preferred:
[0042] Continue as Figure 5 As shown in (b), the pulse modulation sub-circuit 12 is a gate combination circuit, which includes an XOR gate and a NOR gate, wherein:
[0043] The two input terminals of the XOR gate are respectively used as the first pulse signal input terminal 121 and the second pulse signal input terminal 122 of the pulse modulation sub-circuit 12. The output terminal is electrically connected to one input terminal of the NOR gate. In the embodiment shown in the figure, one input terminal of the XOR gate receives the pulse signal Ck<5:0>, the other input terminal receives the pulse signal Ck<7:12>, and the output terminal of the XOR gate outputs the pulse signal out0<0:5>.
[0044] The other input terminal of the NOR gate is the pulse width control signal input terminal 123 of the pulse modulation sub-circuit 12, and the output terminal of the NOR gate is the pulse control signal output terminal 124 of the pulse modulation sub-circuit 12. In the embodiment shown in the figure, the other input terminal of the NOR gate receives the pulse width control signal pulseWidth<5:0>.
[0045] In this way, the pulse modulation sub-circuit 12 can modulate the pulse signals Ck<5:0> and Ck<7:12> output by the pulse generation sub-circuit 11 into the required pulse control signal PActl<5:0> according to the pulse width control signal pulseWidth<5:0> provided by the user.
[0046] In a further embodiment, the above-described gate combination circuit may further include a first inverter inv and / or a second inverter inv, wherein:
[0047] The first inverter is electrically connected between the output terminal of the XOR gate and the input terminal of the NOR gate. In the embodiment shown in the figure, the input terminal of the first inverter receives the pulse signal out0<0:5> output by the XOR gate, inverts it, and outputs it to one input terminal of the NOR gate.
[0048] The second inverter is connected to the output of the NOR gate. The output of the second inverter serves as the pulse control signal output 124 of the pulse modulation sub-circuit 12. In the embodiment shown in the figure, the input of the second inverter receives the pulse signal output by the NOR gate, inverts it, and outputs the pulse control signal PActl<5:0>.
[0049] In this embodiment, the circuit driving capability can be greatly improved by using an inverter. Figure 5 The output waveform of the direct pulse generation circuit is as follows: Figure 6 As shown, by Figure 6 It can be seen that the width of each pulse control signal increases in binary form.
[0050] The all-digital power amplifier 20 amplifies the pulse control signal output from the direct pulse generation circuit 10 and outputs it through the output matching network 30 to generate a high-precision radar pulse signal. It can take various forms that are easy for those skilled in the art to conceive of. For ease of implementation, the all-digital power amplifier 20 preferably includes a differential amplifier module 21 controlled by the pulse control signal output from the direct pulse generation circuit 10. The differential amplifier module 21 can be composed of a common-source common-gate transistor.
[0051] In a further embodiment, such as Figure 7 As shown, the differential amplifier module may include symmetrically designed two-sided paths, each side path including at least one column of branches, and each column of branches including a first electronic switch and a second electronic switch connected in series, wherein:
[0052] The gate of the first electronic switch in each path is connected to the output terminal of each pulse control signal of the direct pulse generation circuit 10, and the drain is electrically connected to the amplified signal output terminal of the differential amplifier module on that side. The source is electrically connected to the drain of the corresponding second electronic switch. In the embodiment shown in the figure, each path includes 6 columns of branches. The gate of the first electronic switch (the electronic switch located at the top) in each column of branches receives the pulse control signal PActl output by the direct pulse generation circuit 10 from the outside to the inside. <5> PActl <4> PActl <3> PActl <2> PActl <1> PActl <0> ;
[0053] The gate of the second electronic switch in each path is electrically connected to one of the pair of differential signals formed by the clock signal Clkin of the pulse generator circuit 10, and the drain is grounded. In the embodiment shown in the figure, the gate of the second electronic switch in the left path (the lower electronic switch) receives the inp signal in the pair of differential signals formed by Clkin, and the gate of the second electronic switch in the right path (the lower electronic switch) receives the inn signal in the pair of differential signals formed by Clkin.
[0054] Therefore, Figure 7 In the embodiment shown, the differential amplifier module is 6-bit and consists of 6 common-source cascode transistors with a width that increases by binary, so that the all-digital power amplifier 20 is controlled by the pulse control signal PActl<5:0> output by the direct pulse generation circuit 10.
[0055] In the prior art, power amplifiers are typically analog circuits. This application embodiment achieves a fully digital power amplifier through the aforementioned structure. Furthermore, it can be understood that, to further improve the control capability of the power amplifier, each side of its differential amplifier module preferably includes at least two parallel branches. Therefore, in this application embodiment, the number m of the pulse modulation sub-circuits 12 of the direct pulse generation circuit 10 is preferably an integer greater than or equal to 2. Based on this, the pulse generation sub-circuit 11 is preferably used to generate at least four pulse signals with different delays; that is, n is preferably an integer greater than or equal to 4.
[0056] In various embodiments of this application, the first electronic switch and the second electronic switch can both be P-type transistors (specifically, they can be metal-oxide-semiconductor field-effect transistors, i.e., MOS transistors).
[0057] The output matching network 30 is used to match the impedance of the antenna (e.g., 50 ohms) to the impedance required by the all-digital power amplifier 20, thereby transmitting the power of the all-digital power amplifier 20 to the antenna. For ease of implementation, the output matching network 30 may include an on-chip transformer 31.
[0058] In a further embodiment, such as Figure 3 and Figure 7 As shown, the two ends of the primary coil of the on-chip transformer 31 are electrically connected to the two amplified signal output terminals of the all-digital power amplifier 20, respectively. One end of the secondary coil of the on-chip transformer 31 serves as the output terminal Pout of the pulse radar transmitter chip, and the other end is grounded. Thus, using... Figure 5-7 The output waveform of the pulse radar transmitter chip is as follows: Figure 8 As shown.
[0059] In summary, this application Figure 5-7 The resulting pulse radar transmitter chip embodiment is a low-power, high-precision, ultra-wideband fully digital pulse radar transmitter chip based on CMOS (Complementary Metal-Oxide-Semiconductor) technology. This transmitter chip directly generates pulse signals via radio frequency signals, and simultaneously generates a high-precision radar pulse signal through an output matching network based on an on-chip transformer, achieving low power consumption. With a pulse transmit power of 10dBm, the power consumption of the entire transmitter chip can be reduced to below 2mW. Furthermore, the pulse period frequency is strictly controlled by the input signal frequency, thereby improving the power consumption and performance of the UWB system based on this transmitter chip.
[0060] On the other hand, embodiments of this application provide an electronic device including the aforementioned radar transmitter chip. Since the structure of the radar transmitter chip is the same as described above, it will not be repeated here.
[0061] The electronic device of this application embodiment includes a pulse radar transmitter chip comprising a direct pulse generation circuit, a fully digital power amplifier, and an output matching network connected in sequence. The direct pulse generation circuit operates at an ultra-wideband frequency and includes a pulse generation sub-circuit and a pulse modulation sub-circuit. The pulse generation sub-circuit generates at least two pulse signals with different delays, and the pulse modulation sub-circuit modulates each pulse signal output by the pulse generation sub-circuit into a pulse control signal. In this way, the direct pulse generation circuit directly generates a pulse control signal through a radio frequency signal, which is sent to the fully digital power amplifier and then output through the output matching network, thereby generating a high-precision radar pulse signal. Furthermore, the entire circuit is a fully digital circuit with low power consumption, thereby improving the standby and operating time of the UWB system based on this chip.
[0062] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0063] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0064] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. A pulse radar transmitter chip, characterized in that, The circuit includes a direct pulse generation circuit, a fully digital power amplifier, and an output matching network connected in sequence. The direct pulse generation circuit operates at an ultra-wideband frequency and includes a pulse generation sub-circuit and a pulse modulation sub-circuit, wherein: The pulse generation sub-circuit is used to generate at least n pulse signals with different delays, where n is an integer greater than or equal to 2; The pulse modulation sub-circuit comprises m units, used to modulate the pulse signals at the output terminals of the pulse generation sub-circuit into pulse control signals, where m is an integer greater than or equal to 1. The first and second pulse signal input terminals of each pulse modulation sub-circuit are electrically connected to the output terminals of the pulse generation sub-circuit, respectively. The pulse width control signal input terminal of each pulse modulation sub-circuit is used to receive the pulse width control signal. The pulse control signal output terminal of each pulse modulation sub-circuit is electrically connected to the signal input terminal of the all-digital power amplifier to output a pulse control signal to the all-digital power amplifier. Wherein: The pulse generation sub-circuit includes at least two D flip-flops. The clock input port of each D flip-flop is connected to the same clock signal. The data input port of the first D flip-flop is connected to the power supply. The data input ports of the remaining D flip-flops are respectively connected to the data output ports of the preceding D flip-flop. The signal lines leading from the data output ports of the D flip-flops are sequentially used as the first pulse signal output terminal, the second pulse signal output terminal, and so on, up to the nth pulse signal output terminal of the pulse generation sub-circuit. The number of D flip-flops is greater than or equal to n. Each pulse modulation sub-circuit is a gate combination circuit, which includes XOR gates and NOR gates, wherein: The two input terminals of the XOR gate are respectively used as the first pulse signal input terminal and the second pulse signal input terminal of the pulse modulation sub-circuit, and the output terminal is electrically connected to one input terminal of the NOR gate. The other input terminal of the NOR gate is the pulse width control signal input terminal of the pulse modulation sub-circuit, and the output terminal of the NOR gate is the pulse control signal output terminal of the pulse modulation sub-circuit. The all-digital power amplifier includes a differential amplifier module controlled by a pulse control signal output from the direct pulse generation circuit, and the differential amplifier module is composed of a common-source common-gate transistor. The differential amplifier module includes symmetrically designed two-sided paths, each side path including at least one column of branches, and each column of branches including a first electronic switch and a second electronic switch connected in series, wherein: The gate of the first electronic switch in each path is electrically connected to the output terminal of each pulse control signal of the direct pulse generation circuit, the drain is electrically connected to the output terminal of the differential amplifier module corresponding to that side, and the source is electrically connected to the drain of the corresponding second electronic switch. The gate of the second electronic switch in each path is electrically connected to one of the pair of differential signals formed by the clock signal of the pulse generation sub-circuit, and the drain is grounded.
2. The pulse radar transmitter chip according to claim 1, characterized in that, In the pulse generation sub-circuit, the signal lines from the data output ports of each D flip-flop are sequentially led out as the first pulse signal output terminal, the second pulse signal output terminal, and the nth pulse signal output terminal, respectively. Alternatively, in the pulse generation sub-circuit, starting from the first D flip-flop, the signal lines leading out from the data output ports of the odd-numbered D flip-flops are sequentially used as the first pulse signal output terminal, the second pulse signal output terminal, and so on up to the nth pulse signal output terminal. Alternatively, in the pulse generation sub-circuit, starting from the second D flip-flop, the signal lines leading out from the data output ports of the even-numbered D flip-flops are respectively used as the first pulse signal output terminal, the second pulse signal output terminal, and so on up to the nth pulse signal output terminal.
3. The pulse radar transmitter chip according to claim 1, characterized in that, The first pulse signal input terminal of each pulse modulation sub-circuit is electrically connected to the m-th pulse signal output terminal to the first pulse signal output terminal of the pulse generation sub-circuit, respectively. The second pulse signal input terminal of each pulse modulation sub-circuit is electrically connected to the n-m+1-th pulse signal output terminal to the n-th pulse signal output terminal of the pulse generation sub-circuit, respectively. The pulse width control signal input terminal of each pulse modulation sub-circuit is used to receive the m-th pulse width control signal to the first pulse width control signal. The pulse control signal output terminal of each pulse modulation sub-circuit is electrically connected to the signal input terminal of the all-digital power amplifier to output the m-th pulse control signal to the first pulse control signal to the all-digital power amplifier, where m is n / 2 rounded down.
4. The pulse radar transmitter chip according to claim 3, characterized in that, n is an integer greater than or equal to 4, and m is an integer greater than or equal to 2.
5. The pulse radar transmitter chip according to claim 1, characterized in that, The gate combination circuit further includes a first inverter and / or a second inverter, wherein: The first inverter is electrically connected between the output terminal of the XOR gate and the input terminal of the NOR gate; The input terminal of the second inverter is electrically connected to the output terminal of the NOR gate, and the output terminal of the second inverter serves as the pulse control signal output terminal of the pulse modulation sub-circuit.
6. The pulse radar transmitter chip according to claim 1, characterized in that, Both the first electronic switch and the second electronic switch are P-type; And / or, each side path includes at least two columns of said branches connected in parallel.
7. The pulse radar transmitter chip according to claim 1, characterized in that, The output matching network includes an on-chip transformer.
8. The pulse radar transmitter chip according to claim 7, characterized in that, The two ends of the primary coil of the on-chip transformer are electrically connected to the amplified signal output terminal of the all-digital power amplifier, and one end of the secondary coil of the on-chip transformer serves as the output terminal of the pulse radar transmitter chip, while the other end is grounded.
9. An electronic device, characterized in that, Includes the pulse radar transmitter chip as described in any one of claims 1-8.