Encrypted burst communication receiving method realized based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses an encryption burst communication receiving method based on an FPGA, and belongs to the technical field of burst communication. According to the invention, the problems of poor synchronization performance and poor anti-interference capability at the receiving end in the existing method are solved. According to the method, the carrier synchronization range is expanded by introducing the pilot frequency to enable the synchronization heads to be '1', the limitation that a conventional frequency offset estimation algorithm can only work under the condition that the Doppler frequency shift is smaller than 0.5 times of the symbol rate is broken through, and the capacity of the system for adapting to the high-dynamic environment is improved. A spreading code continuous tracking working mode is designed, coarse estimation and synchronization are carried out in a frame header part, spreading codes are still adopted in an information part, and continuous tracking is carried out, so that the system can adjust the phase of the spreading codes in real time in the whole frame to solve the problem of phase error accumulation caused by adopting a low-precision clock; the problems that when one frame of data at the sending end is long, the synchronization performance is reduced when a low-precision clock is adopted, and even effective synchronization cannot be achieved are solved. The method can be applied to the field of burst communication.

Description

Technical Field

[0001] This invention belongs to the field of burst communication technology, specifically relating to an encrypted burst communication receiving method based on FPGA implementation. Background Technology

[0002] Burst communication, with its discontinuous information transmission and uncertain start and end times, possesses strong concealment and is difficult to intercept. Furthermore, its anti-interference capabilities are enhanced by technologies such as frequency hopping, and it can flexibly utilize fragmented frequency bands to improve spectral efficiency. It has important applications in satellite communication and aerospace telemetry and control. Traditional burst communication systems often have high requirements for the accuracy of transmitting and receiving clocks. Using high-precision clocks increases production costs, significantly limiting the application of burst communication technology. However, using low-precision clocks leads to inconsistencies in the center frequencies of transmitting and receiving clocks, and the unstable clock frequency fluctuates around the center frequency, also causing frequency deviations. When a burst communication frame is long, this frequency deviation causes phase errors to accumulate within a frame, significantly degrading the synchronization performance of the receiver and even preventing effective synchronization. Moreover, in communication scenarios involving high-speed movement of low-Earth orbit satellites, burst communication technology is also subject to various interference factors such as interference signals, environmental noise, and Doppler shift. These factors can severely interfere with communication signals, increasing the difficulty of demodulation at the receiver.

[0003] Therefore, designing a burst communication frame structure that can adapt to high dynamic environments using a low-precision clock, and designing a corresponding receiving method based on the frame structure, is essential for reducing product production costs, improving receiver synchronization performance, and enhancing system anti-interference capabilities. Summary of the Invention

[0004] This invention addresses the problems of poor synchronization performance and anti-interference capability at the receiving end in existing methods by proposing an encrypted burst communication receiving method based on FPGA implementation.

[0005] The technical solution adopted by this invention to solve the above-mentioned technical problems is: an encrypted burst communication receiving method based on FPGA, the method specifically including the following steps:

[0006] Step 1: The transmitting end modulates the data frame, which includes the frame header and the information payload, and then transmits the modulated data frame.

[0007] Step 2: The receiving end multiplies the received signal by the local carrier to obtain the in-phase branch signal. and orthogonal branch signals ;

[0008] In-phase branch signal and orthogonal branch signals The data are fed into shift registers, and the spreading code sequence read from the FPGA's random access memory is used as the coefficients of the matched filter.

[0009] The matched filter coefficients and the in-phase branch signal After multiplying the outputs of the shift register, the multiplication results are accumulated, and the square of the accumulated results is calculated to obtain the relevant integral results of the in-phase branch.

[0010] The matched filter coefficients and the quadrature branch signals After multiplying the outputs of the shift registers, the multiplication results are accumulated, and the square of the accumulated results is calculated to obtain the relevant integral results of the orthogonal branches.

[0011] The correlation integral results of the in-phase branches and the correlation integral results of the orthogonal branches are added together to obtain the final correlation integral result;

[0012] step

[0013] Step 3: Make a decision on the final relevant integral result, that is, compare the final relevant integral result with the decision threshold:

[0014] If the final correlation integral result is greater than the decision threshold, the pseudocode acquisition is successful, the starting position of the spreading code is output, and then step four is executed.

[0015] If the final relevant integral result is not greater than the decision threshold, return to step two to continue processing the received signal;

[0016] Step 4: Based on the in-phase branch signal Orthogonal branch signals The system continuously tracks the starting position of the spreading code, performs carrier synchronization, spreading code tracking, and demodulation of received data based on the continuous tracking results, until the synchronization lock-out state is reached. Then, the system is reset and returns to step two to capture the pseudocode of the next data frame.

[0017] Furthermore, the local carrier includes an in-phase carrier and a quadrature carrier, wherein the in-phase carrier is... The orthogonal carrier is , Indicates the carrier frequency. Indicates time.

[0018] Furthermore, after the pseudocode is successfully captured, the backward protection process in the decision phase is initiated simultaneously with the continuous tracking process. The specific backward protection process in the decision phase is as follows:

[0019] The correlation integral result of the matched filter output is continuously monitored to see if it is greater than the threshold. When the correlation integral result of the matched filter output is not greater than the threshold, the number of anti-lockdown protection times is increased by 1.

[0020] No action is needed before the number of anti-lockout protection cycles exceeds b. The value of b here can be set based on experience.

[0021] After the number of anti-lockout protection attempts exceeds b, the system is immediately reset and the number of anti-lockout protection attempts is cleared to 0, and the pseudocode capture of the next frame begins.

[0022] Furthermore, the specific process of spreading code tracking is as follows:

[0023] Step A1: Obtain the lead branch spreading code and the lag branch spreading code from the FPGA's random access memory. It should be noted that the lead branch spreading code, the lag branch spreading code, and the current branch spreading code are all read from the random access memory. However, the lead branch spreading code is half a chip time ahead of the current branch spreading code, and the lag branch spreading code is half a chip time behind the current branch spreading code.

[0024] The spread spectrum code of the lead branch and the signal of the in-phase branch are combined. The correlation value is obtained by performing correlation and integration operations, and then the square of the correlation value is used as the correlation integration result of the in-phase branch based on the lead branch spreading code;

[0025] The lead branch spreading code and the quadrature branch signal The correlation value is obtained by performing correlation and integration operations, and then the square of the correlation value is used as the correlation integration result of the orthogonal branch based on the lead branch spreading code;

[0026] The correlation integral result of the in-phase branch based on the lead branch spreading code is added to the correlation integral result of the quadrature branch based on the lead branch spreading code to obtain the final correlation integral result based on the lead branch spreading code.

[0027] The lagging branch spreading code and the in-phase branch signal The correlation value is obtained by performing correlation and integration operations, and then the square of the correlation value is used as the correlation integration result of the in-phase branch based on the hysteresis branch spreading code;

[0028] The lag branch spreading code and the quadrature branch signal The correlation value is obtained by performing correlation and integration operations, and the square of the correlation value is used as the orthogonal branch correlation integration result based on the hysteresis branch spreading code;

[0029] The correlation integral result of the in-phase branch based on the lag branch spreading code is added to the correlation integral result of the quadrature branch based on the lag branch spreading code to obtain the final correlation integral result based on the lag branch spreading code.

[0030] Step A2: Determine if the condition is met: The final correlation integral result based on the lead branch spreading code or the final correlation integral result based on the lag branch spreading code is greater than the threshold. ;

[0031] If the conditions are met, proceed to step A3;

[0032] If the conditions are not met, proceed to step A4;

[0033] Step A3: Determine whether the following condition is met: the final correlation integral result based on the lead branch spreading code is greater than the final correlation integral result based on the lag branch spreading code;

[0034] If satisfied, an enable signal adjust_en is sent to the spreading code generator to reduce the spreading code output clock period by increasing the counting step length, and then the process returns to step A1.

[0035] If the condition is not met, no action is required; simply return to step A1.

[0036] Step A4: Increment the number of anti-lockout protection counts by 1 (the number of anti-lockout protection counts is initially initialized to 0), and then determine whether the number of anti-lockout protection counts is greater than b times;

[0037] If the number of times the anti-lockout protection is applied is no more than b, no action is required, and the process can directly return to step A1.

[0038] If the number of anti-lockout protection attempts exceeds b, the system will be reset and the backward protection count will be cleared to zero before starting the next pseudocode capture.

[0039] Furthermore, the specific processes of carrier synchronization and receiver data demodulation are as follows:

[0040] Step B1: Based on the in-phase branch signal And the in-phase branch signal obtained from the current branch spreading code. According to the orthogonal branch signals And the current branch spreading code to obtain the orthogonal branch signal ;

[0041] The receiver obtains the orthogonal branch signal based on the current branch spreading code. Demodulate the information sent by the sender;

[0042] Step B2, convert the in-phase branch signal and orthogonal branch signals These are respectively used as the real and imaginary parts of the current symbol code, i.e., the despreading... The expression for each information symbol code element is:

[0043] (1)

[0044] in, For frequency offset, For local carrier phase, Indicates the first The BPSK modulation phase of each information symbol code element Equivalent Gaussian white noise, The base of the natural logarithm. Represents the imaginary unit;

[0045] The final coarse frequency offset estimation result is obtained based on the conjugate complex multiplication result of 16 pairs of adjacent information symbol codes, and the fine frequency offset estimation result is obtained based on the 16 sets of coarse frequency offset estimation results.

[0046] Step B3: Convert the calculated fine frequency offset estimation result and the final coarse frequency offset estimation result into a frequency control word. Doppler frequency shift compensation of the carrier is performed by adding a frequency control word adjustment amount to the original frequency control word of the numerically controlled oscillator IP core. Then, the carrier phase offset is estimated based on the received information symbol symbols.

[0047] The phase offset estimation result is then fed into the IP core of the numerically controlled oscillator to complete the phase offset compensation, and the actual in-phase carrier and quadrature carrier of the received signal are output for further down-conversion processing of the received signal.

[0048] Furthermore, the final coarse frequency offset estimation result is obtained based on the conjugate complex multiplication of 16 pairs of adjacent information symbol codes, specifically as follows:

[0049] Calculate the first Information symbol code element With the The result of the conjugate complex multiplication of each information symbol code element:

[0050] (2)

[0051] in, The first part represents the despreading. Information symbol code element conjugate, The sampling interval is... Indicates the first The BPSK modulation phase of each information symbol code element This represents the signal after multiplication (i.e., the result of conjugate complex multiplication).

[0052] The frequency offset is estimated based on the arctangent function as follows:

[0053] (4)

[0054] in, This represents the real part of the signal after multiplication. This represents the imaginary part of the signal after multiplication. Indicates based on the first The first information symbol code element and the first Frequency offset estimation results for each information symbol code element;

[0055] (5)

[0056] in, Indicates based on the first The first information symbol code element and the first Frequency offset estimation results for each information symbol code element This represents the final coarse frequency offset estimation result (i.e., as a final coarse frequency offset estimation result).

[0057] Furthermore, the process of obtaining the fine frequency offset estimation result based on the 16 sets of coarse frequency offset estimation results is specifically as follows:

[0058] (6)

[0059] in, Indicates the first The final coarse frequency offset estimation result of the second step. This represents the result of the fine frequency bias estimation.

[0060] Furthermore, the calculated final coarse frequency offset estimate is converted into a frequency control word, specifically:

[0061] (7)

[0062] in, It is the clock frequency of the IP core of the numerically controlled oscillator. The number of bits for the frequency control word. This is the frequency control word adjustment amount based on the coarse frequency offset estimation result.

[0063] Furthermore, the calculated fine frequency offset estimation result is converted into a frequency control word, specifically:

[0064] (8)

[0065] in, This is the frequency control word adjustment amount based on the precise frequency offset estimation result.

[0066] Furthermore, the estimation process for the carrier phase offset is as follows:

[0067] After squaring the received information symbol code and then taking the phase, we have:

[0068] (9)

[0069] in, Indicates the received number Each information symbol code element, Indicates taking the phase. Indicates the first The BPSK modulation phase of each information symbol code element The value is 0 or ,

[0070] but The phase is:

[0071] (10)

[0072] The final phase bias estimation result is as follows:

[0073] (11)

[0074] in, This represents the final phase bias estimation result. Indicates the received number The phase of each information symbol code element.

[0075] The beneficial effects of this invention are:

[0076] This invention proposes a frame structure that expands the carrier synchronization range by introducing pilot signals to make the synchronization header all "1"s. This overcomes the limitation of conventional frequency offset estimation algorithms, which can only operate at Doppler shifts less than 0.5 times the symbol rate, thus increasing the system's adaptability to highly dynamic environments. Simultaneously, to prevent malicious information theft by other users, complex orthogonal codes are used for encryption in the information portion of the frame structure, improving information security. Furthermore, a continuous tracking mode for the spreading code is designed. Coarse estimation and synchronization are performed in the frame header, while the spreading code is still used for continuous tracking in the information portion. This allows the system to adjust the spreading code phase in real time throughout the frame to address the phase error accumulation problem caused by the use of a low-precision clock. It also solves the problem of decreased synchronization performance or even ineffective synchronization when using a low-precision clock for long data frames at the transmitting end.

[0077] The method of this invention can be implemented using a low-precision clock, thus indirectly reducing the cost of the product; at the same time, by introducing backward protection, it prevents the correlation peak from suddenly dropping below the threshold under high dynamic environment, which would cause the pseudo-code synchronization ring to lose lock and lead to the problem of missing symbols, thereby enhancing the anti-interference capability of the system. Attached Figure Description

[0078] Figure 1 This is a flowchart of an encrypted burst communication receiving method based on FPGA according to the present invention;

[0079] Figure 2This is a schematic diagram of the frame structure designed by the method of the present invention;

[0080] Figure 3 This is an interaction diagram of the various parts of this invention implemented using FPGA;

[0081] In the diagram: DDS is a numerically controlled oscillator. The in-phase carrier recovered by the numerically controlled oscillator. For the quadrature carrier recovered by the numerically controlled oscillator, pn_code is the pre-generated spreading code read out in segments and stored in RAM, pn_lead is the spreading code of the leading branch, pn_lag is the spreading code of the lagging branch, pn_lag is the spreading code of the current branch, adjust_en is the spreading code phase adjustment enable signal, I_in represents the output signal of the in-phase branch after integration with the spreading code period as the integration time, and Q_in represents the output signal of the quadrature branch after integration with the spreading code period as the integration time.

[0082] Figure 4 This is a schematic diagram of the segmented matched filter used in the acquisition process of this invention;

[0083] In the diagram: sample_clk is the sampling clock. It is a spreading code. This invention takes a 1024-bit spreading code sequence as an example. Indicates the first in the spreading code sequence Bit, This represents a 256-bit 16-bit shift register connected end to end. This indicates that the shift register is located at the th position in this structure. One location, It is a multiplexer. This indicates that the multiplexer is located at the first position in this structure. In each position, the MCU is a multiplexer;

[0084] Figure 5 This is a flowchart of the capture and backward protection process of the present invention;

[0085] Figure 6 This is a flowchart of the continuous tracking process of the present invention;

[0086] Figure 7 This is a schematic diagram of the received baseband signal and local spreading code when continuous code tracking is not used;

[0087] Figure 8 This is a schematic diagram of the received baseband signal and the local spreading code when using continuous code tracking. Detailed Implementation

[0088] This invention first designs the frame structure at the transmitting end, such as... Figure 2 As shown, a frame of data includes two parts: a frame header and a payload. The frame header consists of a synchronization header (SYNC) and a frame delimiter (SFD).

[0089] (1) The synchronization header is generated by the transmitter spreading the all-1 data using pseudocode. The generated synchronization header is mainly used by the receiver to capture burst packets and correct frequency and phase offsets. The length of the synchronization header can be selected by the user, but it must be greater than the length of information bits required to complete one capture, one coarse frequency offset estimation, one fine frequency offset estimation, and one phase offset estimation. The synchronization header in this invention is 293 bits, which is sufficient to complete one coarse frequency offset estimation, one fine frequency offset estimation, and one phase offset estimation, and reserves enough data length for the initial capture process.

[0090] Furthermore, it should be noted that the pseudocode used by the transmitting end should be a code group with sharp autocorrelation and low cross-correlation characteristics, such as an m-sequence or a Gold sequence.

[0091] (2) Frame delimiters can assist in pseudocode fine synchronization. The SFD segment is a user-defined frame delimiter with the lowest possible probability of occurrence. In this invention, the EB90 segment with an extremely low probability of occurrence is used as the SFD segment. After the receiver demodulates to the EB90, the location of the information payload can be quickly located.

[0092] (3) The information payload needs to be encrypted using complex orthogonal codes. In order to continuously track the information part, the code group selected by this invention should have strong pseudo-randomness, sharp autocorrelation characteristics and low cross-correlation characteristics, for example, the sequence after truncating a long m sequence.

[0093] It should also be noted that the method of the present invention processes the received signal in real time. Therefore, the signals processed by the same processing method in the present invention are all signals that enter the receiving end in real time when the same method is run multiple times, rather than the same signal being processed repeatedly.

[0094] Specific implementation method one: Combining Figure 1 and Figure 3 This embodiment describes an encrypted burst communication receiving method implemented using FPGA. The method specifically includes the following steps:

[0095] Step 1: After the transmitting end modulates the data frame, which includes the frame header and the information payload, it transmits the modulated data frame using burst communication.

[0096] Step 2: The receiving end multiplies the received signal by the local carrier (i.e., removes the carrier modulated on the received signal through down-conversion processing) to obtain the in-phase branch signal. and orthogonal branch signals ;

[0097] The local carrier includes in-phase carriers and quadrature carriers, wherein the in-phase carrier is... The orthogonal carrier is , Indicates the carrier frequency. Indicates time;

[0098] In-phase branch signal and orthogonal branch signals The data are fed into shift registers, and the spreading code sequence read from the FPGA's Random Access Memory (RAM) is used as the coefficients of the matched filter. Figure 3 The spreading code generator includes a spreading code generator and a random access memory (RAM). The spreading code generator generates the spreading code, which is then stored in the RAM. The spreading code generated by the spreading code generator has the same function as the pseudo-code used for spreading at the transmitter. Furthermore, the spreading code sequence is read in four segments, and using the same multiplication structure for all four segments effectively reduces resource consumption.

[0099] The matched filter coefficients and the in-phase branch signal After multiplying the output of the shift register, the multi-stage adder uses a pipelined approach to accumulate the multiplication results, and then calculates the square of the accumulated results to obtain the relevant integral results of the in-phase branch.

[0100] The matched filter coefficients and the quadrature branch signals After multiplying the output of the shift register, the multi-stage adder uses a pipelined approach to accumulate the multiplication results, and then calculates the square of the accumulated results to obtain the relevant integral results of the orthogonal branch.

[0101] The correlation integral results of the in-phase branches and the correlation integral results of the orthogonal branches are added together to obtain the final correlation integral result;

[0102] It should be noted that the matched filter structure in this invention is as follows: Figure 4 As shown, this invention takes a 16x oversampling rate as an example. Therefore, in order to maximize the utilization of the time of each spreading code, a 16-bit shift register is used. Since the number of bits of each spreading code is 256, 256 16-bit registers are needed. The output of the last-stage shift register is sent to the first-stage shift register. Under the control of the sampling clock, a baseband sampling signal is sent every 4 clock cycles. The output of the last-stage shift register is used as the input of the first-stage shift register for the remaining 3 clock cycles. In this way, after a certain period of time, the data will fill the entire shift register.

[0103] Furthermore, in order to reduce the resource consumption related to the calculation signal and the spreading code during the actual calculation, the correlation operation of one cycle is divided into four segments for calculation. The four segments of the spreading code share the same calculation module, thereby reducing the resource consumption to 1 / 4 of the original.

[0104] Step 3: Make a decision on the final relevant integral result, that is, compare the final relevant integral result with the decision threshold:

[0105] If the final correlation integral result is greater than the decision threshold, the pseudocode acquisition is successful, the starting position of the spreading code is output (i.e., the timing reference of the output symbol), and then step four is executed;

[0106] If the final relevant integral result is not greater than the decision threshold, return to step two to continue processing the received signal;

[0107] Step 4: Based on the in-phase branch signal Orthogonal branch signals The system continuously tracks the starting position of the spreading code (all related operations during the continuous tracking process require the participation of the starting position of the spreading code). Based on the continuous tracking results, it performs carrier synchronization, spreading code tracking, and demodulation of received data until the synchronization loss state is reached. Then, the system is reset and returns to step two to capture the pseudocode of the next data frame.

[0108] Furthermore, once the pseudocode is successfully captured, the backward protection process in the decision phase and the continuous tracking process are initiated simultaneously, such as... Figure 5 As shown, the backward protection process in the judgment stage is as follows:

[0109] The system continuously monitors whether the correlation integral result of the matched filter output is greater than the threshold. Whenever the correlation integral result of the matched filter output is not greater than the threshold, the number of anti-lock-out protection counts is increased by 1. Synchronization is maintained until the number of anti-lock-out protection counts is greater than b. After the number of anti-lock-out protection counts is greater than b, the system is immediately reset and the number of anti-lock-out protection counts is cleared to 0, and the pseudocode capture of the next frame begins.

[0110] The spreading code tracking and carrier synchronization processes are explained in detail below:

[0111] 1. Spread code tracking:

[0112] Because the transmit and receive clocks are out of sync, the phase difference between the signal spreading code and the local spreading code will continue to accumulate. Therefore, after the spreading code is successfully acquired, the phase of the spreading code needs to be tracked in real time and continuously throughout the entire frame time to ensure the accuracy of the spreading code bit synchronization. This is to achieve long frame burst communication code synchronization in the case of transmit and receive clock out of sync, and to prevent loss of lock after pseudo-code synchronization through backward protection.

[0113] like Figure 6As shown, the specific process of spreading code tracking is as follows:

[0114] Step A1: Obtain the lead branch spreading code and the lag branch spreading code from the FPGA's random access memory;

[0115] The spread spectrum code of the lead branch and the signal of the in-phase branch are combined. The correlation value is obtained by performing correlation and integration operations, and then the square of the correlation value is used as the correlation integration result of the in-phase branch based on the lead branch spreading code;

[0116] The lead branch spreading code and the quadrature branch signal The correlation value is obtained by performing correlation and integration operations, and then the square of the correlation value is used as the correlation integration result of the orthogonal branch based on the lead branch spreading code;

[0117] The correlation integral result of the in-phase branch based on the lead branch spreading code is added to the correlation integral result of the quadrature branch based on the lead branch spreading code to obtain the final correlation integral result based on the lead branch spreading code.

[0118] The lagging branch spreading code and the in-phase branch signal The correlation value is obtained by performing correlation and integration operations, and then the square of the correlation value is used as the correlation integration result of the in-phase branch based on the hysteresis branch spreading code;

[0119] The lag branch spreading code and the quadrature branch signal The correlation value is obtained by performing correlation and integration operations, and the square of the correlation value is used as the orthogonal branch correlation integration result based on the hysteresis branch spreading code;

[0120] The correlation integral result of the in-phase branch based on the lag branch spreading code is added to the correlation integral result of the quadrature branch based on the lag branch spreading code to obtain the final correlation integral result based on the lag branch spreading code.

[0121] Step A2: Determine if the condition is met: The final correlation integral result based on the lead branch spreading code or the final correlation integral result based on the lag branch spreading code is greater than the threshold. ;

[0122] If the conditions are met, proceed to step A3;

[0123] If the conditions are not met, proceed to step A4;

[0124] Step A3: Determine whether the following condition is met: the final correlation integral result based on the lead branch spreading code is greater than the final correlation integral result based on the lag branch spreading code;

[0125] If satisfied, an enable signal adjust_en is sent to the spreading code generator. The clock period of the spreading code output is reduced by increasing the counting step length, so that the phase of the signal information and the phase of the local spreading code slide relative to each other to adjust the phase until the final correlation integral value of the leading branch is nearly equal to the final correlation integral value of the lagging branch. Then, return to step A1 to continue to maintain synchronization.

[0126] If the conditions are not met, no action is required; return to step A1 to continue maintaining synchronization.

[0127] Step A4: Increment the number of anti-lockdown protection counts by 1, and then determine whether the number of anti-lockdown protection counts is greater than b times (During the synchronization process, due to the influence of channel noise interference on the receiver, the correlation peak may be lower than the threshold. Therefore, this invention sets the number of backward protection counts to b, that is, the number of times the correlation peak is lower than the threshold cannot exceed b times).

[0128] If the number of times the anti-lockout protection is not greater than b, no action is required, and the process can be directly returned to step A1 to continue maintaining synchronization.

[0129] If the number of anti-lockout protection attempts exceeds b, the system will be reset and the number of backward protection attempts will be cleared to zero. (It should be noted that if the number of anti-lockout protection attempts in either the backward protection of the decision section or the backward protection of the spreading code tracking section exceeds b, the system will be reset, and then the next pseudocode capture will begin.)

[0130] 2. Carrier synchronization and data demodulation

[0131] like Figure 3 As shown, the specific process of carrier synchronization and receiver data demodulation is as follows:

[0132] Step B1: Based on the in-phase branch signal And the in-phase branch signal obtained from the current branch spreading code. According to the orthogonal branch signals And the current branch spreading code to obtain the orthogonal branch signal ;

[0133] The receiver obtains the orthogonal branch signal based on the current branch spreading code. Demodulate the information sent by the sender;

[0134] Step B2, convert the in-phase branch signal and orthogonal branch signals These are respectively used as the real and imaginary parts of the current symbol code, i.e., the despreading... The expression for each information symbol code element is:

[0135] (1)

[0136] in, For frequency offset, For local carrier phase, Indicates the first The BPSK modulation phase of each information symbol code element Equivalent Gaussian white noise, The base of the natural logarithm. Represents the imaginary unit;

[0137] The cmpy IP core is used to perform conjugate complex multiplication on two adjacent symbol codes. The real and imaginary parts of the two multiplicands are concatenated as the input of the multiplier. The first 22 bits of the input current signal are used as the real part, and the 25th to 46th bits of the input delay signal are used as the imaginary part. The first 45 bits of the multiplier output are the real part, and the 49th to 93rd bits are the imaginary part.

[0138] The result of conjugate complex multiplication of adjacent symbols is:

[0139] (2)

[0140] in, The first part represents the despreading. Information symbol code element conjugate, The sampling interval is... Indicates the first The BPSK modulation phase of each information symbol code element This indicates the signal after multiplication;

[0141] Signal after multiplication phase for:

[0142] (3)

[0143] Frequency offset estimation under DPSK modulation that relies on conventional data The possible values ​​are In order to leave only the frequency-related terms in formula (3), it is necessary to remove The process involves transforming data falling in the second and third quadrants to the first and fourth quadrants. However, when the frequency offset term itself falls in the second and third quadrants, this operation will incorrectly transform the data to the first and fourth quadrants. This is why conventional frequency offset estimation algorithms that rely on data have limited frequency estimation capabilities. However, this invention only performs frequency offset estimation at the frame header pilot, and this part of the data frame is designed as a sequence of all 1s. Since it is always 0, we have Therefore, the frequency offset is estimated based on the arctangent function as follows:

[0144] (4)

[0145] in, This represents the real part of the signal after multiplication. This represents the imaginary part of the signal after multiplication. Indicates based on the first The first information symbol code element and the first Frequency offset estimation results for each information symbol code element;

[0146] To reduce the impact of noise, this invention takes the average of 16 frequency offset estimation results as the final coarse frequency offset estimation result, and then averages the 16 coarse frequency offset estimation results to obtain the final fine frequency offset estimation result. Since the frame header length in this invention is 293 bits, after the frame header completes the coarse and fine frequency offset estimation, there is still enough length left for the initial capture, while ensuring a good suppression effect on noise.

[0147] (5)

[0148] in, Indicates based on the first The first information symbol code element and the first Frequency offset estimation results for each information symbol code element This represents the final coarse frequency offset estimation result;

[0149] (6)

[0150] in, Indicates the first The final coarse frequency offset estimation result of the second step. This indicates the result of the fine frequency offset estimation;

[0151] Step B3: Convert the calculated fine frequency offset estimation results and the final coarse frequency offset estimation results into frequency control words:

[0152] (7)

[0153] (8)

[0154] in, It is the clock frequency of the IP core of the numerically controlled oscillator. The number of bits for the frequency control word. The frequency control word adjustment amount is based on the coarse frequency offset estimation result. This is the frequency control word adjustment amount based on the precise frequency offset estimation result;

[0155] Doppler frequency shift compensation for the carrier is achieved by adding a frequency control word adjustment to the original frequency control word of the IP core of the numerically controlled oscillator (the final coarse frequency offset estimation result is sent to the direct digital frequency generator to complete the coarse frequency correction, then the fine frequency offset estimation is started, and the local carrier is compensated again using the obtained fine frequency estimation value), and then the carrier phase offset is estimated based on the information symbol code elements that are received.

[0156] The specific process of estimating the carrier phase offset based on the continuously received information symbol code is as follows:

[0157] Since carrier frequency offset estimation and compensation have been completed, the residual frequency offset can be considered to be close to 0 at this point. Taking the phase of the received information symbol after squaring the symbol, we have:

[0158] (9)

[0159] in, Indicates the received number Each information symbol code element, Indicates taking the phase. Indicates the first The BPSK modulation phase of each information symbol code element The value is 0 or ,

[0160] but The phase is:

[0161] (10)

[0162] To reduce the impact of noise, this invention averages the results of eight phase bias estimates as the final phase bias estimate. That is, the final phase bias estimate is:

[0163] (11)

[0164] in, This represents the final phase bias estimation result. Indicates the received number The phase of each information symbol code element;

[0165] The phase offset estimation result is then fed into the IP core of the numerically controlled oscillator to complete the phase offset compensation, and the actual in-phase carrier and quadrature carrier of the received signal are output.

[0166] It should also be noted that although the frequency offset is assumed to be 0 during calculation, there may still be a small residual frequency offset after fine frequency offset compensation. Therefore, phase offset estimation needs to continue working in the remaining frames. Through continuous phase offset estimation, the frequency drift of the transmitter can be compensated in real time, making demodulation more accurate.

[0167] from Figure 7 As can be seen, when a lower precision clock is used, resulting in a large deviation between the transmit and receive clocks, without continuous code tracking, the phase deviation between the signal spreading code and the local spreading code within a long frame will increase over time, severely impacting subsequent despreading and demodulation. The code synchronization result of the method in this invention is as follows... Figure 8 As shown, the spreading code generated by the method of the present invention is always aligned with the signal spreading code, effectively avoiding the problem of asynchronous transmitting and receiving spreading code clocks affecting despreading and demodulation.

[0168] The above examples of the present invention are merely illustrative of the computational model and process of the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is impossible to exhaustively list all possible implementations here. Any obvious variations or modifications derived from the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A method for receiving encrypted burst communication based on FPGA, characterized in that, The method specifically includes the following steps: Step 1: The transmitting end modulates the data frame, which includes the frame header and the information payload, and then transmits the modulated data frame. Step 2: The receiving end multiplies the received signal by the local carrier to obtain the in-phase branch signal. and orthogonal branch signals ; In-phase branch signal and orthogonal branch signals The data are fed into shift registers, and the spreading code sequence read from the FPGA's random access memory is used as the coefficients of the matched filter. The matched filter coefficients and the in-phase branch signal After multiplying the outputs of the shift register, the multiplication results are accumulated, and the square of the accumulated results is calculated to obtain the relevant integral results of the in-phase branch. The matched filter coefficients and the quadrature branch signals After multiplying the outputs of the shift registers, the multiplication results are accumulated, and the square of the accumulated results is calculated to obtain the relevant integral results of the orthogonal branches. The correlation integral results of the in-phase branches and the correlation integral results of the orthogonal branches are added together to obtain the final correlation integral result; step Step 3: Make a decision on the final relevant integral result, that is, compare the final relevant integral result with the decision threshold: If the final correlation integral result is greater than the decision threshold, the pseudocode acquisition is successful, the starting position of the spreading code is output, and then step four is executed. If the final relevant integral result is not greater than the decision threshold, return to step two to continue processing the received signal; Step 4: Based on the in-phase branch signal Orthogonal branch signals The system continuously tracks the starting position of the spreading code, performs carrier synchronization, spreading code tracking, and demodulation of received data based on the continuous tracking results, until the synchronization lock-out state is reached. Then, the system is reset and returns to step two to capture the pseudocode of the next data frame.

2. The encrypted burst communication receiving method based on FPGA according to claim 1, characterized in that, The local carrier includes in-phase carriers and quadrature carriers, wherein the in-phase carrier is... The orthogonal carrier is , Indicates the carrier frequency. Indicates time.

3. The encrypted burst communication receiving method based on FPGA according to claim 2, characterized in that, Once the pseudocode is successfully captured, the backward protection process in the decision phase begins simultaneously with the continuous tracking process. The specific backward protection process in the decision phase is as follows: The correlation integral result of the matched filter output is continuously monitored to see if it is greater than the threshold. When the correlation integral result of the matched filter output is not greater than the threshold, the number of anti-lockdown protection times is increased by 1. No action is required until the number of anti-lockout protection cycles exceeds b. After the number of anti-lockout protection attempts exceeds b, the system is immediately reset and the number of anti-lockout protection attempts is cleared to 0, and the pseudocode capture of the next frame begins.

4. The encrypted burst communication receiving method based on FPGA according to claim 3, characterized in that, The specific process of spreading code tracking is as follows: Step A1: Obtain the lead branch spreading code and the lag branch spreading code from the FPGA's random access memory. It should be noted that the lead branch spreading code, the lag branch spreading code, and the current branch spreading code are all read from the random access memory. However, the lead branch spreading code is half a chip time ahead of the current branch spreading code, and the lag branch spreading code is half a chip time behind the current branch spreading code. The spread spectrum code of the lead branch and the signal of the in-phase branch are combined. The correlation value is obtained by performing correlation and integration operations, and then the square of the correlation value is used as the correlation integration result of the in-phase branch based on the lead branch spreading code; The lead branch spreading code and the quadrature branch signal The correlation value is obtained by performing correlation and integration operations, and then the square of the correlation value is used as the correlation integration result of the orthogonal branch based on the lead branch spreading code; The correlation integral result of the in-phase branch based on the lead branch spreading code is added to the correlation integral result of the quadrature branch based on the lead branch spreading code to obtain the final correlation integral result based on the lead branch spreading code. The lagging branch spreading code and the in-phase branch signal The correlation value is obtained by performing correlation and integration operations, and then the square of the correlation value is used as the correlation integration result of the in-phase branch based on the hysteresis branch spreading code; The lag branch spreading code and the quadrature branch signal The correlation value is obtained by performing correlation and integration operations, and the square of the correlation value is used as the orthogonal branch correlation integration result based on the hysteresis branch spreading code; The correlation integral result of the in-phase branch based on the lag branch spreading code is added to the correlation integral result of the quadrature branch based on the lag branch spreading code to obtain the final correlation integral result based on the lag branch spreading code. Step A2: Determine if the condition is met: The final correlation integral result based on the lead branch spreading code or the final correlation integral result based on the lag branch spreading code is greater than the threshold. ; If the conditions are met, proceed to step A3; If the conditions are not met, proceed to step A4; Step A3: Determine whether the following condition is met: the final correlation integral result based on the lead branch spreading code is greater than the final correlation integral result based on the lag branch spreading code; If satisfied, send an enable signal adjust_en to the spreading code generator to reduce the spreading code output clock period, and return to step A1. If the condition is not met, no action is required; simply return to step A1. Step A4: Increment the number of anti-lockout protection attempts by 1, and then determine whether the number of anti-lockout protection attempts is greater than b. If the number of times the anti-lockout protection is applied is no more than b, no action is required, and the process can directly return to step A1. If the number of anti-lockout protection attempts exceeds b, the system will be reset and the backward protection count will be cleared to zero before starting the next pseudocode capture.

5. The encrypted burst communication receiving method based on FPGA according to claim 4, characterized in that, The specific process of carrier synchronization and receiver data demodulation is as follows: Step B1: Based on the in-phase branch signal And the in-phase branch signal obtained from the current branch spreading code. According to the orthogonal branch signals And the current branch spreading code to obtain the orthogonal branch signal ; The receiver obtains the orthogonal branch signal based on the current branch spreading code. Demodulate the information sent by the sender; Step B2, convert the in-phase branch signal and orthogonal branch signals These are respectively used as the real and imaginary parts of the current symbol code, i.e., the despreading... The expression for each information symbol code element is: (1) in, For frequency offset, For local carrier phase, Indicates the first The BPSK modulation phase of each information symbol code element Equivalent Gaussian white noise, The base of the natural logarithm. Represents the imaginary unit; The final coarse frequency offset estimation result is obtained based on the conjugate complex multiplication result of 16 pairs of adjacent information symbol codes, and the fine frequency offset estimation result is obtained based on the 16 sets of coarse frequency offset estimation results. Step B3: Convert the calculated fine frequency offset estimation result and the final coarse frequency offset estimation result into a frequency control word. Doppler frequency shift compensation of the carrier is performed by adding a frequency control word adjustment amount to the original frequency control word of the numerically controlled oscillator IP core. Then, the carrier phase offset is estimated based on the received information symbol symbols. The phase offset estimation result is then fed into the IP core of the numerically controlled oscillator to complete the phase offset compensation, and the actual in-phase carrier and quadrature carrier of the received signal are output.

6. The encrypted burst communication receiving method based on FPGA according to claim 5, characterized in that, The final coarse frequency offset estimation result is obtained based on the conjugate complex multiplication of 16 pairs of adjacent information symbol codes, specifically as follows: Calculate the first Information symbol code element With the The result of the conjugate complex multiplication of each information symbol code element: (2) in, The first part represents the despreading. Information symbol code element conjugate, The sampling interval is... Indicates the first The BPSK modulation phase of each information symbol code element This indicates the signal after multiplication; The frequency offset is estimated based on the arctangent function as follows: (4) in, This represents the real part of the signal after multiplication. This represents the imaginary part of the signal after multiplication. Indicates based on the first The first information symbol code element and the first Frequency offset estimation results for each information symbol code element; (5) in, Indicates based on the first The first information symbol code element and the first Frequency offset estimation results for each information symbol code element This represents the final coarse frequency offset estimation result.

7. The encrypted burst communication receiving method based on FPGA according to claim 6, characterized in that, The fine frequency offset estimation result is obtained based on 16 sets of coarse frequency offset estimation results, specifically as follows: (6) in, Indicates the first The final coarse frequency offset estimation result of the second step. This represents the result of the fine frequency bias estimation.

8. The encrypted burst communication receiving method based on FPGA according to claim 7, characterized in that, The calculated final coarse frequency offset estimate is converted into a frequency control word, specifically: (7) in, It is the clock frequency of the IP core of the numerically controlled oscillator. The number of bits for the frequency control word. This is the frequency control word adjustment amount based on the coarse frequency offset estimation result.

9. The encrypted burst communication receiving method based on FPGA according to claim 8, characterized in that, The calculated fine frequency offset estimation result is converted into a frequency control word, specifically: (8) in, This is the frequency control word adjustment amount based on the precise frequency offset estimation result.

10. The encrypted burst communication receiving method based on FPGA according to claim 9, characterized in that, The process for estimating the carrier phase offset is as follows: After squaring the received information symbol code and then taking the phase, we have: (9) in, Indicates the received number Each information symbol code element, Indicates taking the phase. Indicates the first The BPSK modulation phase of each information symbol code element The value is 0 or , but The phase is: (10) The final phase bias estimation result is as follows: (11) in, This represents the final phase bias estimation result. Indicates the received number The phase of each information symbol code element.

Images