Servo controller for low-orbit constellation feed antenna

Abstract

The invention discloses a servo controller for a low-orbit constellation feed antenna, and the controller comprises a dual-core fault-tolerant main control unit (2) which is used for achieving the operation processing of a main control mode and a monitoring mode; the multi-channel intelligent power driving unit (3) is used for integrating a multi-channel circuit into a single package; the comprehensive interface management and health monitoring unit (4) is used for realizing external communication, signal acquisition, system state real-time monitoring and health data storage; the embedded test and on-orbit maintenance interface unit (5) is used for supporting on-orbit self-test, on-orbit software injection and on-orbit part hardware logic reconstruction, and the integrated packaging shell (1) is used for integrating all the units together. According to the invention, the bandwidth and the response speed of a servo loop can be greatly improved, and the relative motion of high-speed change between low-orbit constellations can be better tracked.

Description

Technical Field

[0001] This invention relates to the field of spacecraft attitude control and communication technology, and in particular to a servo controller for low-Earth orbit constellation feed antennas. Background Technology

[0002] Low Earth orbit (LEO) satellite constellations are the core infrastructure for realizing global high-speed communication networks. Their onboard feed link antennas need to establish and maintain high-precision, high-stability pointing between the earth station and the high-speed moving satellites, which places extremely stringent requirements on the dynamic performance, reliability, size, and weight of the servo control system.

[0003] In existing technologies, spaceborne antenna servo controllers typically employ a distributed architecture, where discrete modules such as control computers, power drivers, sensor interfaces, and communication units are interconnected via backplanes or cables. This architecture has the following inherent drawbacks: 1. Reliability bottleneck: Numerous connectors and cables between modules are a major source of single-point failures; electromagnetic compatibility (EMC) design is complex and susceptible to the effects of space radiation. 2. Low integration and large size and weight: Discrete modules occupy valuable space and weight resources on the satellite, hindering the application of miniaturized satellite platforms. 3. Performance limitations: Inter-module communication bandwidth and latency limit the improvement of control bandwidth, making it difficult to meet the requirements for rapid and accurate tracking of high-speed moving targets in low Earth orbit (such as adjacent satellites and ground stations). 4. Poor testability and maintainability: System-level testing is complex, and on-orbit software updates or fault reconfiguration are difficult.

[0004] Therefore, there is an urgent need for a servo controller solution that can adapt to harsh space environments and has high reliability, high integration, and high performance. Summary of the Invention

[0005] This invention provides a servo controller for low-Earth orbit constellation-fed antennas. Through a highly integrated architecture design, redundancy reconfiguration strategy, and intelligent health management, it significantly improves system reliability, reduces size and weight, enhances dynamic control performance, and improves on-orbit maintainability.

[0006] This invention is achieved using the following technical solution: a servo controller for a low-Earth orbit constellation-fed antenna, comprising an integrated package housing. The integrated package housing integrates a dual-core fault-tolerant main control unit, a multi-channel intelligent power drive unit, a comprehensive interface management and health monitoring unit, and an embedded test and on-orbit maintenance interface unit. The dual-core fault-tolerant main control unit is used to handle operation in both main control and monitoring modes; the multi-channel intelligent power drive unit integrates multi-channel circuits into a single package; the comprehensive interface management and health monitoring unit enables external communication, signal acquisition, real-time system status monitoring, and health data storage; and the embedded test and on-orbit maintenance interface unit supports on-orbit self-testing, on-orbit software injection, and on-orbit partial hardware logic reconfiguration.

[0007] Furthermore, the dual-core fault-tolerant main control unit, the multi-channel intelligent power drive unit, the integrated interface management and health monitoring unit, and the embedded test and on-orbit maintenance interface unit are all highly integrated physically and electrically on the integrated package housing via a high-speed on-chip bus and a custom redundant backplane.

[0008] Furthermore, the dual-core fault-tolerant main control unit integrates: The orbit and attitude calculation module is used to receive orbit and attitude data provided by the satellite system in real time, and integrate local sensor feedback from the antenna mechanism to calculate the antenna target pointing angle. The adaptive control algorithm module, based on advanced algorithms such as model predictive control or adaptive sliding mode control, calculates high-precision control commands in real time. The task and fault management module is used to realize task synchronization and cross-verification between the two cores, and seamlessly switch to the healthy core to run independently when a single core failure is detected, so as to realize fault tolerance management of faults and work.

[0009] Furthermore, the multi-channel intelligent power drive unit uses multi-chip module or system-in-package technology to integrate multiple drive channels into a single package, and each drive channel integrates an independent digital signal processor core for local execution of current loop closed-loop control.

[0010] Furthermore, the integrated interface management and health monitoring unit integrates: Multi-protocol communication interface, used to support multiple on-board standard buses for communication with satellite platforms; The sensor has a high-precision interface for connecting to a rotary transformer and an absolute encoder to achieve high-resolution angle digital conversion. The full-state health monitoring circuit is used to collect real-time data on voltage, current, temperature and radiation dose at key points inside the controller, and to perform threshold comparison and trend analysis. Non-volatile memory is used to store health history data, fault logs, and on-orbit maintenance procedures.

[0011] Furthermore, the boundary scan and high-speed data port provided by the embedded test and on-orbit maintenance interface unit support on-orbit self-test, on-orbit software injection, and on-orbit partial reconfiguration. The on-orbit partial reconfiguration is a dynamic reconfiguration of local logic functions at the programmable gate array (FPGA) device level to bypass permanently damaged units.

[0012] Furthermore, the high-speed on-chip bus adopts a star or dual-ring topology and has a time-triggered mechanism to ensure deterministic and low-latency data transmission between units.

[0013] Furthermore, the custom redundant backplane adopts a cold backup circuit design, integrates power distribution network and signal routing, and uses relays to physically isolate critical power and signal paths.

[0014] Furthermore, the servo controller is installed inside the satellite payload bay and is connected to the satellite's integrated electronic system via an RS422 bus to acquire orbital parameters and attitude references.

[0015] Furthermore, the servo controller employs a 2-out-of-3 checksum method to correct the particle flipping problem. Specifically, the 2-out-of-3 checksum method involves backing up the data to be checked into three copies and storing them in different addresses. The data of the same bit in the program is compared pairwise. If all the data are the same, it proves that the program content in that address is correct. If a bit is different, it indicates that the data content of that bit has shifted or changed and needs to be corrected. The data at that address is first bitwise ANDed, and then the three resulting data are bitwise ORed. The final data is the corrected data, and the corrected data content is rewritten into the corresponding storage address.

[0016] The beneficial effects of this invention are as follows: This invention has high reliability. It adopts a dual-core main control, redundant bus and cold backup circuit design to eliminate single point of failure. It can also monitor and predictive maintain in real time, turning passive maintenance into active prevention. In addition, the use of highly integrated packaging reduces the dependence on external interconnection and reduces the sensitivity to single event effect (SEE) and total dose effect (TID).

[0017] This invention condenses traditional sub-unit level systems to the board or even chip level through multi-chip module (MCM) or system-in-package (SiP) technology, integrated packaging, and highly integrated application-specific integrated circuits (ASIC / FPGA). This reduces the size and weight by more than 50%, power consumption by more than 30%, and the distributed processing architecture (monitoring + master control drive) significantly improves the servo loop bandwidth and response speed, enabling better tracking of the high-speed relative motion between low-orbit constellations.

[0018] This invention also supports on-orbit testing, software upgrades, and even hardware logic reconfiguration, greatly extending the effective lifespan of satellites and reducing the total lifespan cost. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of the present invention; Figure 2 A flowchart for software three-mode redundancy; In the diagram, 1-integrated package housing, 2-dual-core fault-tolerant main control unit, 3-multi-channel intelligent power drive unit, 4-integrated interface management and health monitoring unit, 5-embedded test and on-orbit maintenance interface unit, 6-high-speed on-chip bus, and 7-custom redundant backplane. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] See Figure 1 , Figure 2A servo controller for low-orbit constellation-fed antennas includes an integrated package housing 1, a dual-core fault-tolerant main control unit 2, a multi-channel intelligent power drive unit 3, an integrated interface management and health monitoring unit 4, and an embedded test and on-orbit maintenance interface unit 5. The dual-core fault-tolerant main control unit 2, the multi-channel intelligent power drive unit 3, the integrated interface management and health monitoring unit 4, and the embedded test and on-orbit maintenance interface unit 5 are all highly integrated physically and electrically within the integrated package housing 1 via a high-speed on-chip bus 6 and a custom redundant backplane 7.

[0025] In this embodiment, the dual-core fault-tolerant main control unit 2 is based on two high-performance processors operating in master control and monitoring modes. It integrates: an orbit and attitude calculation module: receiving real-time orbit and attitude data from the satellite system and fusing feedback from local sensors (such as resolvers and encoders) of the antenna mechanism to calculate the antenna target pointing angle; an adaptive control algorithm module: incorporating advanced algorithms based on model predictive control (MPC) or adaptive sliding mode control to calculate high-precision control commands in real time; and a task and fault management module: responsible for task synchronization and cross-validation between the two cores, and seamlessly switching to the healthy core to run independently when a single-core fault is detected, achieving "fault-to-operation" fault tolerance.

[0026] In this embodiment, the multi-channel intelligent power drive unit 3 adopts multi-chip module (MCM) or system-in-package (SiP) technology to integrate multiple motor drive channels (H-bridge), current sampling, and overcurrent / overtemperature protection circuit channels into a single package. Each channel has an independent digital signal processor (DSP) core, which can perform current loop control locally and receive instructions from the main control unit through a high-speed bus to achieve distributed computing, reduce the load on the main control unit, and improve the system response speed and control bandwidth.

[0027] In this embodiment, the integrated interface management and health monitoring unit 4 integrates: a multi-protocol communication interface supporting onboard standard buses such as CAN and RS422 for communication with the satellite platform; a high-precision sensor interface directly connected to rotary transformers (RDCs), absolute encoders, etc., to complete high-resolution angle digital conversion; a full-state health monitoring circuit that collects real-time data on voltage, current, temperature, and radiation dose at key points within the controller, and performs threshold comparison and trend analysis; and a non-volatile memory storing historical health data, fault logs, and on-orbit maintenance procedures.

[0028] In this embodiment, the embedded test and on-orbit maintenance interface unit 5 provides dedicated boundary scan (JTAG) and high-speed data ports, supporting: On-orbit self-test (BIT): self-testing of the controller's internal functions and performance upon power-up or periodically. On-orbit software injection (IoS): allowing ground control to update and upgrade control algorithms and fault handling strategies via telemetry channels. On-orbit partial reconfiguration: dynamically reconfiguring local logic functions at the FPGA device level to bypass permanently damaged units.

[0029] In this embodiment, the high-speed on-chip bus 6 adopts a star or dual-ring topology and has a time-triggered mechanism to ensure deterministic and low-latency data transmission between units.

[0030] In this embodiment, the custom redundant backplane 7 adopts a cold backup circuit design, integrates power distribution network and signal routing, and uses relays to physically isolate critical power and signal paths.

[0031] In some embodiments, the aforementioned servo controller can be installed inside the satellite payload bay and connected to the satellite's integrated electronic system via an RS422 bus to acquire orbital parameters and attitude references. It directly drives four stepper motors (one for the azimuth axis and one for the pitch axis of the two antennas) of the antenna pointing mechanism via high-density rectangular electrical connectors and receives feedback from the resolver. After the controller is powered on, the dual-core fault-tolerant main control unit 2 initiates a self-test, and the integrated interface management and health monitoring unit 4 performs initialization checks on the power supply and status of each module. During normal operation, the dual-core fault-tolerant main control unit 2 calculates the antenna pointing command and sends it to each local FPGA of the power drive module via RS422. The FPGA performs precise current loop control to drive the motor movement, and the integrated interface management and health monitoring unit 4 synchronously collects the resolver signal and provides closed-loop feedback to the main controller.

[0032] When an abnormal temperature rise is detected in a power channel, an interrupt is reported to the main controller. The main controller's task and fault management module can decide to reduce the drive current limit of that channel or switch to the backup drive circuit, and report to the ground via the telemetry channel. If inconsistent calculation results are detected in the main controller's single core, the system instantly switches to the backup core and records the fault event. Maintenance commands uploaded from the ground station can activate the embedded test interface to perform in-depth testing on specified functional modules of the controller, or inject new control algorithm software packages to achieve performance optimization.

[0033] This servo controller employs a master-slave backup approach for antenna attitude control. The design involves two independent control systems controlling the attitudes of two antennas. The satellite communicates with these two independent control systems via an RS422 bus. The satellite's OC level (12V pulse signal) is sent separately to each control system. Each control system has backups in its power conversion, FPGA control, resolver decoding, and excitation sections, using a one-to-one backup configuration. The main and backup circuits are identical, forming independent systems that do not interfere with each other. Furthermore, the servo controller includes a refresh controller circuit. This circuit mitigates the single-event upset (SEE) effect in the configuration memory of the Xilinx SRAM-type FPGA. The refresh control chip reads the FPGA bitstream file from the configuration refresh data storage circuit and performs power-on configuration and timed refresh on the target FPGA via the SELECTMAP interface. Current detection hardening technology is used, with platform overcurrent as the locking criterion. When locking is detected, a monostable circuit cuts off the power supply, and power is automatically restored after a few seconds once the chip exits the lock.

[0034] Particle flipping is a common phenomenon in the aerospace field. It occurs when aerospace equipment operates in high-altitude environments, where sensitive nodes may be struck by energy particles generated by solar activity, causing changes in the state of storage units. Therefore, this invention employs a method for verifying and correcting particle flipping: a two-out-of-three checksum. The principle of the two-out-of-three checksum is to back up the program (data) to be checked into three copies (the original program) and store them in different addresses. The data at the same bit in each address is compared pairwise. If all data are the same, the program content at that address is correct. If a bit is different, it indicates that the data content at that bit has shifted or changed, requiring correction. The three bits at that address are first bitwise ANDed, then bitwise ORed. The final result is the corrected data, which is then rewritten into the corresponding storage address.

[0035] Three-out-of-two verification process: The program in this project is mainly divided into two parts: BootLoader and APP. Each part is backed up into three copies and stored in different flash addresses (i.e., BootLoader1, 2, 3 and APP1, 2, 3). After power-on, the program starts with BootLoader1. Upon startup, the program determines whether a three-out-of-two verification is needed for the APP. If verification is required and the result is incorrect, the APP program is corrected. If the verification result is normal or no verification is needed, the program jumps to APP1. Once APP1 is running normally, it verifies 1KB of data every 50ms (first verifying BootLoader, then verifying APP). If errors are found in the BootLoader's verification result, the errors are directly corrected, and verification continues until the current verification is complete. After the BootLoader part has completed all verifications, it begins verifying its own APP part. If the verification result is normal, it waits for the next new verification. If the verification result shows an error, it first needs to determine whether the erroneous part includes APP1. If APP1 is fine, it directly corrects the erroneous parts of APP2 and APP3. If APP1 itself has an error, it first corrects the erroneous parts of APP2 and APP3. After all programs have been verified and corrected, it jumps back to the BootLoader1 program to correct the APP1 program. After the correction and verification are successful, it jumps back to the APP1 program and repeats the above loop. For details, please refer to [link to documentation]. Figure 2 .

[0036] It should be noted that the terms "connection" and "setting" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "connection" or "setting" may explicitly or implicitly include one or more of that feature. Furthermore, the terms "connection" and "setting," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Moreover, for the foregoing embodiments, for the sake of simplicity, they are all described as a series of actions; however, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Secondly, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0037] The above embodiments describe the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Modifications and variations made by those skilled in the art without departing from the spirit and scope of the invention should be within the protection scope of the appended claims.

Claims

1. A servo controller for a low-orbit constellation-fed antenna, characterized in that, The system includes an integrated package housing (1), which integrates a dual-core fault-tolerant main control unit (2), a multi-channel intelligent power drive unit (3), an integrated interface management and health monitoring unit (4), and an embedded test and on-orbit maintenance interface unit (5). The dual-core fault-tolerant main control unit (2) is used to realize the operation processing of the main control and monitoring modes; the multi-channel intelligent power drive unit (3) is used to integrate multi-channel circuits into a single package; the integrated interface management and health monitoring unit (4) is used to realize external communication, signal acquisition, real-time monitoring of system status, and health data storage; and the embedded test and on-orbit maintenance interface unit (5) is used to support on-orbit self-testing, on-orbit software injection, and on-orbit partial hardware logic reconfiguration.

2. A servo controller for a low-orbit constellation-fed antenna as described in claim 1, characterized in that, The dual-core fault-tolerant main control unit (2), multi-channel intelligent power drive unit (3), integrated interface management and health monitoring unit (4), and embedded test and on-orbit maintenance interface unit (5) are all highly integrated physically and electrically on the integrated package housing (1) via high-speed on-chip bus (6) and custom redundant backplane (7).

3. A servo controller for a low-orbit constellation-fed antenna as described in claim 1, characterized in that, The dual-core fault-tolerant main control unit (2) integrates: The orbit and attitude calculation module is used to receive orbit and attitude data provided by the satellite system in real time, and integrate local sensor feedback from the antenna mechanism to calculate the antenna target pointing angle. The adaptive control algorithm module, based on advanced algorithms such as model predictive control or adaptive sliding mode control, calculates high-precision control commands in real time. The task and fault management module is used to realize task synchronization and cross-verification between the two cores, and seamlessly switch to the healthy core to run independently when a single core failure is detected, so as to realize fault tolerance management of faults and work.

4. A servo controller for a low-orbit constellation-fed antenna as described in claim 1, characterized in that, The multi-channel intelligent power drive unit (3) uses multi-chip module or system-level packaging technology to integrate multiple drive channels into a single package, and each drive channel integrates an independent digital signal processor core for local execution of current loop closed-loop control.

5. A servo controller for a low-orbit constellation-fed antenna as described in claim 1, characterized in that, The integrated interface management and health monitoring unit (4) integrates: Multi-protocol communication interface, used to support multiple on-board standard buses for communication with satellite platforms; The sensor has a high-precision interface for connecting to a rotary transformer and an absolute encoder to achieve high-resolution angle digital conversion. The full-state health monitoring circuit is used to collect real-time data on voltage, current, temperature and radiation dose at key points inside the controller, and to perform threshold comparison and trend analysis. Non-volatile memory is used to store health history data, fault logs, and on-orbit maintenance procedures.

6. A servo controller for a low-orbit constellation-fed antenna as described in claim 1, characterized in that, The embedded test and on-orbit maintenance interface unit (5) provides boundary scan and high-speed data ports, supporting on-orbit self-test, on-orbit software injection and on-orbit partial reconfiguration. The on-orbit partial reconfiguration is to dynamically reconfigure local logic functions at the FPGA device level to bypass permanent damage units.

7. A servo controller for a low-orbit constellation-fed antenna as described in claim 2, characterized in that, The high-speed on-chip bus (6) adopts a star or dual-ring topology and has a time-triggered mechanism to ensure the determinism and low latency of data transmission between units.

8. A servo controller for a low-orbit constellation-fed antenna as described in claim 2, characterized in that, The custom redundant backplane (7) adopts a cold backup circuit design, integrates power distribution network and signal routing, and uses relays to physically isolate critical power and signal paths.

9. A servo controller for a low-orbit constellation-fed antenna as described in any one of claims 1 to 8, characterized in that, The servo controller is installed inside the satellite payload bay and is connected to the satellite's integrated electronic system via an RS422 bus to obtain orbital parameters and attitude references.

10. A servo controller for a low-orbit constellation-fed antenna as described in claim 9, characterized in that, The servo controller uses a 2-out-of-3 checksum method to correct the particle flipping problem. Specifically, the 2-out-of-3 checksum method involves backing up the data to be checked into three copies and storing them in different addresses. The data of the same bit in the program is compared pairwise. If all the data are the same, it proves that the program content in that address is correct. If the data of a certain bit is different, it means that the data content of that bit has been offset or changed and the data needs to be corrected. The data at that address is first bitwise ANDed, and then the three data obtained are bitwise ORed. The final data is the corrected data, and the corrected data content is rewritten into the corresponding storage address.

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