Multi-beam IQ data synchronization method based on source end pre-bias and receiving end shallow cache

Abstract

The invention relates to a multi-beam IQ data synchronization method based on source end pre-bias and receiving end shallow cache. The method comprises the following steps that: a receiving end measures round-trip delay of an optical link and calculates a pre-bias containing integer and decimal components; the sending end adjusts a buffer read pointer and controls a digital fractional delay filter to perform source end compensation; and a receiving end absorbs residual jitter by using a shallow-depth elastic buffer unit, and uniformly triggers reading after a full link is ready. The method has the advantages that the resource consumption of the receiving end is greatly reduced, the certainty low time delay is ensured, the dynamic thermal drift compensation is supported, and the high-precision sample point level alignment is realized.

Description

Technical Field

[0001] This application relates to the field of phased array radar communication, and in particular to a multi-beam IQ data synchronization method based on source-end pre-biasing and receiver-end shallow buffering. Background Technology

[0002] In modern high-performance communication systems and digital phased array radars, multi-beam IQ data is typically transmitted via multiple parallel fiber optic links to improve spectral efficiency and beam pointing accuracy. However, due to inherent differences in the physical length of these fiber optic links in actual engineering deployments, coupled with inconsistencies in the photoelectric conversion modules, the arrival times of multi-beam IQ data transmitted simultaneously at the receiving end are often inconsistent. If this difference in transmission delay between links is not eliminated through technical means, it will directly affect the phase consistency of subsequent beamforming processing.

[0003] The mainstream solution to multi-link synchronization problems in existing technologies typically employs a passive buffering mechanism at the receiver. Under this mechanism, the receiver controller needs to configure a deep first-in-first-out (FIFO) memory or flexible buffer unit for each optical transmission link. Its working principle is to utilize the memory's storage depth to accommodate the data time difference between different links; that is, the link whose data arrives earlier needs to write its data into the memory and wait until the link whose data arrives latest has also completed receiving the data, at which point the receiver uniformly controls all links to read the data.

[0004] While this passive buffering scheme at the receiver achieves data alignment to some extent, it has significant technical limitations in practical applications. First, to cover potential long-distance transmission delay differences between fiber optic links, the receiver must reserve a sufficiently large storage space. This consumes a significant amount of block memory and logic wiring resources within the receiver chip, increasing the system's hardware cost and power consumption. Second, because the connection establishment time of each link is random each time the system powers on, the relative positions of the read / write pointers within the memory are not fixed, causing fluctuations in the total latency of the entire transmission system between different startups. This non-deterministic latency characteristic makes it difficult to meet the requirements of systems with high signal transmission timing stability. Summary of the Invention

[0005] In order to achieve high precision and deterministic latency while reducing the storage resource consumption at the receiving end, this application provides a multi-beam IQ data synchronization method based on source-end pre-biasing and receiver-end shallow buffering.

[0006] This application provides a multi-beam IQ data synchronization method based on source-end pre-biasing and receiver-end shallow buffering, which adopts the following technical solution: A multi-beam IQ data synchronization method based on source-end pre-biasing and receiver-end shallow buffering includes the following steps: S1. The receiver controller measures the round-trip transmission delay of the optical transmission link corresponding to each transmitter controller connected to the receiver controller; S2. The receiving end controller calculates the target pre-offset amount for each of the transmitting end controllers based on the round-trip transmission delay of all the optical transmission links, wherein the target pre-offset amount includes an integer clock cycle component and a fractional clock cycle component. S3. The receiving end controller feeds back the integer clock cycle component and the fractional clock cycle component to the corresponding transmitting end controller; S4. The transmitting end controller uses the integer clock cycle component to adjust the read pointer start time of the source end transmitting buffer unit located inside the transmitting end controller, and uses the fractional clock cycle component to control the digital fractional delay filter to perform fractional delay processing on the multi-beam IQ data to be transmitted. S5. The transmitting end controller sends the processed multi-beam IQ data to be transmitted to the receiving end controller; S6. The receiver controller uses a shallow-depth elastic buffer unit located after the physical layer receiver interface of the receiver controller to receive the multi-beam IQ data, wherein the storage depth of the shallow-depth elastic buffer unit is configured to be less than the delay adjustment range corresponding to the integer clock cycle component, and the shallow-depth elastic buffer unit is only configured to absorb residual phase jitter and cross-clock domain transmission noise after the source active pre-bias operation. S7. When the receiver controller detects that all shallow elastic buffer units corresponding to the optical transmission links are in a non-empty state, the receiver controller generates a global synchronization signal to uniformly trigger the reading operation of all shallow elastic buffer units, thereby realizing the multi-beam IQ data alignment.

[0007] By employing the above technical solution, the receiver controller quantifies the physical link length difference into specific time parameters by measuring the round-trip transmission delay of the optical transmission link, and calculates the target pre-bias amount to compensate for this difference. The transmitter controller uses this target pre-bias amount to reverse-adjust the data transmission logic, compensating for the macroscopic difference of integer clock cycles by delaying the start time of the read pointer of the source-end transmit buffer unit, and using a digital fractional delay filter to perform time-domain interpolation processing on the discrete IQ data sequence to compensate for the fractional differences in subsampling. This active time-domain shift operation at the source end enables the wavefronts of multi-beam IQ data signals transmitted through optical fibers of different lengths to be aligned on the time axis when they arrive at the physical interface of the receiver controller, thereby eliminating the timing deviation caused by the physical link before the data enters the receiving logic.

[0008] The digital fractional delay filter, acting as a fine-tuning unit, introduces a group delay of less than one system clock cycle while maintaining a constant data sampling rate. This effectively corrects subtle errors caused by phase mismatch between the sampling point and the signal waveform. By directly processing the fractional clock cycle component at the transmitting end, the system avoids quantization errors caused by relying solely on integer clock cycle adjustments, ensuring strict phase consistency of multi-beam data and meeting the high-precision synchronization requirements of beamforming algorithms.

[0009] The shallow-depth elastic buffer unit, located after the physical layer receive interface of the receiver controller, is primarily used to isolate cross-clock domain metastability between the optical link recovery clock and the local system clock. Since the macroscopic transmission delay differences between different optical transmission links have been eliminated by pre-biasing operations at the source end, the storage depth of this buffer unit only needs to cover the residual phase jitter range after source-end compensation. Limiting the buffer depth to a small range significantly reduces the occupancy of the receiver chip's internal block memory resources and avoids wiring congestion caused by building deep aligned buffers. This architecture locks the total system transmission delay to the sum of the longest physical link delay and the fixed shallow buffer delay, eliminating delay jumps caused by the randomness of the initial read / write pointer position in traditional deep buffer schemes, and providing a deterministic low-latency transmission channel for radar signal processing.

[0010] Optionally, step S1 includes the following sub-steps: S11. The receiving end controller inserts a preset ranging beacon into the physical layer encoded stream to be transmitted, and broadcasts the ranging beacon to all the transmitting end controllers; S12. After receiving the ranging beacon through its own physical layer receiving interface, each of the transmitting end controllers uses the hardware loopback path connecting its own physical layer receiving interface and its own physical layer transmitting interface to return the ranging beacon to the receiving end controller via the original path. S13. The receiver controller uses a local clock counter to record the time difference from sending the ranging beacon to receiving the returned ranging beacon, and marks the time difference as the round-trip transmission delay.

[0011] By adopting the above technical solution, the receiver controller bypasses the complex encapsulation and decapsulation logic of the upper-layer protocol stack by directly inserting ranging beacons into the physical layer encoded stream, eliminating the uncertainty and jitter caused by software processing. The transmitter controller returns the received beacon along the original path through a hardware loopback path, ensuring that the dwell time of the ranging signal at the transmitter is constant and extremely short, thereby guaranteeing the physical purity of the round-trip transmission delay measurement. The receiver controller uses a local high-frequency clock counter to time this physical process, establishing a unified time reference, which can accurately capture the physical transmission differences of different fiber optic links at the nanosecond level or even finer granularity.

[0012] Optionally, step S2 includes the following sub-steps: S21. The receiver controller selects the maximum value from all measured round-trip transmission delays and defines the maximum value as the maximum link delay; S22. The receiving end controller calculates the difference between the maximum link delay and the round-trip transmission delay of each of the sending end controllers; S23. The receiving end controller takes half of the difference as the target pre-bias value, and performs modulo operation decomposition on the target pre-bias value according to the system clock cycle, thereby separating the integer clock cycle component and the fractional clock cycle component.

[0013] By adopting the above technical solution, the receiver controller sets the maximum selected link delay as the synchronization anchor point for the entire system, forcing all shorter links to align with the longest link, thereby avoiding the risk of data overflow or timing inversion caused by excessive advance transmission. By calculating the difference and halving it, the system maps the bidirectional round-trip delay to a unidirectional transmitter pre-bias. Further decomposing this pre-bias into integer clock cycle components and fractional clock cycle components achieves orthogonal decoupling of the synchronization control dimension, allowing the macroscopic coarse-grained alignment task and the microscopic fine-grained phase adjustment task to be mapped to different hardware execution units respectively.

[0014] Optionally, the digital fractional delay filter in step S4 is a Farrow structure filter or a multiphase interpolation filter. The digital fractional delay filter is configured at the end of the transmission link of the transmitting controller. The digital fractional delay filter is configured to introduce a group delay of less than one system clock cycle while keeping the data sampling rate constant. The group delay represents the overall time shift of the signal waveform of the multi-beam IQ data in the time domain.

[0015] By employing the above technical solution, the digital fractional delay filter, as the actuator for fine-tuning in the time domain, can perform subsampling-level time shifting of multi-beam IQ data signals without changing the data sampling rate or introducing spectral aliasing. This filter dynamically adjusts the filter coefficients to change the group delay of the signal, thereby reconstructing a precisely time-shifted analog waveform envelope between discrete digital sampling points, filling the technical gap of traditional digital logic which can only perform integer clock cycle shifts. This processing method eliminates the quantization phase error caused by clock granularity, ensuring that multiple signals meet the stringent phase consistency requirements of beamforming algorithms when arriving at the receiving end, achieving stepless continuous adjustment of the signal waveform along the time axis.

[0016] Optionally, in step S6, the storage depth of the shallow-depth elastic buffer unit is configured to be 4 to 16 data words, and the shallow-depth elastic buffer unit is not used to compensate for the macroscopic transmission delay differences between different optical transmission links.

[0017] By adopting the above technical solution, the storage depth of the shallow elastic buffer unit is strictly limited to 4 to 16 data words, physically stripping the receiver buffer of its function in compensating for macroscopic fiber link length differences. This capacity limitation forces all macroscopic delay alignment operations to be completed at the source end through pre-biasing, thus strictly defining the role of the receiver buffer as a device for cross-clock domain metastability isolation and absorption of residual micro-jitter. The extremely small buffer depth significantly reduces the consumption of internal block memory resources in the receiver controller chip, avoiding the strain on logic wiring resources. At the same time, this configuration eliminates the delay uncertainty introduced by the initial phase randomness of the deep buffer read / write pointers, locking the total data transmission delay of the system within a very small and fixed physical range, providing a low-latency data channel with strict determinism for the phased array system.

[0018] Optionally, the method further includes a dynamic thermal drift compensation step: S81. The receiving end controller periodically executes steps S1 and S2 during data transmission gaps to obtain real-time delay drift, wherein the real-time delay drift represents the difference between the currently measured round-trip transmission delay and the initially calibrated round-trip transmission delay. S82. If the real-time delay drift exceeds a preset delay drift threshold, the receiving end controller calculates the updated fractional clock cycle component based on the real-time delay drift and sends the updated fractional clock cycle component to the transmitting end controller. S83. The transmitting end controller, while keeping the read pointer position of the source end transmitting buffer unit unchanged, generates corresponding filter tap coefficients using the updated fractional clock cycle component and updates the digital fractional delay filter, wherein the shallow-depth elastic buffer unit is configured to maintain the output continuity of the multi-beam IQ data during the coefficient update of the digital fractional delay filter.

[0019] By employing the above technical solution, the receiver controller periodically probes the physical link status during data transmission gaps, capturing in real time the transmission delay drift caused by changes in the refractive index of the fiber optic medium due to ambient temperature variations and thermal expansion and contraction of the physical length. Comparing the real-time drift with a preset threshold effectively filters out random noise interference during the measurement process, ensuring that the adjustment action is triggered only for physically significant thermal effects. The transmitter controller maps the drift to updated filter tap coefficients, and while maintaining the macroscopic read pointer position locked in the source-end transmit buffer unit, only reconstructs the parameters of the digital fractional delay filter. This operation, without altering the macroscopic timing structure of the data stream, compensates for the thermal drift of the physical link by changing the group delay characteristics of the signal waveform, achieving sub-sampling level dynamic phase correction. During this process, the shallow-depth elastic buffer unit utilizes its small storage margin to absorb transient phase fluctuations generated during filter coefficient switching, ensuring that multi-beam IQ data does not experience bit errors or phase jumps during continuous thermal compensation, maintaining the long-term phase stability required by the beamforming algorithm.

[0020] Optionally, the sub-step of S7 includes: S71. When it is detected that any of the shallow elastic buffer units corresponding to the optical transmission link changes from an empty state to a non-empty state, the receiver controller starts a synchronization timeout timer; S72. Determine whether the shallow elastic buffer units corresponding to all other optical transmission links have changed to a non-empty state within the preset synchronization timeout period; S73. If the determination result is yes, the receiving end controller generates the global synchronization signal; if the determination result is no, the receiving end controller determines that the current synchronization has failed and triggers the link reset process.

[0021] By adopting the above technical solution, the receiver controller establishes a dynamic synchronization time window based on the earliest arriving data stream. When any shallow-depth elastic buffer unit experiences a state flip, the system immediately starts a synchronization timeout timer, defining the maximum allowable time difference range for the arrival of multiple data streams. This decision logic converges the dispersed physical link transmission states into a unified time correlation detection. Only when data from all links arrives within the preset time window is a global synchronization signal triggered, thus ensuring the validity and timing consistency of multi-beam data. If the arrival of all branch data is not detected after the time window expires, the receiver controller will identify a synchronization failure caused by fiber breakage or severe time delay jitter and actively trigger a link reset procedure. This timeout circuit breaker mechanism avoids the system falling into an infinite waiting deadlock state due to a single link failure.

[0022] Optionally, the sub-step of S83 includes: S831. The transmitting controller calculates the difference between the updated fractional clock cycle component and the currently used fractional clock cycle component; S832. Determine whether the absolute value of the difference is less than the preset maximum delay adjustment step size; S833. If the absolute value of the difference is less than the preset maximum delay adjustment step size, the transmitting end controller directly updates the digital fractional delay filter using the updated fractional clock cycle component. S834. If the absolute value of the difference is greater than or equal to the preset maximum delay adjustment step size, the transmitting end controller decomposes the difference into multiple consecutive small adjustment steps and updates the digital fractional delay filter clock cycle by clock cycle until the updated fractional clock cycle component is reached.

[0023] By employing the above technical solution, and comparing the update difference of the fractional clock cycle components with the preset maximum delay adjustment step size, the system mathematically constructs a smooth limiter for the phase adjustment rate. When faced with a large phase correction requirement caused by drastic temperature changes or initial calibration errors, the transmitting controller decomposes the originally abrupt step signal into a series of continuous small adjustment steps, applying them to the filter clock cycle by clock cycle. This strategy of discretizing large-span delay adjustments into a smooth transition process effectively suppresses high-frequency pulse noise and phase discontinuities caused by instantaneous changes in the filter tap coefficients, ensuring the smoothness and spectral purity of the IQ data waveform during dynamic thermal compensation, and preventing downstream signal processing logic lockout due to phase jumps.

[0024] In summary, this application includes at least one of the following beneficial technical effects: 1. The storage resource utilization of the receiver controller is significantly reduced. By actively eliminating macroscopic delay differences between optical transmission links at the transmitter using the target pre-bias, the shallow-depth elastic buffer unit at the receiver no longer undertakes macroscopic alignment tasks, and its storage depth is strictly limited to a small range. This architecture transfers the alignment pressure to the transmitter's logic resources, avoiding the block memory resource exhaustion and logic wiring congestion problems caused by building deep FIFO queues inside the receiver chip, thus optimizing the resource layout of the receiver chip.

[0025] 2. Deterministic low latency for multi-beam IQ data transmission was achieved. By measuring the round-trip transmission delay and using the maximum link delay as the system's synchronization anchor point, combined with active pre-biasing at the source end, the total transmission delay of the system was physically locked to the sum of the longest link delay and the fixed shallow buffer delay. This mechanism eliminates the delay jumps introduced by the uncertainty of the initial phase of the read / write pointers due to the randomness of power-on link establishment in traditional deep buffer schemes, ensuring that the radar or communication system has strictly consistent time response characteristics during different startups and operations.

[0026] 3. It possesses sub-sampling level dynamic thermal drift compensation capability. Utilizing the fine interpolation characteristics of digital fractional delay filters in the time domain, combined with a periodic round-trip delay measurement mechanism, the system can capture and quantify the physical stretching and refractive index drift of the fiber optic medium caused by changes in ambient temperature in real time. The transmitter controller dynamically and smoothly updates the filter coefficients, performing sub-sampling level time shift correction on the signal waveform while maintaining the continuity of the service data stream. This effectively offsets the phase shift caused by thermal effects, ensuring that the phase consistency required by the beamforming algorithm remains stable under complex environmental conditions. Attached Figure Description

[0027] Figure 1 A flowchart illustrating a multi-beam IQ data synchronization method based on source-end pre-biasing and receiver-end shallow buffering is shown in one embodiment of the present invention. Detailed Implementation

[0028] The present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application.

[0029] like Figure 1 As shown, this application embodiment provides a multi-beam IQ data synchronization method based on source-end pre-biasing and receiver-end shallow buffering, including the following steps S1-S7.

[0030] S1. The receiver controller measures the round-trip transmission delay of the optical transmission link corresponding to each transmitter controller connected to the receiver controller.

[0031] In this embodiment, the receiver controller typically refers to the digital signal processing core located in the central equipment room or on the baseband processing unit side, and its physical carrier is usually a field-programmable gate array (FPGA) or a dedicated integrated circuit (IDE). The transmitter controller refers to the control chip distributed in the radio frequency remote unit or active antenna unit on the antenna side. The two are connected through a point-to-multipoint or star topology. The receiver controller acts as a synchronization master node, responsible for initiating measurement tasks and aggregating data.

[0032] An optical transmission link is the physical channel connecting the receiver controller and the transmitter controller, typically composed of optical transceiver modules and optical fiber media. In actual engineering deployments, due to the different installation locations of antenna array elements, the length of the optical fiber connecting each transmitter controller varies (for example, the nearest node may only require 5 meters of fiber, while the farthest node may require 2000 meters). Furthermore, uneven refractive index distribution in the fiber core and batch variations in photoelectric conversion modules can introduce minute device delays. These factors cause signals emitted at the same time to have inconsistent flight times in different links, thus affecting the phase consistency of multi-beam data.

[0033] Round-trip delay refers to the total time required for a signal to travel from the receiver controller, through the optical transmission link to the transmitter controller, and back through the transmitter controller to the receiver controller. For example, the propagation speed of an optical signal in an optical fiber is approximately 200,000 kilometers per second. For a 1-kilometer optical fiber link, the one-way flight time is approximately 5 microseconds, and the round-trip delay is approximately 10 microseconds. The round-trip delay includes the bidirectional optical fiber transmission time as well as the processing time of the internal hardware loopback path at the transmitter.

[0034] This embodiment chooses to measure round-trip time delay instead of one-way delay primarily to avoid the problem of initial clock phase uncertainty. Directly measuring one-way delay requires high-precision absolute time synchronization between the receiver and transmitter. However, when the system first establishes a connection, the clocks at both locations are typically in a free-running state, and their phase relationship is random. Round-trip time delay measurement relies solely on the receiver controller's local clock count, eliminating the need for remote clocks to participate in timing and thus removing the impact of remote clock phase deviations on measurement accuracy.

[0035] Measuring round-trip time delay is used to quantify the differences in length and components of each optical transmission link into specific time parameters. By obtaining accurate round-trip time delay values, the system can determine the distance (in time) between each transmitting controller and the receiving controller.

[0036] Specifically, step S1 includes the following sub-steps S11-S13.

[0037] S11. The receiving end controller inserts a preset ranging beacon into the physical layer encoded stream to be transmitted, and broadcasts the ranging beacon to all the transmitting end controllers.

[0038] S12. After receiving the ranging beacon through its own physical layer receiving interface, each of the transmitting end controllers uses the hardware loopback path connecting its own physical layer receiving interface and its own physical layer transmitting interface to return the ranging beacon to the receiving end controller via the original path.

[0039] S13. The receiver controller uses a local clock counter to record the time difference from sending the ranging beacon to receiving the returned ranging beacon, and marks the time difference as the round-trip transmission delay.

[0040] In this embodiment, the ranging beacon typically uses a special control character defined in the physical layer coding standard, such as the K28.5 character (Comma code) in the 8B / 10B coding scheme, or a predefined pseudo-random sequence with strong autocorrelation. The choice to insert the ranging beacon directly at the physical layer, rather than generating it at the media access control layer or the application layer above, is to avoid complex protocol stack processing logic. Upper-layer protocol stacks typically involve packet encapsulation, checksum calculation, and operating system interrupt scheduling, which introduce millisecond-level or even greater random processing delays. By directly manipulating the data stream and inserting the beacon at the physical coding sublayer, the timing of the ranging signal transmission can be ensured to be precisely controllable and unaffected by system software load.

[0041] In distributed systems, the receiver controller may connect to dozens or even hundreds of transmitter controllers. If a point-to-point polling method is used to send ranging beacons one by one, completing the measurement of all links would consume significant time resources and easily lead to inconsistencies in the environmental baselines between measurements. Broadcast mode allows the receiver controller to send a unified beacon signal, simultaneously triggering the measurement process on all links. Combined with the time-division multiplexing or frequency-division multiplexing response mechanisms of each transmitter controller, a rapid system-wide state scan can be completed.

[0042] A hardware loopback path refers to establishing a physical signal path directly from the receiver to the transmitter within the transmitter controller chip. This path is typically implemented in the physical medium sublayer or physical coding sublayer of the SerDes transceiver, bypassing the transmitter controller's central processing unit or digital signal processing core. In contrast, software forwarding requires a series of steps, including "receive interrupt - memory copy - CPU parsing - repackaging - writing to the transmit register," and its processing time fluctuates drastically due to CPU utilization. The hardware loopback path provides a fixed, constant processing time that is only related to gate delays, eliminating node processing delay jitter and ensuring the purity of round-trip transmission delay measurements, reflecting only the fiber optic link length and the physical characteristics of the optoelectronic module.

[0043] The local clock counter is a high-frequency counting unit inside the receiver controller, typically operating at frequencies of hundreds of megahertz or even gigahertz. For example, a counter clock frequency of 250MHz corresponds to a time granularity of 4 nanoseconds. When the receiver controller sends the first bit of the ranging beacon at the physical layer, the counter starts or records the current count value T1; when the receiver controller recognizes the first bit of the returning beacon, it records the current count value T2.

[0044] S2. The receiving end controller calculates the target pre-bias amount for each of the transmitting end controllers based on the round-trip transmission delay of all the optical transmission links, wherein the target pre-bias amount includes an integer clock cycle component and a fractional clock cycle component.

[0045] In physical terms, the target pre-bias is an artificially imposed negative delay or waiting time. Since the propagation speed of optical signals in a physical medium is limited by the speed of light, the longer the physical link, the later the signal arrives. To achieve alignment, the system must follow the physical causality of "faster waits for slower," meaning that the transmitter controller with the shorter physical link (faster transmission) must artificially wait a period before sending data, ensuring its signal arrives at the receiver at the same time as the longest link (slowest transmission). This waiting time is the target pre-bias.

[0046] Decomposing time into integer and fractional clock cycle components is to accommodate the discrete characteristics of digital logic circuits. Digital systems are typically driven by a fixed-frequency master clock (e.g., 200MHz, corresponding to a period of 5ns). For large macroscopic time delays (e.g., 100ns), digital logic can easily achieve this using a simple counter or a FIFO queue pointer offset (e.g., offset by 20 clock cycles). This is the integer clock cycle component, corresponding to a coarse-tuning mechanism in hardware.

[0047] However, the differences in physical links are not integer multiples of clock cycles. The remaining tiny time difference, less than one clock cycle (e.g., 2.3 ns), cannot be handled by simple digital counting. Special signal processing algorithms (such as interpolation filtering) must be used to simulate the signal delay between the two sampling points. This is the fractional clock cycle component, corresponding to the hardware fine-tuning mechanism. This splitting strategy achieves decoupling between wide range and high precision: the integer component covers the microsecond-level differences caused by long-distance fiber optics, while the fractional component corrects for nanosecond or picosecond-level phase residuals, thus achieving high-precision synchronization across the entire range without significantly increasing hardware complexity.

[0048] Specifically, step S2 includes the following sub-steps S21-S23.

[0049] S21. The receiver controller selects the maximum value from all measured round-trip transmission delays and defines the maximum value as the maximum link delay.

[0050] In step S21, selecting the maximum link delay as the system's synchronization benchmark is a necessary choice based on physical causality. In the physical world, signal transmission speed cannot exceed the speed of light; therefore, the system cannot catch up with the shorter link by accelerating the signal on the longest link. It can only force the signal on the shorter link to slow down or wait to accommodate the longest link. This is similar to the shortest plank principle in the barrel effect, where the longest link determines the minimum total transmission delay of the entire system.

[0051] S22. The receiving controller calculates the difference between the maximum link delay and the round-trip transmission delay of each of the sending controllers.

[0052] The difference calculated in step S22 represents the surplus in physical transmission time for each short link relative to the longest link. The larger this difference, the shorter the link, the earlier the signal arrives, and therefore the longer the waiting time that needs to be compensated.

[0053] S23. The receiving end controller takes half of the difference as the target pre-bias value, and performs modulo operation decomposition on the target pre-bias value according to the system clock cycle, thereby separating the integer clock cycle component and the fractional clock cycle component.

[0054] In step S23, the difference is divided by 2 because step S1 measures the bidirectional round-trip transmission delay, which includes both the outbound and return journeys. However, in actual service data synchronization, the system only focuses on the one-way outbound delay from the sender to the receiver. Assuming the uplink and downlink paths of the fiber optic link have physical symmetry, the one-way delay difference is half of the round-trip delay difference.

[0055] S3. The receiving end controller feeds back the integer clock cycle component and the fractional clock cycle component to the corresponding transmitting end controller.

[0056] S4. The transmitting end controller uses the integer clock cycle component to adjust the start time of the read pointer of the source end transmission buffer unit located inside the transmitting end controller, and uses the fractional clock cycle component to control the digital fractional delay filter to perform fractional delay processing on the multi-beam IQ data to be transmitted.

[0057] In this embodiment, the feedback channel is implemented in reverse through an existing optical communication link. Specifically, this can be achieved by utilizing a low-speed optical control channel, or by encapsulating the latency parameters in the operation, management, and maintenance field of the service frame header. The data transmission format typically employs compact binary encoding, for example, the high 16 bits representing the integer number of cycles and the low 16 bits representing the fixed-point number of fractional cycles, to ensure transmission efficiency.

[0058] The source-side transmit buffer unit is typically served by a transmit first-in-first-out (FIFO) queue. In normal operating mode, after data is written to this FIFO queue via the write clock field, once it reaches half full or a preset threshold, the read clock field immediately starts the read pointer to begin reading and transmitting data.

[0059] Adjusting the read pointer start time using integer clock cycle components essentially performs a macroscopic "clock-cycle shift" of the data stream. For example, suppose the system specifies that the read pointer should start on the 100th clock cycle (time T) after a global reset. If the calculated integer component is N=20, the sending controller will modify the read logic start condition to the 120th clock cycle (time T+N). This means the data resides in the FIFO queue for an additional 20 cycles, artificially introducing a 20-cycle delay.

[0060] Fractional delay processing occurs after the first-in-first-out (FIFO) queue and before the digital-to-analog converter (DAC) or physical layer interface in the signal processing flow. After data is read from the FIFO queue, it first enters the digital fractional delay filter for fine-tuning before being sent to the physical interface for transmission.

[0061] Integer coarse adjustment utilizes FIFO (First-In-First-Out) queue pointer operations, enabling near-infinite latency compensation (limited only by the FIFO queue depth) with extremely low resource consumption, resolving microsecond-level differences caused by long-distance fiber optics. Decimal fine adjustment employs filters, focusing on sub-sampling accuracy, addressing the high-precision requirements of phase alignment. The combination of these two methods avoids the problem of excessively high filter order caused by solely using filters to handle large latency, and also avoids the inability to align phases using only FIFO queues.

[0062] Specifically, the digital fractional delay filter in step S4 is a Farrow structure filter or a multiphase interpolation filter. The digital fractional delay filter is configured at the end of the transmission link of the transmitting controller. The digital fractional delay filter is configured to introduce a group delay of less than one system clock cycle while keeping the data sampling rate constant. The group delay represents the overall time shift of the signal waveform of the multi-beam IQ data in the time domain.

[0063] The reason for choosing Farrow structure filters or polyphase interpolation filters is their variability in coefficients and support for real-time dynamic adjustment. Unlike fixed-coefficient FIR filters, the Farrow structure allows the equivalent impulse response of the filter to be changed in real time by inputting a delay control parameter (i.e., the fractional component), thereby dynamically adjusting the group delay at runtime without overloading the FPGA image.

[0064] Maintaining a constant data sampling rate is crucial for system design. Achieving fine-grained delays by increasing the sampling rate (upsampling) significantly increases data bandwidth pressure and may introduce spectral aliasing. Digital fractional delay filters can operate at the original sampling rate without requiring additional resampling hardware, saving spectral resources and computational power.

[0065] A group delay of less than one system clock cycle physically fills the gaps between integer clock cycles. Since the system clock is discrete (e.g., one edge every 5ns), pure digital logic cannot reach time points within 5ns. This filter, through mathematical operations, creates continuous time adjustment capability within this discrete grid.

[0066] The overall time shift of the signal waveform in the time domain is achieved through mathematical interpolation. The filter calculates the signal amplitude that should exist at a time after a fractional time delay, based on the amplitudes of the current sample and surrounding samples.

[0067] S5. The transmitting controller sends the processed multi-beam IQ data to the receiving controller.

[0068] S6. The receiver controller uses a shallow-depth elastic buffer unit located after the physical layer receiver interface of the receiver controller to receive the multi-beam IQ data, wherein the storage depth of the shallow-depth elastic buffer unit is configured to be less than the delay adjustment range corresponding to the integer clock cycle component, and the shallow-depth elastic buffer unit is only configured to absorb residual phase jitter and cross-clock domain transmission noise after the source active pre-bias operation.

[0069] At this point, the data streams processed by S4 exhibit differences in their physical transmission times. Data sent from closer transmitters is artificially delayed more, while data sent from farther transmitters is delayed less or not at all. This differentiation aims to offset the differences in fiber optic transmission delays, ensuring that all data streams arrive at the receiver at roughly the same time.

[0070] Shallow-depth elastic buffers typically employ small-capacity first-in-first-out queues built on register files or distributed RAM, rather than resource-intensive block memory. Located at the boundary between the clock domain recovered by the receiver's physical layer clock recovery circuit and the system's local clock domain, its primary function is to safely transfer data from the unstable recovered clock domain to the stable local clock domain.

[0071] If the buffer unit is very deep (e.g., capable of holding 1000 words), designers may prefer to use it to absorb the large delays caused by fiber length. By limiting its depth (e.g., much smaller than the hundreds of cycles corresponding to fiber differences), the possibility of macroscopic alignment by relying on receiver-side buffering is physically eliminated, thus forcing the system to rely on source-side pre-biasing to solve macroscopic synchronization problems.

[0072] Residual phase jitter mainly originates from photoelectric conversion jitter in the optical module, phase noise in the clock recovery circuit, and crosstalk in the PCB traces. Transmission noise includes metastable fluctuations that may occur during cross-clock domain transmission. The small capacity of the shallow-depth buffer unit is just enough to cover these nanosecond or picosecond-level fluctuations, ensuring data integrity.

[0073] Specifically, in step S6, the storage depth of the shallow-depth elastic buffer unit is configured to be 4 to 16 data words, and the shallow-depth elastic buffer unit is not used to compensate for the macroscopic transmission delay differences between different optical transmission links.

[0074] Typically, to prevent metastability, data needs to be processed for at least two clock cycles (2-3 clock cycles) when crossing domains. On top of this, adding a small jitter margin, a depth of 4 to 8 words is usually sufficient, while 16 words is a very conservative upper limit.

[0075] Macroscopic transmission delay differences refer to significant time differences caused by variations in the physical length of optical fibers. For example, a 1km difference in fiber length can result in a delay of approximately 5 microseconds, corresponding to 500 clock cycles at a 100MHz clock speed. This is a huge order of magnitude, far exceeding the capacity of a shallow buffer.

[0076] If the source does not correctly execute the S4 pre-bias operation, a difference of 500 cycles between long and short links will directly impact this shallow cache with a depth of only 16 words. For short-link data, the cache will overflow instantly; for long-link data, the cache will run out instantly. This will directly lead to data loss and synchronization failure, demonstrating the indispensability of source-side pre-biasing.

[0077] Traditional solutions require a Block RAM with a depth greater than 512 to compensate for a 1km difference at the receiver. For a 1024-channel phased array system, this would exhaust the FPGA's storage resources. This solution, however, requires only a few dozen triggers, resulting in negligible resource consumption and significantly reduced chip area.

[0078] Furthermore, the shallower the buffer, the smaller the range of distance between the read and write pointers (e.g., fixed between 4 and 8). This means that the delay of data passing through the buffer is a fixed value with extremely low uncertainty, thereby locking the total system latency within a very narrow window, meeting the stringent requirements of radar systems for latency determinism.

[0079] S7. When the receiver controller detects that all shallow elastic buffer units corresponding to the optical transmission links are in a non-empty state, the receiver controller generates a global synchronization signal to uniformly trigger the reading operation of all shallow elastic buffer units, thereby realizing the multi-beam IQ data alignment.

[0080] At the physical level, a non-empty status flag in a shallow-depth elastic buffer unit (typically a first-in, first-out sequence) indicates that the data for that channel has successfully crossed the clock domain and is stably stored in the buffer awaiting retrieval. Only when the buffer units of all links connected to the receiver controller (e.g., 1024 channels) simultaneously indicate non-empty status does it signify that the data for the entire phased array has arrived at the receiver, providing the physical basis for beamforming.

[0081] The logic for generating the global synchronization signal is implemented in hardware through a large-scale AND logic gate or an equivalent state machine. The receiver controller takes the non-empty signals of all shallow-depth elastic buffer units as inputs and performs logical operations. Only when all input conditions are met simultaneously will the output of the logic gate flip to a high level, generating a global synchronization pulse.

[0082] Since the source-end pre-biasing in step S4 has eliminated the macroscopic transmission delay differences between links, theoretically, the time difference between all data streams arriving at the receiver has been compressed to a very small range. Therefore, the first data word read from each first-out-first-out queue at this time must correspond to the IQ data sample at the same sampling time (e.g., t=0). Through this concurrent reading mechanism, the multiple parallel data streams are strictly aligned on the time axis before entering subsequent digital signal processing modules (such as beamformers).

[0083] Timing constraints are crucial in this process. The clock distribution network inside the receiver controller must undergo strict clock skew control to ensure that the physical delay difference of the global synchronization signal arriving at each FIFO queue read port is controlled at the picosecond level, which is much less than a system clock cycle. This is to prevent different channels from starting to read at different clock cycles due to inconsistent signal arrival times, thus compromising synchronization accuracy.

[0084] Specifically, the sub-steps of S7 include S71-S73.

[0085] S71. When it is detected that any of the shallow elastic buffer units corresponding to the optical transmission link changes from an empty state to a non-empty state, the receiver controller starts a synchronization timeout timer.

[0086] S72. Determine whether the shallow elastic buffer units corresponding to all other optical transmission links have changed to a non-empty state within the preset synchronization timeout period.

[0087] S73. If the determination result is yes, the receiving end controller generates the global synchronization signal; if the determination result is no, the receiving end controller determines that the current synchronization has failed and triggers the link reset process.

[0088] The synchronization timeout timer is set to define an acceptable window of residual error. Although the source-side pre-bias has compensated for most of the latency, residual random jitter may still exist in the physical link. The timer limits the maximum tolerable time for the system to wait for all data to arrive, preventing the system from falling into a deadlock state of infinite waiting due to a link failure or packet loss.

[0089] The receiver controller monitors the logical OR output of the non-empty signals of all channels. When the data from the physically fastest transmitting channel arrives at the receiver and is written into the FIFO sequence, its non-empty signal flips. This action immediately triggers a timer to start counting through the OR gate. This marks the earliest arrival time of the current synchronization cycle.

[0090] The preset synchronization timeout range is typically set slightly larger than the number of clock cycles that the depth of the FIFO queue can accommodate. For example, if the depth of the FIFO queue is 8 words, the timeout threshold can be set to 10 cycles. If the earliest arriving data waits in the FIFO queue for more than 10 cycles before the latest data arrives, the earliest arriving data will be lost due to FIFO queue overflow, meaning synchronization has failed.

[0091] When the timer's count reaches a preset threshold, the logic circuit checks the state of the global AND gates. If the global synchronization signal has not yet been generated (i.e., some channels are still empty), it is determined that the synchronization has timed out.

[0092] If a timeout occurs, it means that the delay data measured in step S1 may be invalid (e.g., due to a sudden change in fiber length caused by external force stretching), or that the source-end pre-bias parameters were calculated incorrectly. Forcing processing in this situation will result in incorrect beam pointing. Therefore, the controller must reset all transmit and receive logic and re-execute the delay measurement and calibration process from S1 to S4 to ensure system reliability.

[0093] Specifically, the method further includes a dynamic thermal drift compensation step S8, which specifically includes S81-S83.

[0094] S81. The receiving end controller periodically executes steps S1 and S2 during data transmission gaps to obtain real-time delay drift, wherein the real-time delay drift represents the difference between the currently measured round-trip transmission delay and the initially calibrated round-trip transmission delay.

[0095] S82. If the real-time delay drift exceeds a preset delay drift threshold, the receiving end controller calculates the updated fractional clock cycle component based on the real-time delay drift and sends the updated fractional clock cycle component to the transmitting end controller.

[0096] S83. The transmitting end controller, while keeping the read pointer position of the source end transmitting buffer unit unchanged, generates corresponding filter tap coefficients using the updated fractional clock cycle component and updates the digital fractional delay filter, wherein the shallow-depth elastic buffer unit is configured to maintain the output continuity of the multi-beam IQ data during the coefficient update of the digital fractional delay filter.

[0097] Temperature fluctuations can alter the refractive index of optical fiber cores and cause thermal expansion and contraction of the fiber's physical length. Although the change per unit length is small, in long-distance transmission and high-frequency carrier applications, the accumulated time delay changes translate into a non-negligible phase rotation, directly reducing the pointing accuracy and gain of the beamforming system.

[0098] The receiver controller inserts ranging beacons using a silence period defined in the communication protocol (such as the guard interval in TDD or the interval between radar pulse transmissions). This time-slot multiplexing mechanism ensures that the measurement signal does not occupy service bandwidth or conflict with high-throughput IQ data streams.

[0099] The measurement circuitry and photoelectric conversion devices themselves inherently possess quantization noise and random jitter. If the system responds to every tiny measurement fluctuation, it will cause frequent oscillations in the transmitter filter coefficients, increasing power consumption and introducing additional phase noise. Only when the accumulated changes in the physical link exceed the delay drift threshold (e.g., 0.1 ns) does the system recognize substantial thermal drift and trigger compensation.

[0100] Thermal drift is a slow, continuous physical process, with very few instantaneous jumps exceeding one clock cycle. Locking the read pointer of the source-end transmit buffer ensures the stability of the macroscopic data frame structure and prevents data duplication or loss caused by pointer adjustments. The system only adjusts the digital fractional delay filter to perform minute stretching or compression of the signal waveform on a subsampling time scale.

[0101] In this process, the shallow-depth elastic buffer unit plays a crucial buffering role. When the coefficients of the digital fractional delay filter are updated, the group delay of the output signal will change slightly (e.g., the delay increases by 50 ps). The shallow-depth buffer unit at the receiver uses its internal storage margin to absorb this instantaneous phase transient, ensuring that the data stream output to the subsequent processing logic remains smooth in timing and will not be interrupted due to parameter switching at the source.

[0102] Specifically, the sub-steps of S83 include S831-S834.

[0103] S831. The transmitting controller calculates the difference between the updated fractional clock cycle component and the currently used fractional clock cycle component.

[0104] S832. Determine whether the absolute value of the difference is less than the preset maximum delay adjustment step size.

[0105] S833. If the absolute value of the difference is less than the preset maximum delay adjustment step size, the transmitting controller directly updates the digital fractional delay filter using the updated fractional clock cycle component.

[0106] S834. If the absolute value of the difference is greater than or equal to the preset maximum delay adjustment step size, the transmitting end controller decomposes the difference into multiple consecutive small adjustment steps and updates the digital fractional delay filter clock cycle by clock cycle until the updated fractional clock cycle component is reached.

[0107] If the time delay parameter is abruptly changed from one value to another, the output waveform of the digital fractional delay filter will exhibit discontinuous steps at the switching moment. This discontinuity in the time domain manifests as spectral regrowth in the frequency domain, generating high-frequency interference components, which may lead to phase-locked loop (PLL) loss of lock at the receiver or misjudgment by subsequent demodulation algorithms.

[0108] The preset maximum delay adjustment step size specifies the maximum magnitude of the filter group delay change per unit time (e.g., a maximum adjustment of 0.01 cycles per clock cycle), thereby limiting the sliding speed of the signal waveform on the time axis and ensuring the smoothness of the adjustment process.

[0109] For minute differences (smaller than the maximum step size), the transmitter controller employs direct update logic. This typically corresponds to normal minor thermal drift correction or fine-tuning of measurement noise. Directly applying the new parameters eliminates residual errors as quickly as possible, improving the system's dynamic response.

[0110] For large differences (greater than or equal to the maximum step size), the transmitting controller employs a decomposed step strategy. This may occur when the system has just started up and thermal equilibrium has not yet been established, or when the ambient temperature changes drastically. The controller initiates ramp generation logic, cutting the total target difference into a series of intermediate values ​​that conform to the step size limit.

[0111] Cycle-by-cycle updates enable smooth time delay sliding in both the digital and analog domains. The controller loads a new intermediate coefficient each clock cycle, causing the filter's group delay to gradually approach the target value in tiny steps. This process mathematically reconstructs the continuous trajectory of the signal waveform along the time axis, physically eliminating the risks associated with phase abrupt changes and ensuring the phase continuity and spectral purity of the IQ data during dynamic compensation.

[0112] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0113] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A multi-beam IQ data synchronization method based on source-end pre-biasing and receiver-end shallow buffering, characterized in that, Includes the following steps: S1. The receiver controller measures the round-trip transmission delay of the optical transmission link corresponding to each transmitter controller connected to the receiver controller; S2. The receiving end controller calculates the target pre-offset amount for each of the transmitting end controllers based on the round-trip transmission delay of all the optical transmission links, wherein the target pre-offset amount includes an integer clock cycle component and a fractional clock cycle component. S3. The receiving end controller feeds back the integer clock cycle component and the fractional clock cycle component to the corresponding transmitting end controller; S4. The transmitting end controller uses the integer clock cycle component to adjust the read pointer start time of the source end transmitting buffer unit located inside the transmitting end controller, and uses the fractional clock cycle component to control the digital fractional delay filter to perform fractional delay processing on the multi-beam IQ data to be transmitted. S5. The transmitting end controller sends the processed multi-beam IQ data to be transmitted to the receiving end controller; S6. The receiver controller uses a shallow-depth elastic buffer unit located after the physical layer receiver interface of the receiver controller to receive the multi-beam IQ data, wherein the storage depth of the shallow-depth elastic buffer unit is configured to be less than the delay adjustment range corresponding to the integer clock cycle component, and the shallow-depth elastic buffer unit is only configured to absorb residual phase jitter and cross-clock domain transmission noise after the source active pre-bias operation. S7. When the receiver controller detects that all shallow elastic buffer units corresponding to the optical transmission links are in a non-empty state, the receiver controller generates a global synchronization signal to uniformly trigger the reading operation of all shallow elastic buffer units, thereby realizing the multi-beam IQ data alignment.

2. The multi-beam IQ data synchronization method according to claim 1, characterized in that, Step S1 includes the following sub-steps: S11. The receiving end controller inserts a preset ranging beacon into the physical layer encoded stream to be transmitted, and broadcasts the ranging beacon to all the transmitting end controllers; S12. After receiving the ranging beacon through its own physical layer receiving interface, each of the transmitting end controllers uses the hardware loopback path connecting its own physical layer receiving interface and its own physical layer transmitting interface to return the ranging beacon to the receiving end controller via the original path. S13. The receiver controller uses a local clock counter to record the time difference from sending the ranging beacon to receiving the returned ranging beacon, and marks the time difference as the round-trip transmission delay.

3. The multi-beam IQ data synchronization method according to claim 1, characterized in that, Step S2 includes the following sub-steps: S21. The receiver controller selects the maximum value from all measured round-trip transmission delays and defines the maximum value as the maximum link delay; S22. The receiving end controller calculates the difference between the maximum link delay and the round-trip transmission delay of each of the sending end controllers; S23. The receiving end controller takes half of the difference as the target pre-bias value, and performs modulo operation decomposition on the target pre-bias value according to the system clock cycle, thereby separating the integer clock cycle component and the fractional clock cycle component.

4. The multi-beam IQ data synchronization method according to claim 1, characterized in that, The digital fractional delay filter in step S4 is a Farrow structure filter or a polyphase interpolation filter. The digital fractional delay filter is configured at the end of the transmission link of the transmitting controller. The digital fractional delay filter is configured to introduce a group delay of less than one system clock cycle while keeping the data sampling rate constant. The group delay represents the overall time shift of the signal waveform of the multi-beam IQ data in the time domain.

5. The multi-beam IQ data synchronization method according to claim 1, characterized in that, In step S6, the storage depth of the shallow-depth elastic buffer unit is configured to be 4 to 16 data words, and the shallow-depth elastic buffer unit is not used to compensate for the macroscopic transmission delay differences between different optical transmission links.

6. The multi-beam IQ data synchronization method according to claim 4, characterized in that, The method further includes a dynamic thermal drift compensation step: S81. The receiving end controller periodically executes steps S1 and S2 during data transmission gaps to obtain real-time delay drift, wherein the real-time delay drift represents the difference between the currently measured round-trip transmission delay and the initially calibrated round-trip transmission delay. S82. If the real-time delay drift exceeds a preset delay drift threshold, the receiving end controller calculates the updated fractional clock cycle component based on the real-time delay drift and sends the updated fractional clock cycle component to the transmitting end controller. S83. The transmitting end controller, while keeping the read pointer position of the source end transmitting buffer unit unchanged, generates corresponding filter tap coefficients using the updated fractional clock cycle component and updates the digital fractional delay filter, wherein the shallow-depth elastic buffer unit is configured to maintain the output continuity of the multi-beam IQ data during the coefficient update of the digital fractional delay filter.

7. The multi-beam IQ data synchronization method according to claim 1, characterized in that, The sub-step of S7 includes: S71. When it is detected that any of the shallow elastic buffer units corresponding to the optical transmission link changes from an empty state to a non-empty state, the receiver controller starts a synchronization timeout timer; S72. Determine whether the shallow elastic buffer units corresponding to all other optical transmission links have changed to a non-empty state within the preset synchronization timeout period; S73. If the determination result is yes, the receiving end controller generates the global synchronization signal; if the determination result is no, the receiving end controller determines that the current synchronization has failed and triggers the link reset process.

8. The multi-beam IQ data synchronization method according to claim 6, characterized in that, The sub-step of S83 includes: S831. The transmitting controller calculates the difference between the updated fractional clock cycle component and the currently used fractional clock cycle component; S832. Determine whether the absolute value of the difference is less than the preset maximum delay adjustment step size; S833. If the absolute value of the difference is less than the preset maximum delay adjustment step size, the transmitting end controller directly updates the digital fractional delay filter using the updated fractional clock cycle component. S834. If the absolute value of the difference is greater than or equal to the preset maximum delay adjustment step size, the transmitting end controller decomposes the difference into multiple consecutive small adjustment steps and updates the digital fractional delay filter clock cycle by clock cycle until the updated fractional clock cycle component is reached.

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