Pad structures in memory circuits, methods of making pad structures in memory circuits, and systems utilizing memory circuits

Abstract

A pad structure in a memory circuit, a method of manufacturing a pad structure in a memory circuit, and a system utilizing a memory circuit are disclosed. The contact pad structure includes at least a first pad and a second pad. A first pad is on a first contact point and is connected to a first word line (WL), the first WL being longitudinally arranged in a first direction and being a first distance from the first contact point. A second pad is on a second contact point and is connected to a second WL that is longitudinally arranged in the first direction and is a second distance from the second contact point. The first pad and the second pad are aligned in the second direction based on the first contact point and the second contact point, respectively. The first WL and the second WL correspond to row lines of the memory circuit.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 720,167, filed November 13, 2024, and U.S. Patent Application No. 19 / 230,073, filed June 5, 2025, the disclosures of which are fully set forth herein and are incorporated herein by reference in their entirety. Technical Field

[0002] The disclosure generally relates to memory devices. More specifically, the subject matter disclosed herein relates to contact pad structures for word lines in memory circuits. Background Technology

[0003] This background section is intended to provide context only, and the disclosure of any concept in this section does not constitute an admission that the concept is prior art.

[0004] Three-dimensional (3-D) memory fabrication has been popular. 3-D memory devices, such as vertically stacked dynamic random access memory (VSDRAM) and vertical NAND (V-NAND) flash memory, consist of memory cells stacked vertically to increase storage density. A characteristic of 3-D memory circuitry is the staircase-style arrangement of control lines. Steps are used to form the electrical connections between the control gate and contacts. However, as the number of layers increases, the usable area of ​​the memory channels decreases. Additionally, structural support for a large number of layers can be problematic. Therefore, staircase-free designs aim to eliminate the staircase construction while maintaining the desired density at the same level. A specific feature of staircase-free memory circuitry is the contact structure used for word lines.

[0005] Existing technologies for contact pads used in designing word lines have several problems. One problem is the large parasitic capacitance in the pad area. Another problem is the difficulty in aligning the contact pads.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the disclosed background technology, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0007] To overcome these problems, a system and method for providing a contact pad structure for a memory loop (WL) in a three-dimensional (3-D) memory device are described herein. In some embodiments, the contact pad structure includes at least a first pad and a second pad. The first pad is on and connected to a first contact point, the first WL being arranged longitudinally in a first direction and spaced a first distance from the first contact point. The second pad is on and connected to a second contact point, the second WL being arranged longitudinally in the first direction and spaced a second distance from the second contact point. The first pad and the second pad are aligned in a second direction based on the first contact point and the second contact point. The first WL and the second WL correspond to row lines of a memory circuit.

[0008] In some embodiments, the first pad and the second pad, as well as the first WL and the second WL, are made of conductive material. In some embodiments, the first direction and the second direction are substantially perpendicular. The first pad and the second pad are separated by insulating segments arranged longitudinally in the first direction, and are respectively located within a first portion of the first WL and a second portion of the second WL. Attached Figure Description

[0009] In the following sections, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a system utilizing a 3-D memory circuit according to an embodiment.

[0011] Figure 2 This is a diagram illustrating the pad structure in a 3-D memory circuit according to an embodiment.

[0012] Figure 3 This is a diagram showing a comparison between a pad structure with partial connections and a pad structure with through connections according to an embodiment.

[0013] Figure 4 This is a diagram illustrating the first stage of the manufacturing process of the pad structure according to an embodiment.

[0014] Figure 5 This is a diagram illustrating the second stage of the manufacturing process of the pad structure according to an embodiment.

[0015] Figure 6 This is a diagram illustrating the third stage of the manufacturing process of the pad structure according to an embodiment.

[0016] Figure 7 This is a diagram illustrating the fourth stage of the manufacturing process of the pad structure according to an embodiment.

[0017] Figure 8 This is a diagram illustrating the fifth stage of the manufacturing process of the pad structure according to an embodiment.

[0018] Figure 9 This is a diagram illustrating the sixth stage of the manufacturing process of the pad structure according to an embodiment.

[0019] Figure 10 This is a diagram illustrating the seventh stage of the manufacturing process of the pad structure according to an embodiment.

[0020] Figure 11 This is a diagram illustrating the eighth stage of the manufacturing process of the pad structure according to an embodiment.

[0021] Figure 12 This is a diagram illustrating key features of the pad structure according to an embodiment.

[0022] Figure 13 This is a diagram illustrating a first alternative configuration of the pad structure according to an embodiment.

[0023] Figure 14 This is a diagram illustrating a second alternative construction of the pad structure according to an embodiment.

[0024] Figure 15 This is a flowchart illustrating the process of manufacturing a pad structure for a memory circuit according to an embodiment.

[0025] Figure 16 This is a flowchart illustrating the process of etching contacts in a multilayer structure as part of a process for manufacturing a pad structure for a memory circuit, according to an embodiment.

[0026] Figure 17 This is a flowchart illustrating a portion of the process for forming a lateral recess isolation as a pad structure for manufacturing a memory circuit according to an embodiment.

[0027] Figure 18 This is a flowchart illustrating a process for forming a self-aligning plug, which is part of the process for manufacturing a pad structure for a memory circuit according to an embodiment. Detailed Implementation

[0028] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, those skilled in the art will understand that aspects of the disclosure may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.

[0029] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment," "in an embodiment," or "according to an embodiment" (or other phrases with similar meanings) appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" should not be construed as necessarily preferred or advantageous over other embodiments. Additionally, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Furthermore, depending on the context discussed herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-determined", "pixel-specific", etc.) may occasionally be used interchangeably with their corresponding non-hyphenated versions (e.g., "two-dimensional", "predetermined", "pixel-specific", etc.), and uppercase entries (e.g., "counter clock", "row select", "pixout", etc.) may be used interchangeably with their corresponding non-uppercase versions (e.g., "counter clock", "row select", "pixout", etc.). Such occasional interchangeability should not be considered inconsistent with each other.

[0030] Furthermore, depending on the context of this discussion, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various figures shown and discussed herein (including component diagrams) are for illustrative purposes only and are not drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to others. Additionally, reference numerals have been repeated in the figures where appropriate to indicate corresponding and / or similar elements.

[0031] The terminology used herein is for the purpose of describing some exemplary embodiments only and is not intended to limit the claimed subject matter. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0032] It will be understood that when an element or layer is referred to as being on, "connected to," or "bonded to" another element or layer, it may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or layers present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, there are no intermediate elements or layers present. The same reference numerals always denote the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] As used herein, unless explicitly defined as such, the terms "first," "second," etc., are used as labels for nouns that follow them and do not indicate any kind of order (e.g., spatial, temporal, logical, etc.). Furthermore, the same reference numerals may be used in two or more figures to denote parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such use is merely for simplification and ease of discussion and does not imply that the construction or architectural details of such components or units are identical across all embodiments, or that such commonly referenced parts / modules are the only way to implement some of the exemplary embodiments disclosed herein.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject pertains. It will also be understood that, unless clearly defined herein, terms (such as those defined in general dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0035] Many applications, particularly in artificial intelligence (AI) and signal processing, require massive storage capacity and high-throughput computing. To meet these needs, high-density memory circuits with 3D fabrication have been developed. Hereinafter, systems and methods are described as techniques for providing contact pad structures for word lines (WLs) in 3D memory devices. In some embodiments, the contact pad structure includes at least a first pad and a second pad. The first pad is located at a first contact point and connected to a first WL, which is longitudinally arranged in a first direction and spaced a first distance from the first contact point. The second pad is located at a second contact point and connected to a second WL, which is longitudinally arranged in the first direction and spaced a second distance from the second contact point. The first pad and the second pad are aligned in a second direction based on the first and second contact points, respectively. The first WL and the second WL correspond to row lines of the memory circuit.

[0036] In some embodiments, the first pad and the second pad, as well as the first WL and the second WL, are conductive materials. In some embodiments, the first direction and the second direction are substantially perpendicular. The first pad and the second pad are separated by insulating segments arranged longitudinally in the first direction and are located within a first portion of the first WL and a second portion of the second WL, respectively.

[0037] The contact pad structure described herein offers several technical advantages. The pad is located within a small portion adjacent to the contact element (WL), rather than occupying the entire length of the WL. Therefore, parasitic capacitance is significantly reduced, improving signal integrity in high-speed applications. By using conductive materials (e.g., metals) only where contact is required, the manufacturing process is simplified and costs are reduced. Furthermore, the pad is self-aligning by means of the contact element, eliminating the need for alignment processes or tooling. This is particularly advantageous in the manufacturing process.

[0038] In the following text, the accompanying drawings depicting various components, structures, interconnections, constructions, and manufacturing steps are primarily for illustrative purposes. They are not intended to accurately describe these elements. In some cases, relevant portions in the drawings are shown clearly, while other portions are shown with lower sharpness or definition to avoid confusion and improve clarity. These portions may have been referenced in preceding drawings and therefore do not need to be described again. These portions may also have little to do with the portions being described. Furthermore, the shading of parts in the drawings may not have a consistent design and may be altered to maintain sharpness and contrast in the drawings. For example, portion A in… Figure X The image may have a light shading, but it may have a dark shading in Figure Y. Furthermore, as mentioned above, components in the accompanying drawings may not be drawn to scale.

[0039] Figure 1This is a block diagram illustrating a system utilizing 3-D memory circuitry according to an embodiment. System 100 includes digital baseband circuitry 105, radio frequency (RF) transceiver circuitry 150, and analog baseband circuitry 170. System 100 may represent a digital system or a mobile system. When system 100 is used as a digital system without mobile circuitry, RF transceiver circuitry 150 and analog baseband circuitry 170 are not used. Additionally, when system 100 is used as a mobile device, many digital features are scaled down, and some features may be unavailable.

[0040] The digital baseband circuit 105 includes a central processing unit (CPU) 110, a memory controller 120, and an input / output (I / O) controller 130. System 100 may include more or fewer components than those listed above. Additionally, components may be integrated into another component. This integration may be partial and / or overlapping. For example, memory controller 120 and I / O controller 130 may be integrated into a single controller.

[0041] CPU 110 is a programmable device that can execute programs or sets of instructions to perform tasks. CPU 110 can be a host that controls or manages other processors or devices. Specifically, CPU 110 may include an application programming interface (API), application, or driver executed by CPU 110 to perform specific tasks. CPU 110 may be a general-purpose processor, a digital signal processor, a microcontroller, or a specially designed processor. CPU 110 may include a single core or multiple cores. Each core may have multiple threads. CPU 110 may have simultaneous multithreading features to further utilize the parallelism caused by multiple threads across multiple cores. Additionally, CPU 110 may have multiple levels of internal cache. CPU 110 communicates with other devices in the system via bus 115. Bus 115 can be any suitable bus that connects CPU 110 to other devices. For example, bus 115 may be a direct media interface (DMI). Bus 115 may also include other custom buses (such as a bus for interfacing to the analog portion when system 100 is used as a mobile device).

[0042] Memory controller 120 controls memory devices such as main memory 122, cache memory 124, and flash memory 126. Main memory 122 includes RAM comprising static random access memory (RAM) (SRAM) and dynamic RAM (DRAM), and / or read-only memory (ROM) and other types of memory. DRAM may include synchronous DRAM (SDRAM), DDR SDRAM with variants such as second-generation double data rate (DDR2), DDR3, DDR4, DDR5, and DDR6. Main memory 122 may store instructions or programs loaded from a mass storage device that, when executed by CPU 110, cause CPU 110 to perform a specific task. Main memory 122 may also store data used in operation. ROM may be a solid-state drive (SSD) and includes instructions, programs, constants, or data that are maintained regardless of whether it is powered on or off. In one embodiment, main memory 122 includes 3-D memory devices or circuitry 128 (such as VSDRAM and V-NAND flash memory), or any other memory device having memory cells vertically stacked to increase storage density.

[0043] I / O controller 130 controls input device 132, output device 134, and mass storage device 136. Input device 132 may include a keyboard, mouse, image sensor or camera, game console, and microphone. Other input devices, such as styluses, joysticks, scanners, and light pens, may also be available. Input devices may also have a user interface that interfaces with a computer or laptop computer 142 and / or user 144. Output device 134 may include a printer, monitor or screen, headphones, and multi-monitor sets. When used as a computing device without mobile features, a monitor is a high-resolution display. For gaming and other multi-monitor modes, multi-monitor sets provide high resolution with multiple monitors (e.g., three monitors). When used for mobile communications, a screen provides the user with a primary interface for navigation, accessing various applications, and performing tasks. The screen may use an organic light-emitting diode (OLED) (Super Retina) display with multi-touch or haptic touch features. Mass storage device 136 may include CD-ROM, hard disk, and solid-state drive (SSD). I / O controller 130 also has a network interface card (NIC) 146 that provides an interface to a network and wireless medium (or network) 148.

[0044] Additional devices or bus interfaces can be used for interconnection and / or expansion. Some examples may include the Peripheral Component Interconnect Fast (PCIe) bus, Universal Serial Bus (USB), etc.

[0045] The RF transceiver circuit 150 includes a transmitter 152, an antenna array 158, a voltage-controlled oscillator (VCO) 156, and a receiver 154. The RF transceiver circuit 150 operates in the high GHz band to accommodate modern cellular devices such as wireless fifth generation (5G).

[0046] Transmitter 152 transmits digital baseband data to antenna array 158. Transmitter 152 may include a digital-to-analog converter (DAC), an automatic gain controller (AGC), intermediate frequency (IF) circuitry, a mixer, RF circuitry, and a power amplifier (PA). Other components may include filters, amplifiers, multiplexers, coaxial cables, phase shifters, etc. The DAC converts digital data f1 (not shown) into an analog signal f2 (not shown). The AGC automatically adjusts the signal amplitude of f2 to generate a signal f3 (not shown) to maintain a consistent strength level in dynamic and changing environments. The IF circuitry performs intermediate frequency processing (such as filtering) to generate a signal f4 (not shown). The mixer converts the frequency of signal f4 to another frequency. This is done by mixing signal f4 with a signal v from VCO 156. t (Not shown) Mixing is used to accomplish this. Mixing here refers to frequency modulation that transforms signal f4 into a signal f5 (not shown) of a different frequency. For the transmitter, the transformed frequency is higher than the frequency of f4. This conversion is called upconversion. For 5G communication, the frequency range can include low-frequency bands (below 1 GHz), mid-frequency bands (1 GHz to 6 GHz), and high-frequency bands (24 GHz to 53 GHz or higher). The resulting signal f5 then undergoes various radio frequency processing (such as high-pass filtering) performed by RF circuitry to produce signal f6 (not shown). Signal f6 is boosted and amplified by a PA to produce signal f7 (not shown). Signal f7 then enters antenna array 158 to be transmitted to the appropriate destination and medium (e.g., a base station). Antenna array 158 uses beamforming to focus the radio waves from f7 in the desired direction. Antenna array 158 can be used for both transmitting and receiving. In reception, antenna array 158 receives RF signals and transmits them to receiver 154. The number of antennas in antenna array 158 depends on the desired coverage area. Antenna array 158 may include antennas 161, 162, 163, and 164 configured to operate in conjunction with 5G communication, Gigabit LTE, Wi-Fi (e.g., 2.4 GHz, 5 GHz, and 6 GHz), and Bluetooth, respectively. The number of antennas may be more or less than the above.

[0047] The VCO 156 couples multiple in-phase oscillators together to provide low phase noise oscillation. The VCO 156 directs the signal v at a specific frequency. t and v r(Not shown) Generated to the mixer. The VCO 156 may include multiple oscillator core circuits (or VCO cores) to provide high-frequency periodic signals.

[0048] Receiver 154 processes the received signal r7 (not shown) in the reverse manner of transmitter 152. Receiver 154 may include a low-noise amplifier (LNA), RF circuitry, a mixer, IF circuitry, AGC, and an analog-to-digital converter (ADC). Receiver 154 may include more or fewer components than those listed above. The LNA amplifies the weak signal r7 while maintaining a good signal-to-noise ratio (SNR) to produce a signal r6 (not shown) for further processing. Signal r6 is then processed by RF circuitry (e.g., bandpass filtering) to provide signal r5 (not shown). Additional filtering may be performed in the next stage. Signal r5 is then compared with signal v from VCO 156. r A mixer is used to downconvert signal r5 to a signal r4 (not shown) at a suitable low frequency. Similar to the mixer in transmitter 152, but with the opposite operation, the mixer in receiver performs frequency modulation to convert the high-frequency signal r5 into the low-frequency signal r4. Signal r4 is processed by an IF circuit (e.g., additional filtering) to produce signal r3 (not shown). An AGC amplifies and enhances the signal and generates signal r2 (not shown). An ADC converts analog signal r2 into digital data r1 (not shown) that will be processed by CPU 110.

[0049] Analog baseband circuit 170 provides analog processing for various components. Analog baseband circuit 170 controls the processing of signals and data between digital baseband circuit 105 and RF transceiver circuit 150. Analog baseband circuit 170 may include analog and digital components for performing various tasks, including modulation / demodulation and controlling RF transceiver circuit 150, and special circuitry for 3G, 4G / LTE, Bluetooth, and 5G communications (e.g., baseband unit (172)). Analog baseband circuit 170 may also interface with audio device circuit 174, sensor circuit 176, subscriber identity module (SIM) card 178, and other components. Audio device circuit 174 may include operation blocks for processing audio signals and performing audio-related functions such as filtering, correlation, and speech recognition. Audio device circuit 174 may include digital circuitry for performing Fast Fourier Transform (FFT) to perform signal processing in the frequency domain. Sensor circuitry 176 may include various sensors, such as proximity sensors, ambient light sensors, motion sensors (accelerometers and gyroscopes), compasses, barometers, fingerprint sensors for touch recognition (ID), image sensors for facial ID, light detection and ranging (LiDAR) scanners, etc. SIM card 178 is a small, portable chip that stores the user's phone number and carrier information, allowing the device to connect to a cellular network.

[0050] The power and battery circuitry (or power / battery) 180 provides backup power and battery supply to the entire system. The power and battery circuitry 180 may include a charger to charge the battery. The battery may be a rechargeable lithium-ion battery. Power management may be performed by application software and circuitry to provide low-power modes and performance management.

[0051] System 100 is an example illustrating the role of 3-D memory devices in laptop, desktop, or mobile environments. In many cases, the environment of the application adds additional requirements, including low power consumption, reliable signal integrity, fault tolerance, and reliable operation under extreme conditions, including heat and confined spaces. Examples of other applications that would benefit from 3-D memory devices or circuits include mobile communications (e.g., smartphones, base stations, user equipment), cameras, vehicles, entertainment (e.g., games, multimedia, music, movies), technical design (e.g., animation, graphics), medical (e.g., visualization, medical imaging), robotics, drones, automated test equipment, audio processing, speech synthesizers, video and image analytics, vision, automated facial recognition, artificial intelligence (AI) applications, and data centers.

[0052] Figure 2 This is a diagram illustrating the pad structure in a 3-D memory circuit 128 according to an embodiment. The 3-D memory circuit 128 includes a circuit system of memory cells for stacking, word lines (WLs), bit lines, select transistors, and interconnects for data transfer and control. These components are not shown in the diagram. Figure 2 As shown in the image. Conversely... Figure 2 The 3-D structures 210, 220, and 250 are shown.

[0053] 3-D structure 210 depicts a typical 3-D circuit comprising several layers of semiconductor fabrication material, including dielectrics, oxides, silicon, and others. 3-D structure 210 includes cutouts showing WL pad regions 215 corresponding to 3-D structures 220 and 250. 3-D structure 220 shows WLs 222 and 224 extending along the length of WL pad regions 215. WLs 222 and 224 are deposited with a conductive material including metals. 3-D structure 250 shows pad structure 260 and contact posts 265. Although only one component of each type is labeled, other similar components are also labeled accordingly. Pad structure (or contact pad structure) 260 is the structure that connects contact posts 265 to WLs 222 and 224. Contact posts 265 and other posts can be holes, vias, or plugs filled with a conductive material including metals (such as tungsten (W)). Contact posts 265 provide electrical connections to various interconnect elements in the circuit, such as WLs, bit lines, etc. like Figure 2As shown, contact post 265 is connected to pad structure 260, which in turn is connected to WL 222 and 224. In some embodiments, pad structure 260 may include a first pad 262 and a second pad 264.

[0054] Figure 3 This is a diagram illustrating a comparison between a pad structure 260 with partial connections and a pad structure with integral connections according to an embodiment. The comparison is shown using top views 310 and 350. Top view 310 shows a view from the top of pad structure 260, and top view 350 shows a view from the top of a pad structure with integral connections, which includes a whole or nearly whole WL in the WL pad region. Top view 350 may correspond to the prior art.

[0055] The pad structure 260 includes two regions separated by a dielectric or insulating layer (or insulating segment) 345. In some embodiments, the dielectric or insulating layer (or insulating segment) 345 may include one of a dielectric and an oxide. The two regions include two pads: a first pad 312 and a second pad 314. The first pad 312 is disposed, placed, positioned, arranged, located at, or on the first contact point 322. The first contact point 322 is shown in dashed lines to indicate that it is below the first pad 312. The first contact point 322 is used to make electrical contact with one or more points or components in the circuit. The first pad 312 is placed directly on and connected to the first contact point 322. In addition to being connected to the first contact point 322, the first pad 312 is also connected to a WL 332. The WL 332 extends from the WL of a memory cell in the memory circuit. The WL 332 is arranged longitudinally or elongated in a first direction 320 and is located at a first distance d1 from the first contact point 322.

[0056] The second pad 314 is similarly constructed in a symmetrical manner. The second pad 314 is disposed, placed, positioned, arranged, located on, or situated on the second contact point 324. The second contact point 324 is shown in dashed lines to indicate that it is below the second pad 314. The second contact point 324 is used to make electrical contact with one or more points or components in the circuit. The second pad 314 is placed directly on and connected to the second contact point 324. In addition to being connected to the second contact point 324, the second pad 314 is also connected to WL 334. WL 334 extends from the WL of the memory cell in the memory circuit. WL 334 is arranged longitudinally or longitudinally in the first direction 320 and is a second distance d2 from the second contact point 324. WL 332 and 334 correspond to the row lines of the memory circuit 128. Assuming that the geometry of WL 332 and 334 is similar, the distances d1 and d2 are also similar.

[0057] At least three aspects exist in the pad structure 260. In the first aspect, the width of WL 332 or 334 is much smaller than the width of the first pad 312 or the second pad 314. Therefore, even if WL 332 or 334 extends the entire length of the WL pad region, the total area of ​​WL 332 or 334 is much smaller than if the width of WL 332 or 334 were the same as the width of the first pad 312 or the second pad 314. This aspect will become relevant when compared with the pad structure shown in top view 350. In the second aspect, the first pad 312 and the second pad 314 have small areas, occupying only a local segment 342 of the first WL 332 and a local segment 344 of the second WL 334, respectively. Typically, this small area only needs to be large enough to make a good connection with the corresponding contact point so as to cover the entire contact point. Therefore, the total area of ​​metal in the entire pad structure, including the WL and the pads, is much smaller than if the entire length of the WL were used to connect to the contact point. In the third aspect, the first pad and the second pad are aligned in the second direction 330 based on the first contact point and the second contact point, respectively. Since the position of the contact point provides the position of the pad, the alignment is self-alignment.

[0058] Top view 350 shows a first WL 362 and a second WL 364. These two WLs are separated by a dielectric or insulating layer 365 extending along the WL. These two WLs occupy the entire width from the outer layer to the insulating layer 365. They are positioned directly above all contact points and areas without contact points (such as regions 371 and 372). Contact points typically include a core region 355 and a dielectric circular segment 353 surrounding the core region 355. As illustrated in segment 374, the two WLs extend the entire length. Compared to the pad structure in top view 310, the pad structure in top view 350 utilizes significantly more metal and therefore introduces more parasitic capacitance. Numerous wasted metal areas exist (such as regions 371 and 372).

[0059] Pad structure 260 can be passed Figures 4 to 11 The manufacturing process shown is formed. Figures 4 to 11 The illustrations shown are for illustrative purposes only and are not intended to describe exact components or structures. As mentioned earlier, in some cases, related components in the figures are shown clearly, while other components are shown with lower sharpness or definition to avoid confusion and improve clarity. Some components may be shown with white outlines or boundary lines to provide good visual display. These components may have been referenced in the preceding figures and therefore do not need to be described again. These components may also have little to do with the components being described. In addition, the shading of components in the figures may not have a consistent design and may be altered to maintain sharpness and contrast in the figures. Figures 4 to 11 Each of the accompanying diagrams shows three views: a 3-D view with a cutout in the upper left corner, a vertical view in the upper right corner, and a top view at the bottom.

[0060] Figure 4 This is a diagram illustrating the first stage 400 of the manufacturing process of the pad structure according to an embodiment. The first stage 400 includes views 410, 450, and 470. View 410 is a 3-D view with cutouts to show the overall structure. View 450 shows a vertical plane. View 470 shows a top view.

[0061] In view 410, the first stage 400 extends WL 412 and 414 into the WL pad region to become WL 422 and WL 424, respectively. The separator dielectric layer 416 becomes 426 in the WL pad region. In view 450, horizontal lines 414 and 412 represent WL. View 450 also shows horizontal lines 425 and 454. In view 470, WL 422 and 424 are shown as extending parallel within the WL pad region 475.

[0062] Figure 5 This is a diagram illustrating a second stage 500 of the manufacturing process for a pad structure according to an embodiment. The second stage 500 includes a 3-D view 510, a vertical view 550, and a top view 570. The second stage 500 performs a cell metal contact (CMC) process to create contact holes, vias, or plugs. The second stage 500 includes steps for forming contact holes: forming a hard mask, patterning using the hard mask to create a pattern, and etching using the pattern.

[0063] 3-D view 510 shows the etching of contact hole 515 and WL 422 and 424. Vertical view 550 shows the etching of contact hole 515 as seen on a vertical surface. Reference numeral 515 indicates any of the etched contact holes and is not necessarily the same contact hole. Because CMC etching does not create any new components when viewed from the top, top view 570 is similar. Figure 4 The top view is the same as 470 in the figure.

[0064] Figure 6 This is a diagram illustrating the third stage 600 of the manufacturing process of the pad structure according to an embodiment. The third stage 600 includes a 3-D view 610, a vertical view 650, and a top view 670. The third stage 600 performs multilayer etching via WL.

[0065] 3-D view 610 shows the etching of contact hole 615 and WL 422 and 424. Vertical view 550 shows the etching of contact hole 615 as seen on a vertical surface. Reference numeral 615 indicates any of the etched contact holes and is not necessarily the same contact hole. Because CMC etching does not create any new components when viewed from above, the top view 670 shows the etching of contact hole 615. Figure 4 The top view is the same as 470 in the figure.

[0066] In 3-D view 610, contact hole 615 is shown as further etched down through the layer. Vertical view 650 shows the same situation in a vertical view. Top view 670 shows the initial arrangement of contact points 675. Two locations of contact point 685 are shown.

[0067] Figure 7 This is a diagram illustrating the fourth stage 700 of the manufacturing process of the pad structure according to an embodiment. The fourth stage 700 includes a 3-D view 710, a vertical view 750, and a top view 770. The fourth stage 700 performs the formation and finishing of lateral recess isolation. The formation and finishing of the lateral recess isolation includes the steps of lateral etching, dielectric deposition, and removal of excess dielectric.

[0068] 3-D view 710 shows contact hole 715 and WL 422 and 424. Vertical view 750 shows contact hole 715 on a vertical surface. Top view 770 shows the location of two contact points 785.

[0069] Figure 8 This is a diagram illustrating the fifth stage 800 of the manufacturing process of the pad structure according to an embodiment. The fifth stage 800 includes a 3-D view 810, a vertical view 850, and a top view 870. The fifth stage 800 performs etching to reach the target layer.

[0070] 3-D view 810 shows contact holes 815 extending further downward to contact the final or target layer and WL 422 and 424. Vertical view 850 shows contact holes 815 on a vertical surface. Top view 870 shows the locations of the two contact points 885.

[0071] Figure 9 This is a diagram illustrating a sixth stage 900 of the manufacturing process of the pad structure according to an embodiment. The sixth stage 900 includes a 3-D view 910, a vertical view 950, and a top view 970. The sixth stage 900 performs self-aligning plug formation and deposits oxide on the contact points based on the contact points.

[0072] 3-D view 910 shows contact hole 915 with contact pads formed, and WL 422 and 424. Vertical view 950 shows contact hole 915 on a vertical surface. Top view 970 shows the positions of two contact points 985 and the positions of first contact pad 982 and second contact pad 984.

[0073] Figure 10 This is a diagram illustrating the seventh stage 1000 of the manufacturing process of the pad structure according to an embodiment. The seventh stage 1000 includes a 3-D view 1010, a vertical view 1050, and a top view 1070. The seventh stage 1000 performs cleaning or removal of the gate oxide.

[0074] 3-D view 1010 shows gate oxides 1012 and 1014 and WL 422 and 424. Vertical view 1050 shows region 1055 on a vertical surface. Top view 1070 shows the location of the first contact pad 1082 and the second contact pad 1084.

[0075] Figure 11 This is a diagram illustrating the eighth stage 1100 of the manufacturing process of the pad structure according to an embodiment. The eighth stage 1100 includes a 3-D view 1110, a vertical view 1150, and a top view 1170. The eighth stage 1100 performs the deposition of conductive material into the contact holes. Examples of conductive materials include one or more alloys of tungsten, titanium nickel, platinum, rhodium, aluminum copper, silver, gold, or the above metals, or titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.

[0076] 3-D view 1110 shows contact holes 1122, 1124, 1132, and 1134 filled with metal, and WL 422 and 424. In some embodiments, 3-D view 1110 shows regions 1112 and 1114 formed after the removal of gate oxides 1012 and 1014. Vertical view 1150 shows contact holes 1132 and 1134 on a vertical surface. Top view 1170 shows the formation of a first contact pad 1172 and a second contact pad 1174, and corresponding pairs including a first contact pad 1182 and a second contact pad 1184.

[0077] Figure 12 This is a diagram illustrating key features of the pad structure according to an embodiment. Key features of the pad structure are shown in views 1210 and 1250. View 1210 shows a 3-D cutout having pad regions 1215, WL 422 and 424, and a first pad 1212 and a second pad 1214. View 1250 includes a pad structure 1255 comprising a first pad 1252 and a second pad 1254. Key features include: (1) WL 422 and 424 extending and not occupying the entire width of the contact pad; (2) pad region 1215 showing a second pad 1214 partially disposed in a small region at the contact point; and (3) the first pad 1252 and the second pad 1254 respectively positioned at the respective contact points and connected to WL 422 and 424.

[0078] The basic construction of the pad structure is as follows: Figure 3 As shown in the diagram. This basic construction can also be further modified in at least two alternative constructions.

[0079] Figure 13 This is a diagram illustrating a first alternative configuration 1300 of the pad structure according to an embodiment. The first alternative configuration 1300 is shown in three views 1310, 1350, and 1370.

[0080] View 1310 includes an end 1311, a base connector 1314, and a region 1315 including a connector 1312 connected to a conductive pad. End 1311 is an end with a contact hole filled with metal. End 1311 connects to base connector 1314. Connector 1312 is a silicon connector and is located above the conductive pad of base connector 1314. View 1350 shows contact holes 1316 and 1313 and the region corresponding to view 1370. View 1370 shows base connector 1374 and a region 1375 including connector 1372. Base connector 1374 is a modified version of base connector 1314. The connector is separated by dielectric separators 1371 and 1373. The silicon portion of base connector 1314 is removed, leaving only the metal base connector 1374. Connector 1372 is modified according to connector 1312 by replacing the silicon portion with metal. In other words, the silicon connector 1312 above the first conductive pad of the base connector 1314 is replaced with metal. Some dimensional values ​​are provided for illustrative purposes. The width of connector 1372 is approximately 65 nm. The distance between dielectric spacers 1371 and 1373 is approximately 61 nm.

[0081] Figure 14 This is a diagram illustrating a second alternative configuration 1400 of the pad structure according to an embodiment. The second alternative configuration 1400 includes views 1410 and 1450. View 1410 shows two contact holes 1411 and 1412 and the area corresponding to view 1450.

[0082] View 1450 shows base connector 1452 and connector 1455. In some embodiments, view 1450 shows region 1454 including connector 1455. Base connector 1452 is connected to a pad. The connector is separated by dielectric separators 1451 and 1453. Connector 1455 is originally made of silicon. A portion of connector 1455 above the conductive pad of base connector 1452 is replaced by a T-shaped metal structure. Some dimensional values ​​are provided for illustrative purposes. The portion of connector 1455 replaced by metal is approximately 100 nm long. The portion extending from the metal is approximately 45 nm long. The distance between dielectric separators 1451 and 1453 is approximately 61 nm. The thickness of the connector is approximately 22 nm.

[0083] Figure 15 This is a flowchart illustrating a process 1500 for manufacturing a pad structure for a memory circuit according to an embodiment.

[0084] Initially, process 1500 extends the word lines (WL) of the memory circuitry to the WL pad area (box 1510). This extension extends the entire length of the WL as needed, but has a narrow width sufficient to make connections with the contact points. These WLs in Figures 4 to 11These are shown as WL 422 and 424. Next, process 1500 etches the contacts (box 1520) in the multilayer structure. [The remaining text appears to be incomplete and possibly contains errors. A more accurate translation would require the full context.] Figure 16 The etching is further described below. Then, process 1500 forms and trims lateral recesses (box 1530). This is to provide contact holes, vias, or plugs to pass through layers or levels of the WL. Next, process 1500 forms self-aligning plugs at the contact points (box 1540). Self-alignment is performed due to the location of the contact points, and this alignment is in a direction substantially perpendicular to the direction in which the WL extends.

[0085] Then, process 1500 removes the oxide portion around the contact point (box 1550). Next, process 1500 forms a conductive pad around the contact point (box 1560). This is to provide material for conductivity. Process 1500 is then terminated. In some embodiments, the conductive pad can be formed around the contact point by filling the contact hole with a conductive material.

[0086] Figure 16 This illustrates an embodiment. Figure 15 The flowchart shown is a process 1520 for etching contacts in a multilayer structure, which is part of the process for manufacturing a pad structure for a memory circuit.

[0087] At the outset, process 1520 forms a hard mask (box 1610). This can be accomplished using various techniques. In some embodiments, this can be done by depositing a thin film of silicon dioxide, silicon nitride, or a specific metal on a substrate. Next, process 1520 uses the hard mask to pattern it to create a pattern (box 1620). In some embodiments, this can be accomplished using photolithography. Then, process 1520 uses the pattern to etch (box 1630). Etching can be performed using any suitable technique, such as wet etching or dry etching. Next, process 1520 etches contact holes at multiple layers (box 1640) and then terminates.

[0088] Figure 17 This illustrates an embodiment. Figure 15 The flowchart shown is a part of the process for forming a lateral recessed isolation as part of the process for manufacturing a pad structure for a memory circuit.

[0089] At the start, process 1530 performs lateral etching (box 1710). The etching technique can be any suitable technique (including wet or dry etching). Next, process 1530 deposits dielectric into the holes of the contact vias (box 1720). Then, process 1530 removes excess dielectric to finish the contact vias (box 1730). Process 1530 is then terminated.

[0090] Figure 18 This illustrates an embodiment. Figure 15The flowchart shown is a process 1540 for forming a self-aligning plug, which is part of the process for manufacturing a pad structure for a memory circuit.

[0091] At the start, process 1540 performs etching to reach the target layer (box 1810). This is accomplished by etching deep into the layer until the target layer is reached. Next, process 1540 deposits oxide on the contact points based on the contact points (box 1820). Process 1540 is then terminated.

[0092] Embodiments of the subject matter and operations described in this specification may be implemented in digital electronic circuit systems, or in computer software, firmware, or hardware that includes the structures disclosed in this specification and their equivalents, or in a combination of one or more of these. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs (i.e., one or more modules of computer program instructions) encoded on a computer storage medium to be executed by or control the operation of a data processing device. Optionally or additionally, the program instructions may be encoded on artificially generated propagating signals (e.g., machine-generated electrical, optical, or electromagnetic signals), which are generated as encoded information to be transmitted to a suitable receiver device for execution by the data processing device. The computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof, or may be included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof. Furthermore, although the computer storage medium is not a propagating signal, it may be a source or destination of computer program instructions encoded in artificially generated propagating signals. Computer storage media may also be one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices), or may be included in one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). Additionally, the operations described herein can be implemented as operations performed by a data processing device on data stored on one or more computer-readable storage devices or received from other sources.

[0093] While this specification may contain numerous specific details of implementation, these details should not be construed as limiting the scope of any claimed subject matter, but rather as descriptions of specific features of particular embodiments. Specific features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination and even initially claimed in this way, one or more features from a claimed combination may be removed from the combination in some cases, and a claimed combination may refer to a sub-combination or a variation of a sub-combination.

[0094] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific or sequential order shown, or to perform all of the shown operations to achieve the desired result. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0095] Therefore, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing can be advantageous.

[0096] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied across a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any particular exemplary teachings discussed above, but is defined by the appended claims.

Claims

1. A pad structure in a memory circuit, comprising: A first pad is located at a first contact point and connected to a first letter line, the first letter line being arranged longitudinally in a first direction and at a first distance from the first contact point; as well as The second pad is located at the second contact point and connected to the second letter line, the second letter line being arranged longitudinally in the first direction and at a second distance from the second contact point. Wherein, the first pad and the second pad are aligned in the second direction based on the first contact point and the second contact point, respectively, and The first word line and the second word line correspond to the row lines of the memory circuit.

2. The pad structure according to claim 1, wherein, The first direction is perpendicular to the second direction.

3. The pad structure according to claim 1, wherein, The first pad and the second pad are separated by an insulating section arranged longitudinally in a first direction.

4. The pad structure according to claim 1, wherein, The first pad and the second pad are located within the first part of the first letter line and the second part of the second letter line, respectively.

5. The pad structure according to claim 1, wherein, Memory circuits have a three-dimensional structure.

6. The pad structure according to claim 1, wherein, At least one of the first and second pads is connected to a vertical contact hole filled with conductive material.

7. The pad structure according to claim 1, wherein, A portion of the silicon connector above one of the first and second pads was replaced with metal.

8. The pad structure according to claim 1, wherein, A portion of the silicon connector above one of the first and second pads is replaced by a metal structure with a T-shape.

9. The pad structure according to claim 1, wherein, At least one of the first and second pads comprises a metal and titanium nitride, wherein the metal comprises one of tungsten and gold.

10. The pad structure according to claim 1, wherein, The insulating section includes either dielectric or oxide.

11. A method for manufacturing a pad structure in a memory circuit, comprising: Extend the word lines of the memory circuit to the word line pad area; Etching contacts in a multilayer structure; Create a horizontal recessed isolation area and then repair it; A self-aligning plug is formed at the contact point; Remove the oxide residue around the contact points; and A conductive pad is formed around the contact point.

12. The method according to claim 11, wherein, The steps involved in etching contacts in a multilayer structure include: Form a hard mask; Use hard masks to pattern to create patterns; Etching using patterns; and Etch contact holes at multiple layers.

13. The method according to claim 11, wherein, The steps for creating and repairing the lateral recessed isolation include: Perform lateral etching; Deposited dielectric; and Remove excess dielectric.

14. The method according to claim 11, wherein, The steps to form a self-aligning plug include: Perform etching to reach the target layer; and Oxides are deposited on the contact points based on the contact points.

15. The method according to claim 11, wherein, The step of forming a conductive pad around the contact point includes: Use conductive material to fill the contact holes.

16. The method according to claim 11, wherein, Memory circuits have a three-dimensional structure.

17. The method according to claim 15, wherein, Conductive materials include metals and titanium nitride, with metals including either tungsten or gold.

18. The method according to claim 11, further comprising: Replace part of the silicon connector above the conductive pad with metal.

19. The method according to claim 11, further comprising: Replace part of the silicon connector above the conductive pad with a T-shaped metal structure.

20. A system utilizing memory circuitry, comprising: Memory circuitry, including: The letter line pad area has a pad structure, which includes: A first pad, located at a first contact point and connected to a first letter, the first letter being arranged longitudinally in a first direction and spaced a first distance from the first contact point; and The second pad is located at the second contact point and connected to the second letter line, the second letter line being arranged longitudinally in the first direction and at a second distance from the second contact point. Wherein, the first pad and the second pad are aligned in the second direction based on the first contact point and the second contact point, respectively, and The first word line and the second word line correspond to the row lines of the memory circuit.

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