Gray scale lithography ICP transfer modeling closed loop method and system

Abstract

The application discloses a gray-scale lithography ICP transfer modeling closed-loop method and system applied to the field of micro-nano optical master mold manufacturing and process development, the scheme is developed around the selection ratio modeling, three sample piece development, outsourcing data back and version solidification, the system comprises an input module, a selection ratio modeling and parameter recommendation module, a three sample piece plan and DOE management module, a measurement and acceptance module, a process solidification and version management module and an output module; the method comprises PR / Si etching rate test, selection ratio and reachable depth calculation, three sample piece DOE, measurement update, full-size verification and formula solidification output, so as to improve the profile retention, process reproducibility and master mold production consistency.

Description

Technical Field

[0001] This invention relates to the field of micro-nano optical mold manufacturing and process development, and particularly to a closed-loop method and system for grayscale photolithography ICP transfer modeling. Background Technology

[0002] In the process of forming a three-dimensional photolithography (PR) profile using grayscale lithography and further fabricating a silicon master mold, the ICP transfer of the PR profile to the silicon substrate is a key development step for subsequent working mold replication and nanoimprint mass production. The development stage typically requires first determining the etching rates of the PR and silicon under a specific cavity formulation, then judging whether the target depth is achievable, and verifying profile retention, roughness, and uniformity through sample fabrication.

[0003] However, existing development methods often rely on empirical formulas or single trial engravings, making it difficult to simultaneously consider selectivity, micro-loading, sidewall morphology, and in-plane uniformity. When the external cavity, layout density, or target depth changes, the model cannot be reconstructed quickly, which can easily lead to contour distortion, increased roughness, increased scattering risk, and decreased lifespan of the master mold and mass production consistency. Summary of the Invention

[0004] The core of this invention lies in: establishing an updatable selectivity model around R_Si and R_PR, combining a three-sample development closed loop of "rate test sample - grayscale step and representative structure sample - full-size verification sample", jointly modeling and gating ICP parameter window, contour error, roughness and scattering risk, and binding and solidifying the external cavity version, formula window, acceptance index and traceability data package.

[0005] To solve the above problems, the present invention adopts the following technical solution.

[0006] A closed-loop method for grayscale lithography ICP transfer modeling includes the following steps:

[0007] A. Obtain the target PR profile, target silicon depth distribution, manufacturing constraints, and outsourced cavity version;

[0008] B. Generate or update the target depth field h for ICP transfer. * _Si(x,y) and PR thickness field t_PR(x,y);

[0009] C. Perform manufacturing data generation, manufacturing / copying, and measurement acceptance, specifically including:

[0010] C1. The silicon etching rate R_Si and the PR etching rate R_PR were measured under the same cavity version.

[0011] C2. Calculate the selection ratio, reachability depth, and ICP initial parameter window;

[0012] C3. Perform DOE development according to the three-sample sequence;

[0013] C4. Measure and update the model parameters;

[0014] C5. Conduct full-caliber verification;

[0015] C6. Solidify the etching formula, acceptance criteria, and version binding relationship of the master mold;

[0016] D. Output process formula, acceptance report and traceability data package.

[0017] Furthermore, the specific operations in step C2 include: calculating the selection ratio S = R_Si / R_PR, and the target depth field h. * The required PR thickness Δt_PR and the achievable depth window corresponding to _Si(x,y) are determined, and the initial ICP parameter set is determined accordingly.

[0018] The specific operations of step C3 include: sequentially performing DOE on the rate test sample, grayscale step and representative structure sample, and full-size verification sample;

[0019] The specific operations in step C4 include updating the selection ratio model and parameter window based on the etching depth, in-plane uniformity, roughness, and contour error returned by each sample.

[0020] Furthermore, after the master mold etching formula and acceptance criteria are solidified in step C6 and before the output in step D, the silicon master mold that has passed full-size verification is copied into a replaceable working mold. The working mold is assigned a unique number and the number of copies, the number of times it is put into service, and the lifetime count are recorded for use in subsequent imprinting production.

[0021] Furthermore, when the replaceable working mold enters the printing production stage, roll-to-sheet printing is adopted and the demolding force is monitored at each printing or preset batch interval. When the demolding force exceeds the threshold, the anti-sticking layer is reprocessed, the working mold is replaced, or the printing parameters are adjusted.

[0022] Furthermore, after measuring and updating the model parameters in step C4 and before curing in step C6, the surface roughness and scattering index of the sample or silicon master mold are subjected to gating acceptance. Step C6 is only entered when both roughness and scattering risk meet the threshold.

[0023] Furthermore, the specific operations in step D include: outputting the master mold / working mold number, the external cavity version, the formula window, the acceptance results, and batch traceability information.

[0024] A closed-loop system for grayscale lithography ICP transfer modeling includes:

[0025] The input module is used to obtain the target PR profile, target silicon depth distribution, manufacturing constraints, and outsourced cavity version;

[0026] The selection ratio modeling and parameter recommendation module is used to calculate the selection ratio and reachable depth window based on the R_Si and R_PR measured by the test piece, and to generate the initial parameter set for ICP.

[0027] The three-sample planning and DOE management module is used to generate the development sequence, layout, and data feedback templates for rate test samples, grayscale ladder and representative structure samples, and full-size verification samples.

[0028] The metrology and acceptance module is used to evaluate and update the model based on the etching depth, in-plane uniformity, roughness, contour error, and scattering index returned from outsourced projects.

[0029] The process solidification and version management module is used to solidify the selection ratio model, master mold etching formula, acceptance criteria, and the binding relationship between the outsourced cavity version.

[0030] The output module is used to output process formulas, acceptance reports, and traceability data packages.

[0031] Furthermore, this system also includes an ICP transfer process parameter management module. This module reads the current cavity version and historical parameter window between steps C1 and C2. After sample measurement and model parameter updates are completed in step C4, and before step C5 begins, a candidate space selection ratio model SR_cand(x,y) and a candidate parameter window W_cand are formed for full-size caliber verification. After verification in step C5, if the verification passes, SR_cand(x,y) and W_cand are solidified into SR_final(x,y) and W_final before step C6, and finally bound to the external cavity version v_ch, acceptance threshold version, and template version. If the verification fails, the candidate version is discarded and the system returns to step C3 or C4 for reconstruction.

[0032] Furthermore, the system also includes a module for numbering and lifespan counting of the master mold and the working mold. After step C6, the module for numbering and lifespan counting of the master mold and the working mold uniquely identifies, counts the lifespan, and records the online history of the working mold obtained by copying the silicon master mold.

[0033] Furthermore, the system also includes a demolding force monitoring and contact angle monitoring module, which operates after the working mold is put into imprinting production. It is used to evaluate the health of the anti-stick layer and trigger anti-sticking treatment or replace the working mold when the threshold is exceeded.

[0034] Furthermore, the system also includes a roughness measurement module, which operates between steps C4 and C5 and between steps C5 and C6, for gating the surface roughness and scattering risk of the sample or silicon master mold.

[0035] Furthermore, the system also includes a rework and reprocessing process management module, which operates when step C5 fails to pass the acceptance threshold and is used to guide the sample or master mold to a sequence of re-cleaning, re-etching, re-measuring, or reconstructing samples.

[0036] Compared with the prior art, the advantages of this invention are:

[0037] (1) This scheme measures R_Si and R_PR under the same cavity version and establishes a selection ratio model to link the target silicon depth, PR thickness requirements and ICP parameter window, thereby reducing trial and error and improving the contour retention of the grayscale PR contour to silicon master mold.

[0038] (2) This scheme uses a three-sample closed loop of “rate test sample - gray scale and representative structure sample - full-size verification sample” to form a unified development path for formula update, uniformity assessment, roughness / scattering gating and full-size aperture verification, which is conducive to quickly reconstructing the process window when the external cavity changes.

[0039] (3) This solution links the development stage with subsequent working mold copying, imprinting production and rework decisions through process solidification and version management, master mold / working mold numbering and life count, and traceability data packet output, thereby improving the master mold life management capability and mass production consistency. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the overall system structure of the present invention;

[0041] Figure 2 This is a schematic cross-sectional view of the planar prescription lens / microstructure stack of the present invention;

[0042] Figure 3 This is a schematic diagram of the three sample DOEs, candidate models, and final curing process of the present invention;

[0043] Figure 4 This is a schematic diagram of the radial profile of the phase reset / step height of the present invention;

[0044] Figure 5 This is a schematic diagram of the design-manufacturing-metering closed-loop chain of the present invention;

[0045] Figure 6 This is a schematic diagram illustrating the error convergence of the closed-loop iteration of the present invention;

[0046] Figure 7 This is a schematic diagram illustrating the binding relationship between the selection ratio model hierarchy and version tracing in this invention;

[0047] Figure 8This is a schematic diagram illustrating typical defects / roughness / scattering risks of the present invention;

[0048] Figure 9 This is a schematic diagram of an optional embodiment / alternative module of the present invention;

[0049] Figure 10 This is a schematic diagram of the QC gating and rework strategy process of the present invention;

[0050] Figure 11 This is a schematic diagram of the optional double-sided / multi-layer / alignment reference structure of the present invention;

[0051] Figure 12 This is a schematic diagram illustrating the manufacturing constraints and tolerance budget of the present invention. Detailed Implementation

[0052] The technical solutions will now be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention.

[0053] First implementation method:

[0054] Please see Figure 1 and Figure 3 The grayscale lithography ICP transfer modeling closed-loop method (grayscale lithography ICP transfer refers to the transfer of grayscale PR contours to silicon master mold ICP) includes the following steps:

[0055] A. Obtain the target PR profile, target silicon depth distribution, manufacturing constraints, and outsourced cavity version;

[0056] B. Generate or update the target depth field h for ICP transfer. * _Si(x,y) and PR thickness field t_PR(x,y);

[0057] C. Perform manufacturing data generation, manufacturing / copying, and measurement acceptance, specifically including:

[0058] C1. The silicon etching rate R_Si and the PR etching rate R_PR were measured under the same cavity version.

[0059] C2. Calculate the selection ratio, reachability depth, and ICP initial parameter window;

[0060] Specifically: calculate the selection ratio S = R_Si / R_PR, and the target depth field h. * The required PR thickness Δt_PR and the achievable depth window corresponding to _Si(x,y) are determined, and the initial ICP parameter set is determined accordingly.

[0061] C3. Perform DOE development according to the three-sample sequence;

[0062] Specifically: DOEs are executed sequentially on the rate test sample, the grayscale step and representative structure sample, and the full-size verification sample;

[0063] C4. Measure and update the model parameters;

[0064] Specifically: The selection ratio model and parameter window are updated based on the etching depth, in-plane uniformity, roughness, and contour error returned by each sample.

[0065] C5. Conduct full-caliber verification;

[0066] C6. Solidify the etching formula, acceptance criteria, and version binding relationship of the master mold;

[0067] D. Output process formulas, acceptance reports, and traceability data packages (i.e., manufacturing data packages), such as: output master mold / working mold number, outsourced cavity version, formula window, acceptance results, and batch traceability information. The traceability data package (i.e., manufacturing data package) may include the following: Figure 7 As shown.

[0068] After the master mold etching formula and acceptance criteria are solidified in step C6 and before the output in step D, the silicon master mold that has passed full-size verification is copied into a replaceable working mold. The working mold is assigned a unique number and the number of copies, the number of times it is put into service and the lifetime count are recorded for use in subsequent imprinting production.

[0069] When the replaceable working mold enters the printing production stage, roll-to-sheet printing is adopted and the demolding force is monitored at each printing or preset batch interval. When the demolding force exceeds the threshold, the anti-sticking layer is reprocessed, the working mold is replaced, or the printing parameters are adjusted.

[0070] After measuring and updating the model parameters in step C4 and before curing in step C6, the surface roughness and scattering index of the sample or silicon master mold are subjected to gating acceptance. Step C6 is only entered when both roughness and scattering risk meet the threshold.

[0071] A grayscale lithography ICP transfer modeling closed-loop system, used to execute the above method, includes:

[0072] The input module is used to execute step A, which is to obtain the target PR profile, target silicon depth distribution, manufacturing constraints, and outsourced cavity version;

[0073] The selection ratio modeling and parameter recommendation module is used to execute steps C1 and C2, namely, to calculate the selection ratio and reachable depth window based on the R_Si and R_PR measured by the test piece, and to generate the initial set of ICP parameters.

[0074] The three-sample planning and DOE management module is used to execute step C3, which is used to generate the development sequence, layout and data feedback templates for rate test samples, grayscale steps and representative structure samples, and full-size verification samples.

[0075] The metrology and acceptance module is used to perform steps C4 to C5, which are used to evaluate and update the model based on the etching depth, in-plane uniformity, roughness, contour error, and scattering index returned by the outsourced team.

[0076] The process solidification and version management module is used to execute step C6, which is used to solidify the selection ratio model, master mold etching formula, acceptance criteria, and external cavity version binding relationship.

[0077] The output module is used to execute step D, which is to output the process formula, acceptance report and traceability data package.

[0078] This system also includes an ICP transfer process parameter management module. This module reads the current cavity version and historical parameter window between steps C1 and C2. After sample measurement and model parameter updates are completed in step C4, and before step C5 begins, a candidate space selection ratio model SR_cand(x,y) and a candidate parameter window W_cand are formed for full-size caliber verification. After verification in step C5, if the verification passes, SR_cand(x,y) and W_cand are solidified into SR_final(x,y) and W_final before step C6, and finally bound to the external cavity version v_ch, acceptance threshold version, and template version. If the verification fails, the candidate version is discarded and the system returns to step C3 or C4 for reconstruction.

[0079] Specifically: After completing the local / representative structural sample measurement and updating the model parameters in step C4, the candidate space selection ratio model SR_cand(x,y) and candidate parameter window W_cand obtained in this round are first frozen, and the full-size aperture sample is verified once without freely changing the master formulation using this candidate version; the verification output includes at least the full-aperture RMS depth error, maximum absolute depth error, in-plane uniformity, surface roughness, and scattering risk. If the verification passes, SR_cand(x,y) and W_cand are solidified into SR_final(x,y) and W_final and bound to the version before step C6; if the verification fails, the candidate version is discarded and the process returns to step C3 or step C4 for reconstruction.

[0080] The system also includes a module for numbering and lifespan counting of master molds and working molds. After step C6 and in the subsequent copying / imprinting stages, the module for numbering and lifespan counting of master molds and working molds uniquely identifies, counts, and records the online history of the working molds copied from the silicon master mold, and continuously updates it in the subsequent imprinting production process.

[0081] The system also includes a demolding force monitoring and contact angle monitoring module. The demolding force monitoring and contact angle monitoring module runs after the working mold is put into the printing production. It can collect the demolding force at each printing or preset batch interval, or periodically measure the contact angle to evaluate the health of the anti-stick layer. When the index exceeds the threshold, it triggers reprocessing or replacement of the working mold.

[0082] The system also includes a roughness measurement module, which operates between steps C4 and C5 and between steps C5 and C6. This module is used to gate the surface roughness and scattering risk of the sample or silicon master mold. Only samples that meet the threshold are allowed to proceed to full-size verification or formulation curing.

[0083] The system also includes a rework and reprocessing process management module. When the acceptance threshold is not passed in step C5, the rework and reprocessing process management module will run and direct the task to re-cleaning, re-etching, re-measuring or reconstructing the sample sequence according to the reason code, and record the rework history in the traceability data packet.

[0084] The following will provide specific examples illustrating this system and method:

[0085] In step A, the input module receives: (1) the target PR profile or PR thickness distribution t_PR(x,y) obtained from upstream grayscale lithography; and (2) the target silicon depth distribution h. * _Si(x,y); (3) Process constraints, including allowable coil power, bias power, cavity pressure, etching time, gas flow range, and roughness / scattering threshold; (4) External cavity version v_ch and batch information. The output of this step is the target dataset and constraint dataset for this round of development.

[0086] In step B, the processor generates a target depth field h for ICP development based on the target PR profile and the target silicon depth distribution. * _Si(x,y) and PR thickness field t_PR(x,y). If the target comes from a grayscale lithography sample, the PR surface height can be measured first using a white light interferometer or profilometer, and then converted into t_PR(x,y); if the target comes from a layout or DMD grayscale design file, the design height map is imported as a discrete mesh.

[0087] In step C1, the ratio modeling and parameter recommendation module is selected to arrange rate testing: a uniform PR test wafer and a bare silicon test wafer are placed under the same cavity version v_ch, respectively. The etching test time is t_test, and the initial PR thickness t_PR,0, the thickness after etching t_PR,1, and the silicon etching depth d_Si,test are recorded. Thus, the PR etching rate R_PR = (t_PR,0 - t_PR,1) / t_test, and the silicon etching rate R_Si = d_Si,test / t_test are obtained.

[0088] In step C2, the selection ratio S = R_Si / R_PR is calculated based on R_Si and R_PR obtained in C1, and combined with the target silicon depth h. * The required removable thickness Δt_PR≈h is estimated using Si(x,y). * _Si(x,y) / S. Then, combining the allowable coil power P_coil, bias power P_bias, cavity pressure p_ch, etching time t_etch, and gas flow rate F_g, a set of initial ICP parameters satisfying the constraints is generated for subsequent DOE. The purpose of this step is to narrow the search space and avoid blindly attempting etching on the full-size aperture.

[0089] In step C3, the three-sample planning and DOE management modules sequentially generate and distribute three types of samples: the first sample is a rate test sample, used to confirm the stability of R_Si and R_PR; the second sample is a grayscale step and representative structure sample, the representative structure including at least different local pattern densities, local pitches, and edge / center positions; the third sample is a full-size 45mm diameter verification sample, used to verify the real target structure. The data templates corresponding to each sample require external feedback of formulation parameters, uniformity, roughness, and profile error.

[0090] In step C4, the metrology and acceptance module analyzes the data returned by the samples. For the second and third samples, the actual silicon depth h_Si(x,y) is measured using a white light interferometer, profilometer, or profilometer, and the depth error e_h(x,y) = h_Si(x,y) - h is calculated. * The parameters _Si(x,y), in-plane uniformity U, surface roughness Rq / Ra, and scattering index H were then used to update the parameterized models of SR(x,y) and ε_load(x,y) using regression.

[0091] In step C5, the metrology and acceptance module makes a comprehensive judgment on the full-size verification sample, combining... Figure 10As shown, preferably, at least the following acceptance criteria are set: the full-aperture RMS depth error is less than the threshold τ_RMS, the maximum absolute depth error is less than the threshold τ_max, the surface roughness Rq is less than the threshold τ_Rq, the scattering risk H is less than the threshold τ_H, and the in-plane uniformity U satisfies the threshold τ_U (i.e., τ_RMS, τ_max, τ_Rq, τ_H, and τ_U represent the acceptance thresholds for RMS depth error, maximum absolute depth error, roughness, scattering risk, and in-plane uniformity, respectively). Only when all criteria meet the thresholds is the current parameter window considered ready to enter the solidification stage.

[0092] In step C6, the process solidification and version management module solidifies the verified recipe window, selection ratio model, ε_load(x,y) model parameters, external cavity version v_ch, acceptance threshold, and data template version, forming a version binding relationship with the master mold number. If the result of C5 does not meet the threshold, the rework and reprocessing process management module will direct the task to re-cleaning, re-etching, re-measurement, or return to C3 to reconstruct the sample sequence based on the reason code.

[0093] Therefore, the logical order of steps C4 to C6 is: "Local / representative structure measurement and model update (C4) → Perform full-caliber verification with the updated model (C5) → Freeze the formula and version relationship only when the full-caliber sample meets the acceptance criteria (C6)". This setup fully supports the closed-loop development logic of "modeling-verification-solidification" in the public content.

[0094] In step D, the output module outputs the process formula, acceptance report, and traceability data package (manufacturing data package). The traceability data package includes at least: master mold number, working mold number (if copied), outsourced cavity version, sample type, formula parameters, selection ratio model version, roughness and scattering acceptance results, batch information, and timestamp.

[0095] The following are Figures 2-12 Further explanation is provided for the attached diagrams in the middle section: Figure 2 The subsequent planar microstructure stack-up object served by the silicon master mold developed by this method is shown to illustrate the target structure of the process closed loop in this case. Figure 4 The figure shows the radial profile of the grayscale step and phase reset type representative structure, which shows that the same development window needs to take into account the transfer fidelity of both continuous ramp segments and steep reset segments. Figure 5 The design-manufacturing-metrization closed-loop link is shown, indicating that the parameter update results will be fed back into the next round of initial formulation guessing. That is, the parameter update results of this round of metrology will serve as the initial basis for the next round of formulation design. The "metrology" here mainly includes etching depth, uniformity, roughness and scattering risk, rather than generalized whole-machine wavefront metrology. Figure 6The curves show that as the number of iterations increases, the RMS depth error gradually decreases and tends to converge. Figure 8 The roughness and scattering risks corresponding to scratches, particles, seams, bubbles, residual layers and collapses / notches are shown, and these defects, along with contour errors, can be used together for QC grading and rework decisions. Figure 9 This paper illustrates alternative embodiments of the method that can be used for single-sided microstructures, double-sided microstructures, and subsequent imprint replication. Specifically, Embodiment A corresponds to the grayscale lithography route for single-sided microstructures, Embodiment B corresponds to the direct transfer route from the Si master mold, and Embodiment C corresponds to the working mold / mass production route for NIL replication. Figure 10 This illustrates QC gating and rework strategies; Figure 11 The optional structures of double-sided / multi-layer or alignment references are shown to illustrate that when the silicon master mold serves a double-sided / multi-layer structure or when the alignment reference needs to be transferred synchronously, the selection of this case is still applicable to modeling and three-sample closed loop, with the key point being that the transfer accuracy of the alignment reference is included as an additional gating item in the version fix. Figure 12 The diagram illustrates manufacturing constraints and tolerance budgets. The relative contributions of each error source can be used to determine the priority optimization targets, based on... Figure 12 In the budget chart, those with a relatively large contribution from drift, sidewall / microgroove, and replication error should be given priority in process optimization and rework criteria.

[0096] S represents the global average selection ratio obtained from the rate test, written as S = R_Si / R_PR; SR(x,y) represents the general notation for the spatial selection ratio model; SR_cand(x,y) represents the candidate version used for freezing and validation in step C5 after the update in step C4; SR_final(x,y) represents the final version solidified after passing step C5 and before step C6. Steps C1 and C2 use S for initial window estimation, while steps C4 and later use SR(x,y) and its candidate / final versions for depth prediction in model updates and full-size validation.

[0097] The selection ratio modeling and depth error update formulas used in steps C1 to C4 are as follows:

[0098] In step C1, the uniform PR test wafer and the bare silicon test wafer are etched and tested for time t_test under the same ICP cavity version v_ch to obtain the initial PR thickness t_PR,0, the thickness after etching t_PR,1, and the silicon etching depth d_Si,test. From this, we can calculate: S = R_Si / R_PR; where R_PR represents the etching rate of the photoresist under a given cavity version and test time, and R_Si represents the etching rate of the silicon substrate under the same conditions.

[0099] In step C2, for the target silicon depth h *_Si(x,y), according to the selected ratio SR, the required removable PR thickness is estimated as: Δt_PR≈h * _Si(x,y) / S; where Δt_PR represents the target silicon depth h. * _Si(x,y) is the required PR thickness to be removed.

[0100] In steps C3 and C4, when considering micro-loading and in-plane inhomogeneity, a spatial term is introduced into the depth prediction, where t_PR(x,y) is the thickness distribution of the PR to be transferred, SR(x,y) is the spatial selection ratio after sample regression, and ε_load(x,y) represents the additional loading error caused by micro-loading and its corresponding local layout density, local pitch, and in-plane position effects. In the depth prediction formula, this term is reflected as an additional correction term for the local transferred depth.

[0101] h_Si(x,y)=SR(x,y)t_PR(x,y)+ε_load(x,y);

[0102] Where h_Si(x,y) represents the actual silicon depth distribution after etching, h * _Si(x,y) represents the target silicon depth distribution, t_PR(x,y) represents the PR thickness distribution to be transferred, SR(x,y) represents the effective spatial selectivity, and ε_load(x,y) represents the additional loading error term.

[0103] In this embodiment, the three samples are as follows: the first sample is used for rate testing and provides R_Si and R_PR; the second sample is a grayscale step and representative structure sample, used to fit the parameters of SR(x,y) and ε_load(x,y); the third sample is a full-size 45mm diameter verification sample, used to verify whether the RMS depth error, in-plane uniformity, surface roughness, and scattering index meet the mass production threshold. Figure 6 The example data shows that the RMS depth error decreases as the number of closed-loop iterations increases, indicating that the selection ratio model update can gradually converge; according to Figure 12 As can be seen from the budget diagram, the selection factor has a relatively large contribution from drift, sidewall / microgroove and replication error, and should be given priority as the target for process optimization.

[0104] The above description is merely a preferred embodiment of the present invention; it encompasses all the protection scope of the present invention. Any equivalent substitutions or modifications made by those skilled in the art within the technical scope disclosed in the present invention, based on the technical solutions and improved concepts of the present invention, should be covered within the protection scope of the present invention.

Claims

1. A closed-loop method for grayscale photolithography ICP transfer modeling, characterized in that: Includes the following steps: A. Obtain the target PR profile, target silicon depth distribution, manufacturing constraints, and outsourced cavity version; B. Generate or update the target depth field h for ICP transfer. * _Si(x,y) and PR thickness field t_PR(x,y); C. Perform manufacturing data generation, manufacturing / copying, and measurement acceptance, specifically including: C1. The silicon etching rate R_Si and the PR etching rate R_PR were measured under the same cavity version. C2. Calculate the selection ratio, reachability depth, and ICP initial parameter window; Step C2 specifically includes: calculating the selection ratio S = R_Si / R_PR, and the target depth field h. * The required PR thickness Δt_PR and the achievable depth window corresponding to _Si(x,y) are determined, and the initial ICP parameter set is determined accordingly. C3. Perform DOE development according to the three-sample sequence; The specific operations of step C3 include: sequentially performing DOE on the rate test sample, grayscale step and representative structure sample, and full-size verification sample; C4. Measure and update the model parameters; The specific operations in step C4 include: updating the selection ratio model and parameter window based on the etching depth, in-plane uniformity, roughness and contour error returned by each sample; C5. Conduct full-caliber verification; C6. Solidify the etching formula, acceptance criteria, and version binding relationship of the master mold; D. Output process formula, acceptance report and traceability data package.

2. The grayscale photolithography ICP transfer modeling closed-loop method according to claim 1, characterized in that: After the master mold etching formula and acceptance criteria are solidified in step C6 and before the output in step D, the silicon master mold that has passed full-size verification is copied into a replaceable working mold. The working mold is assigned a unique number and the number of copies, the number of times it is put into service and the lifetime count are recorded for use in subsequent imprinting production.

3. The grayscale photolithography ICP transfer modeling closed-loop method according to claim 2, characterized in that: When the replaceable working mold enters the printing production stage, roll-to-sheet printing is adopted and the demolding force is monitored at each printing or preset batch interval. When the demolding force exceeds the threshold, the anti-sticking layer is reprocessed, the working mold is replaced, or the printing parameters are adjusted.

4. The grayscale photolithography ICP transfer modeling closed-loop method according to claim 3, characterized in that: After measuring and updating the model parameters in step C4 and before curing in step C6, the surface roughness and scattering index of the sample or silicon master mold are subjected to gating acceptance. Step C6 is only entered when both roughness and scattering risk meet the threshold.

5. The grayscale photolithography ICP transfer modeling closed-loop method according to claim 4, characterized in that: Step D includes the following specific operations: outputting the master mold / working mold number, the external cavity version, the formula window, the acceptance results, and batch traceability information.

6. A grayscale lithography ICP transfer modeling closed-loop system, used to execute the method of claim 5, characterized in that: include: The input module is used to obtain the target PR profile, target silicon depth distribution, manufacturing constraints, and outsourced cavity version; The selection ratio modeling and parameter recommendation module is used to calculate the selection ratio and reachable depth window based on the R_Si and R_PR measured by the test piece, and to generate the initial parameter set for ICP. The three-sample planning and DOE management module is used to generate the development sequence, layout, and data feedback templates for rate test samples, grayscale ladder and representative structure samples, and full-size verification samples. The metrology and acceptance module is used to evaluate and update the model based on the etching depth, in-plane uniformity, roughness, contour error, and scattering index returned from outsourced projects. The process solidification and version management module is used to solidify the selection ratio model, master mold etching formula, acceptance criteria, and the binding relationship between the outsourced cavity version. The output module is used to output process formulas, acceptance reports, and traceability data packages.

7. The grayscale photolithography ICP transfer modeling closed-loop system according to claim 6, characterized in that: It also includes an ICP transfer process parameter management module. This module reads the current cavity version and historical parameter window between steps C1 and C2. After sample measurement and model parameter updates are completed in step C4, and before step C5 begins, a candidate space selection ratio model SR_cand(x,y) and a candidate parameter window W_cand are formed for full-size caliber verification. After verification in step C5, if the verification passes, SR_cand(x,y) and W_cand are solidified into SR_final(x,y) and W_final before step C6, and finally bound to the external cavity version v_ch, the acceptance threshold version, and the template version. If the verification fails, the candidate version is discarded and the process returns to step C3 or C4 for reconstruction.

8. The grayscale photolithography ICP transfer modeling closed-loop system according to claim 6, characterized in that: It also includes a numbering and lifetime counting module for the master mold and the working mold. After step C6, the numbering and lifetime counting module for the master mold and the working mold uniquely identifies, counts lifetimes, and records online history for the working mold copied from the silicon master mold.

9. The grayscale lithography ICP transfer modeling closed-loop system according to claim 6, characterized in that: It also includes a demolding force monitoring and contact angle monitoring module, which operates after the working mold is put into imprinting production. The two modules are used to evaluate the health of the anti-stick layer and trigger anti-sticking treatment or replace the working mold when the threshold is exceeded.

10. The grayscale photolithography ICP transfer modeling closed-loop system according to claim 6, characterized in that: It also includes a roughness measurement module, which operates between steps C4 and C5 and between steps C5 and C6, and is used to gate the surface roughness and scattering risk of the sample or silicon master mold.

11. The grayscale lithography ICP transfer modeling closed-loop system according to claim 6, characterized in that: It also includes a rework and reprocessing process management module, which operates when step C5 fails to pass the acceptance threshold. This module is used to guide the sample or master mold to a sequence of samples that are cleaned, etched, measured, or reconstructed.

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