Method for overcoming servo interruption fluctuation of VxWorks real-time control system by adopting FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the technical field of embedded real-time control systems, in particular to a method for overcoming servo interrupt fluctuation of a VxWorks real-time control system by adopting an FPGA (Field Programmable Gate Array), which realizes key time sequence processing such as interrupt signal management, hardware anti-shake, software optimization, hardware triggering and the like through the FPGA. It is ensured that submitted data subjected to servo interrupt processing of the VxWorks system has predictable time sequence characteristics, and data support is provided for system debugging and optimization. When the method is actually tested in a certain multi-axis motion control system, the stability and the precision of the control system are ensured under the condition that control interruption is delayed by 15 microseconds, and the rate precision and the stability are both improved from 1 * 10 <-5 > to 1 * 10 <-6 >. Through deep collaborative design of the FPGA and the VxWorks software, respective advantages of hardware parallelism and software flexibility are brought into full play, optimization of system performance is realized, the problem of interrupt response fluctuation of the VxWorks system in a complex application scene is effectively solved, and reliable technical support is provided for an embedded system with a high real-time requirement.

Description

Technical Field

[0001] This application relates to the field of embedded real-time control system technology, and in particular to a method for overcoming servo interruption fluctuations in a VxWorks real-time control system using an FPGA. Background Technology

[0002] A three-axis inertial navigation test turntable consists of a turntable body, a turntable control system, and supporting cables. The turntable control system comprises a control computer, motion controllers, a control cabinet, a power amplifier, and control software. This equipment possesses precise control capabilities for angular rate and angular position, ensuring its suitability for calibration, compensation, and performance testing of inertial navigation products and other navigation and control products, providing stable and reliable testing conditions. The control system hardware is based on an industrial control computer, integrating a CPCI bus control chassis and multiple bus-expanded FPGA servo control circuits. It uses a high-precision Renishaw BISS protocol absolute encoder for position feedback and a high-performance torque motor and driver for motor drive. The human-machine interface software is developed under Windows 7, and the real-time motion control software is developed based on VxWorks 6.9, integrating a fully digital closed-loop motion control algorithm with a servo control cycle of 0.5ms, employing PID control and feedforward control algorithms.

[0003] Through the collaboration of hardware and software, the entire system effectively ensures the low-speed accuracy and stability of the turntable, as well as its acceleration capability, positioning speed, and stability. During system debugging, an abnormal noise occurred when the outer frame operated at a speed of 100° / second. Troubleshooting revealed large fluctuations in position control deviation during the anomaly, with the deviation increasing as the turntable speed increased. Since position triggering is completed within the servo cycle, fluctuations in interrupt response were suspected. Testing showed that the maximum interrupt fluctuation time was ±15 microseconds. In embedded real-time operating systems, the determinism of interrupt response time is a key indicator of system real-time performance. This fluctuation becomes particularly pronounced under high load conditions, severely impacting the system's determinism and reliability.

[0004] VxWorks, as a high-performance real-time operating system, is renowned for its microsecond-level interrupt handling capabilities, but it still faces the issue of interrupt response time fluctuations in practical applications. According to available data, in a standard VxWorks 6.9 system environment, the theoretical minimum time interval for handling CPCI interrupts is approximately 5.84 microseconds. However, in complex applications, the actual measured interrupt response time fluctuation range can be much larger than this theoretical minimum. Actual testing showed that the Advantech 3329 motherboard exhibited interrupt time fluctuations of ±8 microseconds at a 2kHz interrupt response frequency, while the Advantech 973 motherboard, under the same conditions, showed fluctuations of ±15 microseconds. This demonstrates that the magnitude of response time fluctuations is influenced by many factors.

[0005] Current common solutions primarily focus on software-level optimization, including increasing interrupt priority, optimizing interrupt service routines, and interrupt masking. However, these methods not only increase software complexity but also fail to fundamentally address hardware-level interrupt contention and the uncertainty of software execution paths. Especially when handling interrupts from high-speed interfaces such as CPCI, due to hardware architecture limitations, dedicated interrupt controllers using Advanced Programmable Interrupt Controllers (APICs) lack load adaptability and cannot dynamically adjust based on system status. Pure software scheduling optimization and improved task scheduling algorithms cannot resolve the fluctuations at the hardware interrupt level. Therefore, the optimization effects of traditional methods are limited and cannot meet the needs of applications with high real-time requirements.

[0006] In recent years, some studies have proposed interrupt management schemes that incorporate FPGAs. For example, a "Monitoring-Driven HW / SWInterrupt Overload Prevention" architecture uses an FPGA to monitor software load and adaptively adjust interrupt service rates. However, these schemes still have significant shortcomings in interrupt priority adaptation, multi-clock domain synchronization, and deep integration with VxWorks. Summary of the Invention

[0007] This application addresses the interrupt response fluctuation problem in VxWorks real-time control systems by providing an FPGA-based hardware management solution. This method uses FPGA hardware to process critical signals affected by interrupt fluctuations, such as multi-interrupt management, position feedback signal triggering, and control deviation conversion, thereby overcoming the interrupt response time fluctuation of VxWorks real-time control systems and greatly improving the speed accuracy, stability, and reliability of the control system.

[0008] Specifically, this application provides a method for overcoming servo interrupt fluctuations in a VxWorks real-time control system using an FPGA, implemented through an FPGA interrupt management module, an FPGA-based hardware triggering module, and a VxWorks software processing module. The FPGA interrupt management module is responsible for receiving, aggregating, filtering, and prioritizing interrupts. The FPGA-based hardware triggering module is responsible for hardware triggering of position data acquisition and initiating closed-loop control deviation digital-to-analog conversion. The VxWorks software processing module provides specially optimized drivers and task scheduling mechanisms. The method includes: Interrupt reception phase: Peripheral interrupt signals first arrive at the FPGA interrupt management module; Preprocessing stage: The FPGA performs filtering and debouncing on the raw interrupts; Scheduling decision phase: The timing of interrupt submission is determined based on factors such as priority and system status; Interrupt submission phase: The FPGA submits an interrupt to the system via CPCI MSI-X or a traditional interrupt line; System processing phase: The VxWorks system executes a simplified ISR to read the interrupt status in the FPGA; and initiates improved processing for position data triggering and control quantity digital-to-analog conversion. Interrupt completion phase: The system confirms the completion of interrupt handling by writing to the register.

[0009] Furthermore, the FPGA interrupt management module combines multiple external interrupt sources into a single interrupt signal and sends it to VxWorks.

[0010] Furthermore, the FPGA interrupt management module directly writes interrupt information to a designated memory location in the system, reducing interrupt response time.

[0011] Furthermore, the FPGA interrupt management module performs hardware debouncing on the input interrupt signal, and only signals that stabilize at a specific level for more than a preset clock cycle are recognized as valid interrupts.

[0012] Furthermore, the FPGA-based hardware triggering module decomposes the position feedback input function into two parts: one part is position trigger latching, and the other part is data reading.

[0013] Furthermore, the FPGA-based hardware triggering module generates pulses of a fixed frequency through the FPGA to achieve position triggering latching, thereby avoiding fluctuations caused by interruptions.

[0014] Furthermore, the current loop signal from the FPGA-based hardware trigger module to the driver is directly converted and written to the buffer after being processed by the VxWoks software, and the signal to start the conversion circuit is implemented by the FPGA generating a pulse of a fixed frequency.

[0015] Furthermore, the ISR of the VxWorks software processing module identifies the specific interrupt source by reading the FPGA's status register.

[0016] Furthermore, the VxWorks software processing module control program ISR interrupt response subroutine only performs necessary operations: confirming the interrupt, reading the FPGA status register, and notifying relevant work tasks.

[0017] Furthermore, the VxWorks software processing module ISR quickly clears the interrupt flag in the FPGA through PIO operations to avoid repeated triggering.

[0018] The above-mentioned technical solution of this application has the following advantages: The method provided in this application for overcoming servo interrupt fluctuations in VxWorks real-time control systems using FPGA transfers the interrupt management function from the software level to the FPGA hardware level. By utilizing the hardware parallel processing capability and deterministic timing characteristics of FPGA, the preprocessing, buffering and scheduling of external interrupts are implemented at the hardware level. This transforms the large number of discrete interrupts that are traditionally handled directly by VxWorks into a regularized and predictable event stream, fundamentally eliminating the impact of uncertainty in interrupt response. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a structural diagram of the interrupt debouncing filter circuit provided in an embodiment of this application; Figure 2 This is a structural diagram of the interrupt selection control management module provided in an embodiment of this application; Figure 3 A block diagram illustrating the implementation principle of the precision timer function provided in this application embodiment; Figure 4 This is a block diagram illustrating the functional implementation principle of the position trigger signal module provided in the embodiments of this application. Figure 5 The main program flowchart provided for the embodiments of this application; Figure 6 This is a flowchart of an interrupt service routine provided in an embodiment of this application. Detailed Implementation

[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and processes are omitted so as not to obscure the description of this application with unnecessary detail.

[0022] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0023] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. "A plurality" means "two or more."

[0025] The specific embodiments of this application will be described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate this application, but are not intended to limit the scope of this application.

[0026] The purpose of this application is to provide a method for overcoming interrupt fluctuations in Vx real-time control systems using FPGA, thereby addressing the problems of large interrupt response time fluctuations, insufficient system stability, and poor control precision in existing technologies. By implementing intelligent interrupt management and data processing through FPGA hardware, the real-time performance and reliability of the VxWorks system are significantly improved.

[0027] The system architecture of this application includes the following core components: FPGA interrupt management module: responsible for interrupt reception, aggregation, filtering and priority processing; FPGA-based hardware triggering module: responsible for hardware triggering of position data acquisition and starting closed-loop control deviation digital-to-analog conversion; VxWorks software processing module: providing specially optimized drivers and task scheduling mechanisms.

[0028] FPGA Interrupt Management Module: Implements a configurable interrupt management controller within the FPGA, combining multiple external interrupt sources into a single interrupt signal and sending it to VxWorks. For example, multiple external interrupt sources can be configured into a group. This controller combines multiple interrupts such as timer interrupts, asynchronous serial port interrupts, clock synchronization, and other peripheral interrupts, sharing a single interrupt line. The FPGA notifies VxWorks of events through a single interrupt line, rather than multiple independent interrupt lines as in traditional methods. VxWorks' ISR identifies the specific interrupt source by reading the FPGA's status register. In the CPCI architecture, the MSI mechanism is used, where the FPGA directly writes interrupt information to a designated system memory location, reducing interrupt response time. Digital Filtering: Performs hardware debouncing on the input interrupt signal. Only signals that stabilize at a specific level for more than a preset clock cycle are considered valid interrupts, eliminating false triggers caused by signal jitter at the hardware level and improving the hardware limitations of various CPUs.

[0029] FPGA-based hardware triggering module: As is known from the principles of control systems, the execution accuracy of the servo cycle directly affects the accuracy of the entire system. In software interrupt servo programs, the input of position feedback and the output of closed-loop control are most affected by fluctuations. First, the position sensor latches the current position based on the trigger signal and transmits it to the FPGA through multiple serial synchronous clocks. After being converted into parallel data, it is sent to the buffer, and the software can read the data from the corresponding registers. Based on this principle, this application decomposes the input function of position feedback into two parts: one is position trigger latching, and the other is data reading. First, the FPGA generates a fixed-frequency pulse to realize position trigger latching, thereby avoiding interruption fluctuations, while the data reading function is implemented in the vxWoks software. Similarly, the output control function of the control closed loop is also decomposed into writing to the buffer first, the current loop signal to the driver is processed in the vxWoks software and directly converted to be written to the buffer, and the signal to start the conversion circuit is implemented by the FPGA generating a fixed-frequency pulse.

[0030] VxWorks control program processing optimization: The control program's ISR interrupt response subroutine follows a fast-in, fast-out principle, performing only necessary operations: acknowledging the interrupt, reading the FPGA status register, notifying relevant tasks, and then immediately exiting. The ISR uses PIO operations to quickly clear the interrupt flag in the FPGA, avoiding repeated triggering. In particular, the handling of timer interrupt tasks needs improvement; the triggering function for software-triggered position data and the control closed-loop output software start-up conversion function have been removed.

[0031] The complete workflow for this application is as follows: (1) Interrupt reception stage: Peripheral interrupt signals first arrive at the FPGA interrupt management module; (2) Preprocessing stage: The FPGA performs filtering and debouncing on the original interrupts; (3) Scheduling decision phase: The timing of interrupt submission is determined based on factors such as priority and system status; (4) Interrupt submission phase: The FPGA submits an interrupt to the system via CPCI MSI-X or a traditional interrupt line; (5) System processing stage: The VxWorks system executes a simplified ISR, reads the interrupt status in the FPGA, and initiates improved processing for position data triggering and control quantity digital-to-analog conversion; (6) Interrupt completion stage: The system confirms the completion of interrupt handling by writing to the register.

[0032] Compared with the prior art, this application has the following significant advantages: (1) Significantly improve system real-time performance: Through the FPGA interrupt management mechanism, the interrupt frequency processed by VxWorks is reduced by 50%-80%, and the interrupt response time fluctuation is reduced by more than 60%, ensuring that the system meets strict real-time requirements.

[0033] (2) Enhance system reliability: Through hardware filtering, monitoring retransmission and multi-level buffering mechanism, interrupt loss and data error are effectively prevented, which is especially suitable for safety-critical systems.

[0034] (3) Hardware / software co-optimization: Through deep co-design of FPGA and VxWorks, the advantages of hardware parallelism and software flexibility are fully utilized to achieve the optimization of system performance.

[0035] Project verification showed that both the rate accuracy and stability improved from 1×10⁻⁶. -5 Increased to 1×10 -6 .

[0036] The following is a description through specific embodiments.

[0037] Example 1. Hardware FPGA Logic Design 1.1 Interrupt Control Management Module The core interrupt controller in the FPGA adopts a hierarchical state machine design, mainly comprising the following sub-modules: Interrupt input interface: Supports multiple interrupt triggering methods: level triggering and edge triggering; configurable input filtering to prevent signal jitter; input signal synchronization to avoid metastability issues. The structure of the interrupt debouncing filter circuit is as follows: Figure 1 As shown.

[0038] Priority Arbiter: The structure of the interrupt selection control management module is as follows: Figure 2 As shown.

[0039] 1.2 Timer Generation Control Module A 32-bit modulo-configurable counter with a clock frequency of 40MHz and a duty cycle of 50%; it provides a time window comparison function for precise timing control; the configurable time window (typically 1-1000μs). The block diagram of the precision timer function implementation is shown below. Figure 3 As shown.

[0040] 1.3 Position Trigger Signal Module A signal with a settable delay time and pulse width is generated based on the falling edge of the timer to trigger the position sensor. The `Pluse_D` module latches the delay time and pulse width parameters, the `delay_count` module determines the delay time, and the `pluse_count` module determines the pulse width. The block diagram of the position trigger signal module is shown below. Figure 4 As shown.

[0041] 1.4 Control Quantity Digital-to-Analog Conversion Start Signal Analog Processing Module A hardware signal with a configurable delay time and pulse width is generated based on the falling edge of the timer to initiate the digital-to-analog conversion. Its principle is similar to the previous module, except for the delay time and pulse width. The `Pluse_D` module latches the delay time and pulse width parameters, the `delay_count` module determines the delay time, and the `Pluse_count` module determines the pulse width.

[0042] 2. VxWork software program optimization The control program ISR runs on the motion controller host, developed based on VxWorks, and is a key component of the entire software system. This program can generate motion trajectories according to actual needs, realize position and rate closed-loop control; implement digital PID, velocity / acceleration feedforward, and various composite correction filter algorithms; realize position and rate dual closed-loop control; and achieve real-time data acquisition from the actual position sensor. Its main program flowchart is shown below. Figure 5 As shown, the interrupt service routine flow is as follows: Figure 6 As shown.

[0043] like Figure 6As shown, the original design sends an I / O signal via software at the beginning of the software interrupt routine. This signal triggers the position, and the position sensor latches the current position based on this signal. This position is then transmitted to the FPGA via multiple serial synchronous clocks, converted into parallel data, and stored in a buffer. The software can then read the data from the corresponding registers. Therefore, in this process, the timing of the I / O signal transmission significantly impacts the latching accuracy of the position sensor. Fluctuations in the interrupt response will inevitably affect the stability of the entire control system. Therefore, this embodiment modifies this operating mechanism by moving the software-triggered position data triggering function to the FPGA. The trigger is generated via an interrupt request signal from the FPGA's internal timer, processed by a deterministic delay pulse circuit.

[0044] Similarly, the original control closed-loop output control signal to the driver's current loop, which is directly converted after calculation and written to the buffer, will also be affected by servo response fluctuations, thus affecting the stability of the entire control system. This embodiment modifies this operating mechanism to implement hardware triggering, that is, a timer interrupt request signal is generated inside the FPGA, and a conversion signal is generated through a conversion circuit with a determined delay to start the digital-to-analog conversion of the control quantity.

[0045] This embodiment overcomes the adverse effects of servo interrupt fluctuations by employing FPGA hardware-assisted interrupt management, hardware triggering of position sensors, and hardware initiation of control deviation digital-to-analog conversion, bringing significant benefits to the VxWorks system. Through deep co-design of FPGA and VxWorks, this embodiment fully leverages the respective advantages of hardware parallelism and software flexibility to optimize system performance. Actual testing using this method in a multi-axis motion control system showed that, with a control interrupt delay of 15μs, the stability and accuracy of the control system were ensured. Testing revealed that the rate accuracy and stability both improved from 1×10⁻⁶. -5 Increased to 1×10 -6 This embodiment leverages the advantages of hardware parallelism and software flexibility through deep collaborative design between FPGA and VxWorks software, achieving optimal system performance and effectively solving the interrupt response fluctuation problem of VxWorks real-time control system in complex application scenarios. It provides reliable technical support for embedded systems with high real-time requirements.

[0046] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application.

[0047] It should be clarified that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. This application is not limited to the specific structures described above and shown in the figures. Furthermore, for the sake of brevity, detailed descriptions of known methods and techniques are omitted here.

[0048] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for overcoming servo interruption fluctuations in a VxWorks real-time control system using an FPGA, characterized in that, This is achieved through an FPGA interrupt management module, an FPGA-based hardware triggering module, and a VxWorks software processing module. The FPGA interrupt management module is responsible for receiving, aggregating, filtering, and prioritizing interrupts. The FPGA-based hardware triggering module is responsible for hardware triggering of position data acquisition and initiating closed-loop control deviation digital-to-analog conversion. The VxWorks software processing module provides specially optimized drivers and task scheduling mechanisms. The method includes: Interrupt reception phase: Peripheral interrupt signals first arrive at the FPGA interrupt management module; Preprocessing stage: The FPGA performs filtering and debouncing on the raw interrupts; Scheduling decision phase: The timing of interrupt submission is determined based on factors such as priority and system status; Interrupt submission phase: The FPGA submits an interrupt to the system via CPCI MSI-X or a traditional interrupt line; System processing phase: The VxWorks system executes a simplified ISR to read the interrupt status in the FPGA; and initiates improved processing for position data triggering and control quantity digital-to-analog conversion. Interrupt completion phase: The system confirms the completion of interrupt handling by writing to the register.

2. The method for overcoming servo interruption fluctuations in a VxWorks real-time control system using FPGA as described in claim 1, characterized in that, The FPGA interrupt management module combines multiple external interrupt sources into a single interrupt signal and sends it to VxWorks.

3. The method for overcoming servo interruption fluctuations in a VxWorks real-time control system using FPGA as described in claim 1, characterized in that, The FPGA interrupt management module directly writes interrupt information to a designated memory location in the system, reducing interrupt response time.

4. The method for overcoming servo interruption fluctuations in a VxWorks real-time control system using FPGA as described in claim 1, characterized in that, The FPGA interrupt management module performs hardware debouncing on the input interrupt signal, and only signals that stabilize at a specific level for more than a preset clock cycle are recognized as valid interrupts.

5. The method for overcoming servo interruption fluctuations in a VxWorks real-time control system using FPGA as described in claim 1, characterized in that, The FPGA-based hardware triggering module decomposes the position feedback input function into two parts: position trigger latching and data reading.

6. The method for overcoming servo interruption fluctuations in a VxWorks real-time control system using FPGA as described in claim 1, characterized in that, The FPGA-based hardware triggering module generates pulses of a fixed frequency through the FPGA to achieve position triggering latching, thereby avoiding fluctuations caused by interruptions.

7. The method for overcoming servo interruption fluctuations in a VxWorks real-time control system using FPGA as described in claim 1, characterized in that, The current loop signal from the FPGA-based hardware trigger module to the driver is directly converted and written to the buffer after being processed by the VxWoks software. The signal to start the conversion circuit is implemented by the FPGA generating a pulse of a fixed frequency.

8. The method for overcoming servo interruption fluctuations in a VxWorks real-time control system using FPGA as described in claim 1, characterized in that, The ISR of the VxWorks software processing module identifies the specific interrupt source by reading the FPGA's status register.

9. The method for overcoming servo interruption fluctuations in a VxWorks real-time control system using FPGA as described in claim 1, characterized in that, The VxWorks software processing module control program ISR interrupt response subroutine only performs necessary operations: confirming the interrupt, reading the FPGA status register, and notifying relevant work tasks.

10. The method for overcoming servo interruption fluctuations in a VxWorks real-time control system using FPGA as described in claim 1, characterized in that, The VxWorks software processing module ISR quickly clears the interrupt flag in the FPGA through PIO operations to avoid repeated triggering.

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