Display device for improving touch noise

Abstract

The invention relates to a display device for improving touch noise. A display device includes: a first display surface; a second display surface; a touch sensor array disposed to overlap the first display surface and the second display surface; a first gamma circuit configured to divide a first voltage difference between the first high-level source voltage and the low-level source voltage to generate a first gamma reference voltage for the first display surface; and a second gamma circuit configured to divide a second voltage difference between a second high-level source voltage and a low-level source voltage to generate a second gamma reference voltage for the second display surface, in which one frame includes a first period and a second period after the first period, the first high-level source voltage and the low-level source voltage are DC voltages in a first period of time and AC voltages in a second period of time, and the second high-level source voltage and the low-level source voltage are AC voltages in the first period of time and DC voltages in the second period of time.

Description

Technical Field

[0001] This disclosure relates to a device, and more specifically, for example, but not limited to, a display device for improving touch noise. Background Technology

[0002] As the display panel becomes thinner, the parasitic capacitance between the display electrodes and the touch electrodes increases. This parasitic capacitance can be the path through which touch noise flows into the touch sensor. For example, in the touch sensor, the display drive voltage supplied to the display electrodes can be identified as noise, and the parasitic capacitance can be the path through which noise caused by the display drive voltage flows into the touch sensor. The touch noise flowing into the touch sensor may increase with the increase in parasitic capacitance or with rapid changes in the pattern of the display drive voltage.

[0003] Recently, various attempts have been made to reduce touch noise caused by display driving voltage, but there are limitations in improving the level and uniformity of touch noise. Summary of the Invention

[0004] In order to overcome the above-mentioned problems in the prior art, the present disclosure can provide a display device that can improve the level and uniformity of touch noise caused by display driving voltage.

[0005] To achieve these objectives and other advantages and in accordance with the purposes of this disclosure, as implemented and broadly described herein, a display device includes: a first display surface including a first pixel connected to a first data line and configured to display first image data; a second display surface including a second pixel connected to a second data line and configured to display second image data; a touch sensor array configured to overlap with the first and second display surfaces; a first gamma circuit configured to divide a first voltage difference between a first high-level source voltage and a first low-level source voltage to generate a first gamma reference voltage required to drive the first display surface; and a second gamma circuit configured to divide a second voltage difference between a second high-level source voltage and a second low-level source voltage to generate a second gamma reference voltage required to drive the second display surface, wherein a frame includes a first time period and a second time period following the first time period, wherein each of the first high-level source voltage and the first low-level source voltage is a direct current (DC) voltage in the first time period and an alternating current (AC) voltage in the second time period, and wherein each of the second high-level source voltage and the second low-level source voltage is an AC voltage in the first time period and a DC voltage in the second time period.

[0006] In another aspect of this disclosure, a display device includes: a first display surface including a first data line and configured to display a first image; a second display surface including a second data line driven to disconnect from the first data line and configured to display a second image; and a touch sensor array configured to overlap with the first and second display surfaces, wherein a frame includes a first time period and a second time period following the first time period, wherein during the first time period, a first data voltage corresponding to the first image is provided to the first data line of the first display surface, and a second compensation voltage is provided to the second data line of the second display surface, the second compensation voltage being independent of the second image and varying with a phase opposite to that of each of the first data voltages, and wherein during the second time period, a second data voltage corresponding to the second image is provided to the second data line of the second display surface, and a first compensation voltage is provided to the first data line of the first display surface, the first compensation voltage being independent of the first image and varying with a phase opposite to that of each of the second data voltages.

[0007] Other systems, methods, features, and advantages will be apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, within the scope of this disclosure, and protected by the appended claims. Nothing in this section should be construed as limiting those claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0008] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0009] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate one or more embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0010] Figure 1 This is a diagram illustrating a display device according to one embodiment of the present disclosure;

[0011] Figure 2A and Figure 2B This is a diagram illustrating an example of a touch electrode layer and a display electrode layer being interconnected via a cathode electrode layer according to one embodiment of the present disclosure;

[0012] Figure 3This is a diagram illustrating touch noise related to a displayed image pattern according to one embodiment of the present disclosure;

[0013] Figure 4 This is a diagram illustrating the driving timing and compensation timing of each of the first and second display surfaces of a display panel according to one embodiment of the present disclosure;

[0014] Figure 5A This is a schematic diagram illustrating the operation of a first display surface and a second display surface according to an embodiment of the present disclosure during a first time period of a frame;

[0015] Figure 5B This is a schematic illustration of the operation of a first display surface and a second display surface during a second time period of a frame according to an embodiment of the present disclosure;

[0016] Figure 6 This is a diagram illustrating the first to third positions of each of the first and second display surfaces according to an embodiment of the present disclosure;

[0017] Figure 7 This is a diagram illustrating an embodiment of the connection configuration between a timing controller and a first data drive circuit and a second data drive circuit according to one embodiment of the present disclosure;

[0018] Figure 8 This is a diagram illustrating a first gamma circuit included in a first data driving circuit and a second gamma circuit included in a second data driving circuit, according to one embodiment of the present disclosure.

[0019] Figure 9 This is a diagram illustrating the connection configuration between a first power control circuit, a first gamma circuit, and a first voltage divider circuit included in a first data drive circuit, and a second power control circuit, a second gamma circuit, and a second voltage divider circuit included in a second data drive circuit, according to one embodiment of the present disclosure.

[0020] Figure 10A and Figure 10B This is a diagram illustrating the specific driving operation of each of the first and second display surfaces according to an embodiment of the present disclosure during a first time period;

[0021] Figure 11A and Figure 11B This is a diagram illustrating the specific driving operation of each of the first and second display surfaces in a second time period according to an embodiment of the present disclosure;

[0022] Figure 12This is a diagram illustrating another embodiment of the connection configuration between a timing controller and a first data drive circuit and a second data drive circuit according to one embodiment of the present disclosure; and

[0023] Figure 13 , Figure 14A and Figure 14B This is a diagram illustrating the connection configuration between a first power generation circuit, a first gamma circuit, and a first voltage divider circuit included in a first data driving circuit, and a second power generation circuit, a second gamma circuit, and a second voltage divider circuit included in a second data driving circuit, according to one embodiment of the present disclosure.

[0024] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals shall be construed as referring to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and depictions of these elements may be exaggerated. Detailed Implementation

[0025] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted or may be briefly discussed where it is determined that such detailed descriptions would unnecessarily obscure the essential points of the inventive concept. The described process steps and / or order of operations are exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals always refer to the same elements. The names of the corresponding elements used in the following explanation may be chosen solely for the convenience of writing the specification and may therefore differ from those used in actual products.

[0026] In the following description, this disclosure will be given more fully with reference to the accompanying drawings, which illustrate exemplary embodiments of the disclosure. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of this disclosure to those skilled in the art.

[0027] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0028] The shapes, sizes, scales, angles, quantities, etc., disclosed in the drawings used to describe various embodiments of this disclosure are merely exemplary, and this disclosure is not limited thereto. The same reference numerals always refer to the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, unless the term "only" is used, the terms "comprising," "having," "including," etc., indicate that additional components may be added. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are also intended to include the plural forms.

[0029] Any implementation described in this article as an "example" is not necessarily to be interpreted as preferred or advantageous over other implementations.

[0030] Even without explicit statement, elements in the various embodiments of this disclosure will be interpreted as including error margins.

[0031] When describing positional relationships, for example, when the positional relationship between two components is described as “~above,” “~above,” “~below,” and “adjacent to~,” one or more other components may be positioned between the two components unless “only” or “direct” is used.

[0032] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0033] Furthermore, when a component or layer is “connected,” “joined,” or “adheded” to another component or layer, unless otherwise stated, the component or layer may not only be directly connected or adhered to the other component or layer, but also indirectly connected or attached to the other component or layer, with one or more intermediate components or layers “set” or “inserted” between the components or layers. This should be understood to mean that components may be arranged to be in direct contact with each other, or may be arranged to be in direct contact with each other.

[0034] The expressions "first element," "second element," and " / or" "third element" should be understood as one of the first element, the second element, and the third element, or any or all combinations of the first element, the second element, and the third element. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0035] The term “at least one” should be understood to include any and all combinations of one or more associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, as one of ordinary skill in the art will understand, the terms “component” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions.

[0037] In contrast, these embodiments may be provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0038] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be partially or entirely linked or combined with each other, and may be interoperable and technically driven differently from each other. The embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0039] In the following description, specific descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the essential points of this disclosure. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0040] Figure 1 This is a diagram illustrating a display device according to one embodiment of the present disclosure.

[0041] Reference Figure 1 According to one embodiment of this disclosure, the display device may be an organic light-emitting display device. The display panel 100 may include a screen for reproducing an input image. The screen may include a pixel array for displaying pixel data (hereinafter referred to as "image data") of the input image.

[0042] The screen may include a first display surface AA1 and a second display surface AA2 driven separately. One edge of the first display surface AA1 and one edge of the second display surface AA2 may contact each other and have a boundary therebetween. A first data driving circuit 110A may be disposed on the other edge of the first display surface AA1 opposite to that edge. A second data driving circuit 110B may be disposed on the other edge of the second display surface AA2 opposite to that edge.

[0043] The first display surface AA1 may include a first data line DL1, a first gate line GL1 intersecting the first data line DL1, and a first pixel PIX. The first pixel PIX may be arranged in the first display surface AA1 in a matrix type defined by the intersection point between the first data line DL1 and the first gate line GL1 to configure a first pixel array. Based on the position of the first pixel PIX emitting light of the same color, the first pixel PIX may be arranged in various types such as striped and diamond patterns.

[0044] The second display surface AA2 may include a second data line DL2, a second gate line GL2 intersecting the second data line DL2, and a second pixel PIX. The second pixel PIX may be arranged in the second display surface AA2 in a matrix type defined by the intersection point between the second data line DL2 and the second gate line GL2 to configure a second pixel array. Based on the position of the second pixel PIX emitting light of the same color, the second pixel PIX may be arranged in various types such as striped and diamond patterns.

[0045] The first display surface AA1 and the second display surface AA2 may not share data lines DL1 and DL2, and furthermore, they may not share gating lines GL1 and GL2. The first data line DL1 provided in the first display surface AA1 and the second data line DL2 provided in the second display surface AA2 may be physically and electrically disconnected from each other. Furthermore, the first gating line GL1 provided in the first display surface AA1 and the second gating line GL2 provided in the second display surface AA2 may be physically and electrically disconnected from each other.

[0046] For various color combinations, the pixel PIX, including those on the first display surface AA1 and the second display surface AA2, may include R pixels that generate red (R) light, G pixels that generate green (G) light, and B pixels that generate blue (B) light. The pixel PIX may also include W pixels that generate white (W) light. RGB pixels or RGBW pixels can constitute a single pixel.

[0047] Each of the pixels (PIX) included in the first display surface AA1 and the second display surface AA2 can be implemented using a pixel circuit connected to a data line DL and a gate line GL via a thin-film transistor (TFT). The pixel circuit may include a light-emitting device, a driving transistor, one or more switching transistors, and a capacitor. The light-emitting device can be implemented as an organic light-emitting diode (OLED), wherein an organic compound layer is disposed between a cathode electrode and an anode electrode. The driving current applied to the light-emitting device can be controlled based on the gate-source voltage of the driving transistor. The gate-source voltage of the driving transistor can be determined by the data voltage corresponding to the image data DATA.

[0048] The pixel circuit can sample the threshold voltage of the driving transistor in the middle of the pixel programming operation performed in a frame period, and can allow the sampled threshold voltage to be reflected in the gate-source voltage (hereinafter referred to as Vgs) of the driving transistor, and thus can prevent drive current distortion due to changes in the threshold voltage of the driving transistor.

[0049] Pixel circuits can be implemented as hybrid types. In hybrid pixel circuits, the semiconductor layers of some transistors may include low-temperature polysilicon (hereinafter referred to as LTPS), and the semiconductor layers of other transistors may be configured with oxide.

[0050] The timing controller 130 can receive first video data DATA1 and second video data DATA2, as well as timing signals synchronized with the first video data DATA1 and second video data DATA2, from a host system (not shown). The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync can define a vertical time period (i.e., a frame time period). The horizontal synchronization signal Hsync can define a horizontal time period (i.e., a time period obtained by dividing a frame time period by the vertical resolution). The data enable signal DE can define the time for transmitting the first video data DATA1 and second video data DATA2 within either the vertical or horizontal time period.

[0051] The timing controller 130 can generate a first source timing control signal DDC1 for controlling the operation timing of the first data drive circuit 110A and a first gating timing control signal GDC1 for controlling the operation timing of the first gating drive circuit 120A based on the timing signals Vsync, Hsync and DE received from the host system.

[0052] The timing controller 130 can generate a second source timing control signal DDC2 for controlling the operation timing of the second data drive circuit 110B and a second gating timing control signal GDC2 for controlling the operation timing of the second gating drive circuit 120B based on the timing signals Vsync, Hsync and DE received from the host system.

[0053] The timing controller 130 can divide a frame into a first time period and a second time period in time, and can control the operation of the display panel driving circuit by using timing control signals DDC1, DDC2, GDC1 and GDC2 so that the image is displayed only on the first display surface AA1 in the first time period and only on the second display surface AA2 in the second time period.

[0054] For this purpose, the timing controller 130 can provide the display panel driving circuit with first timing control signals DDC1 and GDC1 and first image data DATA1 to be displayed on the first display surface AA1 in the first time period, and can also provide the display panel driving circuit with second timing control signals DDC2 and GDC2 and second image data DATA2 to be displayed on the second display surface AA2 in the second time period.

[0055] In addition, the timing controller 130 can provide the display panel driving circuit with second timing control signals DDC2 and GDC2 and second compensation data COMP2, which is provided to the second display surface AA2 in the first time period. It can also provide the display panel driving circuit with first timing control signals DDC1 and GDC1 and first compensation data COMP1, which is provided to the first display surface AA1 in the second time period.

[0056] The timing controller 130 can analyze the first image data DATA1 to be displayed on the first display surface AA1 in the first time period to generate the second compensation data COMP2 to be provided to the second display surface AA2. The timing controller 130 can analyze the second image data DATA2 to be displayed on the second display surface AA2 in the second time period to generate the first compensation data COMP1 to be provided to the first display surface AA1.

[0057] The display panel driver circuit can be connected to the timing controller 130 via an interface circuit.

[0058] The display panel driving circuit may include a first data driving circuit 110A for driving the first display surface AA1 and a second data driving circuit 110B for driving the second display surface AA2.

[0059] The display panel driving circuit may further include a first gating driving circuit 120A for driving the first display surface AA1 and a second data driving circuit 110B and a second gating driving circuit 120B for driving the second display surface AA2.

[0060] The first data driving circuit 110A can drive the first data line DL1 of the first display surface AA1, and the first gating driving circuit 120A can drive the first gating line GL1 of the first display surface AA1. The second data driving circuit 110B can drive the second data line DL2 of the second display surface AA2, and the second gating driving circuit 120B can drive the second gating line GL2 of the second display surface AA2.

[0061] The first data driving circuit 110A can be implemented using multiple driver integrated circuits (ICs). The first data driving circuit 110A can be provided with first image data DATA1 and a first source timing control signal DDC1 from the timing controller 130 during a first time period. The first data driving circuit 110A can generate a first data voltage corresponding to the first image data DATA1 based on the first source timing control signal DDC1 during the first time period and can output the first data voltage to the first data line DL1.

[0062] The first data drive circuit 110A can be provided with first compensation data COMP1 and a first source timing control signal DDC1 from the timing controller 130 during the second time period. The first data drive circuit 110A can generate a first compensation voltage corresponding to the first compensation data COMP1 based on the first source timing control signal DDC1 during the second time period, and can output the first compensation voltage to the first data line DL1.

[0063] The second data driving circuit 110B can be implemented using multiple driver ICs. During a first time period, the second data driving circuit 110B can be provided with second compensation data COMP2 and a second source timing control signal DDC2 from the timing controller 130. Based on the second source timing control signal DDC2, the second data driving circuit 110B can generate a second compensation voltage corresponding to the second compensation data COMP2 during the first time period and can output the second compensation voltage to the second data line DL2.

[0064] The second data driving circuit 110B can be provided with second image data DATA2 and a second source timing control signal DDC2 from the timing controller 130 during the second time period. The second data driving circuit 110B can generate a second data voltage corresponding to the second image data DATA2 based on the second source timing control signal DDC2 during the second time period, and can output the second data voltage to the second data line DL2.

[0065] The first gating drive circuit 120A and the second gating drive circuit 120B can be directly formed in the bezel area outside the screens AA1 and AA2 of the display panel 100.

[0066] The first gating drive circuit 120A can generate a pulse-type first gating signal in a first time period based on the first gating timing control signal GDC1 provided from the timing controller 130, and can output the first gating signal to the first gating line GL1 by line-by-line scanning. The pulse-type first gating signal may include one or more scan signals and light emission control signals. The first gating drive circuit 120A can stop the output of the pulse-type first gating signal in a second time period based on the first gating timing control signal GDC1 provided from the timing controller 130. Thus, the first gating line GL1 can be scanned and driven in a first direction in the first time period, and non-scanning drive of the first gating line GL1 can be performed in the second time period.

[0067] The second gating drive circuit 120B can stop the output of the pulse-type second gating signal based on the second gating timing control signal GDC2 provided from the timing controller 130. The pulse-type second gating signal may include one or more scan signals and light emission control signals. The second gating drive circuit 120B can generate the pulse-type second gating signal based on the second gating timing control signal GDC2 provided from the timing controller 130, and can output the second gating signal to the second gating line GL2 by line-by-line scanning during the first time period. Thus, non-scan driving of the second gating line GL2 can be performed during the first time period, and scanning driving of the second gating line GL2 can be performed in a second direction opposite to the first direction.

[0068] Figure 2A and Figure 2B This is a diagram illustrating an example of how the touch electrode layer and the display electrode layer are connected to each other through the cathode electrode layer.

[0069] In a display device according to one embodiment of the present disclosure, a touch sensor array may also be disposed on the display panel 100. The touch sensors constituting the touch sensor array may be disposed in the screens AA1 and AA2 of the display panel 100 in a unit-on type or an additional type.

[0070] Reference Figure 2A and Figure 2B The touch sensor can be implemented using touch electrodes TE included in the touch electrode layer LTE. The touch electrodes TE can be connected to the touch driving circuit 150 via touch routing lines. The touch driving circuit 150 can transmit touch driving signals STX to the touch sensor and receive touch sensing signals SRX from the touch sensor.

[0071] The touch electrode layer LTE can be electrically connected to the TFT layer LOT via the cathode electrode layer LOL. The cathode electrode layer LOL can be a common electrode layer shared by the first display surface AA1 and the second display surface AA2. The cathode electrode layer LOL may include a cathode electrode CAT connected to the low-level pixel power ELVSS.

[0072] The cathode electrode CAT can be connected to the touch electrode TE via a first parasitic capacitor Cp1, and to the data line DL via a second parasitic capacitor Cp2. Therefore, display noise occurring in the touch electrode TE and the data line DL may flow into the touch sensor through the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2. Each of the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2 can be a noise inflow path.

[0073] Figure 3 This is a diagram illustrating touch noise relative to the displayed image pattern.

[0074] Reference Figure 3 In a display device according to one embodiment of the present disclosure, the touch electrode layer LTE can be protected by a cover window CW attached thereto by an adhesive layer PSA. When the measuring instrument ME measures the noise in contact with a conductive pattern of the cover window CW, it can be seen that the amplitude of the noise flowing into the touch sensor changes based on the displayed image pattern.

[0075] Display noise occurring in the data line DL may increase more in alternating black and white patterns (horizontal one after another, H1b1) than in white image patterns. Therefore, touch noise caused by cathode coupling may increase more in alternating black and white patterns (horizontal one after another, H1b1) than in white image patterns.

[0076] Figure 4 This is a diagram illustrating the driving and compensation timing of each of the first and second display surfaces of the display panel. Figure 5A This is a schematic illustration of the operation of the first and second display surfaces during the first time period of a frame. Figure 5B This is a schematic illustration of the operation of the first and second display surfaces during a second time period of a frame.

[0077] Reference Figure 4 The first display surface AA1 and the second display surface AA2 of the display panel can alternately perform display and touch driving and compensation driving relative to each other.

[0078] Reference Figure 4 and Figure 5AThe first display surface AA1 can perform display and touch driving in the first time period PP1 of a frame. For display driving, the first gate line driving the first display surface AA1 can be scanned in the first direction DIR1 by line-by-line scanning based on the scan driving timing, and the first data voltage can be output to the first data line of the first display surface AA1 sequentially in units of one horizontal row. As a result, the first data voltage can be written into the first pixel of the first display surface AA1 based on the scan driving timing. At this time, the touch sensor of the first display surface AA1 can be driven to perform touch sensing, and thus, the first touch sensing value can be obtained.

[0079] Compensation driving of the second display surface AA2 can be performed in the first time period PP1 to improve touch noise included in the first touch sensing value. For the compensation driving, the second gate line of the second display surface AA2 can perform non-scan driving, and the second compensation voltage COMP for noise cancellation can be sequentially output to the second data line of the second display surface AA2 in a horizontal row unit. The second compensation voltage COMP can be output only to the second data line and can not be written to the second pixel of the second display surface AA2. Based on the non-scan driving of the second gate line, the second pixel of the second display surface AA2 can be floating and can maintain sufficient data voltage in the second time period of the previous frame.

[0080] Reference Figure 4 and Figure 5B The second display surface AA2 can perform display and touch driving in the second time period PP2 of a frame. For display driving, the second gate line driving the second display surface AA2 can be scanned in the second direction DIR2, opposite to the first direction DIR1, by line-by-line scanning, and the second data voltage can be sequentially output to the second data line of the second display surface AA2 in a horizontal row unit based on the scan driving timing. As a result, the second data voltage can be written into the second pixel of the second display surface AA2 based on the scan driving timing. At this time, the touch sensor of the second display surface AA2 can be driven to perform touch sensing, and thus, the second touch sensing value can be obtained.

[0081] Compensation driving of the first display surface AA1 can be performed in the second time period PP2 to improve touch noise included in the second touch sensing value. For the compensation driving, the first gate line of the first display surface AA1 can perform non-scan driving, and the first compensation voltage COMP for noise cancellation can be sequentially output to the first data line of the first display surface AA1 in a horizontal row unit. The first compensation voltage COMP can be output only to the first data line and can be omitted from being written to the first pixel of the first display surface AA1. Based on the non-scan driving of the first gate line, the first pixel of the first display surface AA1 can be floating and can maintain a sufficient first data voltage in the first time period PP1.

[0082] Figure 6 This is a diagram illustrating the first to third positions of each of the first and second display surfaces.

[0083] Reference Figure 6 To perform position-based differential compensation, each of the first display surface AA1 and the second display surface AA2 can be divided into multiple positions. The first display surface AA1 can be divided into P1, P2, and P3 from the first side IP1 towards the second side BP, and the second display surface AA2 can be divided into P1', P2', and P3' from the first side IP2 towards the second side BP. Here, the inventive concept is not limited to the number of division positions in each display surface. The number of division positions can be set to multiple.

[0084] Position-based differential compensation can be used to increase the uniformity of compensation. For example, in the first display surface AA1, the compensation level of P2 corresponding to the central portion can be greater than the compensation level of P1 and / or P3. Similarly, in the second display surface AA2, the compensation level of P2' corresponding to the central portion can be greater than the compensation level of P1 and / or P3.

[0085] The specifics of location-based differential compensation will be described in detail in the following implementation.

[0086] Figure 7 This is a diagram illustrating an embodiment of the connection configuration between the timing controller and the first data drive circuit and the second data drive circuit. Figure 8 This is a diagram illustrating a first gamma circuit included in a first data driving circuit and a second gamma circuit included in a second data driving circuit. Figure 9 This is a diagram illustrating the connection structure of a first power control circuit, a first gamma circuit, and a first voltage divider circuit included in a first data drive circuit, and a second power control circuit, a second gamma circuit, and a second voltage divider circuit included in a second data drive circuit.

[0087] A display device according to one embodiment of the present disclosure can analyze image data to perform position-based differential compensation, and can control the gain and offset of the compensation data based on the analysis results. When controlling the gain and offset of the compensation data, the voltage difference between the high-level source voltage and the low-level source voltage input to the gamma circuit can be controlled differently.

[0088] Reference Figures 7 to 9 The first power control circuit 132 and the first gamma circuit 142 can be embedded in the first data drive circuit 110A, and the second power control circuit 134 and the second gamma circuit 144 can be embedded in the second data drive circuit 110B.

[0089] The timing controller 130 can analyze the first image data to be provided to the first display surface AA1 in the first time period PP1 of a frame, and can control the second gain GA2 and the second offset OFS2 to be provided to the second compensation data of the second display surface AA2 based on its analysis results.

[0090] The timing controller 130 can analyze the second image data to be provided to the second display surface AA2 in the second time period PP2 of a frame, and can control the first gain GA1 and the first offset OFS1 to be provided to the first display surface AA1 based on its analysis results.

[0091] The first power control circuit 132 may include DAC1, AMP11 and AMP12.

[0092] DAC1 can receive a first gain GA1 and a first offset OFS1 that vary with time during the second time period PP2 from the timing controller 130, and can perform digital-to-analog conversion on the first gain GA1 and the first offset OFS1 to provide them to AMP11 and AMP12. The first gain GA1 and the first offset OFS1 may not be provided to AMP11 and AMP12 during the first time period PP1, and may be provided to AMP11 and AMP12 only during the second time period PP2.

[0093] AMP11 and AMP12 can output a first high-level source voltage REFH1 and a first low-level source voltage REFL1 as the drive power for the first gamma circuit 142 during the first time period PP1, respectively, as default DC voltages REFH_DC and REFL_DC. AMP11 can reflect the time-varying first gain GA1 and first offset OFS1 in the default DC voltage REFH_DC during the second time period PP2, and therefore can output the first high-level source voltage REFH1 as an AC voltage. AMP12 can reflect the time-varying first gain GA1 and first offset OFS1 in the default DC voltage REFL_DC during the second time period PP2, and therefore can output the first low-level source voltage REFL1 as an AC voltage.

[0094] Therefore, the levels of the first high-level source voltage REFH1 and the first low-level source voltage REFL1 can remain unchanged during the first time period PP1 regardless of the positions P1, P2, and P3 of the first display surface AA1, and the levels of the first high-level source voltage REFH1 and the first low-level source voltage REFL1 can change during the second time period PP2 based on the positions P1, P2, and P3 of the first display surface AA1.

[0095] The second power control circuit 134 may include DAC2, AMP21, and AMP22.

[0096] DAC2 can receive a second gain GA2 and a second offset OFS2 that vary over time during the first time period PP1 from the timing controller 130, and can perform digital-to-analog conversion on the second gain GA2 and the second offset OFS2 to provide them to AMP21 and AMP22. The second gain GA2 and the second offset OFS2 may not be provided during the second time period PP2, and may be provided to AMP21 and AMP22 only during the first time period PP1.

[0097] AMP21 and AMP22 can output a second high-level source voltage REFH2 and a second low-level source voltage REFL2 as the drive power for the second gamma circuit 144 during the second time period PP2, respectively, as default DC voltages REFH_DC and REFL_DC. AMP21 can reflect the time-varying second gain GA2 and second offset OFS2 in the default DC voltage REFH_DC during the first time period PP1, and therefore can output the second high-level source voltage REFH2 as an AC voltage. AMP22 can reflect the time-varying second gain GA2 and second offset OFS2 in the default DC voltage REFL_DC during the first time period PP1, and therefore can output the second low-level source voltage REFL2 as an AC voltage.

[0098] Therefore, the levels of the second high-level source voltage REFH2 and the second low-level source voltage REFL2 can vary in the first time period PP1 based on the positions P1', P2' and P3' of the second display surface AA2, and the levels of the second high-level source voltage REFH2 and the second low-level source voltage REFL2 can remain unchanged regardless of the positions P1', P2' and P3' of the second display surface AA2.

[0099] The first gamma circuit 142 can divide the first voltage difference between the first high-level source voltage REFH1 and the first low-level source voltage REFL1 to generate the first gamma reference voltages GMA1, GMA2 to GMAa and GMAb required to drive the first display surface AA1. For this purpose, the first gamma circuit 142 may include a first gamma resistor string connected between the first high-level source voltage REFH1 and the first low-level source voltage REFL1. In the first gamma resistor string, the first voltage divider node DN1 may be located between adjacent resistors R, and the voltage of the first voltage divider node DN1 may be the first gamma reference voltages GMA1, GMA2 to GMAa and GMAb.

[0100] The first voltage divider circuit GDAC1 of the first gamma circuit 142 may further include multiple first resistor strings. The first voltage divider circuit GDAC1 may also divide the first gamma reference voltages GMA1, GMA2 to GMAa and GMAb to output a first data voltage corresponding to the first image data or a first compensation voltage corresponding to the first compensation data.

[0101] The second gamma circuit 144 can divide the second voltage difference between the second high-level source voltage REFH2 and the second low-level source voltage REFL2 to generate the second gamma reference voltages GMA1', GMA2' to GMAa' and GMAb' required to drive the second display surface AA2. For this purpose, the second gamma circuit 144 may include a second gamma resistor string connected between the second high-level source voltage REFH2 and the second low-level source voltage REFL2. In the second gamma resistor string, the second voltage divider node DN2 may be located between adjacent resistors R, and the voltage of the second voltage divider node DN2 may be the second gamma reference voltages GMA1', GMA2' to GMAa' and GMAb'.

[0102] The second voltage divider circuit GDAC2 of the second gamma circuit 144 may further include multiple strings of second resistors. The second voltage divider circuit GDAC2 may also divide the second gamma reference voltages GMA1', GMA2' to GMAa' and GMAb' to output a second data voltage corresponding to the second image data or a second compensation voltage corresponding to the second compensation data.

[0103] Figure 10Aand Figure 10B It is a diagram that specifically illustrates the driving operations of each of the first and second display surfaces in the first time period.

[0104] Reference Figure 10A and Figure 10B In the first time period PP1, the first high-level source voltage REFH1 and the first low-level source voltage REFL1 can be DC voltages whose levels do not change regardless of the positions P1', P2' and P3' of the second display surface AA2, and the second high-level source voltage REFH2 and the second low-level source voltage REFL2 can each be AC ​​voltages whose levels change based on the positions P1', P2' and P3' of the second display surface AA2 (i.e., the levels change with time).

[0105] During the first time period PP1, the first data driving circuit can generate a first data voltage corresponding to the first image data based on the first gamma reference voltages GMA1, GMA2 to GMAa and GMAb obtained by dividing the DC voltages REFH1 and REFL1, and can output the first data voltage to the first data line. The first data voltage can vary with the first phase within the amplitude ΔV of the first voltage difference "REFH1-REFL1" between the DC voltages REFH1 and REFL1. The amplitude ΔV of the first voltage difference "REFH1-REFL1" used to determine the first data voltage can be constant regardless of the positions P1, P2, and P3 of the first display surface AA1.

[0106] During the first time period PP1, the second data driving circuit can generate a second compensation voltage COMP corresponding to the second compensation data based on the second gamma reference voltages GMA1', GMA2' to GMAa' and GMAb' obtained by dividing the AC voltages REFH2 and REFL2, and can output the second compensation voltage COMP to the second data line. The second compensation voltage COMP can vary in a second phase opposite to the first phase within the amplitude ΔV, ΔV+α, or ΔV+2α of the second voltage difference "REFH2-REFL2" between the AC voltages REFH2 and REFL2. The amplitude of the second voltage difference "REFH2-REFL2" used to determine the second compensation voltage COMP can vary with time during the first time period PP1, and can be relatively maximized at the timing when the second compensation voltage COMP is provided to the central portion of the second display surface AA2 to improve the uniformity of touch noise. In other words, the magnitude of the second voltage difference “REFH2-REFL2” can be ΔV in P1' of the second display surface AA2, ΔV+2α in P2', or ΔV+α in P3'.

[0107] During the first time period PP1, the first display noise caused by the change in the first data voltage at positions P1, P2, and P3 of the first display surface AA1 can be applied to the cathode electrode layer through a parasitic capacitor. Similarly, during the first time period PP1, the second display noise caused by the change in the second compensation voltage at positions P1', P2', and P3' of the second display surface AA2 can be applied to the cathode electrode layer through a parasitic capacitor.

[0108] In the first time period PP1, the first display noise and the second display noise can have opposite phases and therefore can cancel each other out in the cathode electrode layer. Thus, the amount of display noise flowing into the touch electrode layer can be minimized or prevented from flowing into the touch electrode layer.

[0109] During the first time period PP1, since the first display surface AA1 and the second display surface AA2 are driven simultaneously at their corresponding positions P1-P1', P2-P2' and P3-P3', the display noise caused by data changes can be canceled out by position, and thus the level and uniformity of touch noise throughout the screen can be enhanced.

[0110] Figure 11A and Figure 11B It is a diagram that specifically illustrates the driving operation of each of the first and second display surfaces in the second time period.

[0111] Reference Figure 11A and Figure 11B In the second time period PP2, the first high-level source voltage REFH1 and the first low-level source voltage REFL1 can each be an AC voltage whose level varies based on the positions P1, P2 and P3 of the first display surface AA1 (i.e., the level changes with time), and the second high-level source voltage REFH2 and the second low-level source voltage REFL2 can be DC voltages whose level does not change regardless of the positions P1', P2' and P3' of the second display surface AA2.

[0112] In the second time period PP2, the second data driving circuit can generate a second data voltage corresponding to the second image data based on the second gamma reference voltages GMA1', GMA2' to GMAa' and GMAb' obtained by dividing the DC voltages REFH2 and REFL2, and can output the second data voltage to the second data line. The second data voltage can vary in the first phase within the amplitude ΔV of the second voltage difference "REFH2-REFL2" between the DC voltages REFH2 and REFL2.

[0113] In the second time period PP2, the first data driving circuit can generate a first compensation voltage COMP corresponding to the first compensation data based on the first gamma reference voltages GMA1, GMA2 to GMAa and GMAb obtained by dividing the AC voltages REFH1 and REFL1, and can output the first compensation voltage COMP to the first data line. The first compensation voltage COMP can vary in a second phase opposite to the first phase within the amplitude ΔV, ΔV+α, or ΔV+2α of the first voltage difference "REFH1-REFL1" between the AC voltages REFH1 and REFL1. The amplitude of the first voltage difference "REFH1-REFL1" used to determine the first compensation voltage COMP can vary with time in the second time period PP2, and can be relatively maximized at the timing when the first compensation voltage COMP is provided to the central portion of the first display surface AA1 to improve the uniformity of touch noise. In other words, the amplitude of the first voltage difference "REFH1-REFL1" can be ΔV in P1, ΔV+α in P2, or ΔV+2α in P3 of the first display surface AA1.

[0114] During the second time period PP2, the first display noise, caused by the change in the first compensation voltage at positions P1, P2, and P3 of the first display surface AA1, can be applied to the cathode electrode layer through a parasitic capacitor. Similarly, during the second time period PP2, the second display noise, caused by the change in the second data voltage at positions P1', P2', and P3' of the second display surface AA2, can be applied to the cathode electrode layer through a parasitic capacitor.

[0115] In the second time period PP2, the first display noise and the second display noise can have opposite phases and therefore can cancel each other out in the cathode electrode layer. Thus, the amount of display noise flowing into the touch electrode layer can be minimized or prevented from flowing into the touch electrode layer.

[0116] In the second time period PP2, since the first display surface AA1 and the second display surface AA2 are driven simultaneously at their corresponding positions P1-P1', P2-P2' and P3-P3', the display noise caused by data changes can be canceled out by position, and thus the level and uniformity of touch noise throughout the screen can be enhanced.

[0117] Figure 12 This is a diagram illustrating another embodiment of the connection structure between the timing controller and the first data drive circuit and the second data drive circuit. Figure 13 , Figure 14A and Figure 14BThis is a diagram illustrating the connection configuration between a first power generation circuit, a first gamma circuit, and a first voltage divider circuit included in a first data drive circuit, and a second power generation circuit, a second gamma circuit, and a second voltage divider circuit included in a second data drive circuit.

[0118] Reference Figures 12 to 14B In this embodiment, the number of DACs used can be reduced by one compared to the embodiments described above. The DAC may not be included in the first power generation circuit 232, but may be included in the second power generation circuit 234.

[0119] Reference Figures 12 to 14B The timing controller 130 can analyze the first image data to be provided to the first display surface AA1 in the first time period PP1 of a frame, and can control the gain GA and offset OFS of the second compensation data to be provided to the second display surface AA2 based on its analysis results.

[0120] The timing controller 130 can analyze the second image data to be provided to the second display surface AA2 in the second time period PP2 of a frame, and can control the gain GA and offset OFS of the first compensation data to be provided to the first display surface AA1 based on its analysis results.

[0121] The first power generation circuit 232 may include AMP11 and AMP12, and thus may generate a DC high-level source voltage REFH and a DC low-level source voltage REFL. AMP11 and AMP12 may output the DC high-level source voltage REFH and the DC low-level source voltage REFL as default DC voltages REFH_DC and REFL_DC in the first time period PP1 and the second time period PP2.

[0122] The second power generation circuit 234 may include a DAC, AMP21, and AMP22, and thus can generate an AC high-level source voltage AREFH and an AC low-level source voltage AREFL. The DAC may receive time-varying gain GA and offset OFS from the timing controller 130 during the first time period PP1 and the second time period PP2, and may perform digital-to-analog conversion on the gain GA and offset OFS to provide them to AMP21 and AMP22. AMP21 and AMP22 may reflect the gain GA and offset OFS in the default DC voltage REFH_DC during the first time period PP1, and thus can output the AC high-level source voltage AREFH and the AC low-level source voltage AREFL.

[0123] The selection circuit SEL can alternately connect the output of the first power generation circuit 232 and the output of the second power generation circuit 234 to the input of the first gamma circuit 242, and can also alternately connect the output of the first power generation circuit 232 and the output of the second power generation circuit 234 to the input of the second gamma circuit 244.

[0124] The selection circuit SEL can provide the first gamma circuit 242 with the DC high-level source voltage REFH and the DC low-level source voltage REFL in the first time period PP1, and can provide the first gamma circuit 242 with the AC high-level source voltage AREFH and the AC low-level source voltage AREFFL in the second time period PP2. The specific structure of the first gamma circuit 242 can be compared with... Figure 9 They are basically the same, so their description can be omitted.

[0125] On the other hand, the selection circuit SEL can provide the AC high-level source voltage AREFH and the AC low-level source voltage AREFL to the second gamma circuit 244 in the first time period PP1, and can provide the DC high-level source voltage REFH and the DC low-level source voltage REFL to the second gamma circuit 244 in the second time period PP2. The specific structure of the second gamma circuit 244 can be similar to... Figure 9 They are basically the same, so their description can be omitted.

[0126] This disclosure can improve the level and uniformity of touch noise caused by display drive voltage.

[0127] The effects of this disclosure are not limited to the examples above, and may include a variety of other effects.

[0128] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the technical concept and scope of this disclosure as defined by the appended claims.

Claims

1. A display device, the display device comprising: A first display surface, the first display surface including a first pixel connected to a first data line, and the first display surface being configured to display first image data; A second display surface, the second display surface including a second pixel connected to a second data line, and the second display surface being configured to display second image data; A touch sensor array, wherein the touch sensor array is configured to overlap with the first display surface and the second display surface; A first gamma circuit is configured to divide a first voltage difference between a first high-level source voltage and a first low-level source voltage to generate a first gamma reference voltage required to drive the first display surface. as well as The second gamma circuit is configured to divide the second voltage difference between the second high-level source voltage and the second low-level source voltage to generate the second gamma reference voltage required to drive the second display surface. A frame includes a first time period and a second time period following the first time period. Wherein, each of the first high-level source voltage and the first low-level source voltage is a DC voltage in the first time period and an AC voltage in the second time period, and Each of the second high-level source voltage and the second low-level source voltage is an AC voltage during the first time period and a DC voltage during the second time period.

2. The display device according to claim 1, wherein, The first data line is disconnected from the second data line, and The first pixel and the second pixel share a cathode electrode.

3. The display device according to claim 1, further comprising: A first gating driving circuit is configured to scan and drive a first gating line of the first display surface in a first direction during the first time period, and to non-scan and drive the first gating line during the second time period. as well as A second gating drive circuit is configured to non-scan drive the second gating line of the second display surface during the first time period, and scan drive the second gating line in a second direction opposite to the first direction during the second time period. The first gamma circuit is included in a first data drive circuit connected to the first data line, and The second gamma circuit is included in a second data drive circuit connected to the second data line.

4. The display device according to claim 3, wherein, During the first time period, the first data driving circuit generates a first data voltage corresponding to the first image data based on a first gamma reference voltage obtained by dividing the DC voltage, and outputs the first data voltage to the first data line. The second data driving circuit generates a second compensation voltage corresponding to the second compensation data based on a second gamma reference voltage obtained by dividing the AC voltage, and outputs the second compensation voltage to the second data line. Wherein, when the first data voltage changes with a first phase within the range of the first voltage difference which is the DC voltage, the second compensation voltage changes with a second phase opposite to the first phase within the range of the second voltage difference which is the AC voltage.

5. The display device according to claim 4, wherein, The magnitude of the second voltage difference varies with time during the first time period and is relatively maximum at the timing when the second compensation voltage is provided to the central portion of the second display surface.

6. The display device according to claim 3, wherein, During the second time period, the first data driving circuit generates a first compensation voltage corresponding to the first compensation data based on a first gamma reference voltage obtained by dividing the AC voltage, and outputs the first compensation voltage to the first data line. The second data driving circuit generates a second data voltage corresponding to the second image data based on a second gamma reference voltage obtained by dividing the DC voltage, and outputs the second data voltage to the second data line. Wherein, when the second data voltage changes with a first phase within the range of the second voltage difference which is the DC voltage, the first compensation voltage changes with a second phase opposite to the first phase within the range of the first voltage difference which is the AC voltage.

7. The display device according to claim 6, wherein, The magnitude of the first voltage difference varies with time during the second time period and is relatively maximum at the timing when the first compensation voltage is provided to the central portion of the first display surface.

8. The display device according to claim 3, wherein, The first data driving circuit further includes: A first power control circuit is configured to generate a DC voltage from the first high-level source voltage and the first low-level source voltage during a first time period to provide the DC voltage to the first gamma circuit, and to generate a time-varying AC voltage from the first high-level source voltage and the first low-level source voltage during a second time period to provide the AC voltage to the first gamma circuit; and A second power control circuit is configured to generate a time-varying AC voltage from the second high-level source voltage and the second low-level source voltage during the first time period to provide the AC voltage to the second gamma circuit, and to generate a DC voltage from the second high-level source voltage and the second low-level source voltage during the second time period to provide the DC voltage to the second gamma circuit.

9. The display device according to claim 3, wherein, The first data driving circuit includes: A first power generation circuit is configured to generate a DC voltage from a high-level source voltage and a low-level source voltage. A second power generation circuit, configured to generate a time-varying AC voltage from a high-level source voltage and a low-level source voltage; and A selection circuit is configured to alternately connect the output of the first power generation circuit and the output of the second power generation circuit to the input of the first gamma circuit, and to alternately connect the output of the first power generation circuit and the output of the second power generation circuit to the input of the second gamma circuit.

10. The display device according to claim 9, wherein, The selection circuit provides the DC voltage as the first high-level source voltage and the first low-level source voltage to the first gamma circuit during the first time period, and provides the AC voltage as the first high-level source voltage and the first low-level source voltage to the first gamma circuit during the second time period. The selection circuit provides the AC voltage as the second high-level source voltage and the second low-level source voltage to the second gamma circuit during the first time period, and provides the DC voltage as the second high-level source voltage and the second low-level source voltage to the second gamma circuit during the second time period.

11. A display device, the display device comprising: A first display surface, the first display surface including a first data line, and the first display surface configured to display a first image; A second display surface, the second display surface including a second data line driven to disconnect from the first data line, and the second display surface being configured to display a second image; as well as A touch sensor array, wherein the touch sensor array is configured to overlap with the first display surface and the second display surface. A frame includes a first time period and a second time period following the first time period. During the first time period, a first data voltage corresponding to the first image is provided to the first data line of the first display surface, and a second compensation voltage is provided to the second data line of the second display surface. The second compensation voltage is independent of the second image and varies with a phase opposite to that of each of the first data voltages. During the second time period, a second data voltage corresponding to the second image is provided to the second data line of the second display surface, and a first compensation voltage is provided to the first data line of the first display surface. The first compensation voltage is independent of the first image and changes in phase opposite to that of each of the second data voltages.

12. The display device according to claim 11, further comprising: A first gamma circuit is configured to divide a first voltage difference between a first high-level source voltage and a first low-level source voltage to generate a first gamma reference voltage required to generate the first data voltage and the first compensation voltage. as well as The second gamma circuit is configured to divide the second voltage difference between the second high-level source voltage and the second low-level source voltage to generate a second gamma reference voltage required for generating the second data voltage and the second compensation voltage.

13. The display device according to claim 12, wherein, The first display surface and the second display surface share a cathode electrode included in the pixel.

14. The display device according to claim 12, further comprising: A first gating driving circuit is configured to scan and drive a first gating line of the first display surface in a first direction during the first time period, and to non-scan and drive the first gating line during the second time period. as well as A second gating drive circuit is configured to non-scan drive the second gating line of the second display surface during the first time period, and scan drive the second gating line in a second direction opposite to the first direction during the second time period. The first gamma circuit is included in a first data drive circuit connected to the first data line, and The second gamma circuit is included in a second data drive circuit connected to the second data line.

15. The display device according to claim 14, wherein, During the first time period, the first data driving circuit generates the first data voltage based on a first gamma reference voltage obtained by dividing a DC voltage, and outputs the first data voltage to the first data line. The second data driving circuit generates the second compensation voltage based on a second gamma reference voltage obtained by dividing an AC voltage, and outputs the second compensation voltage to the second data line. Wherein, when the first data voltage changes with a first phase within the range of the first voltage difference which is the DC voltage, the second compensation voltage changes with a second phase opposite to the first phase within the range of the second voltage difference which is the AC voltage.

16. The display device according to claim 15, wherein, The magnitude of the second voltage difference varies with time during the first time period and is relatively maximum at the timing when the second compensation voltage is supplied to the central portion of the second display surface.

17. The display device according to claim 14, wherein, During the second time period, the first data driving circuit generates the first compensation voltage based on a first gamma reference voltage obtained by dividing the AC voltage, and outputs the first compensation voltage to the first data line. The second data driving circuit generates the second data voltage based on a second gamma reference voltage obtained by dividing the DC voltage, and outputs the second data voltage to the second data line. Wherein, when the second data voltage changes with a first phase within the range of the second voltage difference which is the DC voltage, the first compensation voltage changes with a second phase opposite to the first phase within the range of the first voltage difference which is the AC voltage.

18. The display device according to claim 17, wherein, The magnitude of the first voltage difference varies with time during the second time period and is relatively maximum at the timing when the first compensation voltage is provided to the central portion of the first display surface.

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