Data storage optimization method and system in chip memory

Abstract

The invention provides a data storage optimization method and system in a chip memory, and relates to the technical field of data processing.The method comprises the steps that external reasoning request data is temporarily stored in a receiving buffer area of the chip memory, an authentication identifier is extracted, and first-level integrity evaluation is executed based on the authentication identifier to obtain a first evaluation parameter; matching corresponding routing decision information in a fast cache region of a memory according to the first evaluation parameter, selecting a target client from a plurality of distributed clients according to the corresponding routing decision information, generating a connection identifier and a routing context in the memory, and executing second-level stability evaluation on the routing context to obtain a second evaluation parameter; and packaging based on the connection identifier, the routing context and the second evaluation parameter to obtain a control signaling, and sending the control signaling to a target client through a first network port of the chip to trigger establishment of a reverse connection pointing to the chip. According to the invention, dynamic self-adaptive adjustment of the capacity of the on-chip receiving buffer area and the capacity of the rapid buffer area is realized.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a method and system for optimizing data storage in chip memory. Background Technology

[0002] In AI acceleration chip applications targeting collaborative inference with multiple distributed clients, traditional chip memory often uses static partitioning configuration.

[0003] For example, when processing concurrent external inference requests, a certain edge inference chip divides its on-chip memory into a receive buffer and a routing cache, with the ratio of their capacities preset to a constant value at the factory. This passively stores request data and basic routing decision information, and cannot adaptively adjust according to actual business scenarios. When the concurrency of external inference requests, data integrity, client routing status, and transmission link efficiency fluctuate dynamically, the static memory partition may experience issues such as receive buffer overflow and packet loss or idle space, and insufficient cache capacity leading to increased routing decision matching latency. Furthermore, it lacks a linkage optimization mechanism that integrates request authentication integrity, routing stability, and transmission efficiency. Ultimately, this results in low chip memory resource utilization, increased inference request forwarding latency, and poor stability of distributed client connections and data transmission, making it difficult to meet the actual needs of high-concurrency, high-reliability distributed inference services for efficient chip memory scheduling and data storage optimization. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method and system for optimizing data storage in chip memory, so as to realize dynamic adaptive adjustment of the capacity of on-chip receive buffer and fast cache.

[0005] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: A first aspect is a method for optimizing data storage in chip memory, the method comprising: The external inference request data is temporarily stored in the chip memory's receive buffer and the authentication identifier is extracted. Based on the authentication identifier, the first-level integrity assessment is performed to obtain the first assessment parameters. Based on the first evaluation parameters, the corresponding routing decision information is matched in the fast cache of memory to select the target client from multiple distributed clients, and a connection identifier and routing context are generated in memory. The second-level stability evaluation is performed on the routing context to obtain the second evaluation parameters. The control signaling is encapsulated based on the connection identifier, routing context, and second evaluation parameters, and sent to the target client through the chip's first network port to trigger the establishment of a reverse connection to the chip; Upon receiving a reverse connection, the connection identifier is associated and bound with the original request context temporarily stored in memory to obtain a data forwarding channel. The data forwarding channel performs a third-level transmission efficiency evaluation to obtain the third evaluation parameters. A multidimensional framework is constructed using the first, second, and third evaluation parameters, and the framework is uniformly partitioned. The data aggregation degree and the correlation of partition boundaries in each partition are used as optimization constraints. The partition data within the multidimensional framework are weighted and finally solved to obtain the buffer adjustment value of the chip memory. Based on the buffer adjustment value, the capacity ratio of the receive buffer and the fast cache is reconfigured. Based on the reconfigured storage capacity ratio, the request data in the receive buffer is forwarded to the target client through the chip's first network port, and the returned inference results are processed.

[0006] Furthermore, the external inference request data is temporarily stored in the chip's memory receive buffer and the authentication identifier is extracted. Based on the authentication identifier, a first-level integrity assessment is performed to obtain the first assessment parameters, including: In the receive buffer, the message header of the external inference request data is parsed to extract the authentication identifier; the authentication identifier includes at least the request sequence number, digital signature, and timestamp. Based on the extracted digital signature, the signature verification operation is performed through the root certificate pre-installed in the chip's secure storage area to obtain the signature verification result; Based on the extracted timestamp, the timestamp is compared with the chip's local clock to determine whether the external inference request data is within the preset valid time window, thus obtaining the timeliness verification result. Based on the extracted request sequence number, the historical record cache in memory is queried to determine whether the sequence number is valid and has not been reused, and the sequence uniqueness verification result is obtained. The signature verification result, timeliness verification result, and sequence uniqueness verification result are combined and calculated using a preset weighted decision algorithm to generate the first evaluation parameter used to quantify the legality and integrity level of the requested data.

[0007] Furthermore, based on the first evaluation parameters, the corresponding routing decision information is matched in the fast cache of memory to select the target client from multiple distributed clients. A connection identifier and routing context are generated in memory, and a second-level stability evaluation is performed on the routing context to obtain the second evaluation parameters, including: Based on the first evaluation parameters, the system queries and matches the preset routing decision mapping table in the fast cache of memory to obtain the initial routing policy information corresponding to the legality and integrity level of the current request. Based on the initial routing policy information, and combined with the load status and health indicators of multiple distributed clients obtained in real time from the fast cache, one of the multiple distributed clients is calculated and selected as the target client for this request forwarding; In response to the selection of a target client, a globally unique connection identifier is generated in memory for the communication connection to be established, and a routing context containing the network address of the target client, the selected routing policy, and the first evaluation parameter is created. A second-level stability assessment is performed on the routing context. The assessment includes at least a comprehensive analysis based on the target client's historical connection success rate, current network round-trip latency, and the inherent reliability of the routing policy, to obtain the second assessment parameters.

[0008] Furthermore, control signaling is encapsulated based on the connection identifier, routing context, and second evaluation parameters, and sent to the target client through the chip's first network port to trigger the establishment of a reverse connection to the chip, including: The connection identifier, routing context, and second evaluation parameters are assembled according to a preset signaling format and encapsulated to generate a control signaling data packet; The encapsulated control signaling data packet is sent to the selected target client through the chip's first network port; The control signaling data packet is configured to, upon being received and parsed by the target client, trigger the target client to actively initiate a reverse connection to the chip's first network port based on the connection parameters specified in the routing context contained in the target client.

[0009] Furthermore, upon receiving a reverse connection, the connection identifier is associated and bound with the original request context temporarily stored in memory to obtain a data forwarding channel. The data forwarding channel performs a third-level transmission efficiency evaluation to obtain third evaluation parameters, including: When an external connection request is received through the chip's first network port, it verifies whether the connection request is a reverse connection initiated by the target client and extracts the connection identification information carried in the protocol message of the verified reverse connection. The connection identification information is matched and associated with the connection identification and the corresponding original request context temporarily stored in memory. Based on the successful association and binding, a data forwarding channel corresponding to this communication is registered and activated in the chip's network protocol stack. A third-level transmission efficiency assessment is performed on the data forwarding channel. The assessment includes measuring the network round-trip delay, effective bandwidth, and data packet success rate of the data forwarding channel within a preset test period, and generating a third assessment parameter based on the measurement results to quantitatively characterize the current link transmission efficiency.

[0010] Furthermore, a multidimensional framework is constructed using the first, second, and third evaluation parameters, and the framework is uniformly partitioned. Using the data aggregation degree and partition boundary correlation of each partition as optimization constraints, a weighted fitting and final solution are performed on the partitioned data within the multidimensional framework to obtain the chip memory buffer adjustment value. Based on the buffer adjustment value, the capacity ratio of the receive buffer and the fast cache is reconfigured, including: Using the first evaluation parameter, the second evaluation parameter, and the third evaluation parameter as the basic input vector, a multidimensional evaluation framework is constructed in memory; the multidimensional evaluation framework is then subjected to a uniform partitioning operation with preset rules, dividing the entire parameter space into multiple non-overlapping evaluation sub-regions; Based on the evaluation sub-regions, the statistical distribution characteristics of historical and current evaluation parameter points falling into each sub-region are calculated, and the data aggregation degree of each sub-region is quantified. The continuity of parameter distribution on the boundary of each adjacent evaluation sub-region is analyzed, and the correlation and distance between the center point vectors of adjacent sub-regions are calculated, and the correlation of the partition boundary is quantified. Using the data aggregation degree and partition boundary correlation of each partition as joint constraints, an objective optimization function is constructed regarding the ratio of the capacity of the receive buffer and the fast buffer. The buffer adjustment value is obtained by weighted fitting and solving the objective optimization function. Based on the buffer adjustment value, the chip is invoked to dynamically adjust the physical capacity allocation ratio of the receive buffer and the fast cache in the chip's memory, thus completing the reconfiguration.

[0011] Furthermore, based on the reconfigured storage capacity ratio, the request data in the receive buffer is forwarded to the target client via the chip's first network port, and the returned inference results are processed, including: Based on the reconfigured storage capacity ratio of the receive buffer and the fast cache, the data read interface of the receive buffer is called; through the called data read interface, the payload portion of the external inference request data is obtained from the receive buffer. The payload portion is forwarded to the target client via the registered and activated data forwarding channel through the chip's first network port. The inference result data corresponding to the external inference request data returned by the target client is received through the data forwarding channel. The inference result data is parsed and format verified, and the final inference result that passes the verification is output to the result processing unit designated by the chip.

[0012] Secondly, the data storage optimization system in the chip's memory includes: The extraction module is used to temporarily store external inference request data into the receiving buffer of the chip memory and extract the authentication identifier, and perform a first-level integrity assessment based on the authentication identifier to obtain the first assessment parameters. The selected module is used to match the corresponding routing decision information in the fast cache of memory according to the first evaluation parameters, so as to select the target client from multiple distributed clients, and generate connection identifier and routing context in memory, and perform a second-level stability evaluation on the routing context to obtain the second evaluation parameters. The encapsulation module is used to encapsulate control signaling based on connection identifier, routing context and second evaluation parameters, and send it to the target client through the chip's first network port to trigger the establishment of a reverse connection to the chip; The binding module is used to associate and bind the connection identifier with the original request context temporarily stored in memory when a reverse connection is received, so as to obtain a data forwarding channel. The data forwarding channel performs a third-level transmission efficiency evaluation to obtain the third evaluation parameters. The calculation module is used to construct a multidimensional framework using the first, second, and third evaluation parameters, and to uniformly partition the framework. Using the data aggregation degree and the correlation of partition boundaries as optimization constraints, the module performs weighted fitting and final solution on the partition data within the multidimensional framework to obtain the buffer adjustment value of the chip memory. Based on the buffer adjustment value, the capacity ratio of the receive buffer and the fast cache is reconfigured. The processing module is used to forward the request data in the receive buffer to the target client through the chip's first network port based on the reconfigured storage capacity ratio, and to process the returned inference results.

[0013] Thirdly, a computing device includes: One or more processors; A storage device for storing one or more programs that, when executed by one or more processors, cause the one or more processors to implement the method.

[0014] Fourthly, a computer-readable storage medium storing a program that, when executed by a processor, implements the method.

[0015] The above-described solution of the present invention has at least the following beneficial effects: Because it employs a three-tiered approach—extracting authentication identifiers to perform a first-level integrity assessment, performing a second-level stability assessment on the routing context, and performing a third-level transmission efficiency assessment on the data forwarding channel—and then constructing a multi-dimensional framework using these three assessment parameters and uniformly partitioning the data, a weighted fitting solution is performed using the data aggregation degree and partition boundary correlation of each partition as constraints to obtain the buffer adjustment value. This allows for the reconfiguration of the ratio of the receive buffer to the fast buffer capacity. Furthermore, it combines control signaling to trigger reverse connections and associates connection identifiers with the original request context to construct the data forwarding channel. Therefore, it overcomes the limitations of traditional chip memory's static partitioning configuration, which cannot adjust based on external inference of request concurrency, data integrity, and client routing status. The system dynamically and adaptively adjusts the capacity ratio to address technical issues such as receive buffer overflow and packet loss or space idleness, increased routing decision matching delay in the fast buffer, low chip memory resource utilization, increased inference request forwarding latency, and poor stability of distributed client connections and data transmission due to the lack of a linkage optimization mechanism. This achieves the technical effect of dynamically and adaptively adjusting the on-chip receive buffer and fast buffer capacity, improving chip memory resource utilization, reducing inference request forwarding latency, enhancing the stability of distributed client connections and data transmission, and ensuring the legality and integrity of external inference request data, thus meeting the technical requirements of high-concurrency and high-reliability distributed inference services. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating a data storage optimization method in chip memory provided by an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of a data storage optimization system in chip memory provided by an embodiment of the present invention. Detailed Implementation

[0018] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0019] like Figure 1 As shown, embodiments of the present invention propose a data storage optimization method in chip memory, the method comprising the following steps: Step 1: Temporarily store the external inference request data into the chip memory's receive buffer and extract the authentication identifier. Perform a first-level integrity assessment based on the authentication identifier to obtain the first assessment parameters. Step 2: Match the corresponding routing decision information in the fast cache of memory according to the first evaluation parameters, select the target client from multiple distributed clients, generate connection identifier and routing context in memory, and perform a second-level stability evaluation on the routing context to obtain the second evaluation parameters. Step 3: Based on the connection identifier, routing context and second evaluation parameters, control signaling is encapsulated and sent to the target client through the chip's first network port to trigger the establishment of a reverse connection to the chip; Step 4: Upon receiving a reverse connection, the connection identifier is associated and bound with the original request context temporarily stored in memory to obtain a data forwarding channel. The data forwarding channel performs a third-level transmission efficiency evaluation to obtain the third evaluation parameters. Step 5: Construct a multidimensional framework using the first, second, and third evaluation parameters, and partition the framework evenly. Using the data aggregation degree and partition boundary correlation of each partition as optimization constraints, perform weighted fitting and final solution on the partition data within the multidimensional framework to obtain the buffer adjustment value of the chip memory. Based on the buffer adjustment value, reconfigure the capacity ratio of the receive buffer and the fast cache. Step 6: Based on the reconfigured storage capacity ratio, forward the request data in the receive buffer to the target client through the chip's first network port, and process the returned inference results.

[0020] In this embodiment of the invention, the technical means employed include: temporarily storing external inference request data in a receiving buffer and extracting authentication identifiers for a first-level integrity assessment; selecting a target client based on assessment parameters and matching routing decision information; performing a second-level stability assessment of the routing context; encapsulating control signaling to trigger a reverse connection; associating and binding connection identifiers with the original request context to construct a data forwarding channel and performing a third-level transmission efficiency assessment; then constructing a multi-dimensional framework and partitioning it using the three-level assessment parameters; using the aggregation degree of partitioned data and boundary correlation as constraints to weighted fit and solve the buffer adjustment value, thereby reconfiguring the capacity ratio of the receiving buffer and the fast buffer; and finally, forwarding the request data in a targeted manner and processing the inference results. This invention overcomes the technical problems of traditional chip memory, which uses static partitioning configuration and cannot adaptively adjust the buffer capacity ratio according to the dynamic changes of external inference requests, client routing status, and transmission link efficiency. This leads to receive buffer overflow and packet loss or space idleness, increased routing decision matching latency in the fast buffer, and low chip memory resource utilization, increased inference request forwarding latency, and poor stability of distributed client connection and data transmission due to the lack of linkage optimization mechanism. It achieves dynamic adaptive adjustment of on-chip receive buffer and fast buffer capacity, improves chip memory resource utilization and data forwarding efficiency, reduces inference request forwarding latency, and enhances the stability of distributed client connection and data transmission.

[0021] In a preferred embodiment of the present invention, step 1 above may include: Step 1.1: In the receive buffer, parse the header of the external inference request data and extract the authentication identifier. The authentication identifier includes at least the request sequence number, digital signature, and timestamp. Specifically, starting from the initial physical storage address of the chip memory receive buffer, read the complete message content of the external inference request data segment by segment, prioritize locating and parsing all standard fields in the message header, and extract the request sequence number, digital signature, and timestamp from the specified field positions in the message header according to the fixed format of message transmission. After extraction, write the three types of authentication identifier data into the specially allocated temporary authentication data storage area in the chip memory, thus completing the extraction and temporary storage of the authentication identifier.

[0022] Step 1.2: Based on the extracted digital signature, a signature verification operation is performed using the root certificate pre-installed in the chip's secure storage area to obtain the signature verification result. Specifically, this includes: first, sending a verification start command to the built-in storage; the command is transmitted to a dedicated command receiving address 8000; upon receiving the command, the system completes the startup and enters the working state within 1 millisecond; then, reading the root certificate data from the chip's secure storage area (a read-only storage area); the root certificate data starts from a fixed physical address 10000, occupying 256 consecutive bytes of storage space, corresponding to 2048 bits of data, with each 8 bits constituting 1 byte, ending at physical address 10255; the root certificate is stored in RSA2048 format and has been verified at the factory, with a 32-bit cyclic redundancy check (CRC) code attached during storage; while reading the root certificate data, this 32-bit CRC code is verified first to ensure the root certificate data has not been tampered with; only after a successful check match is the complete 2048-bit root certificate data loaded into the internal cache; next, data is retrieved from the temporary authentication data storage area... The system reads the previously extracted and temporarily stored 2048-bit digital signature from addresses 19000 to 19255, and then reads the core payload data of the external inference request from addresses 40000 to 60000 in the receive buffer. The core payload data has a fixed length of 20480 bytes. Using the public key in the root certificate as the verification benchmark, the system initiates a 2048-bit encryption operation. Using modular exponentiation, the system first performs a hash operation on the core payload data to generate a 256-bit hash value, and then uses the private key corresponding to the digital signature to verify the hash value. At the same time, the system compares the digital signature and the core payload data bit by bit in byte order, from byte 1 to byte 256. Every 16 bytes of comparison is completed, and the intermediate result is recorded and stored in the temporary operation buffer. The entire signature verification process takes no more than 8 milliseconds. After verification, a 1-byte signature verification result is generated, where a value of 1 indicates that the signature verification is successful, meaning that the signature and data match perfectly and the root certificate verification is valid, and a value of 0 indicates that the signature verification is unsuccessful, meaning that the signature does not match or the root certificate verification is invalid. Finally, the signature verification result is written to the starting physical address 20000 of the temporary authentication data storage area, while auxiliary data such as intermediate hash values ​​and computation time during the signature verification process are written to addresses 20001 to 20015 of this area, thus completing the full storage of the signature verification result.

[0023] Step 1.3: Based on the extracted timestamp, compare the timestamp with the chip's local clock to determine whether the external inference request data is within a preset valid time window, thus obtaining a timeliness verification result. Specifically, this includes: the chip is equipped with a high-precision real-time clock that synchronizes with the network time server once per second, ensuring that the clock accuracy error does not exceed 1 millisecond. This real-time clock generates a 17-bit standard clock value in real-time, containing the year, month, day, hour, minute, second, and millisecond. For example, 20260205153045678 corresponds to 15:30:45.678 milliseconds on February 5, 2026. The clock value is updated in real time and stored at dedicated addresses 9000 to 9016. The chip first reads the previously extracted timestamp from addresses 18000 to 18016 in the temporary authentication data storage area. This timestamp has the same format as the standard clock value, also a 17-bit number. Then, the chip directly converts the timestamp and the standard clock value, converting them into a total number of milliseconds accumulated since January 1, 2000, 00:00:00:00. For example, the total number of milliseconds corresponding to the standard clock is 820572634567, and the total number of milliseconds corresponding to the timestamp is... The value is 820572634499. Next, the absolute time difference between the two is directly calculated, i.e., 820572634567 minus 820572634499, resulting in an absolute difference of 68 milliseconds. The preset effective time window is 60 seconds before and after, corresponding to a maximum difference of 60,000 milliseconds. When the calculated absolute time difference is ≤ 60,000 milliseconds, the external inference request data is determined to be within the valid transmission time range, generating a 1-byte timeliness verification result, with a value of 1 indicating successful verification. When the absolute time difference is greater than 60,000 milliseconds... When the external inference request data exceeds the valid time range, indicating a risk of expiration or malicious retransmission, a value of 0 is generated to represent a failed verification result. At the same time, the invalid timestamp and the corresponding difference data are written to the chip's error log storage starting address 40000 for easy troubleshooting. Finally, the timeliness verification result is stored in real time to the starting physical address 20016 of the temporary authentication data storage area, and the calculated absolute time difference is stored in the address range 20017 to 20020 of the area in 4-byte unsigned integer format, completing the entire data storage process for timeliness verification.

[0024] Step 1.4: Based on the extracted request sequence number, query the historical record cache in memory to determine whether the sequence number is valid and has not been reused, and obtain the sequence uniqueness verification result. Specifically, this includes: sending a sequence number query instruction to the historical record circular storage area in memory. This query instruction contains the extracted request sequence number data and the query start identifier. This historical record storage area is a read-write area with a starting physical address of 50000 and an ending physical address of 54799, occupying a total of 48000 bytes of storage space. It is specifically used to store 3000 valid request sequence number data that have been processed. Each sequence number occupies 16 bytes of physical storage space. A first-in-first-out circular overwrite mechanism is adopted. When the number of stored sequence numbers reaches 3000, the new sequence number will overwrite the first stored sequence number data. The chip first reads the 16-byte request sequence number extracted this time from the temporary authentication data storage area address 18017 to 18032. This sequence number must conform to the preset 16-bit standard encoding rules. The specific rules are as follows: the first bit is a fixed identifier bit, which can only take uppercase hexadecimal characters with values ​​from 1 to F, and is used to identify the service type of the requested data. The next 15 bits are sequential encoding bits, which can take numbers from 0 to 9 and uppercase hexadecimal characters from A to F. Furthermore, the entire 16-bit sequence number is not allowed to have 8 consecutive identical characters. Sequence numbers that do not conform to these rules are directly determined to be invalid. Subsequently, the sequence number traversal and comparison process is initiated. Starting from the starting address 50000 of the historical record storage area, each 16-byte processed sequence number is read sequentially. The read processed sequence numbers are first stored in the temporary comparison cache addresses 60000 to 60015, and then the request sequence number extracted this time is stored in the temporary comparison cache addresses 60016 to 60031. The sequence numbers are compared byte by byte from 1 to 16 in byte order. Each byte corresponds to 8 bits of binary data. Only when all 16 bytes match completely is the sequence number determined to be duplicated. The entire traversal and comparison process proceeds from newest to oldest, traversing a maximum of 3000 serial numbers in no more than 10 milliseconds. If a matching serial number is found during the traversal, the traversal is immediately terminated, and the serial number is determined to be duplicated and invalid. If no match is found after traversing all 3000 serial numbers, the result is then combined with the encoding rule verification result for further judgment. If no identical serial number is found in the historical record storage area, and the serial number fully conforms to the 16-bit standard encoding rule, the serial number is determined to be valid and not reused, generating a 1-byte sequence uniqueness verification result, with a value of 1 indicating successful verification. If an identical serial number is found or the serial number does not conform to the encoding rule, the serial number is determined to be invalid or reused, generating a value of 0 indicating failed verification. Finally, the sequence uniqueness verification result is synchronously stored in the starting physical address 20032 of the temporary authentication data storage area, while auxiliary data such as the traversal and comparison time and the number of traversed records are stored in addresses 20033 to 20036 of this area, completing the entire sequence uniqueness verification process.

[0025] Step 1.5: Combining the signature verification result, timeliness verification result, and sequence uniqueness verification result, a pre-defined weighted decision algorithm is used to perform fusion calculations to generate the first evaluation parameter used to quantify the legality and integrity level of the request data. Specifically, this includes: calling the built-in 32-bit floating-point arithmetic logic, which supports floating-point numerical operations with a precision of up to 8 decimal places; writing various types of data to the input registers of this arithmetic logic, specifically writing a 1-byte signature verification result to input register address 70000, a 32-bit floating-point weight value of 0.5 to address 70001, and a 1-byte timeliness value to address 70002. Upon receiving the signature verification result, address 70003 is written with a weight value of 0.3 in 32-bit floating-point format, address 70004 is written with a 1-byte sequence uniqueness verification result, and address 70005 is written with a weight value of 0.2 in 32-bit floating-point format. Subsequently, this floating-point arithmetic logic converts each type of verification result into a 32-bit floating-point value, where a verification result value of 1 is converted to a floating-point value of 1.0, and a verification result value of 0 is converted to a floating-point value of 0.0. Then, a weighted multiplication operation is performed: first, the floating-point value corresponding to the signature verification result is multiplied by the weight 0.5 to obtain the signature weighted score; for example, if the signature verification passes, the calculation result is 1.0 × 0.5 = 0.5. The timeliness verification result is multiplied by a weight of 0.3 to obtain the timeliness-weighted score. For example, if the timeliness verification passes, the result is 1.0 × 0.3 = 0.3. The sequence uniqueness verification result is then multiplied by a weight of 0.2 to obtain the uniqueness-weighted score. For example, if the sequence uniqueness verification passes, the result is 1.0 × 0.2 = 0.2. After calculating the three weighted scores, the floating-point operation logic performs a summation operation, adding the signature weighted score, the timeliness weighted score, and the uniqueness weighted score to obtain the intermediate comprehensive score. For example, if all three verifications pass, the intermediate comprehensive score is 0.5 + 0.3. +0.2=1.0; If only the signature verification passes and the other two fail, the intermediate comprehensive score is 0.5+0.0+0.0=0.5; Subsequently, the floating-point operation logic performs normalization processing on the intermediate comprehensive score. Since the value range of the intermediate comprehensive score is itself between 0.0 and 1.0, this normalization process mainly converts the value into a 32-bit continuous floating-point value conforming to the IEEE 754 standard. The specific format is as follows: the first bit is the sign bit, with a value of 0 representing a positive number; the second to ninth bits are the exponent bits, with a value of 127; and the tenth to 32nd bits are the mantissa bits, used to store the specific fractional part to ensure the precision and standardization of the value.The 32-bit continuous floating-point value is the first evaluation parameter. The closer the value is to 1.0, the higher the level of legality and integrity of the external inference request data. The closer the value is to 0.0, the lower the level of legality and integrity of the request data. Values ​​≥ 0.8 are judged as high credibility, values ​​between 0.5 and 0.79 are judged as medium credibility, and values ​​< 0.5 are judged as low credibility. This is how the first evaluation parameter is obtained.

[0026] In this embodiment of the invention, the technical means of extracting the authentication identifier containing the request sequence number, digital signature, and timestamp from the message header of the external inference request data, verifying the digital signature through the root certificate pre-installed in the chip's secure storage area, verifying the timeliness by comparing the timestamp with the chip's local clock, and verifying the uniqueness of the sequence number by querying the memory history cache, and then using a preset weighted decision algorithm to fuse the above three verification results to generate a first evaluation parameter that quantitatively represents the legality and integrity level of the request data, overcomes the technical problems of traditional technologies that have a single dimension for verifying the legality and integrity of external inference request data, are incomplete in verification, cannot effectively prevent illegal scenarios such as data tampering and request replay, and are difficult to quantitatively evaluate the trust level of request data, resulting in a lack of reliable basis for routing decisions and memory optimization. Thus, it achieves comprehensive and accurate verification of the legality and integrity of external inference request data.

[0027] In a preferred embodiment of the present invention, step 2 above may include: Step 2.1: Based on the first evaluation parameters, query and match the preset routing decision mapping table in the memory's fast cache area to obtain the initial routing policy information corresponding to the legitimacy and integrity level of the current request. Specifically, this includes: reading the first evaluation parameters from the dedicated evaluation parameter storage area starting at physical address 30000. This parameter is a 32-bit continuous floating-point value, ranging from 0 to one. After reading, it is temporarily stored in temporary cache addresses 70006 to 70009. The chip's fast cache area is a readable and writable region, starting at physical address 60000 and ending at physical address 80000, occupying a total of 20000 bytes of storage space. The routing decision mapping table is fixedly stored from 60000 to 60383, containing 12 routing decision entries, each occupying 32 bytes, stored sequentially, corresponding to different ranges of the first evaluation parameters and initial routing policy information. The specific mapping rule is that a first evaluation parameter of 0.8 to 0 corresponds to a high-reliability routing policy, 0.5 to 0.79 corresponds to a balanced routing policy, and 0 to 0.49 corresponds to a secure routing policy. The specific information for each strategy is as follows: High-reliability routing strategy priority 1, forwarding port is the chip's second network port, transmission timeout is 50 milliseconds; Balanced routing strategy priority 2, forwarding ports are the chip's second and third network ports, transmission timeout is 80 milliseconds; Secure routing strategy priority 3, forwarding port is the chip's fourth network port, transmission timeout is 100 milliseconds; The matching process is initiated, starting from the first entry, comparing the first evaluation parameter with the entry parameter range one by one, determining whether the parameter is between the minimum and maximum values ​​of the entry, and terminating the process upon successful matching, reading the corresponding 32 bytes of initial routing strategy information, temporarily storing it in the fast cache 60384 to 60415, recording the entry sequence number and matching time, the overall matching time does not exceed six milliseconds, and the initial routing strategy information acquisition is completed.

[0028] Step 2.2: Based on the initial routing policy information and combined with the load status and health indicators of multiple distributed clients obtained in real time from the fast cache, calculate and select one of the distributed clients as the target client for this request forwarding. Specifically, this includes: reading the initial routing policy information from fast cache 60384 to 60415, parsing out the route priority as 1, the forwarding port as the second network port, and the transmission timeout of 50 milliseconds, thus clarifying the forwarding requirements; then reading the real-time status data of eight distributed clients from fast cache 60416 to 60799. Each client's data occupies 48 bytes and includes two parts: load status and health indicators. The load status includes CPU utilization and memory usage, with values ​​ranging from 0 to 100, and thresholds of 80 and 70, respectively. If both are ≤ the threshold, the load is considered normal. The health metrics include the success rate of the last 100 connections, the number of failures in the last 20 hours, and the current connection status. The thresholds are 90 and 3, respectively. A value of 1 for the current connection status represents normal operation, and a value of 0 represents disconnection. All three criteria must be met for the health status to be considered satisfactory. Example client data read: Client 1 has a CPU utilization of 58%, memory usage of 62%, a success rate of 96% in the last 100 connections, 1 failure in the last 20 hours, and a current connection status of 1; Client 7 has a CPU utilization of 75%, memory usage of 68%, a success rate of 88% in the last 100 connections, 4 failures in the last 20 hours, and a current connection status of 0; Client 8 has a CPU utilization of 89%, memory usage of 72%, a success rate of 92% in the last 100 connections, 2 failures in the last 20 hours, and a current connection status of 1. First, a health screening is performed. Client 7 is excluded because its success rate is below 90% and its number of failures exceeds 3. Client 8 is excluded because its CPU and memory usage exceed the thresholds. The remaining 6 clients are considered healthy. If all are unsatisfactory, the data is reread and screened again. If all are still unsatisfactory, the client with the fewest failures is selected as a backup. Next, load screening is performed on qualified clients. The average load is calculated and selected as the minimum among all qualified clients. If there is only one client with normal load, it is selected directly. If all qualified clients have excessively high load, the client with the smallest average load is selected. After selection, the client number 1 and network address 192.168.0.105 are read and temporarily stored in the fast cache from 60800 to 60815. Six clients with qualified health and five clients with normal load are recorded. The entire screening takes 6 milliseconds, not exceeding 8 milliseconds, and the selection of target clients is completed.

[0029] Step 2.3, in response to the selection of the target client, generates a globally unique connection identifier in memory for the upcoming communication connection and creates a routing context containing the target client's network address, the selected routing policy, and the first evaluation parameters. Specifically, this includes: in response to the target client selection operation, initiating the globally unique connection identifier generation process. This identifier is a 20-digit four-digit hexadecimal value, composed of three parts: the first eight bits are the chip's inherent identifier 1A2B3C4D, and the middle eight bits are a hexadecimal value converted from a millisecond-level timestamp; reading the local millisecond-level timestamp 20260205154030123, converting it to an eight-digit hexadecimal value 1A3B5C7D, generating an eight-digit random hexadecimal value 9E8F0A1B, and concatenating the three parts to form the connection identifier 1A2B3C4D1A3B5C7D9E8F0A1B, then querying... The system queries nearly 5,000 generated identifiers in memory for uniqueness verification. After successful verification, these identifiers are converted into 32-bit binary data and stored in temporary connection identifier storage addresses 30089 to 30092. This generation process takes 2 milliseconds, not exceeding 3 milliseconds. Next, a routing context is created. This context occupies 64 bytes and contains four parts: a 16-byte target client IPv4 network address, 32 bytes of initial routing policy information, 4 bytes of first evaluation parameters, and a 12-byte connection identifier generation timestamp. The above four parts of data are organized and concatenated in order. After completing the integrity verification, the data is written to the routing context storage area 30093 to 30156. At the same time, the connection identifier storage addresses 30089-30092 and the routing context storage addresses 30093 to 30156 are recorded in the association table. The entire process takes 4 milliseconds, not exceeding 5 milliseconds, and the routing context creation is completed.

[0030] Step 2.4: Perform a second-level stability assessment on the routing context. This assessment includes a comprehensive analysis based on the target client's historical connection success rate, current network round-trip latency, and the inherent reliability of the routing policy to obtain a second assessment parameter. Specifically, this includes: reading the complete routing context from routing context storage areas 30093 to 30156, parsing the target client's network address, initial routing policy, and the first assessment parameter 0.95; initiating the second-level stability assessment process; and generating the second assessment parameter based on three items. This parameter is an 80-bit integer, ranging from 0 to 100, with higher values ​​indicating higher stability. The first item is the target client's historical connection success rate assessment, reading nearly 1000 connection records from client 1 from historical connection record storage areas 40001 to 45000, counting 930 successful connections, and calculating a success rate of 93%. This success rate serves as the base value for this item; if the number of connections is less than 1000, the actual number is used. The second item is the current network round-trip latency assessment, sending a 60-byte test data packet to client 1 through the chip's first network port. If a response data packet is received within 40 milliseconds, calculate the difference between the sending time (154030123 milliseconds) and the receiving time (154030163 milliseconds). The round-trip delay is 40 milliseconds. The round-trip delay evaluation value is 100 minus the round-trip delay divided by two, with a value ranging from 0 to 100. The third item is the inherent reliability evaluation of the routing policy. The base value for a high-reliability routing policy is 95. This policy has experienced 2 failures in the last 500 uses. One point is deducted for each failure, and the adjusted inherent reliability evaluation value is 93. If the number of failures exceeds 15, the lowest reliability evaluation value is determined. The lowest value is 70. After the three evaluations are completed, the historical connection success rate (weight 40), the current network round-trip delay evaluation value (weight 30), and the inherent reliability evaluation value of the routing policy (weight 30) are calculated according to their weights. After generation, the validity is verified to confirm that 89 is between 0 and 100. After the verification is passed, the data is written to the dedicated evaluation parameter storage area 30158 to 30165. At the same time, the original evaluation data and calculation results are written to 30166 to 30205. The entire evaluation process takes 12 milliseconds, not exceeding 15 milliseconds, to complete the generation of the second evaluation parameter.

[0031] In this embodiment of the invention, by employing a technical approach that involves matching a routing decision mapping table based on first evaluation parameters to obtain the corresponding initial routing strategy, selecting the target client by combining the real-time load status and health indicators of the distributed client, generating a globally unique connection identifier and creating a routing context containing the target client's network address, routing strategy, and first evaluation parameters, and then performing a second-level stability evaluation on the routing context based on the target client's historical connection success rate, network round-trip latency, and the inherent reliability of the routing strategy to obtain the second evaluation parameters, the invention overcomes the technical problems of traditional routing decisions relying on fixed configurations, failing to combine request trust levels and real-time client status for dynamic routing selection, resulting in unbalanced route allocation, incomplete context information, and a lack of quantitative evaluation of connection stability. This leads to low routing matching accuracy, poor communication connection reliability, and an inability to provide stable parameter basis for optimization. Consequently, the invention improves the rationality and accuracy of routing decisions and target client selection, balances the load of distributed clients, constructs a complete and reliable routing context, and quantifies the routing stability evaluation parameters.

[0032] In a preferred embodiment of the present invention, step 3 above may include: Step 3.1: Assemble the connection identifier, routing context, and second evaluation parameters according to the preset signaling format and encapsulate them to generate a control signaling data packet. Specifically, this includes: first, reading the connection identifier data from the corresponding storage area in memory. The connection identifier is stored in a dedicated connection identifier storage area in the chip memory. This storage area starts at physical address 30089 and ends at physical address 30092, occupying four consecutive bytes of storage space. Read all four bytes of connection identifier data one byte at a time. After reading, temporarily store the data in the built-in first-level operation cache area. Then, complete routing context data is read from the routing context storage area. The routing context storage area starts at physical address 30093 and ends at physical address 30156, occupying 64 consecutive bytes of storage space. During the reading process, the continuity of the 64 bytes of data is simultaneously checked. The check process takes no more than two milliseconds to ensure that the routing context data is not missing or disordered. After the check passes, the routing context data is temporarily stored in the subsequent free storage unit of the kernel-level operation cache. Next, the second evaluation parameter is read from the dedicated evaluation parameter storage area. The second evaluation parameter is stored in a continuous eight-byte storage space from physical address 30158 to physical address 30165. After reading, it is directly merged into the data queue to be assembled in the kernel-level operation cache. The three types of data are arranged in order according to the preset control signaling standard format. The order of arrangement is: connection identifier first, then routing context, and finally the second evaluation parameter. After the data is arranged, a 16-byte signaling header is added to the header of the signaling data packet. The signaling header information includes The chip communication identifier field and data packet length identifier field are fixed. The chip communication identifier field occupies eight bytes and its value is a unique communication identification value fixed at the chip factory. The data packet length identifier field occupies eight bytes and is used to record the total number of bytes in the entire control signaling data packet. Four bytes of integrity verification data are fixedly added to the end of the signaling data packet. This verification data is generated by hardware verification logic through unified calculation of the signaling header and core business data. The verification logic takes no more than one millisecond to run. After all data splicing and verification field addition are completed, the total length of the final generated control signaling data packet is fixed at 92 bytes. The encapsulated control signaling data packet is written into the transmit buffer area of ​​the chip memory. The transmit buffer area starts at physical address 40010 and ends at physical address 40101. It is specifically used to temporarily store control data packets to be sent. The entire assembly and encapsulation process of the control signaling data packet takes no more than five milliseconds. After encapsulation, a data packet ready instruction is written to the hardware control register of the chip's first network port, waiting to start the data transmission process.

[0033] Step 3.2: Send the encapsulated control signaling data packet to the selected target client through the chip's first network port. Specifically, this includes: after reading the data packet ready instruction in the hardware control register, immediately starting the initialization configuration process of the first network port. The first network port is the chip's built-in gigabit Ethernet physical communication port, with a fixed port communication rate of 1000 megabits per second and the port working mode set to full-duplex communication mode. The port initialization process is completed within three milliseconds. After initialization, 92 bytes of control signaling data packets are read byte by byte from the chip's memory transmit buffer area. The reading process employs a pipelined transmission method. Each byte of data read is directly transmitted to the physical send buffer of the first network port, with no data waiting delay. The reading and transmission processes are synchronized, with a total time not exceeding four milliseconds. Before sending data, a basic communication handshake verification is performed with the target client. The handshake verification process involves the chip sending a two-byte handshake request signal to the target client through the first network port. The target client must respond with a two-byte handshake response signal within 10 milliseconds. If no valid response signal is received within 10 milliseconds, the chip automatically re-initiates a handshake request. If the second handshake request also fails to receive a valid response, the handshake is considered to have failed, and the handshake failure information is written to the communication error log area in the chip's memory. The starting physical address of this error log area is 50. 010, a single error message occupies 16 bytes of storage space; if the handshake verification is successful, the complete sending process of the control signaling data packet is immediately started. During the data packet sending process, the first network port monitors the data sending status in real time, and records the sending progress once after sending 16 bytes of data. The time taken to send all 92 bytes of data is no more than six milliseconds; after the data is sent, it continuously waits for the target client's reception confirmation signal. The reception confirmation signal is a fixed four-byte length, and the target client must respond within 15 milliseconds. After the chip receives the confirmation signal, it determines that the control signaling data packet has been sent successfully, and writes the successful sending status and sending time information into the communication status record area. The total time taken for the entire data sending process from port initialization to confirmation of reception completion is no more than 30 milliseconds.

[0034] Step 3.3: The control signaling data packet is configured to, upon being received and parsed by the target client, trigger the target client to actively initiate a reverse connection to the chip's first network port based on the connection parameters specified in the routing context contained in the target client. Specifically, after the target client receives the 92-byte control signaling data packet sent by the chip through its own Ethernet communication port, it immediately writes the data packet into a temporary parsing storage area in its local memory. This storage area starts at physical address 60010 and ends at physical address 60100, occupying 92 consecutive bytes of storage space. Subsequently, the client initiates the data packet parsing process through its built-in hardware operation logic, with the parsing time not exceeding eight milliseconds. The parsing process first separates the 16-byte signaling header information from the data packet header and the four-byte checksum data from the tail. The overall integrity of the data packet is verified using the checksum data to confirm no packet loss or tampering. Then, the four-byte connection identifier, 64-byte routing context, and eight-byte second evaluation parameters are extracted sequentially. After extraction, these three types of data are written to their corresponding storage units in local memory. The target client extracts the specified connection parameters from the parsed routing context data using hardware processing logic. These connection parameters include the communication port number, data transmission format, connection timeout, and communication verification mode. The communication port number is fixed at the client's 8888 communication port, the data transmission format is set to the standard Ethernet frame format, the connection timeout is set to 50 milliseconds, and the communication verification mode uses a hardware-level byte-by-byte verification mode. After extracting all connection parameters, the target client immediately initiates the reverse connection establishment process through the Ethernet communication port, actively sending a connection request to the first network port of the AI ​​acceleration chip. The connection request data packet is a fixed 16-byte length, including the client's own... The network address and the extracted connection identifier are used by the chip for identity and connection matching verification. After the target client initiates a connection request, it continuously waits for the chip's connection response signal. The response waiting time strictly follows the 50-millisecond timeout threshold. If a connection allow signal is received from the chip within 50 milliseconds, the client immediately completes the reverse connection link establishment and communication parameter synchronization. After the reverse connection is established, it maintains a long connection state until the inference data transmission is completed. If no valid response signal is received from the chip within 50 milliseconds, the client automatically re-initiates a connection request. If the second request also times out, the reverse connection establishment is determined to have failed. The client writes the connection failure information and the parsed key parameters into the local operation log storage area, and simultaneously sends a 16-byte connection failure notification data packet to the chip. The client continuously listens for the target client's reverse connection request through the first network port. The listening state is maintained for 60 milliseconds. Upon receiving a valid connection request, the client immediately reads the connection identifier and routing context and performs matching verification. After successful verification, a four-byte connection allow signal is sent to the target client, completing the reverse connection establishment process.

[0035] In this embodiment of the invention, because a control signaling data packet is generated by assembling and encapsulating the connection identifier, routing context, and second evaluation parameters according to a preset signaling format, and then sending it to the selected target client through the chip's first network port, and configuring the control signaling data packet to trigger the target client to parse it and actively initiate a reverse connection to the chip's first network port according to the connection parameters specified by the routing context, this invention overcomes the technical problems of non-standard connection establishment command format, incomplete parameters, passive connection initiation method, and lack of linkage with the aforementioned routing stability evaluation parameters in traditional technologies. These problems result in low connection establishment efficiency, parameter mismatch, poor connection stability, and inability to guarantee the coordination between connection establishment, routing strategy, and stability evaluation. This invention achieves standardized control signaling transmission format, ensures complete and accurate transmission of connection-related parameters, efficiently triggers the target client to initiate a reverse connection, improves the success rate and stability of connection establishment, and realizes close linkage between the connection establishment process and the aforementioned routing decision and stability evaluation.

[0036] In a preferred embodiment of the present invention, step 4 above may include: Step 4.1: When an external connection request is received through the chip's first network port, verify whether the connection request is a reverse connection initiated by the target client. Extract the connection identification information carried in the protocol message of the verified reverse connection. Specifically, this includes: continuously monitoring external access connection requests through the first network port, maintaining the monitoring state for a fixed duration of 60 milliseconds; during the monitoring process, reading the access message data in the first network port's receive buffer frame by frame, with the receive buffer starting at physical address 40102 and ending at physical address 40201, occupying 100 consecutive bytes of storage space; when a valid external connection request message is detected, immediately read the entire connection request message into the secondary temporary buffer area. The cache area starts at physical address 30206 and ends at physical address 30305, occupying 100 consecutive bytes of storage space. First, the connection request message is verified for its source by reading the target client network address information carried in the message. This address information is then compared byte by byte with the target client network address temporarily stored in memory, which is located in the storage space between physical addresses 60800 and 60815. The comparison process is executed sequentially starting from the first byte, with each byte comparison taking no more than 0.1 milliseconds and the overall comparison taking no more than two milliseconds. After the byte-by-byte comparison is completed, a multidimensional Manhattan distance geometric matching algorithm is introduced for secondary verification to improve the accuracy and anti-interference ability of the source verification. The specific execution process is as follows: The 16 bytes of data from the target client's network address extracted from the message are used as one-dimensional coordinates, constructing a 16-dimensional geometric vector, denoted as vector M. Each dimension of this vector has a coordinate value ranging from 0 to 255. Simultaneously, another 16-dimensional geometric vector, denoted as vector N, is constructed from the 16 bytes of data from the target client's network address temporarily stored in memory, following the same rules. The Manhattan distance geometric algorithm is then activated to calculate the absolute difference between the corresponding coordinate values ​​of vector M and vector N dimension by dimension. The absolute differences of all dimensions are then summed to obtain the total Manhattan distance between the two 16-dimensional vectors. This total distance ranges from 0 to 4095, where a total distance of 0 represents complete overlap and identical address information, and a smaller total distance indicates higher similarity between the two sets of address information. A valid Manhattan distance threshold of 3 is set. If the calculated total Manhattan distance is less than or equal to 3, the geometric algorithm verification is considered successful, further confirming the consistency of the two sets of address information. If the total Manhattan distance is greater than 3, the geometric algorithm verification is considered unsuccessful, and the connection request source is directly deemed invalid.The geometric algorithm is executed in a dedicated geometric operation cache area, starting at physical address 30310 and ending at physical address 30325, occupying 16 consecutive bytes of storage space. The calculation time for each dimension's coordinate difference is no more than 0.05 milliseconds, and the total calculation time for the Manhattan distance of the entire 16-dimensional vector is no more than 0.8 milliseconds. After merging with the previous byte-by-byte comparison process, the overall source verification time is still no more than 2 milliseconds. If the comparison matches and the geometric algorithm verification passes, the connection request is determined to be a pre-triggered reverse connection initiated by the target client; if the comparison does not match, or If the geometric algorithm verification fails, the current connection request message is discarded and the invalid connection request information is written to the communication error log area, which starts at physical address 50010. Each invalid request message occupies 16 bytes of storage space. If the verification passes, the protocol message of the reverse connection is parsed. The parsing process starts from the beginning of the message, and the message header and check field are stripped off in sequence to locate the connection identification information carried in the core data segment of the message. This connection identification information occupies a fixed four bytes of storage space. The four-byte connection identification information is extracted one byte at a time.

[0037] Step 4.2 involves matching and associating the connection identifier information with the temporary connection identifier and corresponding original request context stored in memory. Based on the successful association, a data forwarding channel corresponding to this communication is registered and activated in the chip's network protocol stack. This specifically includes: reading the extracted connection identifier information from the dedicated identifier comparison cache area, and simultaneously reading the temporary original request context and corresponding connection identifier from the request context storage area in memory. The original request context storage area starts at physical address 30310 and ends at physical address 30469, occupying 160 consecutive bytes of storage space. Each original request context in this area... Each connection is bound to a unique connection identifier. A connection identifier matching process is initiated, performing a byte-by-byte comparison between the extracted connection identifier and the connection identifier bound in the request context storage area. The comparison order follows the storage order of the original request context. The comparison status is recorded after each identifier comparison is completed, and the comparison process takes no more than five milliseconds. When a completely matching connection identifier is detected, the comparison process is immediately terminated, indicating a successful match. If no matching identifier is found, the match is considered a failure, and the failure information is written to the communication status record area, and the current reverse connection link is closed. After a successful match, the extracted connection identifier is compared with the corresponding original request context. The connection binding operation is completed through the chip's memory address mapping logic. A fixed mapping relationship is established between the physical storage address of the connection identifier and the physical storage address of the original request context. This mapping relationship is recorded in the memory's association mapping table area. This mapping table area starts at physical address 30470 and ends at physical address 30569, occupying 100 consecutive bytes of storage space. The binding operation takes no more than three milliseconds. After the connection binding is completed, a data forwarding channel registration operation is performed in the dedicated channel registration area of ​​the chip's network protocol stack. The network protocol stack channel registration area starts at physical address 30570 and ends at physical address 30669, occupying 100 consecutive bytes of storage space. The registration process involves 100 bytes of storage space. The registration content includes the connection identifier, the target client network address, the core parameters of the original request context, and the reverse connection link parameters. After registration, a channel activation command is sent to the network protocol stack. The activation command is written to the protocol stack control register, which has a physical address of 30670 and occupies four bytes of storage space. Upon receiving the activation command, the network protocol stack immediately enables the data forwarding channel, sets the channel status to normal working state, and marks the channel as a dedicated inference data forwarding channel, prohibiting other unrelated data from accessing it. The entire registration and activation process takes no more than eight milliseconds. After activation, a channel ready status flag is generated.

[0038] Step 4.3: Perform a third-level transmission efficiency evaluation on the data forwarding channel. The evaluation includes measuring the network round-trip delay, effective bandwidth, and data packet success rate of the data forwarding channel within a preset test period. Based on the measurement results, generate third evaluation parameters to quantify the current link transmission efficiency. Specifically, after the data forwarding channel is activated, immediately initiate the third-level transmission efficiency evaluation. The evaluation is performed within a preset fixed test period of 50 milliseconds. The evaluation process only targets the currently activated data forwarding channel and does not affect the normal operation of other communication links on the chip. First, a fixed-length test data packet (64 bytes) is sent to the target client. The data packet is transmitted through the activated data forwarding channel. After sending, timing begins with millisecond precision. Within the 50-millisecond test period, three consecutive network round-trip delay measurements are performed. Each measurement records the time of sending the test data packet and the time of receiving the response data packet. The difference between the two times is calculated to obtain the single network round-trip delay value. After three measurements, the average value is taken as the network round-trip delay result of the current data forwarding channel. The total measurement time does not exceed 15 milliseconds. At the same time, the actual total data transmission volume of the forwarding channel is statistically analyzed during the test period. Combined with the test period duration, the effective bandwidth value of the current channel is calculated. The effective bandwidth unit is megabits per second. Invalid data and verification error data are removed in real time during the measurement to ensure the accuracy of the bandwidth value. During the test period, the total number of all transmitted data packets and the number of successfully transmitted data packets are counted. After removing lost and erroneous data packets, the data packet success rate is calculated. The total number of data packets transmitted during the test period is not less than 100 to ensure that the transmission rate statistics are meaningful. The effective thresholds for network round-trip latency are no more than 50 milliseconds, effective bandwidth is no less than 800 megabits per second, and data packet success rate is no less than 99%. If all three measurements meet their respective thresholds, the transmission efficiency is judged to be of excellent level. If any one of them fails to meet the threshold, the corresponding efficiency level is determined based on the actual value. Combining the three measurement results of network round-trip latency, effective bandwidth, and data packet success rate, a third evaluation parameter is generated through hardware calculation logic. The third evaluation parameter is a fixed eight-byte value, ranging from 0 to 100. The larger the value, the higher the transmission efficiency of the current data forwarding channel. After the evaluation parameter is generated, the third evaluation parameter is written to a dedicated evaluation parameter storage area. The starting physical address of this storage area is 30671, and the ending physical address is 30678. At the same time, the original data of the three measurements and the evaluation level information are written to the evaluation auxiliary storage area. The starting physical address of this area is 30679, and the ending physical address is 30728, occupying 50 consecutive bytes of storage space. The entire process of the third-level transmission efficiency evaluation and the generation of the third evaluation parameter takes no more than 20 milliseconds. After the evaluation is completed, an evaluation completion status flag is generated.

[0039] In this embodiment of the invention, by employing technical means to verify the legality of the received external connection request, extract the connection identifier from the verified protocol message, and match and bind it with the connection identifier temporarily stored in memory and the original request context, thereby registering and activating the corresponding data forwarding channel in the chip network protocol stack, and simultaneously measuring the network round-trip delay, effective bandwidth, and data packet success rate of the data forwarding channel to generate a third evaluation parameter for quantifying transmission efficiency, this invention overcomes the technical problems of traditional solutions, such as the lack of legality verification for reverse connections leading to illegal access, the lack of association between the connection identifier and the request context causing data forwarding channel chaos, the inability to quantify the efficiency of the actual transmission link leading to uncontrollable transmission quality, and the lack of transmission dimension support for memory optimization. This achieves the goal of ensuring the legality and security of the reverse connection, realizing the precise binding of the request context and the data forwarding channel, avoiding data forwarding errors, and simultaneously quantifying the transmission efficiency evaluation parameters.

[0040] In a preferred embodiment of the present invention, step 5 above may include: Step 5.1: Using the first, second, and third evaluation parameters as basic input vectors, construct a multi-dimensional evaluation framework in memory. Perform a uniform partitioning operation on the multi-dimensional evaluation framework according to preset rules, dividing the entire parameter space into multiple non-overlapping evaluation sub-regions. Specifically, this includes: sequentially reading the first, second, and third evaluation parameters from a dedicated evaluation parameter storage area. The first evaluation parameter is stored in a four-byte storage space starting at physical address 30000 and ending at physical address 30003; the second evaluation parameter is stored in an eight-byte storage space starting at physical address 30158 and ending at physical address 30165; and the third evaluation parameter is stored in an eight-byte storage space starting at physical address 30671 and ending at physical address 30678. Using the three sets of evaluation parameters as independent dimension inputs, construct a three-dimensional evaluation framework in a dedicated data processing area of ​​the chip memory. This data processing area starts at physical address 30729 and ends at physical address 31228, occupying 500 consecutive bytes of storage space. Each dimension of the three-dimensional evaluation framework... The value range is fixed at 0 to 100, and the framework covers the value space of all valid evaluation parameters. The three-dimensional evaluation framework is partitioned according to the preset uniform partitioning rules. Each dimension is divided into four consecutive equal-length intervals according to the numerical value. The four intervals correspond to the numerical ranges of 0 to 25, 25 to 55, 55 to 75, and 75 to 100, respectively. After the three dimensions are divided into four equal parts, the entire three-dimensional evaluation framework is divided into 64 non-overlapping evaluation sub-regions of the same size. Each evaluation sub-region has a fixed dimensional interval range and an independent region number. The interval boundary region number and spatial coordinates of the 64 evaluation sub-regions are written into the partition information storage area. The storage area starts at physical address 31229 and ends at physical address 31828, occupying 600 consecutive bytes of storage space. The continuity and non-overlap of the sub-regions are checked in real time during the partitioning process. The check process takes no more than three milliseconds. The total time for the construction of the multi-dimensional evaluation framework and the uniform partitioning operation does not exceed eight milliseconds. After the partitioning is completed, a framework partitioning completion status mark is generated.

[0041] Step 5.2: Based on the evaluation sub-regions, calculate the statistical distribution characteristics of historical and current evaluation parameter points falling within each sub-region, and quantify the data aggregation degree of each sub-region; analyze the continuity of parameter distribution on the boundaries of adjacent evaluation sub-regions, calculate the correlation and distance between the center point vectors of adjacent sub-regions, and quantify the partition boundary correlation. Specifically, this includes: reading the interval range and coordinate information of 64 evaluation sub-regions from the partition information storage area, and reading nearly two thousand sets of historical evaluation parameter data from the historical evaluation data storage area (starting physical address 31829, ending physical address 33828, occupying two thousand bytes of continuous storage space); then reading the current three sets of real-time evaluation parameter data, matching all parameter data one by one to the corresponding evaluation sub-regions, and counting the total number of parameter points contained in each evaluation sub-region; performing data aggregation degree calculation for each evaluation sub-region, using the ratio of the number of parameter points in the sub-region to the theoretical maximum carrying capacity of the sub-region as the aggregation degree quantification result. The data aggregation degree value is fixed between 0 and one. The denser the parameter point distribution, the higher the aggregation degree value. When the number of parameter points in the sub-region exceeds 20, the aggregation degree value is not lower than 0. 7. When the number of parameter points in a sub-region is less than five, the aggregation degree value should not exceed 0.3. The data aggregation degree of each evaluation sub-region is written to the regional statistics storage area, which starts at physical address 33829 and ends at physical address 34428, occupying 600 consecutive bytes of storage space. The aggregation degree data of a single region occupies 8 bytes of storage space. The entire aggregation degree calculation and storage process takes no more than 10 milliseconds. After completing the data aggregation degree calculation, the continuity of the boundary parameter distribution of each pair of adjacent evaluation sub-regions is analyzed in turn. The center point vector coordinates of the two adjacent sub-regions are extracted, and the center point vector coordinates of the two groups of centers are calculated. The linear distance between quantities is correlated with the numerical correlation. The correlation value is fixed between 0 and 1. The smaller the distance, the higher the correlation and the stronger the correlation of the partition boundary. The correlation value of the partition boundary is fixed between 0 and 1. All adjacent boundaries of 64 evaluation sub-regions are traversed, and a total of 192 sets of correlation values ​​of adjacent boundaries are calculated. All correlation values ​​are synchronously written to the free cells of the regional statistical storage area. Invalid boundaries with 0 boundary parameter points are removed during the calculation process. The correlation value of the valid boundary is not less than 0.2. The total time of the entire partition boundary correlation quantification calculation process does not exceed 12 milliseconds.

[0042] Step 5.3: Using the data aggregation degree and partition boundary correlation of each partition as joint constraints, construct a target optimization function regarding the ratio of the receive buffer to the fast cache capacity. Perform weighted fitting and solution calculation on the target optimization function to obtain the buffer adjustment value. Specifically, this includes: reading the data aggregation degree and partition boundary correlation values ​​of all evaluation sub-regions, setting joint optimization constraints, with a minimum effective threshold of 0.6 for data aggregation degree and a minimum effective threshold of 0.5 for partition boundary correlation. Only evaluation sub-regions and boundary data that meet both threshold conditions participate in the optimization calculation. Invalid data that does not meet the thresholds are directly removed, and the proportion of valid data retained after removal is not less than 99%. Using the effective data aggregation degree and partition boundary correlation as joint constraints, construct a target optimization function regarding the ratio of the receive buffer to the fast cache capacity in the memory optimization calculation area. The memory optimization calculation area starts at physical address 34429 and ends at physical address 35428, occupying 1000 consecutive bytes of storage space. Perform weighted fitting and solution calculation on the target optimization function through built-in hardware operation logic. The weighted fitting operation assigns a fixed weight of 0.6 to the data aggregation degree and a fixed weight of 0.4 to the partition boundary correlation. During the weighted fitting process, the optimal value of the capacity ratio is calculated iteratively 16 times, with each iteration taking no more than one millisecond. After the iterative fitting is completed, the final solution calculation is performed to obtain the buffer adjustment value used to adjust the buffer capacity. The buffer adjustment value is a 32-bit floating-point value with a fixed range of -0.4 to +0.4. A positive value represents increasing the receiving buffer capacity and decreasing the fast buffer capacity, a negative value represents decreasing the receiving buffer capacity and increasing the fast buffer capacity, and a value of 0 represents keeping the original capacity ratio unchanged. The buffer adjustment value is written to the adjustment result storage area, which starts at physical address 35429 and ends at physical address 35432, occupying four bytes of storage space. Simultaneously, auxiliary data such as the number of iterations for the weighted fitting parameters are written to the optimization calculation auxiliary area. The entire process of constructing the objective optimization function, weighted fitting, and solving the buffer adjustment value takes no more than 15 milliseconds. The objective optimization function is... , For the effective evaluation sub-region numbering of the multidimensional evaluation framework, For the effective adjacent partition boundary numbering, No. The degree of data aggregation in each evaluation sub-region No. The correlation of partition boundaries between adjacent boundaries, Weights are assigned to the degree of data aggregation. Weighting is applied to the correlation between partition boundaries. Adjust the buffer value to be solved. To effectively assess the total number of sub-regions, Total number of valid partition boundaries.

[0043] Step 5.4: Based on the buffer adjustment value, the chip's memory is dynamically adjusted to change the physical capacity allocation ratio of the receive buffer and the fast cache in the chip's memory, completing the reconfiguration. Specifically, this includes: reading the buffer adjustment value from the adjustment result storage area; sending a capacity reconfiguration start instruction to the chip's control register (physical address 35433, occupying four bytes of storage space); immediately entering the capacity adjustment working state upon receiving the instruction; and the initialization verification process taking no more than two milliseconds. The chip's factory default physical capacity ratio of the receive buffer to the fast cache is 5:5, with a fixed total available storage space of 65536 bytes. The receive buffer and the fast cache each occupy 32768 bytes. Dynamic allocation is performed based on the buffer adjustment value. When the buffer adjustment value is +0.4, the capacity ratio of the receive buffer to the fast cache is adjusted to 8:2; when the buffer adjustment value is -0.4, the ratio is adjusted to 2:8. The adjustment process follows the rule that every 0.1 adjustment value corresponds to a 10% capacity change. Capacity allocation is in bytes. The smallest unit ensures that the partitioned storage space addresses are continuous, fragmented, and non-overlapping. The physical address range of the chip memory is re-partitioned, and the start and end physical addresses of the receive buffer and fast cache are updated. The new address information is written to the memory partition configuration register, which starts at physical address 35434 and ends at physical address 35441, occupying eight bytes of storage space. After the address partitioning is completed, a capacity check is performed to verify that the total capacity after reconfiguration is consistent with the original total capacity. At the same time, it is verified that the address boundaries of the two buffers do not overlap or overflow. After the check passes, the new memory partition configuration is locked, and any unauthorized address modification operations are rejected. After the reconfiguration is completed, the updated capacity ratio, address range, reconfiguration time, and other information are written to the memory configuration status area, which starts at physical address 35442 and ends at physical address 35541, occupying 100 bytes of storage space. The total time of the entire dynamic reconfiguration process of the receive buffer and fast cache capacity does not exceed 10 milliseconds. After the reconfiguration is completed, the chip generates a memory partition optimization completion status flag.

[0044] In this embodiment of the invention, a multi-dimensional evaluation framework is constructed based on the first, second, and third evaluation parameters as input vectors and uniformly partitioned. The data aggregation degree and partition boundary correlation of each evaluation sub-region are quantified. This is used as a joint constraint condition to construct the target optimization function for the ratio of the receiving buffer and the fast cache capacity. The buffer adjustment value is obtained by weighted fitting, and then the chip is called to dynamically adjust the physical capacity allocation ratio of the two. Therefore, this invention overcomes the technical problems of traditional chip memory, which lacks a constraint mechanism based on multi-level multi-dimensional evaluation parameters, lacks data distribution and boundary correlation, and has static and rigid capacity allocation. This leads to low memory resource scheduling accuracy, easy partition idleness or bottlenecks, and inability to adapt to real-time service and link status changes. As a result, it achieves fine-grained, dynamic, and adaptive reconfiguration of the chip memory receiving buffer and fast cache capacity, improves the rationality and solution accuracy of the multi-dimensional evaluation framework, maximizes the utilization of on-chip memory resources, and avoids performance bottlenecks caused by capacity imbalance.

[0045] In a preferred embodiment of the present invention, step 6 above may include: Step 6.1: Based on the reconfigured storage capacity ratio of the receive buffer and the fast cache, call the data read interface of the receive buffer. Through the called data read interface, obtain the payload portion of the external inference request data from the receive buffer. Specifically, this includes: first, reading the reconfigured physical address information of the receive buffer from the memory partition configuration register. This register has a starting physical address of 35434 and an ending physical address of 35441, occupying eight consecutive bytes of storage space. Then, read the new starting and ending physical addresses of the receive buffer byte by byte. After reading, perform a validity check on the address information. The verification process includes ensuring address continuity and that the address range is within the total memory storage area of ​​the chip. The verification process takes no more than two milliseconds. If the verification fails, the read operation is immediately terminated, and the address configuration error information is written to the memory configuration status area. This area starts at physical address 35442 and ends at physical address 35541, with each error message occupying 12 bytes of storage space. Based on the verified receive buffer address information, an interface enable command is sent to the control register of the receive buffer data read interface. This control register starts at physical address 35542 and ends at physical address 35545, occupying four consecutive bytes of storage space. After the instruction is written, the data read interface is triggered to enter the working state. The interface initialization time is no more than three milliseconds. After initialization, a ready status signal is sent back. This signal is a single-byte value, where 1 represents ready and 0 represents not ready. After receiving the ready status signal, the actual storage location of the external inference request data in the receive buffer is located through the data read interface. Each piece of external inference request data temporarily stored in the receive buffer is stored in the form of an independent data block. Each data block has a fixed 64-byte request header, followed by the payload of the request data, which is read byte by byte starting from the beginning address of the data block. Upon reaching byte 65, the starting physical address of the payload portion is determined. Simultaneously, the total payload byte count field recorded in the header is read. This field occupies four bytes of storage space and specifies the ending physical address of the payload. The payload data is extracted from the receive buffer via the data read interface in a pipelined transmission manner. The extraction process involves continuous single-byte reading. The read payload data is temporarily stored in the payload temporary buffer area in real time. This buffer area starts at physical address 35556 and ends at physical address 39655, occupying 4100 consecutive bytes of storage space, which can meet the temporary storage requirements of the maximum number of bytes of payload.After extraction, an integrity check is performed on the payload data. The check rules are that the actual number of bytes extracted must be exactly the same as the number of bytes recorded in the message header, and the minimum number of bytes in the payload data must be no less than 10020 bytes and the maximum number of bytes must not exceed 4096 bytes. The check time must not exceed four milliseconds. If the check fails, the payload data is discarded and the incomplete data information is written to the communication error log area. The starting physical address of this area is 50010, and each piece of information occupies 16 bytes of storage space. If the check passes, the temporarily stored payload data is retained, and a payload extraction completion status flag is generated.

[0046] Step 6.2: Through the chip's first network port, the payload portion is forwarded to the target client via the registered and activated data forwarding channel. The inference result data corresponding to the external inference request data returned by the target client is received through the data forwarding channel. Protocol parsing and format verification are performed on the inference result data, and the final inference result that passes verification is output to the chip's designated result processing unit. Specifically, this includes: reading the verified payload data from the payload temporary buffer area, and simultaneously reading the registered and activated data forwarding channel status information from the channel registration area of ​​the network protocol stack. This area starts at physical address 30570 and ends at physical address 30669, occupying 10 consecutive physical addresses. The system uses 0 bytes of storage space to verify that the current status of the data forwarding channel is active. The status field is a single-byte value, where 1 represents active and 0 represents inactive. After successful verification, the payload data is bound to the link parameters of the data forwarding channel. The binding process involves writing the channel identifier into the transmission prefix field of the payload data. This field occupies eight bytes of storage space, and the binding time is no more than two milliseconds. The payload data with the bound channel identifier is then encapsulated into a standard transmission data packet. A 32-byte transmission protocol header is added to the packet header, containing information such as the target client network address, data forwarding channel identifier, and packet length. Four bytes of transmission checksum data are added to the packet tail. The encapsulated transmission data... The total packet size is calculated as the payload size plus 36 bytes. The encapsulated data packet is written into the send buffer of the first network port. This buffer starts at physical address 40010 and ends at physical address 40101, occupying 92 consecutive bytes of storage space. The writing process uses a byte-by-byte overwrite method, with a writing time of no more than five milliseconds. The first network port reads the data packet byte by byte from the send buffer and forwards it to the target client via the activated data forwarding channel. During forwarding, the transmission status is monitored in real time, and the transmission progress is recorded every 250 bytes of data sent. The entire forwarding process takes no more than 20 milliseconds. If the forwarding times out, a retransmission operation is automatically initiated. The timeout threshold is 50 milliseconds. If retransmission fails, the data forwarding failure information is written to the communication status record area. If forwarding is successful, a data forwarding completion status flag is generated. The inference result data returned by the target client is continuously monitored through the receiving buffer area of ​​the first network port. The starting physical address of this receiving buffer area is 40102 and the ending physical address is 40201. It occupies 100 consecutive bytes of storage space and the monitoring time is 100 milliseconds. After the inference result data is detected, the first network port reads the data completely into the inference result temporary cache area. The starting physical address of this area is 39658 and the ending physical address is 43757. It occupies 4100 consecutive bytes of storage space and the reading time does not exceed four milliseconds.The cached inference result data undergoes protocol parsing. Starting from the beginning of the data packet, the 32-byte transport protocol header and 4-byte transport checksum are sequentially stripped to extract the core inference result raw data. During parsing, all redundant protocol-related fields are removed, retaining only the valid inference result content. The parsing time does not exceed three milliseconds. After parsing, the raw inference result data undergoes format verification. Verification includes eight-byte alignment verification, data field integrity verification, and data encoding format compliance verification. The encoding format must conform to the chip's preset binary encoding rules. The passing threshold for format verification is that all verification items pass. If any verification fails, the inference result data is deemed invalid, and invalid data information is written to the communication error log area. The system simultaneously sends a data retransmission request to the target client; if all verification items pass, the final inference result data is determined; the verified final inference result data is output byte by byte to the designated result processing unit via the chip's dedicated data transmission bus. The physical data interface of the result processing unit starts at physical address 43758 and ends at physical address 43765, occupying eight consecutive bytes of storage space. The data output process is synchronous transmission at a rate of 156 bytes per millisecond. After the output is completed, the receive confirmation signal from the result processing unit is read. This signal is a single-byte value, where 1 indicates reception completion and 0 indicates reception error. Upon receiving the reception completion signal, the status information of the inference result output completion is written to the chip's global status register.

[0047] In this embodiment of the invention, by employing a technique that uses the ratio of the reconfigured receive buffer and fast cache storage capacity to call the data reading interface to obtain the inference request payload, and then forwards the payload to the target client via the chip's first network port and the activated data forwarding channel, and performs protocol parsing and format verification on the inference result data returned by the client, and finally outputs the verified final inference result to the designated result processing unit, the technical problems of traditional solutions, such as failure to adapt to dynamically optimized memory space for data reading and forwarding, chaotic data transmission paths, lack of inference result verification mechanisms, resulting in low data forwarding efficiency, insufficient result reliability, and incomplete inference business processing flow, are overcome. This achieves the technical effect of adapting the data reading and forwarding process to memory optimization configuration, realizing accurate targeted transmission of the payload, ensuring the accuracy and standardization of inference results, forming a complete and reliable closed loop for inference request processing and result output, and improving the execution efficiency and stability of distributed inference business.

[0048] like Figure 2 As shown, embodiments of the present invention also provide a data storage optimization system in chip memory, comprising: The extraction module is used to temporarily store external inference request data into the receiving buffer of the chip memory and extract the authentication identifier, and perform a first-level integrity assessment based on the authentication identifier to obtain the first assessment parameters. The selected module is used to match the corresponding routing decision information in the fast cache of memory according to the first evaluation parameters, so as to select the target client from multiple distributed clients, and generate connection identifier and routing context in memory, and perform a second-level stability evaluation on the routing context to obtain the second evaluation parameters. The encapsulation module is used to encapsulate control signaling based on connection identifier, routing context and second evaluation parameters, and send it to the target client through the chip's first network port to trigger the establishment of a reverse connection to the chip; The binding module is used to associate and bind the connection identifier with the original request context temporarily stored in memory when a reverse connection is received, so as to obtain a data forwarding channel. The data forwarding channel performs a third-level transmission efficiency evaluation to obtain the third evaluation parameters. The calculation module is used to construct a multidimensional framework using the first, second, and third evaluation parameters, and to uniformly partition the framework. Using the data aggregation degree and the correlation of partition boundaries as optimization constraints, the module performs weighted fitting and final solution on the partition data within the multidimensional framework to obtain the buffer adjustment value of the chip memory. Based on the buffer adjustment value, the capacity ratio of the receive buffer and the fast cache is reconfigured. The processing module is used to forward the request data in the receive buffer to the target client through the chip's first network port based on the reconfigured storage capacity ratio, and to process the returned inference results.

[0049] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for optimizing data storage in chip memory, characterized in that, The method includes: The external inference request data is temporarily stored in the chip memory's receive buffer and the authentication identifier is extracted. Based on the authentication identifier, the first-level integrity assessment is performed to obtain the first assessment parameters. Based on the first evaluation parameters, the corresponding routing decision information is matched in the fast cache of memory to select the target client from multiple distributed clients, and a connection identifier and routing context are generated in memory. The second-level stability evaluation is performed on the routing context to obtain the second evaluation parameters. The control signaling is encapsulated based on the connection identifier, routing context, and second evaluation parameters, and sent to the target client through the chip's first network port to trigger the establishment of a reverse connection to the chip; Upon receiving a reverse connection, the connection identifier is associated and bound with the original request context temporarily stored in memory to obtain a data forwarding channel. The data forwarding channel performs a third-level transmission efficiency evaluation to obtain the third evaluation parameters. A multidimensional framework is constructed using the first, second, and third evaluation parameters, and the framework is uniformly partitioned. The data aggregation degree and the correlation of partition boundaries in each partition are used as optimization constraints. The partition data within the multidimensional framework are weighted and finally solved to obtain the buffer adjustment value of the chip memory. Based on the buffer adjustment value, the capacity ratio of the receive buffer and the fast cache is reconfigured. Based on the reconfigured storage capacity ratio, the request data in the receive buffer is forwarded to the target client through the chip's first network port, and the returned inference results are processed.

2. The data storage optimization method in chip memory according to claim 1, characterized in that, The external inference request data is temporarily stored in the chip's memory receive buffer, and the authentication identifier is extracted. Based on the authentication identifier, a first-level integrity assessment is performed to obtain the first assessment parameters, including: In the receive buffer, the message header of the external inference request data is parsed to extract the authentication identifier; the authentication identifier includes at least the request sequence number, digital signature, and timestamp. Based on the extracted digital signature, the signature verification operation is performed through the root certificate pre-installed in the chip's secure storage area to obtain the signature verification result; Based on the extracted timestamp, the timestamp is compared with the chip's local clock to determine whether the external inference request data is within the preset valid time window, thus obtaining the timeliness verification result. Based on the extracted request sequence number, the historical record cache in memory is queried to determine whether the sequence number is valid and has not been reused, and the sequence uniqueness verification result is obtained. The signature verification result, timeliness verification result, and sequence uniqueness verification result are combined and calculated using a preset weighted decision algorithm to generate the first evaluation parameter used to quantify the legality and integrity level of the requested data.

3. The data storage optimization method in chip memory according to claim 2, characterized in that, Based on the first evaluation parameters, the corresponding routing decision information is matched in the fast cache of memory to select the target client from multiple distributed clients. A connection identifier and routing context are generated in memory, and a second-level stability evaluation is performed on the routing context to obtain the second evaluation parameters, including: Based on the first evaluation parameters, the system queries and matches the preset routing decision mapping table in the fast cache of memory to obtain the initial routing policy information corresponding to the legality and integrity level of the current request. Based on the initial routing policy information, and combined with the load status and health indicators of multiple distributed clients obtained in real time from the fast cache, one of the multiple distributed clients is calculated and selected as the target client for this request forwarding; In response to the selection of a target client, a globally unique connection identifier is generated in memory for the communication connection to be established, and a routing context containing the network address of the target client, the selected routing policy, and the first evaluation parameter is created. A second-level stability assessment is performed on the routing context. The assessment includes at least a comprehensive analysis based on the target client's historical connection success rate, current network round-trip latency, and the inherent reliability of the routing policy, to obtain the second assessment parameters.

4. The data storage optimization method in chip memory according to claim 3, characterized in that, Control signaling is encapsulated based on the connection identifier, routing context, and second evaluation parameters, and sent to the target client through the chip's first network port to trigger the establishment of a reverse connection to the chip, including: The connection identifier, routing context, and second evaluation parameters are assembled according to a preset signaling format and encapsulated to generate a control signaling data packet; The encapsulated control signaling data packet is sent to the selected target client through the chip's first network port; The control signaling data packet is configured to, upon being received and parsed by the target client, trigger the target client to actively initiate a reverse connection to the chip's first network port based on the connection parameters specified in the routing context contained in the target client.

5. The data storage optimization method in chip memory according to claim 4, characterized in that, Upon receiving a reverse connection, the connection identifier is associated and bound with the original request context temporarily stored in memory to obtain a data forwarding channel. The data forwarding channel performs a third-level transmission efficiency evaluation to obtain third evaluation parameters, including: When an external connection request is received through the chip's first network port, it verifies whether the connection request is a reverse connection initiated by the target client and extracts the connection identification information carried in the protocol message of the verified reverse connection. The connection identification information is matched and associated with the connection identification and the corresponding original request context temporarily stored in memory. Based on the successful association and binding, a data forwarding channel corresponding to this communication is registered and activated in the chip's network protocol stack. A third-level transmission efficiency assessment is performed on the data forwarding channel. The assessment includes measuring the network round-trip delay, effective bandwidth, and data packet success rate of the data forwarding channel within a preset test period, and generating a third assessment parameter based on the measurement results to quantitatively characterize the current link transmission efficiency.

6. The data storage optimization method in chip memory according to claim 5, characterized in that, A multidimensional framework is constructed using the first, second, and third evaluation parameters, and the framework is uniformly partitioned. The data aggregation degree and the correlation of partition boundaries in each partition are used as optimization constraints. The partition data within the multidimensional framework are weighted and fitted, and finally solved to obtain the buffer adjustment value of the chip memory. Based on the buffer adjustment value, reconfigure the capacity ratio of the receive buffer to the fast buffer, including: Using the first evaluation parameter, the second evaluation parameter, and the third evaluation parameter as the basic input vector, a multidimensional evaluation framework is constructed in memory; the multidimensional evaluation framework is then subjected to a uniform partitioning operation with preset rules, dividing the entire parameter space into multiple non-overlapping evaluation sub-regions; Based on the evaluation sub-regions, the statistical distribution characteristics of historical and current evaluation parameter points falling into each sub-region are calculated, and the data aggregation degree of each sub-region is quantified. The continuity of parameter distribution on the boundary of each adjacent evaluation sub-region is analyzed, and the correlation and distance between the center point vectors of adjacent sub-regions are calculated, and the correlation of the partition boundary is quantified. Using the data aggregation degree and partition boundary correlation of each partition as joint constraints, an objective optimization function is constructed regarding the ratio of the capacity of the receive buffer and the fast buffer. The buffer adjustment value is obtained by weighted fitting and solving the objective optimization function. Based on the buffer adjustment value, the chip is invoked to dynamically adjust the physical capacity allocation ratio of the receive buffer and the fast cache in the chip's memory, thus completing the reconfiguration.

7. The data storage optimization method in chip memory according to claim 6, characterized in that, Based on the reconfigured storage capacity ratio, the request data in the receive buffer is forwarded to the target client via the chip's first network port, and the returned inference results are processed, including: Based on the reconfigured storage capacity ratio of the receive buffer and the fast cache, the data read interface of the receive buffer is called; through the called data read interface, the payload portion of the external inference request data is obtained from the receive buffer. The payload portion is forwarded to the target client via the registered and activated data forwarding channel through the chip's first network port. The inference result data corresponding to the external inference request data returned by the target client is received through the data forwarding channel. The inference result data is parsed and format verified, and the final inference result that passes the verification is output to the result processing unit designated by the chip.

8. A data storage optimization system in chip memory, the system implementing the method as described in any one of claims 1 to 7, characterized in that, include: The extraction module is used to temporarily store external inference request data into the receiving buffer of the chip memory and extract the authentication identifier, and perform a first-level integrity assessment based on the authentication identifier to obtain the first assessment parameters. The selected module is used to match the corresponding routing decision information in the fast cache of memory according to the first evaluation parameters, so as to select the target client from multiple distributed clients, and generate connection identifier and routing context in memory, and perform a second-level stability evaluation on the routing context to obtain the second evaluation parameters. The encapsulation module is used to encapsulate control signaling based on connection identifier, routing context and second evaluation parameters, and send it to the target client through the chip's first network port to trigger the establishment of a reverse connection to the chip; The binding module is used to associate and bind the connection identifier with the original request context temporarily stored in memory when a reverse connection is received, so as to obtain a data forwarding channel. The data forwarding channel performs a third-level transmission efficiency evaluation to obtain the third evaluation parameters. The calculation module is used to construct a multidimensional framework using the first, second, and third evaluation parameters, and to uniformly partition the framework. Using the data aggregation degree and the correlation of partition boundaries as optimization constraints, the module performs weighted fitting and final solution on the partition data within the multidimensional framework to obtain the buffer adjustment value of the chip memory. Based on the buffer adjustment value, the capacity ratio of the receive buffer and the fast cache is reconfigured. The processing module is used to forward the request data in the receive buffer to the target client through the chip's first network port based on the reconfigured storage capacity ratio, and to process the returned inference results.

9. A computing device, characterized in that, include: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program that, when executed by a processor, implements the method as described in any one of claims 1 to 7.

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