Core particle verification methods, apparatuses, media, core particles, and computing systems

Abstract

Embodiments of the present disclosure provide a core particle verification method, device, medium, core particle and computing system, relating to the technical field of chips. The core particle verification method can be applied to a verification module, which includes a pre-set verification model and a data acquisition interface connected with a measured module in the core particle. The core particle verification method includes: obtaining a target message communicated by the core particle through the measured module and other core particles, the target message being a message conforming to a general core particle interconnection standard; in a case where the target message meets a pre-set condition, collecting, through the data acquisition interface, algorithm data of a target calibration algorithm executed by the measured module in a link training process; and verifying the target calibration algorithm according to the verification model and the algorithm data, to obtain a verification result of the target calibration algorithm. In this way, the calibration algorithm can be verified, and algorithm logic or parameter errors can be found in time, thereby improving the reliability of core particle verification.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and more specifically, to a chip verification method, apparatus, medium, chip, and computing system. Background Technology

[0002] Universal Chiplet Interconnect Express (UCIe) is an open and unified interconnect protocol for chips, enabling interconnection and communication between chips manufactured by different manufacturers or using different processes. A chip can also be called a die. The UCIe protocol is a layered protocol, which can be divided into, for example, a protocol layer, an adapter layer, and a physical layer.

[0003] In chip design, Verification Intellectual Property (VIP) can be used to verify whether the chip design conforms to specifications and functional requirements of software components. A UCIe VIP specifically designed for UCIe can simulate UCIe protocol-related behaviors, verifying the proper functioning of communication and / or functionality between chips based on the UCIe protocol during chip design and development.

[0004] UCIe VIP solutions typically employ a full-stack VIP architecture, including a protocol layer, an adaptation layer, and a physical layer. In a full-stack VIP architecture, verification of physical layer modules or functions such as scrambling / descrambling, link state machines, and sidebands can be performed based on the inputs and outputs of the physical layer, without needing to concern themselves with the internal implementation of the physical layer. However, as the application scenarios and requirements of chips become increasingly complex, the algorithms implemented at the physical layer also become more intricate. Chips that pass verification based on a full-stack VIP architecture may still exhibit anomalies when running in complex real-world scenarios. Therefore, how to achieve more reliable chip verification in UCIe VIP solutions has become a pressing issue. Summary of the Invention

[0005] One object of this disclosure is to provide a new technical solution for chip verification.

[0006] According to a first aspect of the present disclosure, a chip verification method is provided, applied to a verification module, the verification module including a pre-defined verification model and a data acquisition interface connected to the module under test in the chip; the method includes: Acquire the target message for the communication between the chip and other chips through the module under test, wherein the target message is a message that conforms to the general chip interconnection standard; When the target message meets the preset conditions, the algorithm data of the target calibration algorithm executed by the module under test during the link training process is collected through the data acquisition interface; wherein, the preset conditions are used to characterize whether the module under test starts executing the target calibration algorithm or ends executing the target calibration algorithm, and the algorithm data includes the input data or output data of the target calibration algorithm; The target calibration algorithm is validated based on the validation model and the algorithm data to obtain the validation result of the target calibration algorithm.

[0007] Optionally, the verification module further includes a message acquisition interface connected to the module under test; acquiring the target message for communication between the core and other cores through the module under test includes: The target message is collected based on the message acquisition interface. The target message is the message used by the module under test to communicate with other cores through the sideband channel.

[0008] Optionally, there are multiple data acquisition interfaces; the step of acquiring algorithm data of the target calibration algorithm executed by the module under test during link training through the data acquisition interface includes: A target calibration algorithm corresponding to the target message is determined based on a preset mapping relationship, wherein the preset mapping relationship is used to characterize the correspondence between the type of the target message and the target calibration algorithm; The target acquisition interface corresponding to the target calibration algorithm is determined from the plurality of data acquisition interfaces; The algorithm data corresponding to the target calibration algorithm is obtained through the target acquisition interface.

[0009] Optionally, obtaining the algorithm data corresponding to the target calibration algorithm through the target acquisition interface includes: When the target message indicates that the module under test has started executing the target calibration algorithm, the target acquisition interface is the input interface of the target calibration algorithm, and the algorithm data includes the input data of the target calibration algorithm; or When the target message indicates that the module under test has finished executing the target calibration algorithm, the target acquisition interface is the output interface of the target calibration algorithm, and the algorithm data includes the output data of the target calibration algorithm.

[0010] Optionally, the preset mapping relationship includes at least one of the following: The target message corresponding to the valid channel reference voltage calibration algorithm is the valid channel reference voltage calibration algorithm start or stop message; The target message corresponding to the data channel reference voltage calibration algorithm is the data channel reference voltage calibration start or stop message. The target message corresponding to the effective channel phase center calibration algorithm is the effective channel phase center calibration start or stop message; The target message corresponding to the data channel transmitter phase center calibration algorithm is the data channel transmitter phase center calibration start or stop message. The target message corresponding to the phase center calibration algorithm of the data channel receiver is the data channel receiver phase center calibration start or stop message. The target message corresponding to the transmitter channel offset calibration algorithm is the transmitter channel offset calibration start or stop message. The target message corresponding to the receiver channel offset calibration algorithm is the receiver channel offset calibration start or stop message. The target message corresponding to the tracking calibration algorithm is the tracking calibration start or stop message; The target message corresponding to the resistance calibration algorithm is the resistance calibration start or stop message.

[0011] Optionally, the step of verifying the target calibration algorithm based on the verification model and the algorithm data to obtain the verification result of the target calibration algorithm includes: The input data is processed based on a pre-defined validation model to obtain predicted data; the validation module provides a parameter configuration interface so that users can adjust the model parameters of the validation model through the parameter configuration interface; The verification result of the target calibration algorithm is determined based on the difference between the predicted data and the output data.

[0012] Optionally, the module under test includes multiple data channels; The step of collecting algorithm data of the target calibration algorithm executed by the module under test during the link training process through the data acquisition interface includes: for each data channel, collecting the algorithm data of the data channel when executing the target calibration algorithm through the corresponding data acquisition interface; The step of verifying the target calibration algorithm based on the verification model and the algorithm data includes: for each data channel, verifying the target calibration algorithm of the data channel based on the verification model and the algorithm data of the data channel respectively.

[0013] According to a second aspect of the present disclosure, a chip verification apparatus is provided, including a memory and a processor, the memory being used to store computer instructions, and the processor being used to invoke the computer instructions from the memory to perform the method described in the first aspect.

[0014] According to a third aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon, the computer program implementing the method described in the first aspect when executed by a processor.

[0015] According to a fourth aspect of the present disclosure, a core is provided, and a method for verifying the core includes the method described in the first aspect.

[0016] According to a fifth aspect of the present disclosure, a computing system is provided, the computing system including a plurality of cores, the cores being the cores described in the fourth aspect of the present disclosure.

[0017] Based on the chip verification method provided in this disclosure, algorithm data of the target calibration algorithm is dynamically collected based on the target message trigger. According to the verification model and algorithm data, the target calibration algorithm can be accurately verified, and algorithm logic or parameter errors can be detected in a timely manner. This avoids link stability degradation, performance fluctuations or compatibility issues caused by algorithm defects, thereby improving the reliability of chip verification.

[0018] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0020] Figure 1 This is a schematic diagram of the structure of a computing system provided in an embodiment of this disclosure.

[0021] Figure 2 This is a schematic diagram of the structure of a chip verification system provided in an embodiment of this disclosure.

[0022] Figure 3 This is a schematic flowchart of a chip verification method provided in an embodiment of this disclosure.

[0023] Figure 4 This is a schematic diagram of the structure of a chip verification device provided in an embodiment of this disclosure. Detailed Implementation

[0024] Various exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0025] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit this disclosure or its application or use. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus may be considered part of the specification.

[0026] It should be noted that similar labels and letters in the following figures indicate similar items, so once an item is defined in one figure, it need not be discussed further in subsequent figures.

[0027] This disclosure relates to a technical solution for chip verification. Figure 1 This is a schematic diagram of the structure of a computing system that can apply the technical solutions provided in the embodiments of this disclosure. For example... Figure 1 As shown, the computing system 1000 may include multiple cores, for example... Figure 1 The first core 1100 and the second core 1200, or other cores, are shown.

[0028] The various cores of this computing system can be interconnected using the UCIe protocol, which is a layered protocol, such as... Figure 1 As shown, the UCIe protocol can be divided into a protocol layer, an adaptation layer, and a physical layer. The protocol layer and the adaptation layer communicate via a Frame-Aware Die-to-Die Interface (FDI). The adaptation layer and the physical layer communicate via a Raw Die-to-Die Interface (RDI). The physical layer communicates with the physical layers of other chips via a physical link (PHY Link). This physical link can include multiple physical layer transmission channels, such as a main band channel and a sideband channel. The main band channel is used for high-speed data transmission and can also be called a data transmission channel, data transmission interface, or main band channel. The sideband channel is used for link management and state negotiation and can also be called a link management channel, link management interface, or sideband channel. The protocol layer interconnects with the on-chip network within the chip via dedicated bridging logic. The protocol layer acts as a translator, converting and encapsulating information from the on-chip network into UCIe standard transaction packets, and converting and encapsulating UCIe transaction packets into data packet formats that the on-chip network can recognize and route. The adaptation layer can act as a scheduler, performing flow control, sequencing, and multiplexing of protocol layer transactions, breaking them down into smaller, more regular data units (Flits) for transmission over the physical link. The physical layer can act as a courier, performing the lowest-level electrical or optical signal transmission, efficiently and reliably delivering data units to other cores via actual physical connections (such as microbumps), thereby enabling interconnected communication between cores.

[0029] It should be noted that, Figure 1The structure of the computing system shown is illustrative. The computing system in this embodiment is not limited to the above structure and may include more or fewer devices as needed, and the devices may be combined or split. For example, the computing system may also include other chips. Exemplarily, the computing system may also include other devices such as control devices and display devices. In some examples, the computing system may be a system-on-a-chip (SOC) or chip that includes multiple chips.

[0030] against Figure 1 During the design and development of the computing system shown, a UCIeVIP specifically designed for UCIe can be used to simulate UCIe protocol-related behaviors to verify whether the communication and / or functions between cores based on the UCIe protocol are normal. UCIe VIP schemes typically adopt a full-stack VIP architecture, including a protocol layer, an adaptation layer, and a physical layer. In a full-stack VIP architecture, the scrambling / descrambling, link state machine, sideband channels, and other modules or functions of the physical layer can be verified based on the input and output of the physical layer, without needing to concern themselves with the internal implementation of the physical layer.

[0031] However, as the application scenarios and requirements of chips become increasingly complex, the algorithms implemented at the physical layer also become more intricate. The full-stack VIP architecture in related technologies lacks specific verification for the algorithm modules within the physical layer. Even if there are certain logic or parameter errors during physical layer link training, they may not directly cause training failure. Therefore, failing to verify the physical layer algorithm modules significantly increases the risk of decreased link stability, performance fluctuations, or compatibility issues. Especially in UCIe, there are multiple complex training processes, such as reference voltage (Vref) calibration, signal debiasing adjustment, phase center calibration, offset calibration, tracking calibration, and resistance calibration. These algorithm steps are numerous and interdependent. Existing technologies lack complete reference models and verification methods covering all scenarios, making it difficult for simulation verification results to fully reflect the actual hardware operating state. This affects design optimization and system reliability, resulting in chips that function correctly based on a full-stack VIP architecture still exhibiting anomalies when running in complex real-world scenarios.

[0032] The most time-consuming part of system verification is the link training phase at the physical layer. This phase requires calibration of parameters such as voltage, clock, phase, and eye diagram of high-speed signals, as well as handshaking and synchronization between the two ends of the chip. The calibration of high-speed signal parameters requires sending a large number of data patterns to evaluate the physical link quality, resulting in extremely long simulation times and consuming significant computational resources. Therefore, verification strategies in related technologies generally combine a small amount of full algorithm scanning with most bypass algorithms, which further increases the lack of stability verification for the algorithm modules. Verifying the correctness of algorithms under dynamic, real-time conditions is even more challenging, and related technologies lack efficient, accurate verification mechanisms that can cover all scenarios. Therefore, how to achieve more reliable verification at the physical layer in the UCIe VIP scheme is an urgent problem to be solved.

[0033] To address the issues in related technologies, this disclosure provides a verification module oriented towards the UCIe standard. By introducing an independent data acquisition interface at the physical layer of the core, it enables specialized simulation verification support for various calibration algorithms and training processes. This module can dynamically adjust algorithm parameters according to different processes and training requirements, and can perform real-time monitoring and data acquisition during simulation operation, thereby ensuring the feasibility and effectiveness of algorithm verification. Its design allows direct integration with existing commercial UCIeVIP systems without modifying the protocol layer or adapter layer structure, significantly improving the flexibility and scalability of the verification system. With this verification module, users can independently verify algorithm performance without increasing the overall simulation complexity, improving system development efficiency and link stability.

[0034] Figure 2 This is a schematic diagram of a chip verification system provided in an embodiment of this disclosure. This chip verification system can verify... Figure 1 The VIP system for verifying the core in the illustrated computing system can be, for example, a simulation system for verifying the core, constructed through hardware, software, or a combination of both. This core verification system 2000 may include a module under test (DUT) 2100 and a verification module 2200. The DUT, also known as the device under test (DUT), can be used to simulate or model the physical layer of the core. The verification module can be used to verify the calibration algorithm of the DUT.

[0035] In some examples, such as Figure 2 As shown, the verification module 2200 may include at least one of the following: verification model 2210, acquisition interface 2220, and verification comparison unit 2230.

[0036] The verification model can be a pre-defined reference model used to simulate the target calibration algorithm, also known as the Golden Model. This verification model can calculate the expected output based on the input data of the calibration algorithm, serving as a verification benchmark. For example, the verification model can include reference implementations of various calibration algorithms, such as reference voltage calibration algorithms, phase center calibration algorithms, and channel offset calibration algorithms.

[0037] This acquisition interface can be connected to the module under test (DUT) for acquiring messages and / or data from the DUT. For example, the acquisition interface may include a data acquisition interface and / or a message acquisition interface. The data acquisition interface can be used to acquire algorithm data when the DUT executes the target calibration algorithm during link training. This algorithm data may include input data and / or output data of the target calibration algorithm. For example, the data acquisition interface may include multiple sub-interfaces, each corresponding to a different calibration algorithm and / or a different data channel.

[0038] This verification comparison unit can be used to compare the predicted data generated by the verification model with the actual output data of the module under test, and determine the verification result of the target calibration algorithm based on the comparison result. If the predicted data is the same as or basically consistent with the actual output data, the verification result is passed; if the difference is large (e.g., the absolute value of the difference is greater than or equal to a preset threshold), the verification result is failed. Furthermore, this verification module can also generate a detailed error report based on the verification result.

[0039] Furthermore, the acquisition interface of the verification module may also include a message acquisition interface, which can be used to acquire target messages for communication between the module under test and other core components. These target messages may be messages conforming to common core component interconnection standards, such as messages sent via sideband channels for link management and / or link training.

[0040] This verification system enables the real-time collection of algorithm data during the link training process of the module under test, and compares it with the prediction data of the verification model, thereby achieving independent verification of the physical layer calibration algorithm and improving the accuracy and reliability of the verification.

[0041] Figure 3 This is a schematic flowchart of a chip verification method provided in an embodiment of this disclosure. The chip verification method can be performed by... Figure 2 The verification module shown is executed. Figure 3 As shown, the chip verification method of this embodiment may include the following steps S310 to S330.

[0042] Step S310: Obtain the target message for the core to communicate with other cores through the module under test.

[0043] The target message can be a message that conforms to the general chip interconnect standard.

[0044] In some examples, the target message can be a message sent or received based on a sideband channel. For instance, the target message could be a message used by the module under test (DUT) to communicate with other cores via a sideband channel, such as a message sent to or received from other cores. The DUT can be the physical layer of a core, and other cores can also communicate with the DUT through the physical layer. It should be noted that the target message can also be a message transmitted based on other interfaces or channels.

[0045] For example, the verification module can collect the aforementioned target messages through a message acquisition interface. For instance, the verification module's message acquisition interface can monitor messages sent or received by the module under test via a sideband channel in real time. This sideband channel can be used for link management and state negotiation, and will send start or stop messages for various calibration algorithms during link training.

[0046] In some examples, the target message can be used to characterize the start and / or stop of a target calibration algorithm. This target calibration algorithm can be one or more calibration algorithms that need to be executed during the main band training (MBTRAIN) of the link training, such as reference voltage calibration, phase center calibration, offset calibration, tracking calibration, and resistance calibration. The target message can include start and / or stop messages for the aforementioned target calibration algorithms.

[0047] For example, the target message may include one or more of the following messages: effective channel reference voltage calibration algorithm start or stop message (MBTRAIN_VALVREF), data channel reference voltage calibration start or stop message (MBTRAIN_DATAVREF), effective channel phase center calibration start or stop message (MBTRAIN_VALTRAINCENTER), data channel transmitter phase center calibration start or stop message (MBTRAIN_DATATRAINCENTER1), data channel receiver phase center calibration start or stop message (MBTRAIN_DATATRAINCENTER2), transmitter channel offset calibration start or stop message (MBTRAIN_TXDESKEW), receiver channel offset calibration start or stop message (MBTRAIN_RXDESKEW), tracking calibration start or stop message (MBTRAIN_TRACKCALIBRATION), and resistance calibration start or stop message (MBTRAIN_RESISTANCECALIBRATION).

[0048] In this way, by monitoring the messages in the sideband channel in real time, the verification module can accurately capture the start and stop times of various calibration algorithms during the link training process, providing triggering conditions for subsequent data acquisition and verification. This enables the data acquisition of the verification module to be synchronized with the execution process of the module under test, avoiding data acquisition errors or verification failures caused by timing mismatches.

[0049] Step S320: If the target message meets the preset conditions, collect the algorithm data of the target calibration algorithm executed by the module under test during the link training process through the data acquisition interface.

[0050] The preset conditions can be used to characterize whether the module under test starts or stops executing the target calibration algorithm. The algorithm data can include the input data and / or output data of the target calibration algorithm.

[0051] Step S330: Verify the target calibration algorithm based on the verification model and algorithm data to obtain the verification result of the target calibration algorithm.

[0052] In some examples, the aforementioned verification module can process the input data based on a pre-defined verification model to obtain predicted data; the verification result of the target calibration algorithm can be determined based on the difference between the predicted data and the output data. For example, if the predicted data is consistent with the actual output data (e.g., the difference between the two is within a preset error range), the verification result is passed; if the difference is large (e.g., the difference exceeds the preset error range), the verification result is failed.

[0053] For example, the verification model can be a reference model (such as the Golden model) built based on the theoretical behavior of the target calibration algorithm, capable of calculating the expected output based on the input data. For instance, for an effective channel reference voltage calibration algorithm, the verification model can calculate the eye diagram height corresponding to each voltage point based on the input voltage scan range and step size, and determine the optimal reference voltage value. For a deskip calibration algorithm, the verification model can calculate the delay value that needs to be adjusted based on the input delay data of each channel to achieve timing alignment of each channel.

[0054] For example, the verification model can be algorithmic logic, such as training golden values ​​logic. That is, the computational logic used to generate the expected results of the target calibration algorithm. The verification model can be parameterized or replaced for different protocol versions, different product characteristics, or different project requirements to achieve consistency between the predicted results and the actual decision-making logic of the module under test.

[0055] In this way, the verification model can accurately verify the function of the target calibration algorithm, promptly detect algorithm logic or parameter errors, and improve the reliability of calibration algorithm verification.

[0056] It should be noted that the step of verifying the target calibration algorithm based on the verification model and algorithm data can be performed immediately after the algorithm data (including input data and output data) is collected to improve verification efficiency; or it can be performed after training is completed.

[0057] In some examples, the algorithm data described above can be stored in a dynamic sampling queue. The verification model (logic module) can initiate verification upon receiving a training end indication signal, which may include result update (result_update), window update (win_update), or similar signals. The verification model's operation steps may include: reading all algorithm data (including input and output data) collected during the current training round from the dynamic sampling queue; calling the corresponding algorithm function according to the current mode; calculating and generating prediction data; and writing the prediction data into the expected result queue. This algorithm function may include algorithms such as the maximum window finding algorithm (get_max_win), the minimum difference finding algorithm (get_min_win), the optimal window selection method, and the bit error rate minimization algorithm. In this way, the verification results of the target calibration algorithm can be obtained by comparing the prediction data in the expected result queue with the output data in the dynamic sampling queue.

[0058] In some examples, after obtaining the predicted and output data, the verification module can determine the verification result of the target calibration algorithm based on the difference between the predicted and output data, for example, by comparing the predicted and output data based on the verification comparison unit.

[0059] By using the methods described in steps S310 to S330 above, the algorithm data of the target calibration algorithm is dynamically collected based on the target message trigger. According to the verification model and algorithm data, the target calibration algorithm can be accurately verified, and algorithm logic or parameter errors can be detected in a timely manner. This avoids link stability degradation, performance fluctuations or compatibility issues caused by algorithm defects, thereby improving the reliability of chip verification.

[0060] In some examples disclosed herein, the verification module may provide a parameter configuration interface, allowing users to adjust the model parameters of the verification model. These model parameters may include algorithm process parameters, environmental parameters, performance metrics, such as voltage scan step size, delay adjustment accuracy, and error tolerance.

[0061] For example, this parameter configuration interface can be implemented through registers. For instance, this verification module supports online modification of the verification model parameters via the register interface in the simulation environment, such as adjusting the window comparison strategy, boundary value handling method, and bit error count threshold, thereby adapting to differences in calibration decision conditions across different standard protocols. This modifiability not only improves the versatility of the verification module but also allows for adaptation without reconstructing the entire reference model when the decision algorithm of the module under test is adjusted; only the specific algorithm module needs to be updated.

[0062] Through the parameter configuration interface, users can flexibly adjust the parameters of the verification model according to different process nodes, application scenarios or verification requirements, so that the verification model is closer to the working state of the actual hardware and improves the accuracy and applicability of the verification.

[0063] In some embodiments of this disclosure, the aforementioned chip verification method and the UCIe VIP verification main process can run independently. The verification module can trigger corresponding dynamic data sampling by continuously monitoring target messages. This does not interfere with the execution of the calibration algorithm in the UCIe VIP verification main process; instead, it collects the algorithm data of the calibration algorithm in parallel and performs verification in parallel. For example, the verification module (e.g., the verification comparison unit in the verification module) can run on an independent process, continuously monitoring the status of the predicted data queue and the actual output data queue. Once available data is detected simultaneously, the two are retrieved and compared. If the predicted data matches the actual output data, the verification is considered successful, and a verification success log can be recorded to confirm that the calibration algorithm of the module under test is executed correctly in the current training mode. If they do not match, the verification is considered to have failed, and a detailed error report can be generated, including the predicted data, the actual output data of the module under test, the original sampled data list, the boundary values ​​and window values ​​used in the calculation process, the channel number or module index number where the mismatch occurred, and possible causes.

[0064] In this way, the verification module achieves the asynchronous and non-blocking characteristics of the algorithm verification process, without affecting the sampling and prediction of other modes, and supports parallel verification across modes, thereby completing a comprehensive and accurate verification of the calibration function in a single simulation run.

[0065] For example, the above-described chip verification method may further include: generating a detailed verification report based on the verification results. This report may include one or more of the following: the target calibration algorithm, verification results (success or failure), input data, output data, predicted data, and possible reasons for failure, so that users can obtain the verification results promptly. This allows for a clear presentation of key data during the verification process, facilitating verification engineers to quickly locate and debug problems, further improving verification efficiency.

[0066] Furthermore, in the event of verification failure, an interrupt can be triggered to stop the overall simulation verification, allowing users to promptly identify and resolve the issues leading to the failure. By triggering an interrupt upon verification failure, the verification module can effectively prevent the propagation of errors, avoiding distortion of subsequent simulation results or system crashes caused by algorithmic defects. This significantly shortens the debugging cycle, improves development efficiency, and ensures the correctness and reliability of the final design.

[0067] In some embodiments of this disclosure, the module under test may include multiple data channels. For example, in the UCIe standard, the physical layer may include multiple parallel data channels for high-speed data transmission.

[0068] The verification module can verify the calibration algorithm for each data channel separately. Specifically, the verification module can collect the algorithm data of each data channel when executing the target calibration algorithm through the corresponding data acquisition interface. For example, for the data channel reference voltage calibration algorithm, the verification module can set independent input and output interfaces for each data channel and collect the voltage scan data and optimal reference voltage value of each channel respectively.

[0069] Furthermore, the verification module can verify the target calibration algorithm for each data channel separately, based on the verification model and the algorithm data for that data channel. This allows for independent evaluation of the algorithm performance of each channel, timely detection of algorithm errors in a particular channel, and prevention of the overall link stability being affected by problems in a single channel.

[0070] In this way, by supporting multi-channel parallel verification, the verification module can independently monitor and verify each channel. This improves the verification coverage and accuracy, promptly detects differences or anomalies between channels, ensures the performance consistency of each channel, and enhances the overall reliability of the link.

[0071] In some embodiments of this disclosure, the verification module may support the verification of multiple calibration algorithms. For example, the target calibration algorithm may include one or more of the following first to ninth algorithms.

[0072] The first algorithm, the valid channel reference voltage calibration algorithm, is used to determine the optimal reference voltage (Vref) value for the valid channel (ValidLane) to ensure that the signal can be correctly sampled at the receiver. The verification module can monitor the start or stop message (MBTRAIN_VALVREF) of the valid channel reference voltage calibration algorithm. When the algorithm starts, it acquires the input voltage scan range and step size; when the algorithm ends, it acquires the optimal reference voltage value output and compares it with the predicted value calculated by the verification model.

[0073] The second algorithm, the data channel reference voltage calibration algorithm, can be used to determine the optimal reference voltage value for the data channel. The verification module can monitor the data channel reference voltage calibration start or stop message (MBTRAIN_DATAVREF), collect the algorithm's input and output data, and perform verification and comparison.

[0074] The third algorithm, the effective channel phase center calibration algorithm, is used to determine the optimal sampling phase of the effective channel to ensure that the signal is sampled at the center of the eye diagram. The verification module can monitor the effective channel phase center calibration start or stop message (MBTRAIN_VALTRAINCENTER), collect the algorithm's input and output data, and perform verification comparison.

[0075] The fourth algorithm, the data channel transmitter phase center calibration algorithm, can be used to adjust the signal phase at the data channel transmitter to optimize signal transmission quality. The verification module can monitor the start or stop message of the data channel transmitter phase center calibration (MBTRAIN_DATATRAINCENTER1), collect the input and output data of the algorithm, and perform verification and comparison.

[0076] The fifth algorithm, the data channel receiver phase center calibration algorithm, can be used to adjust the sampling phase of the data channel receiver to optimize signal reception quality. The verification module can monitor the data channel receiver phase center calibration start or stop message (MBTRAIN_DATATRAINCENTER2), collect the algorithm's input and output data, and perform verification and comparison.

[0077] The sixth algorithm, the transmitter channel offset calibration algorithm, can be used to adjust the delay of each channel at the transmitter to achieve timing alignment (deskew). The verification module can monitor the transmitter channel offset calibration start or stop message (MBTRAIN_TXDESKEW), collect the algorithm's input and output data, and perform verification and comparison.

[0078] The seventh algorithm, the receiver channel offset calibration algorithm, can be used to adjust the delay of each channel at the receiver to achieve timing alignment. The verification module can monitor the receiver channel offset calibration start or stop message (MBTRAIN_RXDESKEW), collect the algorithm's input and output data, and perform verification and comparison.

[0079] The eighth algorithm, the tracking calibration algorithm, can be used to dynamically track and adjust signal parameters during link operation to adapt to environmental changes or aging effects. The verification module can monitor the tracking calibration start or stop message (MBTRAIN_TrackCalibration), collect the algorithm's input and output data, and perform verification comparison.

[0080] The ninth algorithm, the resistance calibration algorithm, can be used to calibrate the terminal resistance value to achieve impedance matching and reduce signal reflection. The verification module can monitor the resistance calibration start or stop message (MBTRAIN_ResistanceCalibration), collect the algorithm's input and output data, and perform verification comparison.

[0081] By supporting the verification of multiple calibration algorithms, the verification module can cover various key algorithms in the link training process, achieving comprehensive functional verification. This allows for the timely detection of logical or parameter errors in different algorithms, improving the overall stability and reliability of the link.

[0082] In some examples, the method of acquiring algorithm data of the target calibration algorithm executed by the module under test during link training via the data acquisition interface in step S320 above may include: determining the target calibration algorithm corresponding to the target message based on a preset mapping relationship; determining the target acquisition interface corresponding to the target calibration algorithm from multiple data acquisition interfaces; and acquiring the algorithm data corresponding to the target calibration algorithm through the target acquisition interface. The preset mapping relationship can be used to characterize the correspondence between the type of target message and the target calibration algorithm.

[0083] The data acquisition interface of the verification module, also known as the dynamic sampling interface, can capture key data points of the module under test (DUT) during training in different modes (i.e., executing different calibration algorithms). For example, in the data lane reference voltage calibration (MBTRAIN_DATAVREF) mode, which is used for training the receiver reference voltage (Vref) of the data lane, the dynamic sampling interface can sample the reference voltage control word output to the Physical Medium Attachment (PMA) as input data and record the output results of all data lanes (e.g., 64) as output data. In the valid lane phase center calibration (MBTRAIN_VALTRAINCENTER) mode, which is used for calibrating the phase difference between the valid lane and the clock lane, the dynamic sampling interface can record the optimal phase interpolator code (PI code). In the data channel transmitter phase center calibration (MBTRAIN_DATATRAINCENTER1) mode, this mode is used for transmitter multi-channel deskew calibration. The algorithm sequentially performs transmitter phase interpolator boundary scan and deskew value setting scan for each data channel. The dynamic sampling interface records the phase interpolator value and the deskew value, and records the correspondence between the phase interpolator value and the deskew value.

[0084] The verification module can establish a mapping relationship between corresponding data sampling points (also known as signal sampling locations) and prediction algorithms for various modes (calibration algorithms). For example, in the sampled valid (sample_vld) mode, the dynamic sampling interface collects data such as the scanning window (pass_win), maximum value (pass_max), and minimum value (pass_min) according to the algorithm. The verification model calls the maximum window search (get_max_win) algorithm to find the maximum window and determine the optimal sampling value. In the transmitter-side channel-by-channel deskew (tx_perlane_deskew) mode, the dynamic sampling interface collects the transmitter code of all data channels through the window (tx_code_pass_win). The verification model calls the minimum difference search (get_min_win) algorithm to find the minimum difference and thus determine the optimal scanning value. In this way, the verification module can perform multi-mode, multi-channel full-process sampling and prediction in parallel after interactive triggering without affecting the timing of the module under test.

[0085] In this way, the target acquisition interface can be dynamically selected through a preset mapping relationship. The verification module can accurately acquire the algorithm data of the target calibration algorithm, improving the accuracy and completeness of data acquisition and providing a reliable data foundation for subsequent verification and comparison, thereby improving the accuracy of the verification results. At the same time, since the target acquisition interface is dynamically selected for acquisition, calibration algorithms that have not been executed do not need to be acquired, thus reducing the amount of data acquired, reducing the amount of data analysis, and improving the efficiency of the chip verification method.

[0086] For example, the above-mentioned preset mapping relationship includes one or more of the following first to ninth mapping relationships.

[0087] The first mapping relationship includes: the target message corresponding to the effective channel reference voltage calibration algorithm is the effective channel reference voltage calibration algorithm start or stop message.

[0088] The second mapping relationship includes: the target message corresponding to the data channel reference voltage calibration algorithm is the data channel reference voltage calibration start or stop message.

[0089] The third mapping relationship includes: the target message corresponding to the effective channel phase center calibration algorithm is the effective channel phase center calibration start or stop message.

[0090] The fourth mapping relationship includes: the target message corresponding to the data channel transmitter phase center calibration algorithm is the data channel transmitter phase center calibration start or stop message.

[0091] The fifth mapping relationship includes: the target message corresponding to the phase center calibration algorithm of the data channel receiver is the start or stop message of the phase center calibration of the data channel receiver.

[0092] The sixth mapping relationship includes: the target message corresponding to the transmitter channel offset calibration algorithm is the transmitter channel offset calibration start or stop message.

[0093] The seventh mapping relationship includes: the target message corresponding to the receiver channel offset calibration algorithm is the receiver channel offset calibration start or stop message.

[0094] The eighth mapping relationship includes: the target message corresponding to the tracking calibration algorithm is the tracking calibration start or stop message.

[0095] The ninth mapping relationship includes: the target message corresponding to the resistance calibration algorithm is the resistance calibration start or stop message.

[0096] In this way, by pre-setting the mapping relationship, all calibration algorithms can be fully covered, further improving the accuracy and completeness of data acquisition.

[0097] In some examples, the target acquisition interface described above can be the input or output interface of the target calibration algorithm, and the acquired algorithm data can also include the input or output data of the target calibration algorithm.

[0098] For example, when the target message characterization module under test starts executing the target calibration algorithm, the target acquisition interface can be the input interface of the target calibration algorithm, and the algorithm data can include the input data of the target calibration algorithm.

[0099] For example, when the target message characterization module under test finishes executing the target calibration algorithm, the target acquisition interface can be the output interface of the target calibration algorithm, and the algorithm data can include the output data of the target calibration algorithm.

[0100] In this way, the verification module can more accurately collect the input and output data of the target calibration algorithm, further ensuring the accuracy and completeness of data collection.

[0101] The chip verification method provided in this disclosure establishes an interactive detection mechanism and dynamic sampling interface conforming to standard protocols. When the verification platform detects UCIe standard-compliant sideband channel training messages (such as MBTRAIN_VALVREF, MBTRAIN_DATATRAINCENTER, etc.), it automatically triggers the corresponding dynamic sampling task. The platform acquires training data of the module under test in real time through the data acquisition interface and dynamically adjusts parameters (phase interpolator step, deskip value, reference voltage range, etc.) during operation, thereby identifying and quickly locating problems in advance. The adoption of a multi-mode unified architecture and parallel sampling mechanism enables seamless switching between different training modes without requiring separate environments for each mode. This significantly shortens the overall verification time, accelerates development and debugging, and improves verification efficiency. Lightweight sampling and asynchronous comparison designs reduce computational resource requirements, lessen the pressure on the simulation platform, and support efficient operation of multi-channel and large-scale mode combinations. The verification model can be directly mounted to existing UCIe VIP verification systems without modifying the protocol layer or adaptation layer structure, adapting to different vendors' or versions of protocol implementations and ensuring the portability of the verification environment. By using a unified sampling interface and configurable verification model calculation logic, the consistency between training decisions and expected results is ensured. Real-time comparison can quickly report errors and trigger simulation interruption, thereby improving the success rate of physical layer link training and reducing performance fluctuations caused by algorithm defects.

[0102] This disclosure also provides a chip, and the method for verifying the chip may include all or part of the steps of any chip verification method in the foregoing embodiments of this disclosure. For example, the chip may be obtained after verification based on any chip verification method in the foregoing embodiments of this disclosure. The chip may be a chip interconnected using the UCIe protocol, and its physical layer implements various calibration algorithms, such as reference voltage calibration, deskipation calibration, phase calibration, tracking calibration, resistance calibration, etc.

[0103] By verifying the chip using the aforementioned chip verification method, logical or parameter errors in the physical layer calibration algorithm can be detected in a timely manner, avoiding link instability, performance fluctuations, or compatibility issues caused by algorithm defects. This improves the quality and reliability of the chip, ensuring its stable operation in practical applications.

[0104] This disclosure also provides a computing system that may include multiple chips, and a method for verifying the chips may include all or part of the steps of any of the chip verification methods described in the foregoing embodiments of this disclosure. Exemplarily, the computing system may be a system-on-a-chip (SoC) or chip including multiple chips, with the chips interconnected and communicating via the UCIe protocol. For example, the computing system may be... Figure 1The computing system 1000 shown can be a system that includes computing devices such as GPUs, GPGPUs, NPUs, or TPUs.

[0105] The computing system can be any type of electronic device, such as any type of terminal device, workstation or server, etc., and this embodiment does not limit it.

[0106] Figure 4 This disclosure provides a chip verification device 400, which may include a memory 410 and a processor 420. The memory may be used to store computer instructions, and the processor may be used to retrieve computer instructions from the memory to execute all or part of the steps of any of the methods in the foregoing embodiments of this disclosure. The processor may be one or more processors, which may execute instructions individually or jointly. Similarly, the memory may be one or more memories, which may store the aforementioned computer instructions individually or jointly.

[0107] This disclosure also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements all or part of the steps of any of the methods in the foregoing embodiments of this disclosure. Optionally, the computer-readable storage medium may be a non-transitory storage medium, but is not limited thereto, and may also be a temporary storage medium.

[0108] This disclosure also provides a computer program product that may include a computer program that, when executed by a processor, can implement all or part of the steps of any of the methods in the foregoing embodiments of this disclosure.

[0109] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and apparatuses according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, unit, or part of a circuit. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should be noted that embodiments of the present disclosure may include some or all of the functions marked in the multiple blocks in the drawings, and may also include other functions not shown in the blocks in the drawings. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented in hardware that performs the specified function or action, or in a combination of dedicated hardware and computer instructions. Unless otherwise specified, implementation in hardware, implementation in software, and implementation in a combination of software and hardware may be equivalent.

[0111] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this disclosure is defined by the appended claims.

Claims

1. A chip verification method, characterized in that, A verification module is applied in a chip verification system. The verification module includes a pre-defined verification model and a data acquisition interface connected to the module under test (DUT) within the chip. The chip verification system also includes the DUT and other chips, wherein the chips are interconnected using the UCIe protocol. The DUT is used to simulate or model the physical layer of the chip and perform link training. The method includes: Acquire the target message for the communication between the chip and other chips through the module under test. The target message is a message that conforms to the general chip interconnection standard. The target message is a message sent or received by the module under test through the sideband channel. When the target message meets the preset conditions, the algorithm data of the target calibration algorithm executed by the module under test during the link training process is collected through the data acquisition interface; wherein, the preset conditions are used to characterize whether the module under test starts executing the target calibration algorithm or ends executing the target calibration algorithm, and the algorithm data includes the input data or output data of the target calibration algorithm, and the target calibration algorithm is one or more calibration algorithms executed in the main band training of the link training; The target calibration algorithm is validated based on the validation model and the algorithm data to obtain the validation result of the target calibration algorithm.

2. The method according to claim 1, characterized in that, The verification module further includes a message acquisition interface connected to the module under test; acquiring the target message for communication between the core and other cores through the module under test includes: The target message is collected based on the message collection interface.

3. The method according to claim 1, characterized in that, The data acquisition interface is multiple; the process of acquiring algorithm data of the target calibration algorithm executed by the module under test during link training through the data acquisition interface includes: A target calibration algorithm corresponding to the target message is determined based on a preset mapping relationship, wherein the preset mapping relationship is used to characterize the correspondence between the type of the target message and the target calibration algorithm; The target acquisition interface corresponding to the target calibration algorithm is determined from the plurality of data acquisition interfaces; The algorithm data corresponding to the target calibration algorithm is obtained through the target acquisition interface.

4. The method according to claim 3, characterized in that, The step of obtaining the algorithm data corresponding to the target calibration algorithm through the target acquisition interface includes: When the target message indicates that the module under test has started executing the target calibration algorithm, the target acquisition interface is the input interface of the target calibration algorithm, and the algorithm data includes the input data of the target calibration algorithm; or When the target message indicates that the module under test has finished executing the target calibration algorithm, the target acquisition interface is the output interface of the target calibration algorithm, and the algorithm data includes the output data of the target calibration algorithm.

5. The method according to claim 3, characterized in that, The preset mapping relationship includes at least one of the following: The target message corresponding to the valid channel reference voltage calibration algorithm is the valid channel reference voltage calibration algorithm start or stop message; The target message corresponding to the data channel reference voltage calibration algorithm is the data channel reference voltage calibration start or stop message. The target message corresponding to the effective channel phase center calibration algorithm is the effective channel phase center calibration start or stop message; The target message corresponding to the data channel transmitter phase center calibration algorithm is the data channel transmitter phase center calibration start or stop message. The target message corresponding to the phase center calibration algorithm of the data channel receiver is the data channel receiver phase center calibration start or stop message. The target message corresponding to the transmitter channel offset calibration algorithm is the transmitter channel offset calibration start or stop message. The target message corresponding to the receiver channel offset calibration algorithm is the receiver channel offset calibration start or stop message. The target message corresponding to the tracking calibration algorithm is the tracking calibration start or stop message; The target message corresponding to the resistance calibration algorithm is the resistance calibration start or stop message.

6. The method according to claim 1, characterized in that, The step involves validating the target calibration algorithm based on the validation model and the algorithm data to obtain the validation result of the target calibration algorithm, including... The input data is processed based on a pre-defined verification model to obtain predicted data; The verification module provides a parameter configuration interface, allowing users to adjust the model parameters of the verification model through the parameter configuration interface; The verification result of the target calibration algorithm is determined based on the difference between the predicted data and the output data.

7. The method according to any one of claims 1 to 6, characterized in that, The module under test includes multiple data channels; The step of collecting algorithm data of the target calibration algorithm executed by the module under test during the link training process through the data acquisition interface includes: for each data channel, collecting the algorithm data of the data channel when executing the target calibration algorithm through the corresponding data acquisition interface; The step of verifying the target calibration algorithm based on the verification model and the algorithm data includes: for each data channel, verifying the target calibration algorithm of the data channel based on the verification model and the algorithm data of the data channel respectively.

8. A chip verification device, characterized in that, The device includes a memory and a processor, the memory being used to store computer instructions, and the processor being used to retrieve the computer instructions from the memory to perform the method of any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 7.

10. A core element, characterized in that, The method for verifying the core includes the core verification method as described in any one of claims 1 to 7.

11. A computing system, characterized in that, It includes multiple cores as described in claim 10.

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