Single-phase brushless direct current motor pre-driving circuit

Abstract

The invention discloses a pre-driving circuit of a single-phase brushless direct current motor, which is characterized in that a pre-driver does not directly output GP1, but directly controls the on and off of a second PMOS (P-channel Metal Oxide Semiconductor) tube through the cooperation of a first driving pin FG and a first resistor between the source electrode and the grid electrode of the second PMOS tube, and meanwhile, the on and off of the second PMOS tube are controlled through the cooperation of the first driving pin FG and the first resistor; on and off of the first PMOS tube are controlled by a first resistor between the source electrode and the grid electrode of the third NMOS tube and the source electrode and the grid electrode of the first PMOS tube, so that a GP1 pin and a corresponding driving circuit on the pre-driver are reduced, and furthermore, GN1 and GN2 drive the two NMOS tubes respectively while the GN1 and GN2 drive the two NMOS tubes respectively. When an upper tube and a lower tube of a preceding stage GN1 / GN2 are both turned off, voltage drop on a third resistor is indirectly sampled through a second resistor between a source electrode and a grid electrode of the preceding stage GN1 / GN2, that is, current sampling is completed by multiplexing GN1 / GN2, so that CS pins on a pre-driver are reduced; therefore, the number of pins of the pre-driver and board-level connecting lines are reduced while the driving and current detection functions are reserved, and then the packaging cost of the pre-driver is optimized.

Description

Technical Field

[0001] This invention belongs to the field of single-phase brushless DC motor drive technology, specifically relating to a pre-drive circuit for a single-phase brushless DC motor. Background Technology

[0002] Traditional single-phase BLDC pre-drive solutions, such as Figure 1 As shown, M represents a single-phase brushless DC motor. Its winding ends are connected to the H-bridge outputs OUT1 / OUT2. Besides VCC and GND, the pre-driver's connection pins to the power transistors include four output pins: GP1, GP2, GN1, and GN2, and one input pin CS. GP1 and GP2 are used to drive the PMOS power transistors MP1 and MP2 to turn on and off, respectively; GN1 and GN2 are used to drive the NMOS power transistors MN1 and MN2 to turn on and off, respectively; and the CS pin is used to feedback the winding current information for overcurrent protection within the driver. Additionally, PWM is the pulse width modulation input signal, and FG is the output signal that responds to changes in the magnetic field. Thus, the aforementioned traditional single-phase BLDC pre-driver scheme requires a large number of pins, resulting in numerous board-level connections, complex circuitry, and increased pre-driver packaging costs. Therefore, based on these shortcomings, providing a solution that reduces the number of pins in the pre-driver itself while ensuring drive performance and reliability, and simplifies the peripheral single-phase brushless DC motor pre-driver circuit, has become an urgent problem to solve. Summary of the Invention

[0003] The purpose of this invention is to provide a pre-drive circuit for a single-phase brushless DC motor, which solves the problem that existing single-phase BLDC pre-drive schemes require a large number of pins to implement, resulting in more board-level interconnections, more complex circuits, and thus increased cost of pre-driver packaging.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, a pre-drive circuit for a single-phase brushless DC motor is provided, comprising: A pre-driver, wherein the pre-driver is provided with a first drive pin, a second drive pin and a third drive pin, and the pre-driver is also provided with a pulse signal input pin; The H-bridge drive circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the two PMOS transistors are interconnected and connected to a power supply. The drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically connected to the drain of the second NMOS transistor. The common connection of the two PMOS transistors and the two NMOS transistors serves as the output terminal of the H-bridge drive circuit and is electrically connected to the winding terminal of a single-phase brushless DC motor. The first drive pin of the pre-driver is electrically connected to the gate of the second PMOS transistor and the gate of the third NMOS transistor. The drain of the third NMOS transistor is electrically connected to the gate of the first PMOS transistor, and a first resistor is connected in parallel between the source and gate of both PMOS transistors. The second drive pin of the pre-driver is electrically connected to the gate of the first NMOS transistor, and the third drive pin of the pre-driver is electrically connected to the gate of the second NMOS transistor. The sources of both the first and second NMOS transistors are electrically connected to one end of a third resistor, and the other end of the third resistor and the source of the third NMOS transistor are grounded. A second resistor is connected in parallel between the source and gate of both the first and second NMOS transistors to sample the voltage drop across the third resistor, so as to multiplex the second and third drive pins to complete the current sampling of the winding terminals.

[0005] Based on the above disclosure, the driving circuit provided by this invention does not directly output GP1 in the pre-driver. Instead, it directly controls the turn-on and turn-off of the second PMOS transistor through the cooperation of the first driving pin FG and the first resistor between the source and gate of the second PMOS transistor. Simultaneously, the turn-on and turn-off of the first PMOS transistor are controlled by the first resistor between the source and gate of the third NMOS transistor and the first PMOS transistor, and the gate of the third NMOS transistor is connected to FG. This reduces the number of GP1 pins on the pre-driver and the corresponding internal driving circuitry. Furthermore, the second driving pin GN1 and the third driving pin GN... 2. While driving the first NMOS transistor and the second NMOS transistor respectively, the voltage drop across the third resistor is indirectly sampled through the second resistor between the source and gate of each transistor when both the upper and lower transistors of the preceding stage GN1 / GN2 are turned off. That is, GN1 / GN2 is reused to complete the current sampling. Based on this, the CS pin on the pre-driver is reduced, thereby reducing the number of traces on the PCB board. Thus, through the above design, the pre-driver scheme proposed in this invention reduces the number of pre-driver pins and board-level interconnections while retaining the driving and current detection functions, thereby optimizing the cost of the pre-driver package. Therefore, it is very suitable for large-scale application and promotion.

[0006] In one possible design, the pre-driver includes: a PMOS transistor driving unit, an NMOS transistor driving unit, a current feedback unit, and a drive signal generation unit; The signal input terminal of the drive signal generation unit serves as the input terminal of the pre-driver to receive drive control signals. The output terminal of the drive signal generation unit is electrically connected to the input terminals of the PMOS transistor drive unit and the NMOS transistor drive unit, respectively, and is used to output drive signals to the PMOS transistor drive unit and the NMOS transistor drive unit. The drive control signals include the magnetic field signal generated by the single-phase brushless DC motor and the pulse width modulation signal received based on the pulse signal input pin. The output terminal of the PMOS transistor driving unit serves as the first driving pin, and is electrically connected to the gate of the second PMOS transistor and the gate of the third NMOS transistor, respectively. The first output terminal of the NMOS transistor driving unit serves as the second driving pin and is electrically connected to the gate of the first NMOS transistor, and the second output terminal of the NMOS transistor driving unit serves as the third driving pin and is electrically connected to the gate of the second NMOS transistor. The input terminal of the current feedback unit is electrically connected to the second drive pin and the third drive pin, wherein the output terminal of the current feedback unit is electrically connected to the feedback input terminal of the drive signal generation unit, and the feedback control terminal of the drive signal generation unit is electrically connected to the controlled terminal of the current feedback unit.

[0007] In one possible design, the drive signal generation unit includes a first output terminal, and the drive signal includes a first drive sub-signal output from the first output terminal; The PMOS transistor driving unit includes: a fourth NMOS transistor; The gate of the fourth NMOS transistor is electrically connected to the first output terminal of the drive signal generation unit to receive the first drive sub-signal. The source of the fourth NMOS transistor is grounded, and the drain of the fourth NMOS transistor serves as the first drive pin, which is electrically connected to the gate of the second PMOS transistor and the gate of the third NMOS transistor, respectively.

[0008] In one possible design, the drive signal generation unit includes a second output terminal and a third output terminal, and the drive signal includes a second drive sub-signal output from the second output terminal and a third drive sub-signal output from the third output terminal; The NMOS transistor driving unit includes: a first half-bridge driving circuit and a second half-bridge driving circuit. The input terminal of the first half-bridge driving circuit is electrically connected to the second output terminal of the driving signal generation unit to receive the second driving sub-signal. The output terminal of the first half-bridge driving circuit serves as the first output terminal of the NMOS transistor driving unit and is electrically connected to the gate of the first NMOS transistor. The input terminal of the second half-bridge driving circuit is electrically connected to the third output terminal of the driving signal generation unit to receive the third driving sub-signal. The output terminal of the second half-bridge driving circuit serves as the second output terminal of the NMOS transistor driving unit and is electrically connected to the gate of the second NMOS transistor.

[0009] In one possible design, the first half-bridge drive circuit and the second half-bridge drive circuit have the same circuit structure, wherein the first half-bridge drive circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a first high-side signal driver and a first low-side signal driver; The input terminals of the first high-side signal driver and the first low-side signal driver are both used as input terminals of the first half-bridge driving circuit and are electrically connected to the second output terminal of the driving signal generation unit. The output terminal of the first high-side signal driver is electrically connected to the gate of the fifth NMOS transistor, and the output terminal of the first low-side signal driver is electrically connected to the gate of the sixth NMOS transistor. The source of the fifth NMOS transistor is electrically connected to the drain of the sixth NMOS transistor, wherein the drain of the fifth NMOS transistor is electrically connected to the power supply, the source of the sixth NMOS transistor is grounded, and the common terminal of the fifth NMOS transistor and the sixth NMOS transistor serves as the output terminal of the first half-bridge drive circuit, and is electrically connected to the gate of the first NMOS transistor through the fourth resistor.

[0010] In one possible design, the current feedback unit includes: a seventh NMOS transistor, an eighth NMOS transistor, and a comparator; The drain of the seventh NMOS transistor is electrically connected to the second drive pin, and the drain of the eighth NMOS transistor is electrically connected to the third drive pin. The sources of the seventh and eighth NMOS transistors are both electrically connected to the non-inverting input of the comparator. The inverting input of the comparator is electrically connected to the reference voltage. The gates of the seventh and eighth NMOS transistors are both electrically connected to the feedback control terminal of the drive signal generation unit. The output of the comparator serves as the output of the current feedback unit and is electrically connected to the feedback input of the drive signal generation unit.

[0011] In one possible design, the drive signal includes a first drive sub-signal for driving the PMOS transistor drive unit, and a second and a third drive sub-signal for driving the NMOS transistor drive unit. The drive signal generation unit includes a first drive signal generation circuit, a second drive signal generation circuit, and an auxiliary drive circuit, wherein the first drive signal generation circuit is provided with a PMOS transistor signal output terminal and an auxiliary signal output terminal. The input terminal of the first drive signal generation circuit is electrically connected to the output terminal of the Hall sensor to receive the magnetic field signal. The PMOS transistor signal output terminal of the first drive signal generation circuit is electrically connected to the PMOS transistor driving unit to output a first drive sub-signal to the PMOS transistor driving unit. The auxiliary signal output terminal of the first drive signal generation circuit is electrically connected to the second drive signal generation circuit to output a first auxiliary drive signal to the second drive signal generation circuit. The input terminal of the auxiliary drive circuit is electrically connected to the output terminal of the current feedback unit and the output terminal of the Hall sensor, and is used to receive the feedback signal output by the current feedback unit and the magnetic field signal output by the Hall sensor. The output terminal of the auxiliary drive circuit is electrically connected to the second drive signal generation circuit, and is used to output the second auxiliary drive signal and the third auxiliary drive signal to the second drive signal generation circuit. The input terminal of the second drive signal generation circuit serves as the pulse signal input pin for receiving the pulse width modulation signal. The output terminal of the second drive signal generation circuit is electrically connected to the input terminal of the NMOS transistor drive unit and is used to generate a second sub-drive signal and a third sub-drive signal based on the pulse width modulation signal, the first auxiliary drive signal, the second auxiliary drive signal, and the third auxiliary drive signal, and send them to the NMOS transistor drive unit.

[0012] In one possible design, the first drive signal generation circuit includes: rising and falling edge delay circuits and an XOR gate; The input terminals of the rising and falling edge delay circuits are electrically connected to the output terminals of the Hall sensor. The output terminals of the rising and falling edge delay circuits serve as the signal output terminals of the PMOS transistor and are electrically connected to the PMOS transistor driving unit. The first input terminal of the XOR gate is electrically connected to the output terminal of the Hall sensor, the second input terminal of the XOR gate is electrically connected to the output terminals of the rising and falling edge delay circuits, and the output terminal of the XOR gate serves as the auxiliary signal output terminal and is electrically connected to the second driving signal generation circuit.

[0013] In one possible design, the auxiliary driving circuit includes: a rising edge narrow pulse circuit, rising and falling edge narrow pulse circuits, a first NOR gate, a first rising edge delay circuit, a first NOT gate, a first NAND gate, a second NAND gate, a third NOT gate, and a fourth NOT gate. The input terminal of the rising edge narrow pulse circuit is electrically connected to the output terminal of the current feedback unit, and the input terminals of the rising and falling edge narrow pulse circuits are electrically connected to the output terminal of the Hall sensor. The output terminals of the rising edge narrow pulse circuit and the rising and falling edge narrow pulse circuits are electrically connected to the input terminal of the first NOR gate. The output terminal of the first NOR gate is electrically connected to the input terminal of the first NOT gate through the first rising edge delay circuit, and the output terminal of the first NOT gate is electrically connected to the first input terminals of the first NAND gate and the second NAND gate, respectively. The second input terminal of the first NAND gate is used to receive the fourth auxiliary drive signal, wherein the output terminal of the first NAND gate is electrically connected to the input terminal of the third NOT gate, and the output terminal of the third NOT gate outputs the second auxiliary drive signal; The second output terminal of the second NAND gate is used to receive the fifth auxiliary drive signal. The output terminal of the second NAND gate is electrically connected to the input terminal of the fourth NOT gate. The output terminal of the fourth NOT gate outputs the third auxiliary drive signal. The fourth auxiliary drive signal and the fifth auxiliary drive signal are generated based on the magnetic field signal output by the Hall sensor.

[0014] In one possible design, the second drive signal generation circuit includes a first logic signal generation circuit and a second logic signal generation circuit, wherein the first logic signal generation circuit and the second logic signal generation circuit have the same circuit structure, each including several fifth NOT gates, second NOR gates and third NAND gates, as well as two second rising edge delay circuits and one falling edge delay circuit. Specifically, the first logic signal generation circuit outputs the second driving sub-signal to the NMOS transistor driving unit, and the second logic signal generation circuit outputs the third driving sub-signal to the NMOS transistor driving unit.

[0015] Beneficial effects: (1) The pre-drive scheme proposed in this invention retains the driving and current detection functions while reducing the number of pre-driver pins and board-level interconnections, thereby optimizing the cost of pre-driver packaging. Therefore, it is very suitable for large-scale application and promotion. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a conventional single-phase BLDC pre-drive circuit provided in an embodiment of the present invention; Figure 2 This is an overall circuit diagram of the pre-drive circuit for a single-phase brushless DC motor provided in an embodiment of the present invention; Figure 3 A circuit diagram showing the connection between the single-phase BLDC drive circuit and the PMOS transistor drive unit, NMOS transistor drive unit, and current feedback unit in the pre-drive circuit provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the signal output of the driving signal generation unit provided in an embodiment of the present invention; Figure 5 A schematic diagram of the driving waveform of the pre-driving circuit provided in an embodiment of the present invention; Figure 6 A schematic diagram of a 100% duty cycle drive waveform provided in an embodiment of the present invention; Figure 7 A schematic diagram of the drive waveform when triggering overcurrent protection according to an embodiment of the present invention; Figure 8 A circuit diagram of the first drive signal generation circuit provided in an embodiment of the present invention; Figure 9 A circuit diagram of the auxiliary driving circuit provided in an embodiment of the present invention; Figure 10 A circuit diagram of the second drive signal generation circuit provided in an embodiment of the present invention; Figure 11 A waveform diagram of a key node of the pre-driver provided in an embodiment of the present invention; Figure 12 The input and output waveforms of dly1 and dly2 provided in the embodiments of the present invention; Figure 13 This is a first alternative circuit diagram of the pre-drive circuit provided in an embodiment of the present invention; Figure 14 A second alternative circuit diagram for the pre-driving circuit provided in the embodiments of the present invention; Figure 15 A third alternative circuit diagram for the pre-drive circuit provided in the embodiments of the present invention; Figure 16 A fourth alternative circuit diagram for the pre-drive circuit provided in the embodiments of the present invention; Figure 17 Provided for embodiments of the present invention Figure 3 An alternative circuit diagram; Figure 18 The circuit diagrams for hsdrv1 and hsdrv2 provided in the embodiments of the present invention are shown below; Figure 19 The circuit diagrams for lsdrv1 and lsdrv2 provided in the embodiments of the present invention are shown. Detailed Implementation

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in conjunction with the accompanying drawings and descriptions of the embodiments or the prior art. Obviously, the following description of the structure of the accompanying drawings is only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the description of these embodiments is for the purpose of helping to understand the present invention, but does not constitute a limitation of the present invention.

[0018] It should be understood that although the terms first, second, etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit, without departing from the scope of the exemplary embodiments of the invention.

[0019] It should be understood that the term "and / or" that may appear in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" that may appear in this document describes another relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " that may appear in this document generally indicates that the related objects before and after it are in an "or" relationship.

[0020] Example: See Figures 2-19 As shown, the single-phase brushless DC motor pre-drive circuit provided in this embodiment reduces the number of GP1 and GP2 related drive modules by reusing FG to drive P transistors, and reduces the input of CS pin by reusing GN1 or GN2 to sample load current. At the same time, based on the new architecture, the drive logic and circuit are designed to avoid the risk of OUT1 / OUT2 phase commutation shoot-through in the H-bridge drive circuit, ensuring that the system can work stably and reliably. For example, the pre-drive circuit may include, but is not limited to, a pre-driver and an H-bridge drive circuit, wherein the pre-driver is provided with a first drive pin FG, a second drive pin GN1, and a third drive pin GN2. In this way, the aforementioned three drive pins are used to drive the field-effect transistors in the H-bridge drive circuit, and the second drive pin GN1 and the third drive pin GN2 are used to collect the current at the winding end of the single-phase brushless DC motor, thereby completing the pre-drive of the single-phase brushless DC motor, and thus reducing the number of pre-driver pins while retaining the drive and current detection functions.

[0021] Simultaneously, the pre-driver is also provided with a pulse signal input pin (PWM) to receive pulse width modulation signals used for motor driving; of course, the pre-driver also has VCC and GND pins (e.g., Figure 2 As shown in the figure, this is to achieve the functions of chip power supply and grounding.

[0022] Furthermore, the detailed construction of the H-bridge drive circuit is disclosed below: In this embodiment, the H-bridge drive circuit described herein may include, but is not limited to, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The sources of the two PMOS transistors are interconnected and connected to a power supply. The drain of the first PMOS transistor MP1 is electrically connected to the drain of the first NMOS transistor MN1, and the drain of the second PMOS transistor MP2 is electrically connected to the drain of the second NMOS transistor MN2, thereby forming an H-bridge. The common connection of the two PMOS transistors and the two NMOS transistors serves as the output terminal of the H-bridge drive circuit, which is electrically connected to the winding terminals of the single-phase brushless DC motor. That is, the common connection of the first PMOS transistor MP1 and the first NMOS transistor MN1, and the common connection of the second PMOS transistor MP2 and the second NMOS transistor MN2, respectively serve as the OUT1 and OUT2 terminals of the H-bridge drive circuit, respectively, to connect to the two ends of the winding of the single-phase brushless DC motor.

[0023] Simultaneously, the first drive pin FG of the pre-driver is electrically connected to the gate of the second PMOS transistor MP2 and the gate of the third NMOS transistor MN8. The drain of the third NMOS transistor MN8 is electrically connected to the gate of the first PMOS transistor MP1, and a first resistor (i.e., ...) is connected in parallel between the source and gate of both PMOS transistors. Figure 2 (RP1 and RP2 in the above). Thus, in this embodiment, the pre-driver does not directly output GP1, but instead uses the first drive pin FG in conjunction with RP2 to directly control the turn-on and turn-off of the second PMOS transistor MP2. The turn-on and turn-off of the first PMOS transistor MP1 are controlled by the third NMOS transistor MN8 and RP1, and the gate of the third NMOS transistor MN8 is connected to FG. Therefore, through the aforementioned circuit design, this embodiment reduces the GP1 pin on the pre-driver and the corresponding internal drive circuit.

[0024] Furthermore, in this embodiment, the second drive pin GN1 of the pre-driver is electrically connected to the gate of the first NMOS transistor MN1, and the third drive pin GN2 of the pre-driver is electrically connected to the gate of the second NMOS transistor MN2. The sources of both the first NMOS transistor MN1 and the second NMOS transistor MN2 are electrically connected to one end of the third resistor RCS, and the other end of the third resistor RCS and the source of the third NMOS transistor MN8 are grounded. A second resistor (i.e., ...) is connected in parallel between the source and gate of both the first NMOS transistor MN1 and the second NMOS transistor MN2. Figure 2 RN1 and RN2 in the second resistor are used to sample the voltage drop across the RCS of the third resistor using the second resistor, so as to reuse the second drive pin GN1 and the third drive pin GN2 to complete the current sampling of the winding end.

[0025] Thus, in this embodiment, the pre-driver controls the switching on and off of the two NMOS transistors through GN1 and GN2. At the same time, this embodiment provides a third resistor RCS at the source of the two NMOS transistors. In this way, when both the upper and lower transistors of the preceding stage GN1 / GN2 are turned off, the voltage drop across the third resistor RCS can be indirectly sampled through RN1 and RN2, thereby reusing GN1 / GN2 to complete the current sampling. Based on this, the CS pin on the pre-driver can be reduced, thereby reducing the number of traces on the PCD board.

[0026] Therefore, through the aforementioned circuit design, the pre-drive circuit proposed in this embodiment retains the driving and current detection functions while reducing the number of pre-driver pins and board-level interconnections, thereby optimizing the cost of the pre-driver package. As a result, it is very suitable for large-scale application and promotion.

[0027] Having described the overall architecture of the pre-driver circuit, the detailed circuit components of the pre-driver are provided below: In one possible design, the pre-driver may include, but is not limited to, a PMOS transistor driving unit, an NMOS transistor driving unit, a current feedback unit, and a drive signal generation unit, wherein the connection structure of the aforementioned circuit units is as follows: In practical applications, the signal input terminal of the drive signal generation unit serves as the input terminal of the pre-driver, used to receive drive control signals (wherein, the drive control signals include the magnetic field signal generated by the single-phase brushless DC motor and the pulse width modulation signal received based on the pulse signal input pin). The output terminal of the drive signal generation unit is electrically connected to the input terminals of the PMOS transistor drive unit and the NMOS transistor drive unit, respectively, and is used to output drive signals to the PMOS transistor drive unit and the NMOS transistor drive unit. In this embodiment, the drive signal generation unit is provided with three output terminals, namely the first output terminal, the second output terminal, and the third output terminal. The drive signals include a first drive sub-signal for driving the PMOS transistor drive unit, and a second drive sub-signal and a third drive sub-signal for driving the NMOS transistor drive unit. Thus, the three output terminals output the aforementioned three drive sub-signals in sequence, thereby realizing the driving of two PMOS transistors and two NMOS transistors (two PMOS transistors only require one drive sub-signal to drive, while two NMOS transistors each require one drive sub-signal to drive, and the driving process is described in detail below).

[0028] Furthermore, the output terminal of the PMOS transistor driving unit serves as the first driving pin FG, and is electrically connected to the gate of the second PMOS transistor MP2 and the gate of the third NMOS transistor MN8, respectively. The first output terminal of the NMOS transistor driving unit serves as the second driving pin GN1, and is electrically connected to the gate of the first NMOS transistor MN1. The second output terminal of the NMOS transistor driving unit serves as the third driving pin GN2, and is electrically connected to the gate of the second NMOS transistor MN2.

[0029] Meanwhile, the input terminal of the current feedback unit is electrically connected to the second drive pin GN1 and the third drive pin GN2, and is used to realize the current feedback of the winding terminal of the motor by multiplexing GN1 and GN2. The output terminal of the current feedback unit is electrically connected to the feedback input terminal of the drive signal generation unit, and the feedback control terminal of the drive signal generation unit is electrically connected to the controlled terminal of the current feedback unit.

[0030] As described above, the pre-driver in this embodiment consists of a driving unit responsible for two PMOS transistors, a driving unit responsible for two NMOS transistors, a feedback unit responsible for sampling the winding terminal current, and a driving signal generation unit for generating the driving signal for the entire motor.

[0031] After describing the overall structure of the aforementioned pre-driver, the specific circuit structures of each of the aforementioned drive units are provided below.

[0032] In one specific implementation, the PMOS transistor driving unit may include, but is not limited to, a fourth NMOS transistor MN7, see [link to relevant documentation]. Figure 3 and Figure 4 As shown, the gate of the fourth NMOS transistor MN7 is electrically connected to the first output terminal of the drive signal generation unit, and is used to receive the first drive sub-signal (i.e., receive the first drive sub-signal). Figure 4 The Hlogic_dly signal in the above context), wherein the source of the fourth NMOS transistor MN7 is grounded, and the drain of the fourth NMOS transistor MN7 serves as the first drive pin FG (see [link]). Figure 3 As shown in the figure, the gates of the second PMOS transistor MP2 and the third NMOS transistor MN8 are electrically connected respectively.

[0033] Thus, by using the Hlogic_dly signal output by the drive signal generation unit, combined with the fourth NMOS transistor MN7, the turn-off and turn-on control of the first PMOS transistor MP1 and the second PMOS transistor MP2 can be achieved.

[0034] Furthermore, one circuit configuration of the NMOS transistor driving unit is disclosed below: In specific applications, the NMOS transistor driving unit described herein may include, but is not limited to, a first half-bridge driving circuit and a second half-bridge driving circuit; wherein, the input terminal of the first half-bridge driving circuit is electrically connected to the second output terminal of the driving signal generation unit, and is used to receive the second driving sub-signal (i.e., Figure 3 and Figure 4 (hson1 and lson1 signals in the diagram), the output of the first half-bridge drive circuit serves as the first output of the NMOS transistor drive unit, and is electrically connected to the gate of the first NMOS transistor MN1 (see...). Figure 3 As shown), the input terminal of the second half-bridge drive circuit is electrically connected to the third output terminal of the drive signal generation unit, and is used to receive the third drive sub-signal (i.e. Figure 3 and Figure 4 The output of the second half-bridge drive circuit is used as the second output of the NMOS transistor drive unit and is electrically connected to the gate of the second NMOS transistor MN2. Thus, in this embodiment, a half-bridge drive circuit is configured for each NMOS transistor to realize the on / off control of each NMOS transistor.

[0035] It should be noted that the circuit structures of the first half-bridge drive circuit and the second half-bridge drive circuit provided in this embodiment are the same, and can be found in [reference needed]. Figure 3 As shown, this embodiment takes the first half-bridge drive circuit as an example to illustrate its specific circuit composition.

[0036] In one specific implementation, the first half-bridge drive circuit may include, but is not limited to, the fifth NMOS transistor MN9, the sixth NMOS transistor MN3, the first high-side signal driver hsdrv1, and the first low-side signal driver lsdrv1.

[0037] Among them, see Figure 3As shown, the input terminals of the first high-side signal driver hsdrv1 and the first low-side signal driver lsdrv1 are both used as input terminals of the first half-bridge driving circuit and are electrically connected to the second output terminal of the driving signal generation unit (i.e., the first high-side signal driver hsdrv1 receives the hson1 signal in the second driving sub-signal, while the first low-side signal driver lsdrv1 receives the lson1 signal in the second driving sub-signal). The output terminal of the first high-side signal driver hsdrv1 is electrically connected to the gate of the fifth NMOS transistor MN9, and the output terminal of the first low-side signal driver lsdrv1 is electrically connected to the gate of the sixth NMOS transistor MN3. At the same time, the source of the fifth NMOS transistor MN9 is electrically connected to the drain of the sixth NMOS transistor MN3, the drain of the fifth NMOS transistor MN9 is electrically connected to the power supply, the source of the sixth NMOS transistor MN9 is grounded, and the common connection terminal of the fifth NMOS transistor MN9 and the sixth NMOS transistor MN3 serves as the output terminal of the first half-bridge driving circuit and is electrically connected to the gate of the first NMOS transistor MN1 through the fourth resistor RG1.

[0038] In this way, the on / off state of the fifth NMOS transistor MN9 and the sixth NMOS transistor MN3 can be controlled by the hson1 and lson1 signals output by the drive signal generation unit, thereby realizing the drive control of the first NMOS transistor MN1.

[0039] It should be noted that the circuit structure of the second half-bridge driver circuit is the same as that of the first half-bridge driver circuit, namely, it includes a second high-side signal driver hsdrv2, a second low-side signal driver lsdrv2, NMOS transistors MN10 and MN5. The second high-side signal driver hsdrv2 receives the hson2 signal from the third driver sub-signal, while the second low-side signal driver lsdrv2 receives the lson1 signal from the third driver sub-signal. Its connection structure can be found in [reference needed]. Figure 3 As shown, it will not be elaborated further here.

[0040] Furthermore, see the circuit diagrams for hsdrv1 and hsdrv2. Figure 18 As shown, MN10, MN20, MP10, MP20, MP30, and MP40 constitute the first-stage low-to-high level conversion circuit, and MN40, MN50, MP50, and MP60 constitute the second-stage high-to-low level conversion circuit. R1, C1, and MN30 are used to set the delay time from the falling edge of hson to the falling edge of the gate of MN60. Specifically, hg is connected... Figure 3 The gates of MN9 and MN10 are connected via sw. Figure 3 GN1 or GN2 is used, while D1 is used to clamp the voltage drop of hg and sw to prevent overvoltage in subsequent circuits.

[0041] Furthermore, circuit diagrams for LSDRV1 and LSDRV2 can be found in [reference needed]. Figure 19 As shown, it consists of a chain of inverters with progressively increasing driving capability, wherein, Figure 19 lg connection in Figure 3 The gates of MN3 and MN5.

[0042] Therefore, the half-bridge driving structure formed by MN9 and MN3 can be used to drive the on and off of MN1, and the other half-bridge driving structure formed by MN10 and MN5 can be used to drive the on and off of MN2, thereby realizing the function of GN1 and GN2 pins driving MN1 and MN2.

[0043] After introducing the circuit of the NMOS transistor drive unit, the specific circuit structure of the current feedback unit is provided below.

[0044] In a specific implementation, the current feedback unit, for example, includes: a seventh NMOS transistor MN4, an eighth NMOS transistor MN6, and a comparator comp1, wherein the connection structure of the aforementioned devices is as follows: See Figure 3 As shown, the drain of the seventh NMOS transistor MN4 is electrically connected to the second drive pin GN1 (i.e., the common terminal of MN9 and MN3), and the drain of the eighth NMOS transistor MN6 is electrically connected to the third drive pin GN2 (i.e., the common terminal of MN10 and MN5). The sources of the seventh NMOS transistor MN4 and the eighth NMOS transistor MN6 are both electrically connected to the non-inverting input of the comparator comp1, and the inverting input of the comparator comp1 is electrically connected to the reference voltage vref.

[0045] Simultaneously, the gates of the seventh NMOS transistor MN4 and the eighth NMOS transistor MN6 are both electrically connected to the feedback control terminal of the drive signal generation unit, used to receive the feedback control signal output by the drive signal generation unit. Specifically, the gate of the seventh NMOS transistor MN4 is used to receive the lsns_on1 signal in the feedback control signal (see...). Figure 3 As shown), the gate of the eighth NMOS transistor MN6 receives the lsns_on2 signal from the feedback control signal. Finally, the output of the comparator comp1 serves as the output of the current feedback unit and is electrically connected to the feedback input of the drive signal generation unit (i.e., connected to the OCP pin of the pre-driver, see...). Figure 3 and Figure 4 (As shown).

[0046] Thus, based on the detailed circuit structure description of the drive and current feedback units described above, the entire pre-drive circuit's operation process is as follows: Figure 3The dashed box in the image represents a single-phase BLDC drive circuit formed by discrete components (i.e., Figure 2 (The circuits excluding the pre-driver are shown in the figure). The circuit outside the dashed box is the implementation circuit of the PMOS transistor driving unit, NMOS transistor driving unit, and current feedback unit in the pre-driver proposed in this embodiment.

[0047] MN9 and MN3 form a half-bridge drive structure, driving the switching on and off of MN1. When both MN9 and MN3 are off, the lsns_on1 signal controls MN4 to turn on. The voltage drop generated by the winding current flowing through RCS is sampled by RN1 and MN4 and input to the non-inverting input of comparator comp1. At this time, the voltage at the positive input of comparator comp1 is equal to... Figure 3 The voltage at the CS node in the comparator is high when it exceeds the vref reference voltage. Simultaneously, MN10 and MN5 form another half-bridge drive structure to drive the switching on and off of MN2. When both MN10 and MN5 are off, the lsns_on2 signal controls MN6 to turn on. The voltage drop generated by the winding current flowing through RCS is sampled by RN1 and MN6 to the non-inverting input of comparator comp1. At this time, the voltage at the positive input of comparator comp1 is equal to the voltage at the CS node. When this circuit exceeds the vref reference voltage, the potential of the output OCP node of comp1 flips high.

[0048] Furthermore, the two current sampling circuits are controlled by the magnetic field signal Hlogic and operate alternately. RG1 and RG2 are optional resistors used to limit the gate charging and discharging current of MN1 and MN2, thereby controlling the switching speed of MN1 and MN2. The Hall sensor outputs the aforementioned Hlogic signal. When the N pole is close to the pre-driver IC, the output is high, and when the S pole is close to the pre-driver IC, the output is low. At this time, the drive signal generation unit generates the corresponding hson1 and lson1 (second drive sub-signals), hson2 and lson2 (third drive sub-signals), lsns_on1 and lsns_on2 (feedback control signals), and Hlogic_dly signal (first drive sub-signal, which is the delay signal of Hlogic) through the input Hlogic signal and PWM (pulse width modulation signal).

[0049] Specifically, hson1 and hson2 control the on / off states of MN9 and MN10 via hsdrv1 and hsdrv2 modules, respectively. When the inputs to hson1 and hson2 are high, MN9 and MN10 are on; when the inputs are low, MN9 and MN10 are off. Similarly, lson1 and lson2 control the on / off states of MN3 and MN5 via lsdrv1 and lsdrv2 modules, respectively. When the inputs to lson1 and lson2 are high, MN3 and MN5 are on; when the inputs are low, MN3 and MN5 are off. lsns_on1 and lsns_on2 control the on / off states of MN4 and MN6, respectively, thereby alternately sampling the voltage of the CS node to the non-inverting input of comparator comp1 to complete current sampling for use as overcurrent protection within the driver.

[0050] Furthermore, the following provides Figure 3 and Figure 4 For a typical drive waveform of the entire pre-drive circuit, see [link / reference]. Figure 5 As shown, by Figure 5 It can be seen that GN1 and GN2 alternately output PWM signals and alternately sample the voltage of the CS node. When the Hlogic signal changes from low to high, GN2 first goes low. When Hlogic_dly changes from low to high, GP2 quickly goes low, and GP1 slowly charges up through RP1. After GP1 is fully charged and remains high, GN1 changes from low to high and starts outputting the PWM signal. Similarly, when Hlogic changes from high to low, GN1 first goes low. When Hlogic_dly changes from high to low, GP1 quickly goes low, and GP2 slowly charges up through RP2. After GP2 is fully charged and remains high, GN2 changes from low to high and starts outputting the PWM signal. In addition, when the Hlogic signal is high, the voltage of the GN2 node is equal to the voltage of the CS node, and when Hlogic is low, the voltage of the GN1 node is equal to the voltage of the CS node.

[0051] In addition, this embodiment also provides Figure 3 and Figure 4 See the drive waveform diagram of the entire pre-drive circuit at 100% duty cycle. Figure 6 As shown, when the output is at 100% duty cycle, GN1 / GN2 alternately remain constant at high.

[0052] In addition, this embodiment also provides Figure 3 and Figure 4 The output waveform of the entire pre-drive circuit when it triggers overcurrent protection is shown in the image. Figure 7 As shown; where, from Figure 7 As can be seen, when the Hlogic signal is low, and the CS voltage sampled by GN1 is high (Vref), GN2 goes low and remains low for a set time. Figure 3 When MN1 and MN2 are both off, the current in the electrode windings decays, and then GN2 goes high again, repeating this process alternately. When Hlogic is high, and the CS voltage sampled by GN2 is higher than Vref, GN1 goes low and remains low for a fixed time. Figure 3 When MN1 and MN2 are both in the off state, the current on the electrode winding will decrease, and then GN1 will go high again, and this process will repeat alternately.

[0053] Therefore, based on the detailed circuit description of the two drive units and the current feedback unit described above, the pre-driver provided in this embodiment can use three drive pins to realize the drive control of each field-effect transistor in the H-bridge drive circuit, and realize the current sampling function of the motor winding terminal by reusing the drive pin of the NMOS transistor; thus, the number of pins on the pre-driver can be reduced while retaining the drive and current detection functions.

[0054] In one possible design, the following provides one type of logic circuit for the drive signal generation unit: In specific implementations, the drive signal generation unit described in the example may include, but is not limited to, a first drive signal generation circuit, a second drive signal generation circuit, and an auxiliary drive circuit.

[0055] In this embodiment, the first drive signal generation circuit is provided with a PMOS transistor signal output terminal and an auxiliary signal output terminal. The input terminal of the first drive signal generation circuit is electrically connected to the output terminal of the Hall sensor to receive the magnetic field signal. The PMOS transistor signal output terminal of the first drive signal generation circuit is electrically connected to the PMOS transistor driving unit to output a first drive sub-signal to the PMOS transistor driving unit. The auxiliary signal output terminal of the first drive signal generation circuit is electrically connected to the second drive signal generation circuit to output a first auxiliary drive signal to the second drive signal generation circuit.

[0056] See Figure 8 As shown, the detailed circuit structure of the first drive signal generation circuit is provided below: In specific applications, for example, the first drive signal generation circuit may include, but is not limited to, rising and falling edge delay circuits. Figure 8In this circuit, htl_lth_dly represents the circuit itself, and an XOR gate U1 is used. The inputs of the rising and falling edge delay circuits are electrically connected to the output of the Hall sensor. The output of the rising and falling edge delay circuits serves as the signal output of the PMOS transistor and is electrically connected to the PMOS transistor driving unit (i.e., electrically connected to the gate of MN7). Simultaneously, the first input of the XOR gate U1 is electrically connected to the output of the Hall sensor, and the second input of the XOR gate U1 is electrically connected to the output of the rising and falling edge delay circuit. The output of the XOR gate U1 serves as the auxiliary signal output and is electrically connected to the second drive signal generation circuit, outputting a first auxiliary drive signal (i.e., the lston signal). Thus, htl_lth_dly (rising and falling edge delay circuit) delays the input Hlogic and outputs the Hlogic_dly signal (i.e., the first driving sub-signal); while Hlogic and Hlogic_dly are XORed by gate U1 to output the lston signal (i.e., the first auxiliary driving signal), which is then sent to the second driving signal generation circuit to generate the second and third driving sub-signals.

[0057] Rising and falling edge delay circuits are commonly used in motor drives, and their circuit structure will not be described in detail here.

[0058] After describing the circuit structure of the first drive generation circuit, the connection structure of the auxiliary drive circuit is provided below: In a specific implementation, the input terminal of the auxiliary drive circuit is electrically connected to the output terminal of the current feedback unit (i.e., the output terminal of comparator comp1) and the output terminal of the Hall sensor, for receiving the feedback signal output by the current feedback unit and the magnetic field signal output by the Hall sensor. The output terminal of the auxiliary drive circuit is electrically connected to the second drive signal generation circuit, for outputting the second auxiliary drive signal and the third auxiliary drive signal to the second drive signal generation circuit.

[0059] Optionally, for example, the auxiliary drive circuit may include, but is not limited to, a rising edge narrow pulse circuit ( Figure 9 In this context, lfh_oneshot represents the circuit, and the rising and falling edge narrow pulse circuit ( Figure 9 The circuit in lfh_hfl_oneshot represents the circuit, the first NOR gate U2, and the first rising edge delay circuit ( Figure 9 In this circuit, lfh_dly represents the circuit, and the circuit consists of a first NOT gate U3, a first NAND gate U4, a second NAND gate U5, a third NOT gate U6, and a fourth NOT gate U7. The connection structure of the aforementioned electronic devices is as follows: The input terminal of the rising edge narrow pulse circuit is electrically connected to the output terminal of the current feedback unit (i.e., the output terminal of comparator comp1), and the input terminals of the rising and falling edge narrow pulse circuits are electrically connected to the output terminal of the Hall sensor. The output terminals of the rising edge narrow pulse circuit and the rising and falling edge narrow pulse circuits are electrically connected to the input terminal of the first NOR gate U2. The output terminal of the first NOR gate U2 is electrically connected to the input terminal of the first NOT gate U3 through the first rising edge delay circuit, and the output terminal of the first NOT gate U3 is electrically connected to the first input terminals of the first NAND gate U4 and the second NAND gate U5, respectively.

[0060] Meanwhile, the second input of the first NAND gate U4 is used to receive the fourth auxiliary drive signal (i.e. Figure 9 The hp signal in the signal is mentioned, wherein the output of the first NAND gate U4 is electrically connected to the input of the third NOT gate U6, and the output of the third NOT gate U6 outputs the second auxiliary drive signal. Figure 9 The ls1_oc_on signal in the second NAND gate U5 is used to receive the fifth auxiliary drive signal (i.e., the ls1_oc_on signal in the second NAND gate U5). Figure 9 The hn signal in the second NAND gate U5 is electrically connected to the input of the fourth NOT gate U7, and the output of the fourth NOT gate U7 outputs the third auxiliary drive signal (i.e., the hn signal in the second NAND gate U5). Figure 9 (The ls2_oc_on signal in the context of this).

[0061] In this embodiment, the fourth auxiliary drive signal and the fifth auxiliary drive signal are generated based on the magnetic field signal output by the Hall sensor. For example, but not limited to, the magnetic field signal can be input into a NOT gate to obtain the fifth auxiliary drive signal, and then the fifth auxiliary drive signal is input into another NOT gate to output the fourth auxiliary drive signal. (See also...) Figure 9 The output circuits for hn and hp are shown in the diagram.

[0062] Thus, the lfh_oneshot circuit outputs a high-narrow pulse signal oc_shot after detecting the rising edge of OCP, while the lfh_hfl_oneshot circuit outputs a high-narrow pulse signal hl_shot when it detects the Hlogic signal toggling, including low-to-high and high-to-low transitions. Then, the two signals pass through the first NOR gate to output the en_pro signal. Next, the lfh_dly circuit delays the rising edge of the input signal en_pro and outputs the en_pro_dly signal. Finally, the second auxiliary drive signal and the third auxiliary drive signal are output through the first NOT gate, two NAND gates, the third NOT gate, and the fourth NOT gate.

[0063] Therefore, the first drive generation circuit and the auxiliary drive circuit can generate three auxiliary drive signals. Then, these signals can be combined with the PWM signal and, with the help of the second drive generation circuit, generate the second drive sub-signal, the third drive sub-signal, and the feedback control signal. The process is as follows: The input terminal of the second drive signal generation circuit serves as the pulse signal input pin for receiving the pulse width modulation signal. The output terminal of the second drive signal generation circuit is electrically connected to the input terminal of the NMOS transistor drive unit and is used to generate a second sub-drive signal and a third sub-drive signal based on the pulse width modulation signal, the first auxiliary drive signal, the second auxiliary drive signal, and the third auxiliary drive signal, and send them to the NMOS transistor drive unit.

[0064] In this embodiment, the rising edge narrow pulse circuit, the rising and falling edge narrow pulse circuit, and the rising edge delay circuit are all commonly used circuits for motor drives, and their circuit structures will not be described in detail.

[0065] In a specific implementation, one of the circuit structures of the second drive signal generation circuit is disclosed below: In one specific embodiment, the second drive signal generation circuit includes a first logic signal generation circuit and a second logic signal generation circuit, wherein the first logic signal generation circuit outputs the second drive sub-signal to the NMOS transistor drive unit, and the second logic signal generation circuit outputs the third drive sub-signal to the NMOS transistor drive unit.

[0066] Furthermore, the first logic signal generation circuit and the second logic signal generation circuit have the same circuit structure, both including several fifth NOT gates, second NOR gates and third NAND gates, as well as two second rising edge delay circuits and one falling edge delay circuit.

[0067] See Figure 10 As shown, the first logic signal generation circuit will be used as an example for illustration: First, the input terminals of the fifth NOT gate U8 and the fifth NOT gate U9 both receive pulse width modulation signals (i.e., PWM signals). The output terminal of the fifth NOT gate U8 is connected to the first input terminal of the second NOR gate U10. The second input terminal of the second NOR gate U10 receives the fifth auxiliary drive signal. The output terminal of the second NOR gate U10 is electrically connected to the first input terminal of the second NOR gate U12 through the fifth NOT gate U11, and the second input terminal of the second NOR gate U12 is electrically connected to the output terminal of the first NOT gate U3.

[0068] Meanwhile, the output of the fifth NOT gate U9 is electrically connected to the first input of the second NOR gate U14 through the fifth NOT gate U13. The second input of the second NOR gate U14 receives the fifth auxiliary drive signal. The output of the second NOR gate U14 is electrically connected to the first input of the second NOR gate U15. The second input of the second NOR gate U15 is used to receive the second auxiliary drive signal, and the third input of the second NOR gate U15 is used to receive the first auxiliary drive signal.

[0069] Furthermore, the output of the second NOR gate U12 is electrically connected to the first falling edge delay generation circuit. Figure 10 The two dy1s in the diagram represent the input terminals of the two falling edge delay generation circuits and the first input terminal of the third NAND gate U16, respectively. The output terminal of the first falling edge delay generation circuit is electrically connected to the input terminal of the fifth NOT gate U17. At the same time, the output terminal of the second NOR gate U15 is electrically connected to the input terminal of the fifth NOT gate U18. The output terminal of the fifth NOT gate U18 is electrically connected to the input terminal of the second falling edge delay generation circuit and the first input terminal of the third NAND gate U19. The output terminal of the second falling edge delay generation circuit is electrically connected to the input terminal of the fifth NOT gate U20, and the input terminal of the fifth NOT gate U20 is electrically connected to the second input terminal of the third NAND gate U16. The input terminal of the fifth NOT gate U17 is electrically connected to the second input terminal of the third NAND gate U19.

[0070] The output of the third NAND gate U16 is electrically connected to the input of the fifth NOT gate U21. The output of the fifth NOT gate U21 outputs the hson1 signal from the second driving sub-signal. The output of the third NAND gate U19 is electrically connected to the output of the fifth NOT gate U22, and the output of the fifth NOT gate U22 outputs the lson1 signal from the second driving sub-signal.

[0071] Furthermore, the outputs of the fifth NOT gate U21 and the fifth NOT gate U22 are also electrically connected to the input of the second NOR gate U23. The output of the second NOR gate U23 is electrically connected to the input of the falling edge delay generation circuit dly2. The output of the falling edge delay generation circuit dly2 is electrically connected to the first input of the third NAND gate U24. The second input of the third NAND gate U24 is used to receive the fifth auxiliary drive signal, and the output of the third NAND gate U24 is electrically connected to the input of the fifth NOT gate U25. The output of the fifth NOT gate U25 is used to output the feedback control signal lsns_on1.

[0072] Similarly, see Figure 10 As shown, the second logic signal generation circuit is used to generate the hson2 and lson2 signals in the third driving sub-signal, as well as the feedback control signal lsns_on2. Its circuit structure is the same as that of the first logic signal generation circuit, and will not be described again here.

[0073] Furthermore, the following provides waveform diagrams of key nodes in the drive signal generation unit. (See attached diagram) Figure 11 The diagram is shown to illustrate the logical functions of lfh_oneshot, lfh_hfl_oneshot, lfh_dly, and htl_lth_dly.

[0074] When the lston signal output by Hlogic and Hlogic_dly after the XOR gate is high, lson1 and lson2 simultaneously output high, and further... Figure 3 The circuits shown in lsdrv1 and lsdrv2 turn on MN3 and MN5, and turn off MN1 and MN2, to prevent Hlogic_dly from toggling. Figure 3 If MP1 or MP2 is opened quickly, there is a possibility that MP1 and MN1, or MP2 and MN2 can be directly connected.

[0075] Additionally, if en_pro_dly is low, it indicates that the overcurrent protection OCP has been triggered and the Hlogic signal has toggled. At this time, when Hlogic is high, the hp signal is high, ls1_oc_on is high, and further, lson1 output is high. Figure 3 When GN1 outputs low, MN1 is off, preventing a potential shoot-through between MN1 and MP1 caused by GP1 slowly charging when Hlogic_dly goes high. Similarly, when Hlogic is low, hn is high, ls2_oc_on is high, and further, lson2 outputs high. Figure 3 When GN2 outputs low, MN2 is turned off, avoiding the possibility of a shoot-through between MN2 and MP2 caused by GP2 slowly charging and turning off when Hlogic_dly goes low.

[0076] In addition, this embodiment also provides the input and output waveform diagrams of dy1 and dy2, see [link / reference]. Figure 12 As shown, it is used to illustrate the logical functions of dly1 and dly2, where dly1 is used to set the dead time of hson1, lson1 and hson2, lson2.

[0077] Thus, by using the specific circuit structure disclosed by the given drive signal generation unit, the necessary drive control signals can be provided for the PMOS drive unit, NMOS drive unit, and current feedback unit, thereby completing the drive control of the field-effect transistors in the H-bridge drive circuit and the on / off control of the NMOS transistors in the current feedback unit.

[0078] Therefore, based on the detailed description of the pre-drive circuit for a single-phase brushless DC motor, the drive circuit provided by this invention does not directly output GP1. Instead, it directly controls the turn-on and turn-off of the second PMOS transistor through the first drive pin FG and the first resistor between the source and gate of the second PMOS transistor. Simultaneously, the turn-on and turn-off of the first PMOS transistor are controlled by the first resistor between the source and gate of the third NMOS transistor and the first PMOS transistor, and the gate of the third NMOS transistor is connected to FG. This reduces the number of GP1 pins on the pre-drive circuit and the corresponding internal drive circuitry. Furthermore, the second drive pin GN1 and... While driving the first and second NMOS transistors respectively, the third drive pin GN2 indirectly samples the voltage drop across the third resistor through the second resistor between their respective sources and gates when both the upper and lower transistors of the preceding stage GN1 / GN2 are turned off. That is, GN1 / GN2 is reused to complete current sampling. Based on this, the CS pin on the pre-driver is reduced, thereby reducing the number of traces on the PCB board. Thus, through the above design, the pre-driver scheme proposed in this invention reduces the number of pre-driver pins and board-level interconnections while retaining the driving and current detection functions, thereby optimizing the cost of the pre-driver package. Therefore, it is very suitable for large-scale application and promotion.

[0079] In one possible design, the second aspect of this embodiment provides the first aspect of the embodiment. Figure 2 Alternative solution one, see Figure 13 As shown, in this embodiment Figure 13 The diodes D1 and D2 in the middle are used to clamp the potential of GP1 and GP2. When the power supply voltage, i.e. the source voltage of MP1 and MP2, surges, MP1 and MP2 can be turned on simultaneously to absorb the backflow current.

[0080] In one possible design, the third aspect of this embodiment provides the first aspect of the embodiment. Figure 2 Alternative solution two, see Figure 14 As shown, in this embodiment, NPN transistors Q1 and Q2 are used to drive MP1 and MP2 respectively. VH is a fixed power supply. R3 and R2 are used to limit the driving capability of Q1 and Q2, and at the same time to limit the voltage of GP1 and GP2 to be too low, protect the gate-source voltage difference of MP1 and MP2, and prevent the device from breaking down.

[0081] In one possible design, the fourth aspect of this embodiment provides the first aspect of the embodiment. Figure 2 Alternative solution three, see Figure 15 As shown, it is about to Figure 14 Replace Q1 and Q2 with NMOS transistors MN3 and MN4 to achieve the same function.

[0082] In one possible design, the fourth aspect of this embodiment provides the first aspect of the embodiment. Figure 2 Alternative option four, see Figure 16 As shown, when the VCC voltage is too high, directly driving MN1, MN2, MP1, and MP2 can easily cause the devices to exceed their withstand voltage limits. Therefore, Figure 16 By setting R1 and RP1 to form a voltage divider, the gate-source voltage of MP1 can be protected from breakdown. Similarly, R2 and RP2, RG1 and RN1, and RG2 and RN2 form a voltage divider to protect the gate-source voltages of MP2, MN1, and MN2 from breakdown, thereby improving the stability of the circuit.

[0083] In one possible design, the fifth aspect of this embodiment provides the first aspect of the embodiment. Figure 3 For alternatives, see Figure 17 As shown, this embodiment will Figure 3 The upper transistors of GN1 and GN2 can be replaced with PMOS transistors MP9 and MP10 to achieve the corresponding driving function.

[0084] Of course, the aforementioned replacement schemes are merely examples, and any scheme that achieves the corresponding function is acceptable. This embodiment is not limited to the examples mentioned above.

[0085] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A pre-drive circuit for a single-phase brushless DC motor, characterized in that, include: A pre-driver, wherein the pre-driver is provided with a first drive pin (FG), a second drive pin (GN1) and a third drive pin (GN2), and the pre-driver is also provided with a pulse signal input pin; The H-bridge drive circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the two PMOS transistors are interconnected and connected to a power supply. The drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically connected to the drain of the second NMOS transistor. The common connection of the two PMOS transistors and the two NMOS transistors serves as the output terminal of the H-bridge drive circuit and is electrically connected to the winding terminal of a single-phase brushless DC motor. The first drive pin (FG) of the pre-driver is electrically connected to the gate of the second PMOS transistor and the gate of the third NMOS transistor. The drain of the third NMOS transistor is electrically connected to the gate of the first PMOS transistor, and a first resistor is connected in parallel between the source and gate of both PMOS transistors. The second drive pin (GN1) of the pre-driver is electrically connected to the gate of the first NMOS transistor, and the third drive pin (GN2) of the pre-driver is electrically connected to the gate of the second NMOS transistor. The sources of both the first and second NMOS transistors are electrically connected to one end of a third resistor, and the other end of the third resistor and the source of the third NMOS transistor are grounded. A second resistor is connected in parallel between the source and gate of both the first and second NMOS transistors to sample the voltage drop across the third resistor. The second drive pin (GN1) and the third drive pin (GN2) are then used to complete the current sampling at the winding end.

2. The pre-drive circuit for a single-phase brushless DC motor according to claim 1, characterized in that, The pre-driver includes: a PMOS transistor driving unit, an NMOS transistor driving unit, a current feedback unit, and a driving signal generation unit; The signal input terminal of the drive signal generation unit serves as the input terminal of the pre-driver to receive drive control signals. The output terminal of the drive signal generation unit is electrically connected to the input terminals of the PMOS transistor drive unit and the NMOS transistor drive unit, respectively, and is used to output drive signals to the PMOS transistor drive unit and the NMOS transistor drive unit. The drive control signals include the magnetic field signal generated by the single-phase brushless DC motor and the pulse width modulation signal received based on the pulse signal input pin. The output terminal of the PMOS transistor driving unit serves as the first driving pin (FG), which is electrically connected to the gate of the second PMOS transistor and the gate of the third NMOS transistor, respectively. The first output terminal of the NMOS transistor driving unit serves as the second driving pin (GN1), which is electrically connected to the gate of the first NMOS transistor, and the second output terminal of the NMOS transistor driving unit serves as the third driving pin (GN2), which is electrically connected to the gate of the second NMOS transistor. The input terminal of the current feedback unit is electrically connected to the second drive pin (GN1) and the third drive pin (GN2), wherein the output terminal of the current feedback unit is electrically connected to the feedback input terminal of the drive signal generation unit, and the feedback control terminal of the drive signal generation unit is electrically connected to the controlled terminal of the current feedback unit.

3. The pre-drive circuit for a single-phase brushless DC motor according to claim 2, characterized in that, The drive signal generation unit includes a first output terminal, and the drive signal includes a first drive sub-signal output from the first output terminal. The PMOS transistor driving unit includes: a fourth NMOS transistor; The gate of the fourth NMOS transistor is electrically connected to the first output terminal of the drive signal generation unit to receive the first drive sub-signal. The source of the fourth NMOS transistor is grounded, and the drain of the fourth NMOS transistor serves as the first drive pin (FG), which is electrically connected to the gate of the second PMOS transistor and the gate of the third NMOS transistor, respectively.

4. The pre-drive circuit for a single-phase brushless DC motor according to claim 2, characterized in that, The drive signal generation unit includes a second output terminal and a third output terminal, and the drive signal includes a second drive sub-signal output from the second output terminal and a third drive sub-signal output from the third output terminal. The NMOS transistor driving unit includes: a first half-bridge driving circuit and a second half-bridge driving circuit. The input terminal of the first half-bridge driving circuit is electrically connected to the second output terminal of the driving signal generation unit to receive the second driving sub-signal. The output terminal of the first half-bridge driving circuit serves as the first output terminal of the NMOS transistor driving unit and is electrically connected to the gate of the first NMOS transistor. The input terminal of the second half-bridge driving circuit is electrically connected to the third output terminal of the driving signal generation unit to receive the third driving sub-signal. The output terminal of the second half-bridge driving circuit serves as the second output terminal of the NMOS transistor driving unit and is electrically connected to the gate of the second NMOS transistor.

5. A pre-drive circuit for a single-phase brushless DC motor according to claim 4, characterized in that, The first half-bridge driving circuit and the second half-bridge driving circuit have the same circuit structure. The first half-bridge driving circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a first high-side signal driver, and a first low-side signal driver. The input terminals of the first high-side signal driver and the first low-side signal driver are both used as input terminals of the first half-bridge driving circuit and are electrically connected to the second output terminal of the driving signal generation unit. The output terminal of the first high-side signal driver is electrically connected to the gate of the fifth NMOS transistor, and the output terminal of the first low-side signal driver is electrically connected to the gate of the sixth NMOS transistor. The source of the fifth NMOS transistor is electrically connected to the drain of the sixth NMOS transistor, wherein the drain of the fifth NMOS transistor is electrically connected to the power supply, the source of the sixth NMOS transistor is grounded, and the common terminal of the fifth NMOS transistor and the sixth NMOS transistor serves as the output terminal of the first half-bridge drive circuit, and is electrically connected to the gate of the first NMOS transistor through the fourth resistor.

6. The pre-drive circuit for a single-phase brushless DC motor according to claim 2, characterized in that, The current feedback unit includes: a seventh NMOS transistor, an eighth NMOS transistor, and a comparator; The drain of the seventh NMOS transistor is electrically connected to the second drive pin (GN1), and the drain of the eighth NMOS transistor is electrically connected to the third drive pin (GN2). The sources of the seventh and eighth NMOS transistors are both electrically connected to the non-inverting input of the comparator. The inverting input of the comparator is electrically connected to the reference voltage. The gates of the seventh and eighth NMOS transistors are both electrically connected to the feedback control terminal of the drive signal generation unit. The output of the comparator serves as the output of the current feedback unit and is electrically connected to the feedback input of the drive signal generation unit.

7. A pre-drive circuit for a single-phase brushless DC motor according to claim 2, characterized in that, The driving signals include a first driving sub-signal for driving the PMOS transistor driving unit, and a second driving sub-signal and a third driving sub-signal for driving the NMOS transistor driving unit. The drive signal generation unit includes a first drive signal generation circuit, a second drive signal generation circuit, and an auxiliary drive circuit, wherein the first drive signal generation circuit is provided with a PMOS transistor signal output terminal and an auxiliary signal output terminal. The input terminal of the first drive signal generation circuit is electrically connected to the output terminal of the Hall sensor to receive the magnetic field signal. The PMOS transistor signal output terminal of the first drive signal generation circuit is electrically connected to the PMOS transistor driving unit to output a first drive sub-signal to the PMOS transistor driving unit. The auxiliary signal output terminal of the first drive signal generation circuit is electrically connected to the second drive signal generation circuit to output a first auxiliary drive signal to the second drive signal generation circuit. The input terminal of the auxiliary drive circuit is electrically connected to the output terminal of the current feedback unit and the output terminal of the Hall sensor, and is used to receive the feedback signal output by the current feedback unit and the magnetic field signal output by the Hall sensor. The output terminal of the auxiliary drive circuit is electrically connected to the second drive signal generation circuit, and is used to output the second auxiliary drive signal and the third auxiliary drive signal to the second drive signal generation circuit. The input terminal of the second drive signal generation circuit serves as the pulse signal input pin for receiving the pulse width modulation signal. The output terminal of the second drive signal generation circuit is electrically connected to the input terminal of the NMOS transistor drive unit and is used to generate a second sub-drive signal and a third sub-drive signal based on the pulse width modulation signal, the first auxiliary drive signal, the second auxiliary drive signal, and the third auxiliary drive signal, and send them to the NMOS transistor drive unit.

8. A pre-drive circuit for a single-phase brushless DC motor according to claim 7, characterized in that, The first drive signal generation circuit includes: rising and falling edge delay circuits and an XOR gate; The input terminals of the rising and falling edge delay circuits are electrically connected to the output terminals of the Hall sensor. The output terminals of the rising and falling edge delay circuits serve as the signal output terminals of the PMOS transistor and are electrically connected to the PMOS transistor driving unit. The first input terminal of the XOR gate is electrically connected to the output terminal of the Hall sensor, the second input terminal of the XOR gate is electrically connected to the output terminals of the rising and falling edge delay circuits, and the output terminal of the XOR gate serves as the auxiliary signal output terminal and is electrically connected to the second driving signal generation circuit.

9. A pre-drive circuit for a single-phase brushless DC motor according to claim 7, characterized in that, The auxiliary driving circuit includes: a rising edge narrow pulse circuit, a rising and falling edge narrow pulse circuit, a first NOR gate, a first rising edge delay circuit, a first NOT gate, a first NAND gate, a second NAND gate, a third NOT gate, and a fourth NOT gate; The input terminal of the rising edge narrow pulse circuit is electrically connected to the output terminal of the current feedback unit, and the input terminals of the rising and falling edge narrow pulse circuits are electrically connected to the output terminal of the Hall sensor. The output terminals of the rising edge narrow pulse circuit and the rising and falling edge narrow pulse circuits are electrically connected to the input terminal of the first NOR gate. The output terminal of the first NOR gate is electrically connected to the input terminal of the first NOT gate through the first rising edge delay circuit, and the output terminal of the first NOT gate is electrically connected to the first input terminals of the first NAND gate and the second NAND gate, respectively. The second input terminal of the first NAND gate is used to receive the fourth auxiliary drive signal, wherein the output terminal of the first NAND gate is electrically connected to the input terminal of the third NOT gate, and the output terminal of the third NOT gate outputs the second auxiliary drive signal; The second output terminal of the second NAND gate is used to receive the fifth auxiliary drive signal. The output terminal of the second NAND gate is electrically connected to the input terminal of the fourth NOT gate. The output terminal of the fourth NOT gate outputs the third auxiliary drive signal. The fourth auxiliary drive signal and the fifth auxiliary drive signal are generated based on the magnetic field signal output by the Hall sensor.

10. A pre-drive circuit for a single-phase brushless DC motor according to claim 7, characterized in that, The second driving signal generation circuit includes a first logic signal generation circuit and a second logic signal generation circuit. The first logic signal generation circuit and the second logic signal generation circuit have the same circuit structure, each including several fifth NOT gates, second NOR gates and third NAND gates, as well as two second rising edge delay circuits and one falling edge delay circuit. Specifically, the first logic signal generation circuit outputs the second driving sub-signal to the NMOS transistor driving unit, and the second logic signal generation circuit outputs the third driving sub-signal to the NMOS transistor driving unit.

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